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authorH. Peter Anvin <hpa@zytor.com>2012-02-25 22:33:46 -0800
committerH. Peter Anvin <hpa@zytor.com>2012-02-25 22:33:46 -0800
commit574784d177320e44878266a0858bddfd548b6c87 (patch)
tree0ca0b1d384ff02ed3bffbc912aee964b568fa347
parente9d46c48e4a5db7fe3370337d67e64607f95eed4 (diff)
downloadnasm-574784d177320e44878266a0858bddfd548b6c87.tar.gz
HLE: Move byte codes back to \271-\273
Since we are back to three bytecodes, move them back to the \271-\273 slot to free up the \264 complete quad. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
-rw-r--r--assemble.c19
-rw-r--r--disasm.c6
-rwxr-xr-xinsns.pl6
3 files changed, 15 insertions, 16 deletions
diff --git a/assemble.c b/assemble.c
index 4d8702cb..66acb843 100644
--- a/assemble.c
+++ b/assemble.c
@@ -80,10 +80,6 @@
* \254..\257 - a signed 32-bit operand to be extended to 64 bits.
* \260..\263 - this instruction uses VEX/XOP rather than REX, with the
* V field taken from operand 0..3.
- * \264 - skip this instruction pattern if HLE prefixes present
- * \265 - instruction takes XRELEASE (F3) with or without lock
- * \266 - instruction takes XACQUIRE/XRELEASE with or without lock
- * \267 - instruction takes XACQUIRE/XRELEASE with lock only
* \270 - this instruction uses VEX/XOP rather than REX, with the
* V field set to 1111b.
*
@@ -101,6 +97,9 @@
*
* t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
*
+ * \271 - instruction takes XRELEASE (F3) with or without lock
+ * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
+ * \273 - instruction takes XACQUIRE/XRELEASE with lock only
* \274..\277 - a signed byte immediate operand, from operand 0..3,
* which is to be extended to the operand size.
* \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
@@ -981,12 +980,6 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
ins->vex_wlp = *codes++;
break;
- case 0265:
- case 0266:
- case 0267:
- hleok = c & 3;
- break;
-
case 0270:
ins->rex |= REX_V;
ins->vexreg = 0;
@@ -994,6 +987,12 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
ins->vex_wlp = *codes++;
break;
+ case 0271:
+ case 0272:
+ case 0273:
+ hleok = c & 3;
+ break;
+
case4(0274):
length++;
break;
diff --git a/disasm.c b/disasm.c
index b6e55bc1..46cec8a6 100644
--- a/disasm.c
+++ b/disasm.c
@@ -703,19 +703,19 @@ static int matches(const struct itemplate *t, uint8_t *data,
break;
}
- case 0265:
+ case 0271:
if (prefix->rep == 0xF3)
drep = P_XRELEASE;
break;
- case 0266:
+ case 0272:
if (prefix->rep == 0xF2)
drep = P_XACQUIRE;
else if (prefix->rep == 0xF3)
drep = P_XRELEASE;
break;
- case 0267:
+ case 0273:
if (prefix->lock == 0xF0) {
if (prefix->rep == 0xF2)
drep = P_XACQUIRE;
diff --git a/insns.pl b/insns.pl
index 28c13486..b154dbd7 100755
--- a/insns.pl
+++ b/insns.pl
@@ -726,9 +726,9 @@ sub byte_code_compile($$) {
'jcc8' => 0370, # Match only if Jcc possible with single byte
'jmp8' => 0371, # Match only if JMP possible with single byte
'jlen' => 0373, # Length of jump
- 'hlexr' => 0265,
- 'hlenl' => 0266,
- 'hle' => 0267,
+ 'hlexr' => 0271,
+ 'hlenl' => 0272,
+ 'hle' => 0273,
# This instruction takes XMM VSIB
'vsibx' => 0374,
'vm32x' => 0374,