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| author | Cyrill Gorcunov <gorcunov@gmail.com> | 2018-02-05 20:20:48 +0300 |
|---|---|---|
| committer | Cyrill Gorcunov <gorcunov@gmail.com> | 2018-02-05 20:20:48 +0300 |
| commit | da1cb0e0003a9f2a6be141e4bc5273b1a8681b39 (patch) | |
| tree | da685e06d3e9c1d748221d2446ce43e813c8dbcb | |
| parent | d287398b8df32b4593aad7cc7ea685433400cb9f (diff) | |
| download | nasm-da1cb0e0003a9f2a6be141e4bc5273b1a8681b39.tar.gz | |
Revert "insns.dat: Add VAESENC, VAESENCLAST instructions"
This reverts commit d625f85cd2a3abbdad610d222096a19368df09f9.
Occasionally merged in from the master, while it was here
already in different form.
| -rw-r--r-- | x86/insns.dat | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/x86/insns.dat b/x86/insns.dat index 0bc6d973..a05fdc7e 100644 --- a/x86/insns.dat +++ b/x86/insns.dat @@ -5175,30 +5175,6 @@ PCOMMIT void [ 66 0f ae f8] ; AMD Zen v1 CLZERO void [ 0f 01 fc] FUTURE,AMD -;# Intel instruction extension based on pub number 319433-030 dated October 2017 - -; Intel VAES instructions -VAESENC ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig dc /r] VAES,FUTURE -VAESENCLAST ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig dd /r] VAES,FUTURE -VAESDEC ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig de /r] VAES,FUTURE -VAESDECLAST ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig df /r] VAES,FUTURE - -; Intel VAES + AVX512VL instructions -VAESENC xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig dc /r] AVX512VL,AVX512,VAES,FUTURE -VAESENC ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig dc /r] AVX512VL,AVX512,VAES,FUTURE -VAESENCLAST xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig dd /r] AVX512VL,AVX512,VAES,FUTURE -VAESENCLAST ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig dd /r] AVX512VL,AVX512,VAES,FUTURE -VAESDEC xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig de /r] AVX512VL,AVX512,VAES,FUTURE -VAESDEC ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig de /r] AVX512VL,AVX512,VAES,FUTURE -VAESDECLAST xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig df /r] AVX512VL,AVX512,VAES,FUTURE -VAESDECLAST ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig df /r] AVX512VL,AVX512,VAES,FUTURE - -; Intel VAES + AVX512F instructions -VAESENC zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig dc /r] AVX512,VAES,FUTURE -VAESENCLAST zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig dd /r] AVX512,VAES,FUTURE -VAESDEC zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig de /r] AVX512,VAES,FUTURE -VAESDECLAST zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig df /r] AVX512,VAES,FUTURE - ;# Systematic names for the hinting nop instructions ; These should be last in the file HINT_NOP0 rm16 [m: o16 0f 18 /0] P6,UNDOC |