diff options
| author | H. Peter Anvin <hpa@linux.intel.com> | 2010-08-24 17:28:00 -0700 |
|---|---|---|
| committer | H. Peter Anvin <hpa@linux.intel.com> | 2010-08-24 17:30:00 -0700 |
| commit | 21d4ccc3c338ada6e52b9a10373f138f790c8b5d (patch) | |
| tree | 4bd0b409858c10dbcd41646b36ac0a454c008e14 | |
| parent | 96e8d96045469f57ce6024c16e632aa2fedef231 (diff) | |
| download | nasm-21d4ccc3c338ada6e52b9a10373f138f790c8b5d.tar.gz | |
BR 3052618: handle segment register operations in 64-bit mode
Handle segment register operations in 64-bit mode, and add a few
optimization patterns.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
| -rw-r--r-- | insns.dat | 14 | ||||
| -rw-r--r-- | test/sreg.asm | 65 |
2 files changed, 75 insertions, 4 deletions
@@ -770,12 +770,18 @@ MFENCE void \3\x0F\xAE\xF0 X64,AMD MONITOR void \3\x0F\x01\xC8 PRESCOTT MONITOR reg_eax,reg_ecx,reg_edx \3\x0F\x01\xC8 PRESCOTT,ND MONITOR reg_rax,reg_ecx,reg_edx \3\x0F\x01\xC8 X64,ND -MOV mem,reg_sreg \1\x8C\101 8086,SM +MOV mem,reg_sreg \1\x8C\101 8086,SW MOV reg16,reg_sreg \320\1\x8C\101 8086 MOV reg32,reg_sreg \321\1\x8C\101 386 -MOV reg_sreg,mem \1\x8E\110 8086,SM -MOV reg_sreg,reg16 \1\x8E\110 8086 -MOV reg_sreg,reg32 \1\x8E\110 386 +MOV reg64,reg_sreg \323\1\x8C\101 X64,OPT,ND +MOV rm64,reg_sreg \324\1\x8C\101 X64 +MOV reg_sreg,mem \1\x8E\110 8086,SW +MOV reg_sreg,reg16 \1\x8E\110 8086,OPT,ND +MOV reg_sreg,reg32 \1\x8E\110 386,OPT,ND +MOV reg_sreg,reg64 \323\1\x8E\110 X64,OPT,ND +MOV reg_sreg,reg16 \320\1\x8E\110 8086 +MOV reg_sreg,reg32 \321\1\x8E\110 386 +MOV reg_sreg,rm64 \324\1\x8E\110 X64 MOV reg_al,mem_offs \1\xA0\45 8086,SM MOV reg_ax,mem_offs \320\1\xA1\45 8086,SM MOV reg_eax,mem_offs \321\1\xA1\45 386,SM diff --git a/test/sreg.asm b/test/sreg.asm new file mode 100644 index 00000000..11449a50 --- /dev/null +++ b/test/sreg.asm @@ -0,0 +1,65 @@ + bits 64 + mov es,rax + mov ss,rax + mov ds,rax + mov fs,rax + mov gs,rax + mov es,eax + mov ss,eax + mov ds,eax + mov fs,eax + mov gs,eax + mov es,ax + mov ss,ax + mov ds,ax + mov fs,ax + mov gs,ax + mov es,[rsi] + mov ss,[rsi] + mov ds,[rsi] + mov fs,[rsi] + mov gs,[rsi] + mov es,word [rsi] + mov ss,word [rsi] + mov ds,word [rsi] + mov fs,word [rsi] + mov gs,word [rsi] + mov es,qword [rsi] + mov ss,qword [rsi] + mov ds,qword [rsi] + mov fs,qword [rsi] + mov gs,qword [rsi] + mov rax,es + mov rax,cs + mov rax,ss + mov rax,ds + mov rax,fs + mov rax,gs + mov eax,es + mov eax,ss + mov eax,ds + mov eax,fs + mov eax,fs + mov ax,es + mov ax,ss + mov ax,ds + mov ax,fs + mov ax,gs + mov [rdi],es + mov [rdi],cs + mov [rdi],ss + mov [rdi],ds + mov [rdi],fs + mov [rdi],gs + mov word [rdi],es + mov word [rdi],cs + mov word [rdi],ss + mov word [rdi],ds + mov word [rdi],fs + mov word [rdi],gs + mov qword [rdi],es + mov qword [rdi],cs + mov qword [rdi],ss + mov qword [rdi],ds + mov qword [rdi],fs + mov qword [rdi],gs |