diff options
| author | Cyrill Gorcunov <gorcunov@gmail.com> | 2010-01-03 00:09:41 +0300 |
|---|---|---|
| committer | Cyrill Gorcunov <gorcunov@gmail.com> | 2010-01-03 00:09:41 +0300 |
| commit | c09bd81ff3c23f895a7c70204a49c73743806515 (patch) | |
| tree | 2ea60f5d74f5a423fef9c22bc3b1d39faf53fe01 | |
| parent | 3b4c769d998445727a6b8e77c949ae469c43281e (diff) | |
| download | nasm-c09bd81ff3c23f895a7c70204a49c73743806515.tar.gz | |
BR2924583: fix FMA4 instructions
nasm64developer reported that VFNMADDSD and VFNMADDSS
have "m" and "s" operands swapped in instruction templates
file.
Reported-by: nasm64developer <nasm64developer@users.sf.net>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| -rw-r--r-- | insns.dat | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -2884,10 +2884,10 @@ VFNMADDPS xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm: vex.m3.w1.nds.l0.p1 78 /r /is4] VFNMADDPS ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm: vex.m3.w1.nds.l1.p1 78 /r /is4] AMD,SSE5 VFNMADDSD xmmreg,xmmreg*,xmmrm64,xmmreg [rvms: vex.m3.w0.nds.l0.p1 7b /r /is4] AMD,SSE5 -VFNMADDSD xmmreg,xmmreg*,xmmreg,xmmrm64 [rvms: vex.m3.w1.nds.l0.p1 7b /r /is4] AMD,SSE5 +VFNMADDSD xmmreg,xmmreg*,xmmreg,xmmrm64 [rvsm: vex.m3.w1.nds.l0.p1 7b /r /is4] AMD,SSE5 VFNMADDSS xmmreg,xmmreg*,xmmrm32,xmmreg [rvms: vex.m3.w0.nds.l0.p1 7a /r /is4] AMD,SSE5 -VFNMADDSS xmmreg,xmmreg*,xmmreg,xmmrm32 [rvms: vex.m3.w1.nds.l0.p1 7a /r /is4] AMD,SSE5 +VFNMADDSS xmmreg,xmmreg*,xmmreg,xmmrm32 [rvsm: vex.m3.w1.nds.l0.p1 7a /r /is4] AMD,SSE5 VFNMSUBPD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: vex.m3.w0.nds.l0.p1 7d /r /is4] AMD,SSE5 VFNMSUBPD ymmreg,ymmreg*,ymmrm256,ymmreg [rvms: vex.m3.w0.nds.l1.p1 7d /r /is4] AMD,SSE5 |