diff options
| author | H. Peter Anvin <hpa@zytor.com> | 2002-04-30 21:06:59 +0000 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2002-04-30 21:06:59 +0000 |
| commit | 852c3eecb47943ef12b87ada21c143c478fe9c71 (patch) | |
| tree | b96ac5a24d8939d13d5c30e286815093a22072c6 | |
| parent | dce1e2f795dea9eedb05a1eea1f4c0f3a443b452 (diff) | |
| download | nasm-852c3eecb47943ef12b87ada21c143c478fe9c71.tar.gz | |
NASM 0.98.24nasm-0.98.24
| -rw-r--r-- | doc/nasmdoc.src | 5016 | ||||
| -rw-r--r-- | nasm.h | 2 |
2 files changed, 3851 insertions, 1167 deletions
diff --git a/doc/nasmdoc.src b/doc/nasmdoc.src index cabeff5f..8918e714 100644 --- a/doc/nasmdoc.src +++ b/doc/nasmdoc.src @@ -4,19 +4,24 @@ \# \IR{-D} \c{-D} option \IR{-E} \c{-E} option +\IR{-F} \c{-F} option \IR{-I} \c{-I} option +\IR{-M} \c{-M} option +\IR{-On} \c{-On} option \IR{-P} \c{-P} option \IR{-U} \c{-U} option \IR{-a} \c{-a} option \IR{-d} \c{-d} option \IR{-e} \c{-e} option \IR{-f} \c{-f} option +\IR{-g} \c{-g} option \IR{-i} \c{-i} option \IR{-l} \c{-l} option \IR{-o} \c{-o} option \IR{-p} \c{-p} option \IR{-s} \c{-s} option \IR{-u} \c{-u} option +\IR{-v} \c{-v} option \IR{-w} \c{-w} option \IR{!=} \c{!=} operator \IR{$ here} \c{$} Here token @@ -180,46 +185,49 @@ Object File Format \# \IC{16-bit mode, versus 32-bit mode}{32-bit mode, versus 16-bit mode} \# \IC{c symbol names}{symbol names, in C} + \C{intro} Introduction \H{whatsnasm} What Is NASM? The Netwide Assembler, NASM, is an 80x86 assembler designed for portability and modularity. It supports a range of object file -formats, including Linux \c{a.out} and ELF, NetBSD/FreeBSD, COFF, -Microsoft 16-bit OBJ and Win32. It will also output plain binary -files. Its syntax is designed to be simple and easy to understand, -similar to Intel's but less complex. It supports Pentium, P6 and MMX -opcodes, and has macro capability. +formats, including Linux \c{a.out} and \c{ELF}, \c{NetBSD/FreeBSD}, +\c{COFF}, Microsoft 16-bit \c{OBJ} and \c{Win32}. It will also output +plain binary files. Its syntax is designed to be simple and easy to +understand, similar to Intel's but less complex. It supports \c{Pentium}, +\c{P6}, \c{MMX}, \c{3DNow!}, \c{SSE} and \c{SSE2} opcodes, and has +macro capability. + \S{yaasm} Why Yet Another Assembler? The Netwide Assembler grew out of an idea on \i\c{comp.lang.asm.x86} (or possibly \i\c{alt.lang.asm} - I forget which), which was -essentially that there didn't seem to be a good free x86-series +essentially that there didn't seem to be a good \e{free} x86-series assembler around, and that maybe someone ought to write one. \b \i\c{a86} is good, but not free, and in particular you don't get any -32-bit capability until you pay. It's DOS only, too. +32-bit capability until you pay. It's \c{DOS} only, too. -\b \i\c{gas} is free, and ports over DOS and Unix, but it's not very good, -since it's designed to be a back end to \i\c{gcc}, which always feeds -it correct code. So its error checking is minimal. Also, its syntax -is horrible, from the point of view of anyone trying to actually -\e{write} anything in it. Plus you can't write 16-bit code in it -(properly). +\b \i\c{gas} is free, and ports over \c{DOS} and \c{Unix}, but it's not +very good, since it's designed to be a back end to \i\c{gcc}, which +always feeds it correct code. So its error checking is minimal. Also, +its syntax is horrible, from the point of view of anyone trying to +actually \e{write} anything in it. Plus you can't write 16-bit code in +it (properly). -\b \i\c{as86} is Linux-specific, and (my version at least) doesn't seem to -have much (or any) documentation. +\b \i\c{as86} is \c{Linux-specific}, and (my version at least) doesn't +seem to have much (or any) documentation. \b \i{MASM} isn't very good, and it's expensive, and it runs only under -DOS. +\c{DOS}. -\b \i{TASM} is better, but still strives for \i{MASM} compatibility, which -means millions of directives and tons of red tape. And its syntax is -essentially \i{MASM}'s, with the contradictions and quirks that entails -(although it sorts out some of those by means of Ideal mode). It's -expensive too. And it's DOS-only. +\b \i{TASM} is better, but still strives for \i{MASM} compatibility, +which means millions of directives and tons of red tape. And its syntax +is essentially \i{MASM}'s, with the contradictions and quirks that +entails (although it sorts out some of those by means of Ideal mode). +It's expensive too. And it's \c{DOS-only}. So here, for your coding pleasure, is NASM. At present it's still in prototype stage - we don't promise that it can outperform @@ -229,49 +237,55 @@ on (and thanks to the many people who've done this already! You all know who you are), and we'll improve it out of all recognition. Again. + \S{legal} Licence Conditions Please see the file \c{Licence}, supplied as part of any NASM distribution archive, for the \i{licence} conditions under which you may use NASM. + \H{contact} Contact Information -The current version of NASM (since 0.98) are maintained by H. Peter -Anvin, \W{mailto:hpa@zytor.com}\c{hpa@zytor.com}. If you want to report -a bug, please read \k{bugs} first. +The current version of NASM (since about 0.98.08) are maintained by a +team of developers, accessible through the \c{nasm-devel} mailing list +(see below for the link). +If you want to report a bug, please read \k{bugs} first. NASM has a \i{WWW page} at -\W{http://www.cryogen.com/Nasm}\c{http://www.cryogen.com/Nasm}. +\W{http://www.web-sites.co.uk/nasm}\c{http://www.web-sites.co.uk/nasm}. The original authors are \i{e\-mail}able as -\W{mailto:jules@earthcorp.com}\c{jules@earthcorp.com} and +\W{mailto:jules@dsf.org.uk}\c{jules@dsf.org.uk} and \W{mailto:anakin@pobox.com}\c{anakin@pobox.com}. +The latter is no longer involved in the development team. + +\i{New releases} of NASM are uploaded to the official site +\W{http://www.web-sites.co.uk/nasm}\c{http://www.web-sites.co.uk/nasm}, +and to +\W{ftp://ftp.kernel.org/pub/software/devel/nasm/}\i\c{ftp.kernel.org} +and +\W{ftp://ibiblio.org/pub/Linux/devel/lang/assemblers/}\i\c{ibiblio.org}. +\# \W{ftp://ftp.simtel.net/pub/simtelnet/msdos/asmutl/}\i\c{ftp.simtel.net} +\# and +\# \W{ftp://ftp.coast.net/coast/msdos/asmutil/}\i\c{ftp.coast.net}. -\i{New releases} of NASM are uploaded to -\W{ftp://ftp.kernel.org/pub/software/devel/nasm/}\i\c{ftp.kernel.org}, -\W{ftp://sunsite.unc.edu/pub/Linux/devel/lang/assemblers/}\i\c{sunsite.unc.edu}, -\W{ftp://ftp.simtel.net/pub/simtelnet/msdos/asmutl/}\i\c{ftp.simtel.net} -and -\W{ftp://ftp.coast.net/coast/msdos/asmutil/}\i\c{ftp.coast.net}. Announcements are posted to \W{news:comp.lang.asm.x86}\i\c{comp.lang.asm.x86}, -\W{news:alt.lang.asm}\i\c{alt.lang.asm}, -\W{news:comp.os.linux.announce}\i\c{comp.os.linux.announce} and -\W{news:comp.archives.msdos.announce}\i\c{comp.archives.msdos.announce} -(the last one is done automagically by uploading to -\W{ftp://ftp.simtel.net/pub/simtelnet/msdos/asmutl/}\c{ftp.simtel.net}). - -If you don't have Usenet access, or would rather be informed by -\i{e\-mail} when new releases come out, you can subscribe to the -\c{nasm-announce} email list by sending an email containing the line -\c{subscribe nasm-announce} to -\W{mailto:majordomo@linux.kernel.org}\c{majordomo@linux.kernel.org}. - -If you want information about NASM beta releases, please subscribe to -the \c{nasm-beta} email list by sending an email containing the line -\c{subscribe nasm-beta} to -\W{mailto:majordomo@linux.kernel.org}\c{majordomo@linux.kernel.org}. +\W{news:alt.lang.asm}\i\c{alt.lang.asm} and +\W{news:comp.os.linux.announce}\i\c{comp.os.linux.announce} +\# and +\# \W{news:comp.archives.msdos.announce}\i\c{comp.archives.msdos.announce} +\# (the last one is done automagically by uploading to +\# \W{ftp://ftp.simtel.net/pub/simtelnet/msdos/asmutl/}\c{ftp.simtel.net}). + +If you want information about NASM beta releases, and the current +development status, please subscribe to the \i\c{nasm-devel} email lists +by registering at +\W{http://groups.yahoo.com/group/nasm-devel}\c{http://groups.yahoo.com/group/nasm-devel} +and +\W{http://www.pairlist.net/mailman/listinfo/nasm-devel}\c{http://www.pairlist.net/mailman/listinfo/nasm-devel} + \H{install} Installation @@ -279,21 +293,21 @@ the \c{nasm-beta} email list by sending an email containing the line Once you've obtained the \i{DOS archive} for NASM, \i\c{nasmXXX.zip} (where \c{XXX} denotes the version number of NASM contained in the -archive), unpack it into its own directory (for example -\c{c:\\nasm}). +archive), unpack it into its own directory (for example \c{c:\\nasm}). The archive will contain four executable files: the NASM executable files \i\c{nasm.exe} and \i\c{nasmw.exe}, and the NDISASM executable files \i\c{ndisasm.exe} and \i\c{ndisasmw.exe}. In each case, the -file whose name ends in \c{w} is a \i{Win32} executable, designed to -run under \i{Windows 95} or \i{Windows NT} Intel, and the other one -is a 16-bit \i{DOS} executable. +file whose name ends in \c{w} is a \I{Win32}\c{Win32} executable, +designed to run under \I{Windows 95}\c{Windows 95} or \I{Windows NT} +\c{Windows NT} Intel, and the other one is a 16-bit \I{DOS}\c{DOS} +executable. The only file NASM needs to run is its own executable, so copy (at least) one of \c{nasm.exe} and \c{nasmw.exe} to a directory on your PATH, or alternatively edit \i\c{autoexec.bat} to add the \c{nasm} directory to your \i\c{PATH}. (If you're only installing the -Win32 version, you may wish to rename it to \c{nasm.exe}.) +\c{Win32} version, you may wish to rename it to \c{nasm.exe}.) That's it - NASM is installed. You don't need the \c{nasm} directory to be present to run NASM (unless you've added it to your \c{PATH}), @@ -303,8 +317,7 @@ want to keep the documentation or test programs. If you've downloaded the \i{DOS source archive}, \i\c{nasmXXXs.zip}, the \c{nasm} directory will also contain the full NASM \i{source code}, and a selection of \i{Makefiles} you can (hopefully) use to -rebuild your copy of NASM from scratch. The file \c{Readme} lists the -various Makefiles and which compilers they work with. +rebuild your copy of NASM from scratch. Note that the source files \c{insnsa.c}, \c{insnsd.c}, \c{insnsi.h} and \c{insnsn.c} are automatically generated from the master @@ -315,9 +328,10 @@ files, you will need to rebuild them (and hence, will need a Perl interpreter) if you change \c{insns.dat}, \c{standard.mac} or the documentation. It is possible future source distributions may not include these files at all. Ports of \i{Perl} for a variety of -platforms, including DOS and Windows, are available from +platforms, including \c{DOS} and \c{Windows}, are available from \W{http://www.cpan.org/ports/}\i{www.cpan.org}. + \S{instdos} Installing NASM under \i{Unix} Once you've obtained the \i{Unix source archive} for NASM, @@ -340,7 +354,7 @@ Alternatively, you can give options such as \c{--prefix} to the \c{configure} script (see the file \i\c{INSTALL} for more details), or install the programs yourself. -NASM also comes with a set of utilities for handling the RDOFF +NASM also comes with a set of utilities for handling the \c{RDOFF} custom object-file format, which are in the \i\c{rdoff} subdirectory of the NASM archive. You can build these with \c{make rdf} and install them with \c{make rdf_install}, if you want them. @@ -350,6 +364,7 @@ compile by using the fall-back Unix makefile \i\c{Makefile.unx}. Copy or rename that file to \c{Makefile} and try typing \c{make}. There is also a \c{Makefile.unx} file in the \c{rdoff} subdirectory. + \C{running} Running NASM \H{syntax} NASM \i{Command-Line} Syntax @@ -362,7 +377,7 @@ For example, \c nasm -f elf myfile.asm -will assemble \c{myfile.asm} into an ELF object file \c{myfile.o}. And +will assemble \c{myfile.asm} into an \c{ELF} object file \c{myfile.o}. And \c nasm -f bin myfile.asm -o myfile.com @@ -382,7 +397,7 @@ This will also list the available output file formats, and what they are. If you use Linux but aren't sure whether your system is \c{a.out} or -ELF, type +\c{ELF}, type \c file nasm @@ -391,7 +406,7 @@ installed it). If it says something like \c nasm: ELF 32-bit LSB executable i386 (386 and up) Version 1 -then your system is ELF, and you should use the option \c{-f elf} +then your system is \c{ELF}, and you should use the option \c{-f elf} when you want NASM to produce Linux object files. If it says \c nasm: Linux/i386 demand-paged executable (QMAGIC) @@ -404,6 +419,7 @@ Like Unix compilers and assemblers, NASM is silent unless it goes wrong: you won't see any output at all, unless it gives error messages. + \S{opt-o} The \i\c{-o} Option: Specifying the Output File Name NASM will normally choose the name of your output file for you; @@ -430,6 +446,10 @@ an intervening space. For example: \c nasm -f bin program.asm -o program.com \c nasm -f bin driver.asm -odriver.sys +Note that this is a small o, and is different from a capital O , which +is used to specify the number of optimisation passes required. See \k{opt-On}. + + \S{opt-f} The \i\c{-f} Option: Specifying the \i{Output File Format} If you do not supply the \c{-f} option to NASM, it will choose an @@ -442,7 +462,8 @@ Like \c{-o}, the intervening space between \c{-f} and the output file format is optional; so \c{-f elf} and \c{-felf} are both valid. A complete list of the available output file formats can be given by -issuing the command \i\c{nasm -h}. +issuing the command \i\c{nasm -hf}. + \S{opt-l} The \i\c{-l} Option: Generating a \i{Listing File} @@ -456,9 +477,39 @@ right. For example: \c nasm -f elf myfile.asm -l myfile.lst + +\S{opt-M} The \i\c{-M} Option: Generate \i{Makefile Dependencies}. + +This option can be used to generate makefile dependencies on stdout. +This can be redirected to a file for further processing. For example: + +\c NASM -M myfile.asm > myfile.dep + + +\S{opt-F} The \i\c{-F} Option: Selecting a \i{Debugging Format} + +This option can be used to select a debugging format for the output file. +The syntax is the same as for the -f option, except that it produces +output in a debugging format. + +A complete list of the available debug file formats for an output format +can be seen by issuing the command \i\c{nasm -f <format> -y}. + +This option is not built into NASM by default. For information on how +to enable it when building from the sources, see \k{dbgfmt} + + +\S{opt-g} The \i\c{-g} Option: Enabling \i{Debug Information}. + +This option can be used to generate debugging information in the specified +format. + +See \k{opt-F} for more information. + + \S{opt-E} The \i\c{-E} Option: Send Errors to a File -Under MS-\i{DOS} it can be difficult (though there are ways) to +Under \I{DOS}\c{MS-DOS} it can be difficult (though there are ways) to redirect the standard-error output of a program to a file. Since NASM usually produces its warning and \i{error messages} on \i\c{stderr}, this can make it hard to capture the errors if (for @@ -471,10 +522,11 @@ the errors into a file by typing \c nasm -E myfile.err -f obj myfile.asm + \S{opt-s} The \i\c{-s} Option: Send Errors to \i\c{stdout} The \c{-s} option redirects \i{error messages} to \c{stdout} rather -than \c{stderr}, so it can be redirected under MS-\i{DOS}. To +than \c{stderr}, so it can be redirected under \I{DOS}\c{MS-DOS}. To assemble the file \c{myfile.asm} and pipe its output to the \c{more} program, you can type: @@ -482,6 +534,7 @@ program, you can type: See also the \c{-E} option, \k{opt-E}. + \S{opt-i} The \i\c{-i}\I\c{-I} Option: Include File Search Directories When NASM sees the \i\c{%include} directive in a source file (see @@ -514,6 +567,7 @@ more \c{-i} directives in the \c{NASM} environment variable (see For Makefile compatibility with many C compilers, this option can also be specified as \c{-I}. + \S{opt-p} The \i\c{-p}\I\c{-P} Option: \I{pre-including files}Pre-Include a File \I\c{%include}NASM allows you to specify files to be @@ -528,6 +582,7 @@ directive \c{%include "myinc.inc"} at the start of the file. For consistency with the \c{-I}, \c{-D} and \c{-U} options, this option can also be specified as \c{-P}. + \S{opt-d} The \i\c{-d}\I\c{-D} Option: \I{pre-defining macros} Pre-Define a Macro \I\c{%define}Just as the \c{-p} option gives an alternative to placing @@ -550,6 +605,7 @@ options} which are then tested using \c{%ifdef}, for example For Makefile compatibility with many C compilers, this option can also be specified as \c{-D}. + \S{opt-u} The \i\c{-u}\I\c{-U} Option: \I{Undefining macros} Undefine a Macro \I\c{%undef}The \c{-u} option undefines a macro that would otherwise @@ -567,6 +623,7 @@ point in a Makefile. For Makefile compatibility with many C compilers, this option can also be specified as \c{-U}. + \S{opt-e} The \i\c{-e} Option: Preprocess Only NASM allows the \i{preprocessor} to be run on its own, up to a @@ -584,6 +641,7 @@ which depend on the values of symbols: so code such as will cause an error in \i{preprocess-only mode}. + \S{opt-a} The \i\c{-a} Option: Don't Preprocess At All If NASM is being used as the back end to a compiler, it might be @@ -593,10 +651,42 @@ and increase compilation speeds. The \c{-a} option, requiring no argument, instructs NASM to replace its powerful \i{preprocessor} with a \i{stub preprocessor} which does nothing. + +\S{opt-On} The \i\c{-On} Option: Specifying \i{Multipass Optimization}. + +NASM defaults to being a two pass assembler. This means that if you +have a complex source file which needs more than 2 passes to assemble +correctly, you have to tell it. + +Using the \c{-O} option, you can tell NASM to carry out multiple passes. +The syntax is: + +\b \c{-O0} strict two-pass assembly, JMP and Jcc are handled more + like v0.98, except that backward JMPs are short, if possible. + Immediate operands take their long forms if a short form is + not specified. + +\b \c{-O1} strict two-pass assembly, but forward branches are assembled + with code guaranteed to reach; may produce larger code than + -O0, but will produce successful assembly more often if + branch offset sizes are not specified. + Additionally, immediate operands which will fit in a signed byte + are optimised, unless the long form is specified. + +\b \c{-On} multi-pass optimization, minimize branch offsets; also will + minimize signed immediate bytes, overriding size specification. + If 2 <= n <= 3, then there are 5 * n passes, otherwise there + are n passes. + + +Note that this is a capital O, and is different from a small o, which +is used to specify the output format. See \k{opt-o}. + + \S{opt-t} The \i\c{-t} option: Enable TASM Compatibility Mode -NASM includes a limited form of compatibility with Borland's TASM. -When NASM's -t option is used, the following changes are made: +NASM includes a limited form of compatibility with Borland's \c{TASM}. +When NASM's \c{-t} option is used, the following changes are made: \b local labels may be prefixed with \c{@@} instead of \c{.} @@ -612,20 +702,22 @@ Note that you lose the ability to override the default address type for the instruction. \b \c{%arg} preprocessor directive is supported which is similar to -TASM's ARG directive. +TASM's \c{ARG} directive. \b \c{%local} preprocessor directive \b \c{%stacksize} preprocessor directive -\b unprefixed forms of some directives supported (arg, elif, else, -endif, if, ifdef, ifdifi, ifndef, include, local) +\b unprefixed forms of some directives supported (\c{arg}, \c{elif}, +\c{else}, \c{endif}, \c{if}, \c{ifdef}, \c{ifdifi}, \c{ifndef}, +\c{include}, \c{local}) \b more... For more information on the directives, see the section on TASM Compatiblity preprocessor directives in \k{tasmcompat}. - + + \S{opt-w} The \i\c{-w} Option: Enable or Disable Assembly \i{Warnings} NASM can observe many conditions during the course of assembly which @@ -661,6 +753,15 @@ don't fit in 32 bits (for example, it's easy to type one too many Fs and produce \c{0x7ffffffff} by mistake). This warning class is enabled by default. + +\S{opt-v} The \i\c{-v} Option: Display \i{Version} Info + +Typing \c{NASM -v} will display the version of NASM which you are using, +and the date on which it was compiled. + +You will need the version number if you report a bug. + + \S{nasmenv} The \c{NASM} \i{Environment} Variable If you define an environment variable called \c{NASM}, the program @@ -683,6 +784,7 @@ character} for options. So setting the \c{NASM} variable to the value \c{!-s!-ic:\\nasmlib} is equivalent to setting it to \c{-s -ic:\\nasmlib}, but \c{!-dNAME="my name"} will work. + \H{qstart} \i{Quick Start} for \i{MASM} Users If you're used to writing programs with MASM, or with \i{TASM} in @@ -691,15 +793,17 @@ attempts to outline the major differences between MASM's syntax and NASM's. If you're not already used to MASM, it's probably worth skipping this section. + \S{qscs} NASM Is \I{case sensitivity}Case-Sensitive One simple difference is that NASM is case-sensitive. It makes a difference whether you call your label \c{foo}, \c{Foo} or \c{FOO}. -If you're assembling to DOS or OS/2 \c{.OBJ} files, you can invoke -the \i\c{UPPERCASE} directive (documented in \k{objfmt}) to ensure -that all symbols exported to other code modules are forced to be -upper case; but even then, \e{within} a single module, NASM will -distinguish between labels differing only in case. +If you're assembling to \c{DOS} or \c{OS/2} \c{.OBJ} files, you can +invoke the \i\c{UPPERCASE} directive (documented in \k{objfmt}) to +ensure that all symbols exported to other code modules are forced +to be upper case; but even then, \e{within} a single module, NASM +will distinguish between labels differing only in case. + \S{qsbrackets} NASM Requires \i{Square Brackets} For \i{Memory References} @@ -710,7 +814,7 @@ and tell what opcode is generated by it. You can't do this in MASM: if you declare, for example, \c foo equ 1 -\c bar dw 2 +\c bar dw 2 then the two lines of code @@ -751,6 +855,7 @@ portion outside square brackets and another portion inside. The correct syntax for the above is \c{mov ax,[table+bx]}. Likewise, \c{mov ax,es:[di]} is wrong and \c{mov ax,[es:di]} is right. + \S{qstypes} NASM Doesn't Store \i{Variable Types} NASM, by design, chooses not to remember the types of variables you @@ -767,6 +872,7 @@ but only supports the forms such as \c{LODSB}, \c{MOVSW}, and \c{SCASD}, which explicitly specify the size of the components of the strings being manipulated. + \S{qsassume} NASM Doesn't \i\c{ASSUME} As part of NASM's drive for simplicity, it also does not support the @@ -774,6 +880,7 @@ As part of NASM's drive for simplicity, it also does not support the choose to put in your segment registers, and will never \e{automatically} generate a \i{segment override} prefix. + \S{qsmodel} NASM Doesn't Support \i{Memory Models} NASM also does not have any directives to support different 16-bit @@ -787,6 +894,7 @@ necessary when calling \e{external} functions, and must also keep track of which external variable definitions are far and which are near. + \S{qsfpu} \i{Floating-Point} Differences NASM uses different names to refer to floating-point registers from @@ -799,6 +907,7 @@ As of version 0.96, NASM now treats the instructions with The idiosyncratic treatment employed by 0.95 and earlier was based on a misunderstanding by the authors. + \S{qsother} Other Differences For historical reasons, NASM uses the keyword \i\c{TWORD} where MASM @@ -816,6 +925,7 @@ In addition to all of this, macros and directives work completely differently to MASM. See \k{preproc} and \k{directive} for further details. + \C{lang} The NASM Language \H{syntax} Layout of a NASM Source Line @@ -897,6 +1007,7 @@ Almost any floating-point instruction that references memory must use one of the prefixes \i\c{DWORD}, \i\c{QWORD} or \i\c{TWORD} to indicate what size of \i{memory operand} it refers to. + \H{pseudop} \i{Pseudo-Instructions} Pseudo-instructions are things which, though not real x86 machine @@ -907,6 +1018,7 @@ pseudo-instructions are \i\c{DB}, \i\c{DW}, \i\c{DD}, \i\c{DQ} and \i\c{RESW}, \i\c{RESD}, \i\c{RESQ} and \i\c{REST}, the \i\c{INCBIN} command, the \i\c{EQU} command, and the \i\c{TIMES} prefix. + \S{db} \c{DB} and friends: Declaring Initialised Data \i\c{DB}, \i\c{DW}, \i\c{DD}, \i\c{DQ} and \i\c{DT} are used, much @@ -930,6 +1042,7 @@ be invoked in a wide range of ways: \c{DQ} and \c{DT} do not accept \i{numeric constants} or string constants as operands. + \S{resb} \c{RESB} and friends: Declaring \i{Uninitialised} Data \i\c{RESB}, \i\c{RESW}, \i\c{RESD}, \i\c{RESQ} and \i\c{REST} are @@ -948,6 +1061,7 @@ For example: \c wordvar: resw 1 ; reserve a word \c realarray resq 10 ; array of ten reals + \S{incbin} \i\c{INCBIN}: Including External \i{Binary Files} \c{INCBIN} is borrowed from the old Amiga assembler \i{DevPac}: it @@ -961,6 +1075,7 @@ these three ways: \c incbin "file.dat",1024,512 ; skip the first 1024, and \c ; actually include at most 512 + \S{equ} \i\c{EQU}: Defining Constants \c{EQU} defines a symbol to a given constant value: when \c{EQU} is @@ -981,6 +1096,7 @@ and using the value of \c{$} at the point of reference. Note that the operand to an \c{EQU} is also a \i{critical expression} (\k{crit}). + \S{times} \i\c{TIMES}: \i{Repeating} Instructions or Data The \c{TIMES} prefix causes the instruction to be assembled multiple @@ -1016,6 +1132,7 @@ allows the argument to \c{TIMES} to contain expressions such as \c{64-$+buffer} as above. To repeat more than one line of code, or a complex macro, use the preprocessor \i\c{%rep} directive. + \H{effaddr} Effective Addresses An \i{effective address} is any operand to an instruction which @@ -1076,11 +1193,13 @@ fact, it will also split \c{[eax*2+offset]} into the \c{NOSPLIT} keyword: \c{[nosplit eax*2]} will force \c{[eax*2+0]} to be generated literally. + \H{const} \i{Constants} NASM understands four different types of constant: numeric, character, string and floating-point. + \S{numconst} \i{Numeric Constants} A numeric constant is simply a number. NASM allows you to specify @@ -1101,6 +1220,7 @@ Some examples: \c mov ax,777q ; octal \c mov ax,10010011b ; binary + \S{chrconst} \i{Character Constants} A character constant consists of up to four characters enclosed in @@ -1120,6 +1240,7 @@ memory, it would read \c{abcd} rather than \c{dcba}. This is also the sense of character constants understood by the Pentium's \i\c{CPUID} instruction (see \k{insCPUID}). + \S{strconst} String Constants String constants are only acceptable to some pseudo-instructions, @@ -1146,6 +1267,7 @@ the same effect as \c{db 'a'}, which would be silly. Similarly, three-character or four-character constants are treated as strings when they are operands to \c{dw}. + \S{fltconst} \I{floating-point, constants}Floating-Point Constants \i{Floating-point} constants are acceptable only as arguments to @@ -1174,6 +1296,7 @@ do floating arithmetic it would have to include its own complete set of floating-point routines, which would significantly increase the size of the assembler for very little benefit. + \H{expr} \i{Expressions} Expressions in NASM are similar in syntax to those in C. @@ -1197,20 +1320,24 @@ into the section you are by using \c{($-$$)}. The arithmetic \i{operators} provided by NASM are listed here, in increasing order of \i{precedence}. + \S{expor} \i\c{|}: \i{Bitwise OR} Operator The \c{|} operator gives a bitwise OR, exactly as performed by the \c{OR} machine instruction. Bitwise OR is the lowest-priority arithmetic operator supported by NASM. + \S{expxor} \i\c{^}: \i{Bitwise XOR} Operator \c{^} provides the bitwise XOR operation. + \S{expand} \i\c{&}: \i{Bitwise AND} Operator \c{&} provides the bitwise AND operation. + \S{expshift} \i\c{<<} and \i\c{>>}: \i{Bit Shift} Operators \c{<<} gives a bit-shift to the left, just as it does in C. So \c{5<<3} @@ -1219,12 +1346,14 @@ right; in NASM, such a shift is \e{always} unsigned, so that the bits shifted in from the left-hand end are filled with zero rather than a sign-extension of the previous highest bit. + \S{expplmi} \I{+ opaddition}\c{+} and \I{- opsubtraction}\c{-}: \i{Addition} and \i{Subtraction} Operators The \c{+} and \c{-} operators do perfectly ordinary addition and subtraction. + \S{expmul} \i\c{*}, \i\c{/}, \i\c{//}, \i\c{%} and \i\c{%%}: \i{Multiplication} and \i{Division} @@ -1241,6 +1370,7 @@ Since the \c{%} character is used extensively by the macro \i{preprocessor}, you should ensure that both the signed and unsigned modulo operators are followed by white space wherever they appear. + \S{expmul} \i{Unary Operators}: \I{+ opunary}\c{+}, \I{- opunary}\c{-}, \i\c{~} and \i\c{SEG} @@ -1251,6 +1381,7 @@ computes the \i{one's complement} of its operand, and \c{SEG} provides the \i{segment address} of its operand (explained in more detail in \k{segwrt}). + \H{segwrt} \i\c{SEG} and \i\c{WRT} When writing large 16-bit programs, which must be split into @@ -1305,6 +1436,7 @@ must code NASM supports no convenient synonym for this, though you can always invent one using the macro processor. + \H{crit} \i{Critical Expressions} A limitation of NASM is that it is a \i{two-pass assembler}; unlike @@ -1381,6 +1513,7 @@ problem can be solved by defining \c{offset} before using it, or by forcing byte size in the effective address by coding \c{[byte ebx+offset]}. + \H{locallab} \i{Local Labels} NASM gives special treatment to symbols beginning with a \i{period}. @@ -1437,6 +1570,7 @@ NASM has the capacity to define other special symbols beginning with a double period: for example, \c{..start} is used to specify the entry point in the \c{obj} output format (see \k{dotdotstart}). + \C{preproc} The NASM \i{Preprocessor} NASM contains a powerful \i{macro processor}, which supports @@ -1445,6 +1579,7 @@ conditional assembly, multi-level file inclusion, two forms of macro extra macro power. Preprocessor directives all begin with a \c{%} sign. + \H{slmacro} \i{Single-Line Macros} \S{define} The Normal Way: \I\c{%idefine}\i\c{%define} @@ -1526,6 +1661,7 @@ when defining single-line macros with \c{%assign} (see \k{assign}). You can \i{pre-define} single-line macros using the `-d' option on the NASM command line: see \k{opt-d}. + \S{undef} Undefining macros: \i\c{%undef} Single-line macros can be removed with the \c{%undef} command. For @@ -1542,6 +1678,7 @@ Macros that would otherwise be pre-defined can be undefined on the command-line using the `-u' option on the NASM command line: see \k{opt-u}. + \S{assign} \i{Preprocessor Variables}: \i\c{%assign} An alternative way to define single-line macros is by means of the @@ -1570,12 +1707,14 @@ The expression passed to \c{%assign} is a \i{critical expression} a relocatable reference such as a code or data address, or anything involving a register). + \H{strlen} \i{String Handling in Macros}: \i\c{%strlen} and \i\c{%substr} It's often useful to be able to handle strings in macros. NASM supports two simple string handling macro operators from which more complex operations can be constructed. + \S{strlen} \i{String Length}: \i\c{%strlen} The \c{%strlen} macro is like \c{%assign} macro in that it creates @@ -1596,6 +1735,7 @@ macro that expands to a string, as in the following example: As in the first case, this would result in \c{charcnt} being assigned the value of 8. + \S{substr} \i{Sub-strings}: \i\c{%substr} Individual letters in strings can be extracted using \c{%substr}. @@ -1613,6 +1753,7 @@ index is 1, not 0 and the last index is equal to the value that \c{%strlen} would assign given the same string. Index values out of range result in an empty string. + \H{mlmacro} \i{Multi-Line Macros}: \I\c{%imacro}\i\c{%macro} Multi-line macros are much more like the type of macro seen in MASM @@ -1658,6 +1799,7 @@ things like \c silly 'ab', string_ab ; string_ab: db 'ab' \c silly {13,10}, crlf ; crlf: db 13,10 + \S{mlmacover} \i{Overloading Multi-Line Macros} As with single-line macros, multi-line macros can be overloaded by @@ -1693,6 +1835,7 @@ given. The correct code will still be generated, but the assembler will give a warning. This warning can be disabled by the use of the \c{-w-macro-params} command-line option (see \k{opt-w}). + \S{maclocal} \i{Macro-Local Labels} NASM allows you to define labels within a multi-line macro @@ -1718,6 +1861,7 @@ interfering with the local label mechanism, as described in (the \c{..@} prefix, then a number, then another period) in case they interfere with macro-local labels. + \S{mlmacgre} \i{Greedy Macro Parameters} Occasionally it is useful to define a macro which lumps its entire @@ -1775,6 +1919,7 @@ definition. See \k{sectmac} for a better way to write the above macro. + \S{mlmacdef} \i{Default Macro Parameters} NASM also allows you to define a multi-line macro with a \e{range} @@ -1821,6 +1966,7 @@ The maximum parameter count can be infinite, denoted by \c{*}. In this case, of course, it is impossible to provide a \e{full} set of default parameters. Examples of this usage are shown in \k{rotate}. + \S{percent0} \i\c{%0}: \I{counting macro parameters}Macro Parameter Counter For a macro which can take a variable number of parameters, the @@ -1829,6 +1975,7 @@ number of parameters passed to the macro. This can be used as an argument to \c{%rep} (see \k{rep}) in order to iterate through all the parameters of a macro. Examples are given in \k{rotate}. + \S{rotate} \i\c{%rotate}: \i{Rotating Macro Parameters} Unix shell programmers will be familiar with the \I{shift @@ -1893,6 +2040,7 @@ This is then popped, and the arguments are rotated right again, so the second-to-last argument becomes \c{%1}. Thus the arguments are iterated through in reverse order. + \S{concat} \i{Concatenating Macro Parameters} NASM can concatenate macro parameters on to other text surrounding @@ -1942,6 +2090,7 @@ real names of macro-local labels means that the two usages \c{%\{%foo\}bar} and \c{%%foobar} would both expand to the same thing anyway; nevertheless, the capability is there.) + \S{mlmaccc} \i{Condition Codes as Macro Parameters} NASM can give special treatment to a macro parameter which contains @@ -1973,6 +2122,7 @@ the arguments \c{CXZ} and \c{ECXZ} as valid condition codes; however, \c{%-1} will report an error if passed either of these, because no inverse condition code exists. + \S{nolist} \i{Disabling Listing Expansion}\I\c{.nolist} When NASM is generating a listing file from your program, it will @@ -2010,6 +2160,7 @@ syntax of this feature looks like this: The \i\c{%else} clause is optional, as is the \i\c{%elif} clause. You can have more than one \c{%elif} clause as well. + \S{ifdef} \i\c{%ifdef}: \i{Testing Single-Line Macro Existence} Beginning a conditional-assembly block with the line \c{%ifdef @@ -2035,6 +2186,7 @@ You can test for a macro \e{not} being defined by using definitions in \c{%elif} blocks by using \i\c{%elifdef} and \i\c{%elifndef}. + \S{ifctx} \i\c{%ifctx}: \i{Testing the Context Stack} The conditional-assembly construct \c{%ifctx ctxname} will cause the @@ -2046,6 +2198,7 @@ the preprocessor's context stack has the name \c{ctxname}. As with For more details of the context stack, see \k{ctxstack}. For a sample use of \c{%ifctx}, see \k{blockif}. + \S{if} \i\c{%if}: \i{Testing Arbitrary Numeric Expressions} The conditional-assembly construct \c{%if expr} will cause the @@ -2072,6 +2225,7 @@ they always return either 0 or 1, and treat any non-zero input as 1 is zero, and 0 otherwise). The relational operators also return 1 for true and 0 for false. + \S{ifidn} \i\c{%ifidn} and \i\c{%ifidni}: \i{Testing Exact Text Identity} @@ -2099,6 +2253,7 @@ Like most other \c{%if} constructs, \c{%ifidn} has a counterpart Similarly, \c{%ifidni} has counterparts \i\c{%elifidni}, \i\c{%ifnidni} and \i\c{%elifnidni}. + \S{iftyp} \i\c{%ifid}, \i\c{%ifnum}, \i\c{%ifstr}: \i{Testing Token Types} @@ -2153,10 +2308,12 @@ single string constant, and \c{db %2} would be adequate) or more (in which case, all but the first two would be lumped together into \c{%3}, and \c{db %2,%3} would be required). -\I\c{%ifnid}\I\c{%elifid}\I\c{%elifnid}\I\c{%ifnnum}\I\c{%elifnum}\I\c{%elifnnum}\I\c{%ifnstr}\I\c{%elifstr}\I\c{%elifnstr} +\I\c{%ifnid}\I\c{%elifid}\I\c{%elifnid}\I\c{%ifnnum}\I\c{%elifnum} +\I\c{%elifnnum}\I\c{%ifnstr}\I\c{%elifstr}\I\c{%elifnstr} The usual \c{%elifXXX}, \c{%ifnXXX} and \c{%elifnXXX} versions exist for each of \c{%ifid}, \c{%ifnum} and \c{%ifstr}. + \S{pperror} \i\c{%error}: Reporting \i{User-Defined Errors} The preprocessor directive \c{%error} will cause NASM to report an @@ -2177,6 +2334,7 @@ to be assembled will be quickly warned of their mistake, rather than having to wait until the program crashes on being run and then not knowing what went wrong. + \H{rep} \i{Preprocessor Loops}\I{repeating code}: \i\c{%rep} NASM's \c{TIMES} prefix, though useful, cannot be used to invoke a @@ -2224,6 +2382,7 @@ infinite loop in the preprocessor, which (on multitasking or multi-user systems) would typically cause all the system memory to be gradually used up and other applications to start crashing. + \H{include} \i{Including Other Files} Using, once again, a very similar syntax to the C preprocessor, @@ -2258,6 +2417,7 @@ You can force a file to be included even if there is no \c{%include} directive that explicitly includes it, by using the \i\c{-p} option on the NASM command line (see \k{opt-p}). + \H{ctxstack} The \i{Context Stack} Having labels that are local to a macro definition is sometimes not @@ -2274,6 +2434,7 @@ characterised by a name. You add a new context to the stack using the \i\c{%push} directive, and remove one using \i\c{%pop}. You can define labels that are local to a particular context on the stack. + \S{pushpop} \i\c{%push} and \i\c{%pop}: \I{creating contexts}\I{removing contexts}Creating and Removing Contexts @@ -2291,6 +2452,7 @@ The directive \c{%pop}, requiring no arguments, removes the top context from the context stack and destroys it, along with any labels associated with it. + \S{ctxlocal} \i{Context-Local Labels} Just as the usage \c{%%foo} defines a label which is local to the @@ -2324,6 +2486,7 @@ If you need to define, or access, labels local to the context \e{below} the top one on the stack, you can use \I{%$$}\c{%$$foo}, or \c{%$$$foo} for the context below that, and so on. + \S{ctxdefine} \i{Context-Local Single-Line Macros} NASM also allows you to define single-line macros which are local to @@ -2335,6 +2498,7 @@ will define the single-line macro \c{%$localmac} to be local to the top context on the stack. Of course, after a subsequent \c{%push}, it can then still be accessed by the name \c{%$$localmac}. + \S{ctxrepl} \i\c{%repl}: \I{renaming contexts}Renaming a Context If you need to change the name of the top context on the stack (in @@ -2352,6 +2516,7 @@ labels. So you could replace the destructive code with the non-destructive version \c{%repl newname}. + \S{blockif} Example Use of the \i{Context Stack}: \i{Block IFs} This example makes use of almost all the context-stack features, @@ -2425,6 +2590,7 @@ pushing another context, describing the inner \c{if}, on top of the one describing the outer \c{if}; thus \c{else} and \c{endif} always refer to the last unmatched \c{if} or \c{else}. + \H{stdmac} \i{Standard Macros} NASM defines a set of standard macros, which are already defined @@ -2437,6 +2603,7 @@ implemented as macros which invoke primitive directives; these are described in \k{directive}. The rest of the standard macro set is described here. + \S{stdmacver} \i\c{__NASM_MAJOR__} and \i\c{__NASM_MINOR__}: \i{NASM Version} @@ -2446,6 +2613,7 @@ NASM} being used. So, under NASM 0.96 for example, \c{__NASM_MAJOR__} would be defined to be 0 and \c{__NASM_MINOR__} would be defined as 96. + \S{fileline} \i\c{__FILE__} and \i\c{__LINE__}: File Name and Line Number Like the C preprocessor, NASM allows the user to find out the file @@ -2474,6 +2642,7 @@ here'. You could then write a macro and then pepper your code with calls to \c{notdeadyet} until you find the crash point. + \S{struc} \i\c{STRUC} and \i\c{ENDSTRUC}: \i{Declaring Structure} Data Types The core of NASM contains no intrinsic means of defining data @@ -2527,6 +2696,7 @@ so code such as \c{mov ax,[mystruc.mt_word]} is not valid. correct syntax is \c{mov ax,[mystruc+mt_word]} or \c{mov ax,[mystruc+mytype.word]}. + \S{istruc} \i\c{ISTRUC}, \i\c{AT} and \i\c{IEND}: Declaring \i{Instances of Structures} @@ -2564,6 +2734,7 @@ line: \c db 'hello, world' \c db 13,10,0 + \S{align} \i\c{ALIGN} and \i\c{ALIGNB}: Data Alignment The \c{ALIGN} and \c{ALIGNB} macros provides a convenient way to @@ -2619,6 +2790,7 @@ boundary, for example, is a waste of effort. Again, NASM does not check that the section's alignment characteristics are sensible for the use of \c{ALIGN} or \c{ALIGNB}. + \H{tasmcompat} \i{TASM Compatible Preprocessor Directives} The following preprocessor directives may only be used when TASM @@ -2631,6 +2803,7 @@ compatibility is turned on using the \c{-t} command line switch \b\c{%local} (see \k{local}) + \S{arg} \i\c{%arg} Directive The \c{%arg} directive is used to simplify the handling of @@ -2657,6 +2830,7 @@ the value in i to the value pointed to by j_ptr and returns the sum in the ax register. See \k{pushpop} for an explanation of \c{push} and \c{pop} and the use of context stacks. + \S{stacksize} \i\c{%stacksize} Directive The \c{%stacksize} directive is used in conjunction with the @@ -2688,6 +2862,7 @@ may have been allocated by \c{ENTER}. This form is probably most useful when used in combination with the \c{%local} directive (see \k{local}). + \S{local} \i\c{%local} Directive The \c{%local} directive is used to simplify the use of local @@ -2724,6 +2899,7 @@ each \c{%local} variable declared. It then may be used in the construction of an appropriately sized ENTER instruction as shown in the example. + \C{directive} \i{Assembler Directives} NASM, though it attempts to avoid the bureaucracy of assemblers like @@ -2746,6 +2922,7 @@ order to control particular features of that file format. These \i{format-specific directives}\e{format-specific} directives are documented along with the formats that implement them, in \k{outfmt}. + \H{bits} \i\c{BITS}: Specifying Target \i{Processor Mode} The \c{BITS} directive specifies whether NASM should generate code @@ -2783,6 +2960,13 @@ The \c{BITS} directive has an exactly equivalent primitive form, \c{[BITS 16]} and \c{[BITS 32]}. The user-level form is a macro which has no function other than to call the primitive form. + +\S{USE16 & USE32} \i\c{USE16} & \i\c{USE32}: Aliases for BITS + +The `\c{USE16}' and `\c{USE32}' directives can be used in place of +`\c{BIT 16}' and `\c{BITS 32}', for compatibility with other assemblers. + + \H{section} \i\c{SECTION} or \i\c{SEGMENT}: Changing and \i{Defining Sections} @@ -2802,6 +2986,7 @@ format, by contrast, does not recognise these section names as being special, and indeed will strip off the leading period of any section name that has one. + \S{sectmac} The \i\c{__SECT__} Macro The \c{SECTION} directive is unusual in that its user-level form @@ -2846,6 +3031,7 @@ jump over the data, and also does not fail if, in a complicated \c{OBJ} format module, the user could potentially be assembling the code in any of several separate code sections. + \H{absolute} \i\c{ABSOLUTE}: Defining Absolute Labels The \c{ABSOLUTE} directive can be thought of as an alternative form @@ -2891,6 +3077,7 @@ re-used as data storage for the running TSR. The symbol `tsr_end' can be used to calculate the total size of the part of the TSR that needs to be made resident. + \H{extern} \i\c{EXTERN}: \i{Importing Symbols} from Other Modules \c{EXTERN} is similar to the MASM directive \c{EXTRN} and the C @@ -2923,6 +3110,7 @@ You can declare the same variable as \c{EXTERN} more than once: NASM will quietly ignore the second and later redeclarations. You can't declare a variable as \c{EXTERN} as well as something else, though. + \H{global} \i\c{GLOBAL}: \i{Exporting Symbols} to Other Modules \c{GLOBAL} is the other end of \c{EXTERN}: if one module declares a @@ -2952,6 +3140,7 @@ Like \c{EXTERN}, the primitive form of \c{GLOBAL} differs from the user-level form only in that it can take only one argument at a time. + \H{common} \i\c{COMMON}: Defining Common Data Areas The \c{COMMON} directive is used to declare \i\e{common variables}. @@ -2983,6 +3172,46 @@ Once again, like \c{EXTERN} and \c{GLOBAL}, the primitive form of \c{COMMON} differs from the user-level form only in that it can take only one argument at a time. + +\H{CPU} \i\c{CPU XXX}: Defining CPU Dependencies + +The \i\c{CPU} directive restricts assembly to those instructions which +are available on the specified CPU. + +Options are: + +\b\c{CPU 8086} Assemble only 8086 instruction set + +\b\c{CPU 186} Assemble instructions up to the 80186 instruction set + +\b\c{CPU 286} Assemble instructions up to the 286 instruction set + +\b\c{CPU 386} Assemble instructions up to the 386 instruction set + +\b\c{CPU 486} 486 instruction set + +\b\c{CPU 586} Pentium instruction set + +\b\c{CPU PENTIUM} Same as 586 + +\b\c{CPU 686} Pentium Pro instruction set + +\b\c{CPU PPRO} Same as 686 + +\b\c{CPU P2} Pentium II instruction set + +\b\c{CPU P3} Pentium III and Katmai instruction sets + +\b\c{CPU KATMAI} Same as P3 + +\b\c{CPU P4} Pentium 4 (Willamette) instruction set + +\b\c{CPU WILLAMETTE} Same as P4 + +All options are case insensitive. All instructions will +be selected only if they apply to the selected cpu or lower. + + \C{outfmt} \i{Output Formats} NASM is a portable assembler, designed to be able to compile on any @@ -2999,6 +3228,7 @@ format. This will be generated by removing the \i{extension} name, and substituting an extension defined by the output format. The extensions are given with each format below. + \H{binfmt} \i\c{bin}: \i{Flat-Form Binary}\I{pure binary} Output The \c{bin} format does not produce object files: it generates @@ -3029,6 +3259,7 @@ leaves your file name as it is once the original extension has been removed. Thus, the default is for NASM to assemble \c{binprog.asm} into a binary file called \c{binprog}. + \S{org} \i\c{ORG}: Binary File \i{Program Origin} The \c{bin} format provides an additional directive to the list @@ -3051,6 +3282,7 @@ offset which is added to all internal address references within the file; it does not permit any of the trickery that MASM's version does. See \k{proborg} for further comments. + \S{binseg} \c{bin} Extensions to the \c{SECTION} Directive\I{SECTION, bin extensions to} @@ -3069,6 +3301,7 @@ section start address must be forced to zero. The alignment value given may be any power of two.\I{section alignment, in bin}\I{segment alignment, in bin}\I{alignment, in bin sections} + \H{objfmt} \i\c{obj}: \i{Microsoft OMF}\I{OMF} Object Files The \c{obj} file format (NASM calls it \c{obj} rather than \c{omf} @@ -3116,6 +3349,7 @@ like \c mov ax,[ds:foo] ; this accesses `foo' \c mov [es:foo wrt data],bx ; so does this + \S{objseg} \c{obj} Extensions to the \c{SEGMENT} Directive\I{SEGMENT, obj extensions to} @@ -3178,6 +3412,7 @@ and \c{ALIGN} keywords are mutually exclusive. NASM's default segment attributes are \c{PUBLIC}, \c{ALIGN=1}, no class, no overlay, and \c{USE16}. + \S{group} \i\c{GROUP}: Defining Groups of Segments\I{segments, groups of} The \c{obj} format also allows segments to be grouped, so that a @@ -3214,6 +3449,7 @@ A group does not have to contain any segments; you can still make you are referring to. OS/2, for example, defines the special group \c{FLAT} with no segments in it. + \S{uppercase} \i\c{UPPERCASE}: Disabling Case Sensitivity in Output Although NASM itself is \i{case sensitive}, some OMF linkers are @@ -3226,6 +3462,7 @@ be written entirely in upper case if desired. \c{UPPERCASE} is used alone on a line; it requires no parameters. + \S{import} \i\c{IMPORT}: Importing DLL Symbols\I{DLL symbols, importing}\I{symbols, importing from DLLs} @@ -3248,6 +3485,7 @@ once you have imported it. For example: \c import asyncsel wsock32.dll WSAAsyncSelect + \S{export} \i\c{EXPORT}: Exporting DLL Symbols\I{DLL symbols, exporting}\I{symbols, exporting from DLLs} @@ -3292,16 +3530,18 @@ For example: \c export myfunc myfunc 1234 ; export by ordinal \c export myfunc myfunc resident parm=23 nodata + \S{dotdotstart} \i\c{..start}: Defining the \i{Program Entry Point} -OMF linkers require exactly one of the object files being linked to +\c{OMF} linkers require exactly one of the object files being linked to define the program entry point, where execution will begin when the program is run. If the object file that defines the entry point is assembled using NASM, you specify the entry point by declaring the special symbol \c{..start} at the point where you wish execution to begin. + \S{objextern} \c{obj} Extensions to the \c{EXTERN} Directive\I{EXTERN, obj extensions to} @@ -3341,6 +3581,7 @@ to make externals appear to be relative to any group or segment in your program. It can also be applied to common variables: see \k{objcommon}. + \S{objcommon} \c{obj} Extensions to the \c{COMMON} Directive\I{COMMON, obj extensions to} @@ -3357,7 +3598,7 @@ OMF specification says that they are declared as a number of be declared as ten one-byte elements, five two-byte elements, two five-byte elements or one ten-byte element. -Some OMF linkers require the \I{element size, in common +Some \c{OMF} linkers require the \I{element size, in common variables}\I{common variables, element size}element size, as well as the variable size, to match when resolving common variables declared in more than one module. Therefore NASM must allow you to specify @@ -3383,6 +3624,7 @@ also supports default-\c{WRT} specification like \c{EXTERN} does \c common bar 16:far 2:wrt data \c common baz 24:wrt data:6 + \H{win32fmt} \i\c{win32}: Microsoft Win32 Object Files The \c{win32} output format generates Microsoft Win32 object files, @@ -3393,7 +3635,7 @@ Note that Borland Win32 compilers do not use this format, but use \c{win32} provides a default output file-name extension of \c{.obj}. Note that although Microsoft say that Win32 object files follow the -COFF (Common Object File Format) standard, the object files produced +\c{COFF} (Common Object File Format) standard, the object files produced by Microsoft Win32 compilers are not compatible with COFF linkers such as DJGPP's, and vice versa. This is due to a difference of opinion over the precise semantics of PC-relative relocations. To @@ -3401,6 +3643,7 @@ produce COFF files suitable for DJGPP, use NASM's \c{coff} output format; conversely, the \c{coff} format does not produce object files that Win32 linkers can generate correct output from. + \S{win32sect} \c{win32} Extensions to the \c{SECTION} Directive\I{SECTION, win32 extensions to} @@ -3455,9 +3698,10 @@ qualifiers are: Any other section name is treated by default like \c{.text}. + \H{cofffmt} \i\c{coff}: \i{Common Object File Format} -The \c{coff} output type produces COFF object files suitable for +The \c{coff} output type produces \c{COFF} object files suitable for linking with the \i{DJGPP} linker. \c{coff} provides a default output file-name extension of \c{.o}. @@ -3466,13 +3710,15 @@ The \c{coff} format supports the same extensions to the \c{SECTION} directive as \c{win32} does, except that the \c{align} qualifier and the \c{info} section type are not supported. + \H{elffmt} \i\c{elf}: \i{Linux ELF}\I{Executable and Linkable Format}Object Files -The \c{elf} output format generates ELF32 (Executable and Linkable +The \c{elf} output format generates \c{ELF32} (Executable and Linkable Format) object files, as used by Linux. \c{elf} provides a default output file-name extension of \c{.o}. + \S{elfsect} \c{elf} Extensions to the \c{SECTION} Directive\I{SECTION, elf extensions to} @@ -3517,16 +3763,17 @@ qualifiers are: (Any section name other than \c{.text}, \c{.data} and \c{.bss} is treated by default like \c{other} in the above code.) + \S{elfwrt} \i{Position-Independent Code}\I{PIC}: \c{elf} Special Symbols and \i\c{WRT} -The ELF specification contains enough features to allow +The \c{ELF} specification contains enough features to allow position-independent code (PIC) to be written, which makes \i{ELF shared libraries} very flexible. However, it also means NASM has to be able to generate a variety of strange relocation types in ELF object files, if it is to be an assembler which can write PIC. -Since ELF does not support segment-base references, the \c{WRT} +Since \c{ELF} does not support segment-base references, the \c{WRT} operator is not used for its normal purpose; therefore NASM's \c{elf} output format makes use of \c{WRT} for a different purpose, namely the PIC-specific \I{relocations, PIC-specific}relocation @@ -3574,10 +3821,11 @@ peculiarity of the dynamic linker. A fuller explanation of how to use these relocation types to write shared libraries entirely in NASM is given in \k{picdll}. + \S{elfglob} \c{elf} Extensions to the \c{GLOBAL} Directive\I{GLOBAL, elf extensions to}\I{GLOBAL, aoutb extensions to} -ELF object files can contain more information about a global symbol +\c{ELF} object files can contain more information about a global symbol than just its address: they can contain the \I{symbol sizes, specifying}\I{size, of symbols}size of the symbol and its \I{symbol types, specifying}\I{type, of symbols}type as well. These are not @@ -3606,16 +3854,17 @@ forward references) after the type specifier. Like this: \c .end: This makes NASM automatically calculate the length of the table and -place that information into the ELF symbol table. +place that information into the \c{ELF} symbol table. Declaring the type and size of global symbols is necessary when writing shared library code. For more information, see \k{picglobal}. + \S{elfcomm} \c{elf} Extensions to the \c{COMMON} Directive\I{COMMON, elf extensions to} -ELF also allows you to specify alignment requirements \I{common +\c{ELF} also allows you to specify alignment requirements \I{common variables, alignment in elf}\I{alignment, of elf common variables}on common variables. This is done by putting a number (which must be a power of two) after the name and size of the common variable, @@ -3627,6 +3876,7 @@ doublewords would benefit from 4-byte alignment: This declares the total size of the array to be 128 bytes, and requires that it be aligned on a 4-byte boundary. + \H{aoutfmt} \i\c{aout}: Linux \I{a.out, Linux version}\c{a.out} Object Files The \c{aout} format generates \c{a.out} object files, in the form @@ -3643,16 +3893,17 @@ directives, no special symbols, no use of \c{SEG} or \c{WRT}, and no extensions to any standard directives. It supports only the three \i{standard section names} \i\c{.text}, \i\c{.data} and \i\c{.bss}. + \H{aoutfmt} \i\c{aoutb}: \i{NetBSD}/\i{FreeBSD}/\i{OpenBSD} \I{a.out, BSD version}\c{a.out} Object Files The \c{aoutb} format generates \c{a.out} object files, in the form -used by the various free BSD Unix clones, NetBSD, FreeBSD and -OpenBSD. For simple object files, this object format is exactly the -same as \c{aout} except for the magic number in the first four bytes +used by the various free \c{BSD Unix} clones, \c{NetBSD}, \c{FreeBSD} +and \c{OpenBSD}. For simple object files, this object format is exactly +the same as \c{aout} except for the magic number in the first four bytes of the file. However, the \c{aoutb} format supports \I{PIC}\i{position-independent code} in the same way as the \c{elf} -format, so you can use it to write BSD \i{shared libraries}. +format, so you can use it to write \c{BSD} \i{shared libraries}. \c{aoutb} provides a default output file-name extension of \c{.o}. @@ -3666,6 +3917,7 @@ See \k{elfwrt} for full documentation of this feature. directive as \c{elf} does: see \k{elfglob} for documentation of this. + \H{as86fmt} \c{as86}: Linux \i\c{as86} Object Files The Linux 16-bit assembler \c{as86} has its own non-standard object @@ -3683,40 +3935,43 @@ use of \c{SEG} or \c{WRT}, and no extensions to any standard directives. It supports only the three \i{standard section names} \i\c{.text}, \i\c{.data} and \i\c{.bss}. + \H{rdffmt} \I{RDOFF}\i\c{rdf}: \i{Relocatable Dynamic Object File Format} -The \c{rdf} output format produces RDOFF object files. RDOFF +The \c{rdf} output format produces \c{RDOFF} object files. \c{RDOFF} (Relocatable Dynamic Object File Format) is a home-grown object-file format, designed alongside NASM itself and reflecting in its file format the internal structure of the assembler. -RDOFF is not used by any well-known operating systems. Those writing -their own systems, however, may well wish to use RDOFF as their -object format, on the grounds that it is designed primarily for -simplicity and contains very little file-header bureaucracy. +\c{RDOFF} is not used by any well-known operating systems. Those +writing their own systems, however, may well wish to use \c{RDOFF} +as their object format, on the grounds that it is designed primarily +for simplicity and contains very little file-header bureaucracy. The Unix NASM archive, and the DOS archive which includes sources, both contain an \I{rdoff subdirectory}\c{rdoff} subdirectory holding -a set of RDOFF utilities: an RDF linker, an RDF static-library +a set of RDOFF utilities: an RDF linker, an \c{RDF} static-library manager, an RDF file dump utility, and a program which will load and execute an RDF executable under Linux. \c{rdf} supports only the \i{standard section names} \i\c{.text}, \i\c{.data} and \i\c{.bss}. + \S{rdflib} Requiring a Library: The \i\c{LIBRARY} Directive -RDOFF contains a mechanism for an object file to demand a given +\c{RDOFF} contains a mechanism for an object file to demand a given library to be linked to the module, either at load time or run time. This is done by the \c{LIBRARY} directive, which takes one argument which is the name of the module: \c library mylib.rdl + \S{rdfmod} Specifying a Module Name: The \i\c{MODULE} Directive -Special RDOFF header record is used to store the name of the module. +Special \c{RDOFF} header record is used to store the name of the module. It can be used, for example, by run-time loader to perform dynamic linking. \c{MODULE} directive takes one argument which is the name of current module: @@ -3729,14 +3984,15 @@ To avoid it, you should start module names with \I{$prefix}\c{$}, like: \c module $kernel.core + \S{rdfglob} \c{rdf} Extensions to the \c{GLOBAL} directive\I{GLOBAL, rdf extensions to} -RDOFF global symbols can contain additional information needed by the -static linker. You can mark a global symbol as exported, thus telling -the linker do not strip it from target executable or library file. -Like in ELF, you can also specify whether an exported symbol is a -procedure (function) or data object. +\c{RDOFF} global symbols can contain additional information needed by +the static linker. You can mark a global symbol as exported, thus +telling the linker do not strip it from target executable or library +file. Like in \c{ELF}, you can also specify whether an exported symbol +is a procedure (function) or data object. Suffixing the name with a colon and the word \i\c{export} you make the symbol exported: @@ -3753,6 +4009,7 @@ or \i\c{object} to the directive: \c global kernel_ticks:export data + \H{dbgfmt} \i\c{dbg}: Debugging Format The \c{dbg} output format is not built into NASM in the default @@ -3800,14 +4057,16 @@ yourself (using \c{EXTERN}, for example) if you really need to get a \c{dbg} accepts any section name and any directives at all, and logs them all to its output file. + \C{16bit} Writing 16-bit Code (DOS, Windows 3/3.1) This chapter attempts to cover some of the common issues encountered -when writing 16-bit code to run under MS-DOS or Windows 3.x. It +when writing 16-bit code to run under \c{MS-DOS} or \c{Windows 3.x}. It covers how to link programs to produce \c{.EXE} or \c{.COM} files, how to write \c{.SYS} device drivers, and how to interface assembly language code with 16-bit C compilers and with Borland Pascal. + \H{exefiles} Producing \i\c{.EXE} Files Any large program written under DOS needs to be built as a \c{.EXE} @@ -3827,6 +4086,7 @@ Yann Guidon for contributing the code for this. NASM may also support \c{.EXE} natively as another output format in future releases. + \S{objexe} Using the \c{obj} Format To Generate \c{.EXE} Files This section describes the usual method of generating \c{.EXE} files @@ -3843,6 +4103,8 @@ sources) called \i{FREELINK}, available from \W{http://www.pcorner.com/tpc/old/3-101.html}\i\c{www.pcorner.com}. A third, \i\c{djlink}, written by DJ Delorie, is available at \W{http://www.delorie.com/djgpp/16bit/djlink/}\i\c{www.delorie.com}. +A fourth linker, \i\c{ALINK}, written by Anthony A.J. Williams, is +available at \W{http://alink.sourceforge.net}\i\c{alink.sourceforge.net}. When linking several \c{.OBJ} files into a \c{.EXE} file, you should ensure that exactly one of them has a start point defined (using the @@ -3914,6 +4176,7 @@ The above file, when assembled into a \c{.OBJ} file, will link on its own to a valid \c{.EXE} file, which when run will print `hello, world' and then exit. + \S{binexe} Using the \c{bin} Format To Generate \c{.EXE} Files The \c{.EXE} file format is simple enough that it's possible to @@ -3960,6 +4223,7 @@ A sample program which generates a \c{.EXE} file in this way is given in the \c{test} subdirectory of the NASM archive, as \c{binexe.asm}. + \H{comfiles} Producing \i\c{.COM} Files While large DOS programs must be written as \c{.EXE} files, small @@ -3967,6 +4231,7 @@ ones are often better written as \c{.COM} files. \c{.COM} files are pure binary, and therefore most easily produced using the \c{bin} output format. + \S{combinfmt} Using the \c{bin} Format To Generate \c{.COM} Files \c{.COM} files expect to be loaded at offset \c{100h} into their @@ -4003,6 +4268,7 @@ The \c{bin} format would produce a file called \c{myprog} if no explicit output file name were specified, so you have to override it and give the desired file name. + \S{comobjfmt} Using the \c{obj} Format To Generate \c{.COM} Files If you are writing a \c{.COM} program as more than one module, you @@ -4032,6 +4298,7 @@ your code or data references a symbol offset, all offsets are relative to the same segment base. This is because, when a \c{.COM} file is loaded, all the segment registers contain the same value. + \H{sysfiles} Producing \i\c{.SYS} Files \i{MS-DOS device drivers} - \c{.SYS} files - are pure binary files, @@ -4052,6 +4319,7 @@ which has to go in the header structure, a list of books is given in the Frequently Asked Questions list for the newsgroup \W{news:comp.os.msdos.programmer}\i\c{comp.os.msdos.programmer}. + \H{16c} Interfacing to 16-bit C Programs This section covers the basics of writing assembly routines that @@ -4059,6 +4327,7 @@ call, or are called from, C programs. To do this, you would typically write an assembly module as a \c{.OBJ} file, and link it with your C modules to produce a \i{mixed-language program}. + \S{16cunder} External Symbol Names \I{C symbol names}\I{underscore, in C symbols}C compilers have the @@ -4102,6 +4371,7 @@ The \c{cglobal} macro works similarly. You must use \c{cglobal} before defining the symbol in question, but you would have had to do that anyway if you used \c{GLOBAL}. + \S{16cmodels} \i{Memory Models} NASM contains no mechanism to support the various C memory models @@ -4163,6 +4433,7 @@ to be linked into the same place as the main code segment. In models with a single data segment, or with a default data segment, it is called \i\c{_DATA}. + \S{16cfunc} Function Definitions and Function Calls \I{functions, C calling convention}The \i{C calling convention} in @@ -4299,6 +4570,7 @@ functions expect far calls in large model; and \c{SP} has to be increased by 6 rather than 4 afterwards to make up for the extra word of parameters. + \S{16cdata} Accessing Data Items To get at the contents of C variables, or to declare variables which @@ -4349,6 +4621,7 @@ feature tends to be a configurable option in the C compiler, either using command-line options or \c{#pragma} lines, so you have to find out how your own compiler does it. + \S{16cmacro} \i\c{c16.mac}: Helper Macros for the 16-bit C Interface Included in the NASM archives, in the \I{misc subdirectory}\c{misc} @@ -4411,6 +4684,7 @@ This makes use of the argument to the \c{arg} macro to define a parameter of size 4, because \c{j} is now a far pointer. When we load from \c{j}, we must load a segment and an offset. + \H{16bp} Interfacing to \i{Borland Pascal} Programs Interfacing to Borland Pascal programs is similar in concept to @@ -4440,6 +4714,7 @@ data \e{pointers}, however, are far. use - Borland Pascal will ignore code or data declared in a segment it doesn't like the name of. The restrictions are described below. + \S{16bpfunc} The Pascal Calling Convention \I{functions, Pascal calling convention}\I{Pascal calling @@ -4528,6 +4803,7 @@ This is equivalent to the Pascal code \c procedure SomeFunc(String: PChar; Int: Integer); \c SomeFunc(@mystring, myint); + \S{16bpseg} Borland Pascal \I{segment names, Borland Pascal}Segment Name Restrictions @@ -4550,6 +4826,7 @@ either \c{CODE}, \c{CSEG}, or something ending in \c{_TEXT}. \b Any other segments in the object file are completely ignored. \c{GROUP} directives and segment attributes are also ignored. + \S{16bpmacro} Using \i\c{c16.mac} With Pascal Programs The \c{c16.mac} macro package, described in \k{16cmacro}, can also @@ -4581,6 +4858,7 @@ code and the large-model C version is that \c{PASCAL} is defined instead of \c{FARCODE}, and that the arguments are declared in reverse order. + \C{32bit} Writing 32-bit Code (Unix, Win32, DJGPP) This chapter attempts to cover some of the common issues involved @@ -4591,8 +4869,8 @@ linked with C code generated by a Unix-style C compiler such as shared libraries. Almost all 32-bit code, and in particular all code running under -Win32, DJGPP or any of the PC Unix variants, runs in \I{flat memory -model}\e{flat} memory model. This means that the segment registers +\c{Win32}, \c{DJGPP} or any of the PC Unix variants, runs in \I{flat +memory model}\e{flat} memory model. This means that the segment registers and paging have already been set up to give you the same 32-bit 4Gb address space no matter what segment you work relative to, and that you should ignore all segment registers completely. When writing @@ -4604,26 +4882,29 @@ the stack-section addresses you access local variables and procedure parameters by. Every address is 32 bits long and contains only an offset part. + \H{32c} Interfacing to 32-bit C Programs A lot of the discussion in \k{16c}, about interfacing to 16-bit C programs, still applies when working in 32 bits. The absence of memory models or segmentation worries simplifies things a lot. + \S{32cunder} External Symbol Names Most 32-bit C compilers share the convention used by 16-bit compilers, that the names of all global symbols (functions or data) they define are formed by prefixing an underscore to the name as it -appears in the C program. However, not all of them do: the ELF +appears in the C program. However, not all of them do: the \c{ELF} specification states that C symbols do \e{not} have a leading underscore on their assembly-language names. -The older Linux \c{a.out} C compiler, all Win32 compilers, DJGPP, -and NetBSD and FreeBSD, all use the leading underscore; for these -compilers, the macros \c{cextern} and \c{cglobal}, as given in -\k{16cunder}, will still work. For ELF, though, the leading -underscore should not be used. +The older Linux \c{a.out} C compiler, all \c{Win32} compilers, +\c{DJGPP}, and \c{NetBSD} and \c{FreeBSD}, all use the leading +underscore; for these compilers, the macros \c{cextern} and +\c{cglobal}, as given in \k{16cunder}, will still work. For \c{ELF}, +though, the leading underscore should not be used. + \S{32cfunc} Function Definitions and Function Calls @@ -4721,6 +5002,7 @@ This piece of code is the assembly equivalent of the C code \c int myint = 1234; \c printf("This number -> %d <- should be 1234\n", myint); + \S{32cdata} Accessing Data Items To get at the contents of C variables, or to declare variables which @@ -4772,6 +5054,7 @@ feature is sometimes a configurable option in the C compiler, either using command-line options or \c{#pragma} lines, so you have to find out how your own compiler does it. + \S{32cmacro} \i\c{c32.mac}: Helper Macros for the 32-bit C Interface Included in the NASM archives, in the \I{misc directory}\c{misc} @@ -4807,14 +5090,15 @@ in later procedures. Of course, you don't \e{have} to do that. argument. If no size is given, 4 is assumed, since it is likely that many function parameters will be of type \c{int} or pointers. + \H{picdll} Writing NetBSD/FreeBSD/OpenBSD and Linux/ELF \i{Shared Libraries} -ELF replaced the older \c{a.out} object file format under Linux +\c{ELF} replaced the older \c{a.out} object file format under Linux because it contains support for \i{position-independent code} (\i{PIC}), which makes writing shared libraries much easier. NASM -supports the ELF position-independent code features, so you can -write Linux ELF shared libraries in NASM. +supports the \c{ELF} position-independent code features, so you can +write Linux \c{ELF} shared libraries in NASM. \i{NetBSD}, and its close cousins \i{FreeBSD} and \i{OpenBSD}, take a different approach by hacking PIC support into the \c{a.out} @@ -4846,6 +5130,7 @@ file, so as long as it's being copied it can be relocated too. So you can put ordinary types of relocation in the data section without too much worry (but see \k{picglobal} for a caveat). + \S{picgot} Obtaining the Address of the GOT Each code module in your shared library should define the GOT as an @@ -4889,14 +5174,13 @@ of one of the special PIC relocation types: \i{GOTPC relocation}. With the \i\c{WRT ..gotpc} qualifier specified, the symbol referenced (here \c{_GLOBAL_OFFSET_TABLE_}, the special symbol assigned to the GOT) is given as an offset from the beginning of the -section. (Actually, ELF encodes it as the offset from the operand +section. (Actually, \c{ELF} encodes it as the offset from the operand field of the \c{ADD} instruction, but NASM simplifies this -deliberately, so you do things the same way for both ELF and BSD.) -So the instruction then \e{adds} the beginning of the section, to -get the real address of the GOT, and subtracts the value of +deliberately, so you do things the same way for both \c{ELF} and +\c{BSD}.) So the instruction then \e{adds} the beginning of the section, +to get the real address of the GOT, and subtracts the value of \c{.get_GOT} which it knows is in \c{EBX}. Therefore, by the time -that instruction has finished, -\c{EBX} contains the address of the GOT. +that instruction has finished, \c{EBX} contains the address of the GOT. If you didn't follow that, don't worry: it's never necessary to obtain the address of the GOT by any other means, so you can put @@ -4934,6 +5218,7 @@ Note that due to a peculiarity of the way BSD \c{a.out} format handles this relocation type, there must be at least one non-local symbol in the same section as the address you're trying to access. + \S{picextern} Finding External and Common Data Items If your library needs to get at an external variable (external to @@ -4956,6 +5241,7 @@ has every necessary entry present. Common variables must also be accessed in this way. + \S{picglobal} Exporting Symbols to the Library User If you want to export symbols to the user of the library, you have @@ -5019,6 +5305,7 @@ will give the address of the procedure linkage table for the function, which is where the calling program will \e{believe} the function lives. Either address is a valid way to call the function. + \S{picproc} Calling Procedures Outside the Library Calling procedures outside your shared library has to be done by @@ -5036,6 +5323,7 @@ easier than the GOT-based ones: you simply replace calls such as \c{CALL printf} with the PLT-relative version \c{CALL printf WRT ..plt}. + \S{link} Generating the Library File Having written some code modules and assembled them to \c{.o} files, @@ -5054,6 +5342,7 @@ library file name, with a version number, into the library: You would then copy \c{library.so.1.2} into the library directory, and create \c{library.so.1} as a symbolic link to it. + \C{mixsize} Mixing 16 and 32 Bit Code This chapter tries to cover some of the issues, largely related to @@ -5063,6 +5352,7 @@ routines, which require code that operates in mixed segment sizes, such as code in a 16-bit segment trying to modify data in a 32-bit one, or jumps between different-size segments. + \H{mixjump} Mixed-Size Jumps\I{jumps, mixed-size} \I{operating system, writing}\I{writing operating systems}The most @@ -5107,6 +5397,7 @@ If the \c{WORD} prefix is specified in 16-bit mode, or the \c{DWORD} prefix in 32-bit mode, they will be ignored, since each is explicitly forcing NASM into a mode it was in anyway. + \H{mixaddr} Addressing Between Different-Size Segments\I{addressing, mixed-size}\I{mixed-size addressing} @@ -5164,6 +5455,7 @@ This instruction contains an address specified by a 16-bit offset; it loads a 48-bit far pointer from that (16-bit segment and 32-bit offset), and calls that address. + \H{mixother} Other Mixed-Size Instructions The other way you might want to access data might be using the @@ -5214,6 +5506,7 @@ one. (You can also use the \i\c{o32} prefix to force the 32-bit behaviour when in 16-bit mode, but this seems less useful.) + \C{trouble} Troubleshooting This chapter describes some of the common problems that users have @@ -5221,6 +5514,7 @@ been known to encounter with NASM, and answers them. It also gives instructions for reporting bugs in NASM if you find a difficulty that isn't listed here. + \H{problems} Common Problems \S{inefficient} NASM Generates \i{Inefficient Code} @@ -5234,6 +5528,7 @@ instruction which leaves room for a 32-bit offset. You need to code form of the instruction. This isn't a bug: at worst it's a misfeature, and that's a matter of opinion only. + \S{jmprange} My Jumps are Out of Range\I{out of range, jumps} Similarly, people complain that when they issue \i{conditional @@ -5254,6 +5549,7 @@ branch prediction \e{and} could have used \c{JNE NEAR} instead. So, once again, it's up to the user, not the assembler, to decide what instructions should be generated. + \S{proborg} \i\c{ORG} Doesn't Work People writing \i{boot sector} programs in the \c{bin} format often @@ -5282,6 +5578,7 @@ full, NASM will catch the problem at assembly time and report it, so you won't end up with a boot sector that you have to disassemble to find out what's wrong with it. + \S{probtimes} \i\c{TIMES} Doesn't Work The other common problem with the above code is people who write the @@ -5313,12 +5610,15 @@ in which \c{$} and \c{$$} are offsets from the same section base, and so their difference is a pure number. This will solve the problem and generate sensible code. + \H{bugs} \i{Bugs}\I{reporting bugs} We have never yet released a version of NASM with any \e{known} bugs. That doesn't usually stop there being plenty we didn't know -about, though. Any that you find should be reported to -\W{mailto:hpa@zytor.com}\c{hpa@zytor.com}. +about, though. Any that you find should be reported firstly via the +\i\c{bugtracker} at +\W{http://nasm.2y.net/bugtracker/}\c{http://nasm.2y.net/bugtracker/}, +or if that fails then through one of the contacts in \k{contact} Please read \k{qstart} first, and don't report the bug if it's listed in there as a deliberate feature. (If you think the feature @@ -5395,6 +5695,206 @@ file while TASM can generate an equivalent file without trouble, then send us \e{both} object files, so we can see what TASM is doing differently from us. + +\A{ndisasm} \i{Ndisasm} + + The Netwide Disassembler, NDISASM + +\H{ndisintro} Introduction + + +The Netwide Disassembler is a small companion program to the Netwide +Assembler, NASM. It seemed a shame to have an x86 assembler, +complete with a full instruction table, and not make as much use of +it as possible, so here's a disassembler which shares the +instruction table (and some other bits of code) with NASM. + +The Netwide Disassembler does nothing except to produce +disassemblies of \e{binary} source files. NDISASM does not have any +understanding of object file formats, like \c{objdump}, and it will +not understand \c{DOS .EXE} files like \c{debug} will. It just +disassembles. + + +\H{ndisstart} Getting Started: Installation + +See \k{install} for installation instructions. NDISASM, like NASM, +has a \c{man page} which you may want to put somewhere useful, if you +are on a Unix system. + + +\H{ndisrun} Running NDISASM + +To disassemble a file, you will typically use a command of the form + +\c ndisasm [-b16 | -b32] filename + +NDISASM can disassemble 16-bit code or 32-bit code equally easily, +provided of course that you remember to specify which it is to work +with. If no \i\c{-b} switch is present, NDISASM works in 16-bit mode by +default. The \i\c{-u} switch (for USE32) also invokes 32-bit mode. + +Two more command line options are \i\c{-r} which reports the version +number of NDISASM you are running, and \i\c{-h} which gives a short +summary of command line options. + + +\S{ndiscom} COM Files: Specifying an Origin + +To disassemble a \c{DOS .COM} file correctly, a disassembler must assume +that the first instruction in the file is loaded at address \c{0x100}, +rather than at zero. NDISASM, which assumes by default that any file +you give it is loaded at zero, will therefore need to be informed of +this. + +The \i\c{-o} option allows you to declare a different origin for the +file you are disassembling. Its argument may be expressed in any of +the NASM numeric formats: decimal by default, if it begins with `\c{$}' +or `\c{0x}' or ends in `\c{H}' it's \c{hex}, if it ends in `\c{Q}' it's +\c{octal}, and if it ends in `\c{B}' it's \c{binary}. + +Hence, to disassemble a \c{.COM} file: + +\c ndisasm -o100h filename.com + +will do the trick. + + +\S{ndissync} Code Following Data: Synchronisation + +Suppose you are disassembling a file which contains some data which +isn't machine code, and \e{then} contains some machine code. NDISASM +will faithfully plough through the data section, producing machine +instructions wherever it can (although most of them will look +bizarre, and some may have unusual prefixes, e.g. `\c{FS OR AX,0x240A}'), +and generating `DB' instructions ever so often if it's totally stumped. +Then it will reach the code section. + +Supposing NDISASM has just finished generating a strange machine +instruction from part of the data section, and its file position is +now one byte \e{before} the beginning of the code section. It's +entirely possible that another spurious instruction will get +generated, starting with the final byte of the data section, and +then the correct first instruction in the code section will not be +seen because the starting point skipped over it. This isn't really +ideal. + +To avoid this, you can specify a `\i\c{synchronisation}' point, or indeed +as many synchronisation points as you like (although NDISASM can +only handle 8192 sync points internally). The definition of a sync +point is this: NDISASM guarantees to hit sync points exactly during +disassembly. If it is thinking about generating an instruction which +would cause it to jump over a sync point, it will discard that +instruction and output a `\c{db}' instead. So it \e{will} start +disassembly exactly from the sync point, and so you \e{will} see all +the instructions in your code section. + +Sync points are specified using the \i\c{-s} option: they are measured +in terms of the program origin, not the file position. So if you +want to synchronise after 32 bytes of a \c{.COM} file, you would have to +do + +\c ndisasm -o100h -s120h file.com + +rather than + +\c ndisasm -o100h -s20h file.com + +As stated above, you can specify multiple sync markers if you need +to, just by repeating the \c{-s} option. + + +\S{ndisisync} Mixed Code and Data: Automatic (Intelligent) Synchronisation +\I\c{auto-sync} + +Suppose you are disassembling the boot sector of a \c{DOS} floppy (maybe +it has a virus, and you need to understand the virus so that you +know what kinds of damage it might have done you). Typically, this +will contain a \c{JMP} instruction, then some data, then the rest of the +code. So there is a very good chance of NDISASM being \e{misaligned} +when the data ends and the code begins. Hence a sync point is +needed. + +On the other hand, why should you have to specify the sync point +manually? What you'd do in order to find where the sync point would +be, surely, would be to read the \c{JMP} instruction, and then to use +its target address as a sync point. So can NDISASM do that for you? + +The answer, of course, is yes: using either of the synonymous +switches \i\c{-a} (for automatic sync) or \i\c{-i} (for intelligent +sync) will enable \c{auto-sync} mode. Auto-sync mode automatically +generates a sync point for any forward-referring PC-relative jump or +call instruction that NDISASM encounters. (Since NDISASM is one-pass, +if it encounters a PC-relative jump whose target has already been +processed, there isn't much it can do about it...) + +Only PC-relative jumps are processed, since an absolute jump is +either through a register (in which case NDISASM doesn't know what +the register contains) or involves a segment address (in which case +the target code isn't in the same segment that NDISASM is working +in, and so the sync point can't be placed anywhere useful). + +For some kinds of file, this mechanism will automatically put sync +points in all the right places, and save you from having to place +any sync points manually. However, it should be stressed that +auto-sync mode is \e{not} guaranteed to catch all the sync points, and +you may still have to place some manually. + +Auto-sync mode doesn't prevent you from declaring manual sync +points: it just adds automatically generated ones to the ones you +provide. It's perfectly feasible to specify \c{-i} \e{and} some \c{-s} +options. + +Another caveat with auto-sync mode is that if, by some unpleasant +fluke, something in your data section should disassemble to a +PC-relative call or jump instruction, NDISASM may obediently place a +sync point in a totally random place, for example in the middle of +one of the instructions in your code section. So you may end up with +a wrong disassembly even if you use auto-sync. Again, there isn't +much I can do about this. If you have problems, you'll have to use +manual sync points, or use the \c{-k} option (documented below) to +suppress disassembly of the data area. + + +\S{ndisother} Other Options + +The \i\c{-e} option skips a header on the file, by ignoring the first N +bytes. This means that the header is \e{not} counted towards the +disassembly offset: if you give \c{-e10 -o10}, disassembly will start +at byte 10 in the file, and this will be given offset 10, not 20. + +The \i\c{-k} option is provided with two comma-separated numeric +arguments, the first of which is an assembly offset and the second +is a number of bytes to skip. This \e{will} count the skipped bytes +towards the assembly offset: its use is to suppress disassembly of a +data section which wouldn't contain anything you wanted to see +anyway. + + +\H{ndisbugs} Bugs and Improvements + +There are no known bugs. However, any you find, with patches if +possible, should be sent to \W{mailto:jules@dsf.org.uk}\c{jules@dsf.org.uk} +or \W{mailto:anakin@pobox.com}\c{anakin@pobox.com}, or to the +developer's site \W{http://nasm.2y.net/}\c{http://nasm.2y.net/} +and we'll try to fix them. Feel free to send contributions and +new features as well. + +Future plans include awareness of which processors certain +instructions will run on, and marking of instructions that are too +advanced for some processor (or are \c{FPU} instructions, or are +undocumented opcodes, or are privileged protected-mode instructions, +or whatever). + +That's All Folks! + +I hope NDISASM is of some use to somebody. Including me. :-) + +I don't recommend taking NDISASM apart to see how an efficient +disassembler works, because as far as I know, it isn't an efficient +one anyway. You have been warned. + + \A{iref} Intel x86 Instruction Reference This appendix provides a complete list of the machine instructions @@ -5419,6 +5919,7 @@ groups of instructions with similar functions are lumped together in the same entry. Most of them don't move very far from their alphabetic position because of this. + \H{iref-opr} Key to Operand Specifications The instruction descriptions in this appendix specify their operands @@ -5458,6 +5959,7 @@ register \e{or} a memory reference as an operand. \c{r/m8} is a shorthand for \c{reg8/mem8}; similarly \c{r/m16} and \c{r/m32}. \c{r/m64} is MMX-related, and is a shorthand for \c{mmxreg/mem64}. + \H{iref-opc} Key to Opcode Descriptions This appendix also provides the opcodes which NASM will generate for @@ -5533,6 +6035,7 @@ indicate the address size of the given form of the instruction. Where this does not match the \c{BITS} setting, a \c{67} prefix is required. + \S{iref-rv} Register Values Where an instruction requires a register value, it is already @@ -5578,6 +6081,7 @@ and \c{CR4} is 4. (Note that wherever a register name contains a number, that number is also the register value for that register.) + \S{iref-cc} \i{Condition Codes} The available condition codes are given here, along with their @@ -5614,6 +6118,121 @@ or exactly one of the sign and overflow flags is set); \c{G} and Note that in all cases, the sense of a condition code may be reversed by changing the low bit of the numeric representation. +For details of when an instruction sets each of the status flags, +see the individual instruction, plus the Status Flags reference +in \k{iref-Flags} + + +\S{iref-SSE-cc} \i{SSE Condition Predicates} + +The condition predicates for SSE comparison instructions are the +codes used as part of the opcode, to determine what form of +comparison is being carried out. In each case, the imm8 value is +the final byte of the opcode encoding, and the predicate is the +code used as part of the mnemonic for the instruction (equivalent +to the "cc" in an integer instruction that used a condition code). +The instructions that use this will give details of what the various +mnemonics are, this table is used to help you work out details of what +is happening. + +Predi- imm8 Description Relation where: Emula- Result if QNaN + cate Encod- A Is 1st Operand tion NaN Signals + ing B Is 2nd Operand Operand Invalid + +EQ 000B equal A = B False No + +LT 001B less-than A < B False Yes + +LE 010B less-than- A <= B False Yes + or-equal + +--- ---- greater A > B Swap False Yes + than Operands, + Use LT + +--- ---- greater- A >= B Swap False Yes + than-or-equal Operands, + Use LE + +UNORD 011B unordered A, B = Unordered True No + +NEQ 100B not-equal A != B True No + +NLT 101B not-less- NOT(A < B) True Yes + than + +NLE 110B not-less- NOT(A <= B) True Yes + than-or- + equal + +--- ---- not-greater NOT(A > B) Swap True Yes + than Operands, + Use NLT + +--- ---- not-greater NOT(A >= B) Swap True Yes + than- Operands, + or-equal Use NLE + +ORD 111B ordered A , B = Ordered False No + +The unordered relationship is true when at least one of the two +values being compared is a NaN or in an unsupported format. + +Note that the comparisons which are listed as not having a predicate +or encoding can only be achieved through software emulation, as +described in the "emulation" column. Note in particular that an +instruction such as \c{greater-than} is not the same as \c{NLE}, as, +unlike with the \c{CMP} instruction, it has to take into account the +possibility of one operand containing a NaN or an unsupported numeric +format. + + +\S{iref-Flags} \i{Status Flags} + +The status flags provide some information about the result of the +arithmetic instructions. This information can be used by conditional +instructions (such a \c{Jcc} and \c{CMOVcc}) as well as by some of +the other instructions (such as \c{ADC} and \c{INTO}). + +There are 6 status flags: + +\c CF - Carry flag. + +Set if an arithmetic operation generates a +carry or a borrow out of the most-significant bit of the result; +cleared otherwise. This flag indicates an overflow condition for +unsigned-integer arithmetic. It is also used in multiple-precision +arithmetic. + +\c PF - Parity flag. + +Set if the least-significant byte of the result contains an even +number of 1 bits; cleared otherwise. + +\c AF - Adjust flag. + +Set if an arithmetic operation generates a carry or a borrow +out of bit 3 of the result; cleared otherwise. This flag is used +in binary-coded decimal (BCD) arithmetic. + +\c ZF - Zero flag. + +Set if the result is zero; cleared otherwise. + +\c SF - Sign flag. + +Set equal to the most-significant bit of the result, which is the +sign bit of a signed integer. (0 indicates a positive value and 1 +indicates a negative value.) + +\c OF - Overflow flag. + +Set if the integer result is too large a positive number or too +small a negative number (excluding the sign-bit) to fit in the +destina-tion operand; cleared otherwise. This flag indicates an +overflow condition for signed-integer (two’s complement) arithmetic. + + \S{iref-ea} Effective Address Encoding: \i{ModR/M} and \i{SIB} An \i{effective address} is encoded in up to three parts: a ModR/M @@ -5707,6 +6326,7 @@ and \c{base} is 4, the effective address encoded is not bytes long, and there is no base register (but the index register is still processed in the normal way). + \H{iref-flg} Key to Instruction Flags Given along with each instruction in this appendix is a set of @@ -5720,6 +6340,10 @@ instructions beyond the P6 (Pentium Pro); from the point of view of its instruction set, it can be thought of as a P6 with MMX capability. +\b \c{3DNOW} indicates that the instruction is a 3DNow! one, and will +run on the AMD K6-2 and later processors. ATHLON extensions to the +3DNow! instruction set are documented as such. + \b \c{CYRIX} indicates that the instruction is specific to Cyrix processors, for example the extra MMX instructions in the Cyrix extended MMX instruction set. @@ -5728,6 +6352,11 @@ extended MMX instruction set. and will only run on machines with a coprocessor (automatically including 486DX, Pentium and above). +\b \c{KATMAI} indicates that the instruction was introduced as part +of the Katmai New Instruction set. These instructions are available +on the Pentium III and later processors. Those which are not +specifically SSE instructions are also available on the AMD Athlon. + \b \c{MMX} indicates that the instruction is an MMX one, and will run on MMX-capable Pentium processors and the Pentium II. @@ -5735,10 +6364,20 @@ run on MMX-capable Pentium processors and the Pentium II. management instruction. Many of these may only be used in protected mode, or only at privilege level zero. +\b \c{SSE} and \c{SSE2} indicate that the instruction is a Streaming +SIMD Extension instruction. These instructions operate on multiple +values in a single operation. SSE was introduced with the Pentium III +and SSE2 was introduced with the Pentium 4. + \b \c{UNDOC} indicates that the instruction is an undocumented one, and not part of the official Intel Architecture; it may or may not be supported on any given machine. +\b \c{WILLAMETTE} indicates that the instruction was introduced as +part of the new instruction set in the Pentium 4 and Intel Xeon +processors. These instructions are also known as SSE2 instructions. + + \H{insAAA} \i\c{AAA}, \i\c{AAS}, \i\c{AAM}, \i\c{AAD}: ASCII Adjustments @@ -5755,31 +6394,36 @@ Adjustments These instructions are used in conjunction with the add, subtract, multiply and divide instructions to perform binary-coded decimal arithmetic in \e{unpacked} (one BCD digit per byte - easy to -translate to and from ASCII, hence the instruction names) form. +translate to and from \c{ASCII}, hence the instruction names) form. There are also packed BCD instructions \c{DAA} and \c{DAS}: see \k{insDAA}. -\c{AAA} should be used after a one-byte \c{ADD} instruction whose -destination was the \c{AL} register: by means of examining the value -in the low nibble of \c{AL} and also the auxiliary carry flag -\c{AF}, it determines whether the addition has overflowed, and -adjusts it (and sets the carry flag) if so. You can add long BCD -strings together by doing \c{ADD}/\c{AAA} on the low digits, then -doing \c{ADC}/\c{AAA} on each subsequent digit. - -\c{AAS} works similarly to \c{AAA}, but is for use after \c{SUB} -instructions rather than \c{ADD}. +\b \c{AAA} (ASCII Adjust After Addition) should be used after a +one-byte \c{ADD} instruction whose destination was the \c{AL} +register: by means of examining the value in the low nibble of +\c{AL} and also the auxiliary carry flag \c{AF}, it determines +whether the addition has overflowed, and adjusts it (and sets +the carry flag) if so. You can add long BCD strings together +by doing \c{ADD}/\c{AAA} on the low digits, then doing +\c{ADC}/\c{AAA} on each subsequent digit. + +\b \c{AAS} (ASCII Adjust AL After Subtraction) works similarly to +\c{AAA}, but is for use after \c{SUB} instructions rather than +\c{ADD}. + +\b \c{AAM} (ASCII Adjust AX After Multiply) is for use after you +have multiplied two decimal digits together and left the result +in \c{AL}: it divides \c{AL} by ten and stores the quotient in +\c{AH}, leaving the remainder in \c{AL}. The divisor 10 can be +changed by specifying an operand to the instruction: a particularly +handy use of this is \c{AAM 16}, causing the two nibbles in \c{AL} +to be separated into \c{AH} and \c{AL}. + +\b \c{AAD} (ASCII Adjust AX Before Division) performs the inverse +operation to \c{AAM}: it multiplies \c{AH} by ten, adds it to +\c{AL}, and sets \c{AH} to zero. Again, the multiplier 10 can +be changed. -\c{AAM} is for use after you have multiplied two decimal digits -together and left the result in \c{AL}: it divides \c{AL} by ten and -stores the quotient in \c{AH}, leaving the remainder in \c{AL}. The -divisor 10 can be changed by specifying an operand to the -instruction: a particularly handy use of this is \c{AAM 16}, causing -the two nibbles in \c{AL} to be separated into \c{AH} and \c{AL}. - -\c{AAD} performs the inverse operation to \c{AAM}: it multiplies -\c{AH} by ten, adds it to \c{AL}, and sets \c{AH} to zero. Again, -the multiplier 10 can be changed. \H{insADC} \i\c{ADC}: Add with Carry @@ -5804,9 +6448,13 @@ the multiplier 10 can be changed. \c{ADC} performs integer addition: it adds its two operands together, plus the value of the carry flag, and leaves the result in -its destination (first) operand. The flags are set according to the -result of the operation: in particular, the carry flag is affected -and can be used by a subsequent \c{ADC} instruction. +its destination (first) operand. The destination operand can be a +register or a memory location. The source operand can be a register, +a memory location or an immediate value. + +The flags are set according to the result of the operation: in +particular, the carry flag is affected and can be used by a +subsequent \c{ADC} instruction. In the forms with an 8-bit immediate second operand and a longer first operand, the second operand is considered to be signed, and is @@ -5817,6 +6465,7 @@ form of the instruction. To add two numbers without also adding the contents of the carry flag, use \c{ADD} (\k{insADD}). + \H{insADD} \i\c{ADD}: Add Integers \c ADD r/m8,reg8 ; 00 /r [8086] @@ -5840,9 +6489,13 @@ flag, use \c{ADD} (\k{insADD}). \c{ADD} performs integer addition: it adds its two operands together, and leaves the result in its destination (first) operand. +The destination operand can be a register or a memory location. +The source operand can be a register, a memory location or an +immediate value. + The flags are set according to the result of the operation: in particular, the carry flag is affected and can be used by a -subsequent \c{ADC} instruction (\k{insADC}). +subsequent \c{ADC} instruction. In the forms with an 8-bit immediate second operand and a longer first operand, the second operand is considered to be signed, and is @@ -5850,19 +6503,66 @@ sign-extended to the length of the first operand. In these cases, the \c{BYTE} qualifier is necessary to force NASM to generate this form of the instruction. -\H{insADDPS} \i\c{ADDPS}: Packed Single FP ADD -\c ADDPS xmmreg,mem128 ; 0f 58 /r [KATMAI,SSE] -\c ADDPS xmmreg,xmmreg ; 0f 58 /r [KATMAI,SSE] +\H{insADDPD} \i\c{ADDPD}: ADD Packed Double-Precision FP Values + +\c ADDPD xmm1,xmm2/mem128 ; 66 0F 58 /r [WILLAMETTE,SSE2] + +\c{ADDPD} performs addition on each of two packed double-precision +FP value pairs. + +\c dst[0-63] := dst[0-63] + src[0-63], +\c dst[64-127] := dst[64-127] + src[64-127]. + +The destination is an \c{XMM} register. The source operand can be +either an \c{XMM} register or a 128-bit memory location. + + +\H{insADDPS} \i\c{ADDPS}: ADD Packed Single-Precision FP Values + +\c ADDPS xmm1,xmm2/mem128 ; 0F 58 /r [KATMAI,SSE] + +\c{ADDPS} performs addition on each of four packed single-precision +FP value pairs + +\c dst[0-31] := dst[0-31] + src[0-31], +\c dst[32-63] := dst[32-63] + src[32-63], +\c dst[64-95] := dst[64-95] + src[64-95], +\c dst[96-127] := dst[96-127] + src[96-127]. + +The destination is an \c{XMM} register. The source operand can be +either an \c{XMM} register or a 128-bit memory location. + -\c{ADDPS} performs addition on each of four packed SP FP -number items dst(0-31):=dst(0-31)+src(0-31) -, ..(63-32), etc. +\H{insADDSD} \i\c{ADDSD}: ADD Scalar Double-Precision FP Values -\H{insADDSS} \i\c{ADDSS}: Scalar Single FP ADD +\c ADDSD xmm1,xmm2/mem64 ; F2 0F 58 /r [KATMAI,SSE] + +\c{ADDSD} adds the low double-precision FP values from the source +and destination operands and stores the double-precision FP result +in the destination operand. + +\c dst[0-63] := dst[0-63] + src[0-63], +\c dst[64-127) remains unchanged. + +The destination is an \c{XMM} register. The source operand can be +either an \c{XMM} register or a 64-bit memory location. + + +\H{insADDSS} \i\c{ADDSS}: ADD Scalar Single-Precision FP Values + +\c ADDSS xmm1,xmm2/mem32 ; F3 0F 58 /r [WILLAMETTE,SSE2] + +\c{ADDSD} adds the low single-precision FP values from the source +and destination operands and stores the single-precision FP result +in the destination operand. + +\c dst[0-31] := dst[0-31] + src[0-31], +\c dst[32-127] remains unchanged. + +The destination is an \c{XMM} register. The source operand can be +either an \c{XMM} register or a 32-bit memory location. -\c ADDSS xmmreg,mem128 ; f3 0f 58 /r [KATMAI,SSE] -\c ADDSS xmmreg,xmmreg ; f3 0f 58 /r [KATMAI,SSE] \H{insAND} \i\c{AND}: Bitwise AND @@ -5888,7 +6588,9 @@ number items dst(0-31):=dst(0-31)+src(0-31) \c{AND} performs a bitwise AND operation between its two operands (i.e. each bit of the result is 1 if and only if the corresponding bits of the two inputs were both 1), and stores the result in the -destination (first) operand. +destination (first) operand. The destination operand can be a +register or a memory location. The source operand can be a register, +a memory location or an immediate value. In the forms with an 8-bit immediate second operand and a longer first operand, the second operand is considered to be signed, and is @@ -5896,19 +6598,78 @@ sign-extended to the length of the first operand. In these cases, the \c{BYTE} qualifier is necessary to force NASM to generate this form of the instruction. -The MMX instruction \c{PAND} (see \k{insPAND}) performs the same -operation on the 64-bit MMX registers. +The \c{MMX} instruction \c{PAND} (see \k{insPAND}) performs the same +operation on the 64-bit \c{MMX} registers. + + +\H{insANDNPD} \i\c{ANDNPD}: Bitwise Logical AND NOT of +Packed Double-Precision FP Values + +\c ANDNPD xmm1,xmm2/mem128 ; 66 0F 55 /r [WILLAMETTE,SSE2] + +\c{ANDNPD} inverts the bits of the two double-precision +floating-point values in the destination register, and then +performs a logical AND between the two double-precision +floating-point values in the source operand and the temporary +inverted result, storing the result in the destination register. + +\c dst[0-63] := src[0-63] AND NOT dst[0-63], +\c dst[64-127] := src[64-127] AND NOT dst[64-127]. + +The destination is an \c{XMM} register. The source operand can be +either an \c{XMM} register or a 128-bit memory location. + + +\H{insANDNPS} \i\c{ANDNPS}: Bitwise Logical AND NOT of +Packed Single-Precision FP Values + +\c ANDNPS xmm1,xmm2/mem128 ; 0F 55 /r [KATMAI,SSE] + +\c{ANDNPS} inverts the bits of the four single-precision +floating-point values in the destination register, and then +performs a logical AND between the four single-precision +floating-point values in the source operand and the temporary +inverted result, storing the result in the destination register. -\H{insANDNPS} \i\c{ANDNPS}: Bitwise Logical AND NOT For Single FP +\c dst[0-31] := src[0-31] AND NOT dst[0-31], +\c dst[32-63] := src[32-63] AND NOT dst[32-63], +\c dst[64-95] := src[64-95] AND NOT dst[64-95], +\c dst[96-127] := src[96-127] AND NOT dst[96-127]. -\c ANDNPS xmmreg,mem128 ; 0f 55 /r [KATMAI,SSE] -\c ANDNPS xmmreg,xmmreg ; 0f 55 /r [KATMAI,SSE] +The destination is an \c{XMM} register. The source operand can be +either an \c{XMM} register or a 128-bit memory location. + + +\H{insANDPD} \i\c{ANDPD}: Bitwise Logical AND For Single FP + +\c ANDPD xmm1,xmm2/mem128 ; 66 0F 54 /r [WILLAMETTE,SSE2] + +\c{ANDPD} performs a bitwise logical AND of the two double-precision +floating point values in the source and destination operand, and +stores the result in the destination register. + +\c dst[0-63] := src[0-63] AND dst[0-63], +\c dst[64-127] := src[64-127] AND dst[64-127]. + +The destination is an \c{XMM} register. The source operand can be +either an \c{XMM} register or a 128-bit memory location. \H{insANDPS} \i\c{ANDPS}: Bitwise Logical AND For Single FP -\c ANDPS xmmreg,mem128 ; 0f 54 /r [KATMAI,SSE] -\c ANDPS xmmreg,xmmreg ; 0f 54 /r [KATMAI,SSE] +\c ANDPS xmm1,xmm2/mem128 ; 0F 54 /r [KATMAI,SSE] + +\c{ANDPS} performs a bitwise logical AND of the four single-precision +floating point values in the source and destination operand, and +stores the result in the destination register. + +\c dst[0-31] := src[0-31] AND dst[0-31], +\c dst[32-63] := src[32-63] AND dst[32-63], +\c dst[64-95] := src[64-95] AND dst[64-95], +\c dst[96-127] := src[96-127] AND dst[96-127]. + +The destination is an \c{XMM} register. The source operand can be +either an \c{XMM} register or a 128-bit memory location. \H{insARPL} \i\c{ARPL}: Adjust RPL Field of Selector @@ -5916,12 +6677,13 @@ operation on the 64-bit MMX registers. \c ARPL r/m16,reg16 ; 63 /r [286,PRIV] \c{ARPL} expects its two word operands to be segment selectors. It -adjusts the RPL (requested privilege level - stored in the bottom +adjusts the \i\c{RPL} (requested privilege level - stored in the bottom two bits of the selector) field of the destination (first) operand -to ensure that it is no less (i.e. no more privileged than) the RPL +to ensure that it is no less (i.e. no more privileged than) the \c{RPL} field of the source operand. The zero flag is set if and only if a change had to be made. + \H{insBOUND} \i\c{BOUND}: Check Array Index against Bounds \c BOUND reg16,mem ; o16 62 /r [186] @@ -5933,7 +6695,8 @@ containing two signed values of the same size as its first operand form). It performs two signed comparisons: if the value in the register passed as its first operand is less than the first of the in-memory values, or is greater than or equal to the second, it -throws a BR exception. Otherwise, it does nothing. +throws a \c{BR} exception. Otherwise, it does nothing. + \H{insBSF} \i\c{BSF}, \i\c{BSR}: Bit Scan @@ -5943,16 +6706,19 @@ throws a BR exception. Otherwise, it does nothing. \c BSR reg16,r/m16 ; o16 0F BD /r [386] \c BSR reg32,r/m32 ; o32 0F BD /r [386] -\c{BSF} searches for a set bit in its source (second) operand, -starting from the bottom, and if it finds one, stores the index in +\b \c{BSF} searches for the least significant set bit in its source +(second) operand, and if it finds one, stores the index in its destination (first) operand. If no set bit is found, the -contents of the destination operand are undefined. +contents of the destination operand are undefined. If the source +operand is zero, the zero flag is set. -\c{BSR} performs the same function, but searches from the top +\b \c{BSR} performs the same function, but searches from the top instead, so it finds the most significant set bit. Bit indices are from 0 (least significant) to 15 or 31 (most -significant). +significant). The destination operand can only be a register. +The source operand can be a register or a memory location. + \H{insBSWAP} \i\c{BSWAP}: Byte Swap @@ -5961,7 +6727,9 @@ significant). \c{BSWAP} swaps the order of the four bytes of a 32-bit register: bits 0-7 exchange places with bits 24-31, and bits 8-15 swap with bits 16-23. There is no explicit 16-bit equivalent: to byte-swap -\c{AX}, \c{BX}, \c{CX} or \c{DX}, \c{XCHG} can be used. +\c{AX}, \c{BX}, \c{CX} or \c{DX}, \c{XCHG} can be used. When \c{BSWAP} +is used with a 16-bit register, the result is undefined. + \H{insBT} \i\c{BT}, \i\c{BTC}, \i\c{BTR}, \i\c{BTS}: Bit Test @@ -5995,7 +6763,19 @@ flag, \c{BTR} also resets (clears) the bit in the operand itself. \c{BTS} sets the bit, and \c{BTC} complements the bit. \c{BT} does not modify its operands. -The bit offset should be no greater than the size of the operand. +The destination can be a register or a memory location. The source can +be a register or an immediate value. + +If the destination operand is a register, the bit offset should be +in the range 0-15 (for 16-bit operands) or 0-31 (for 32-bit operands). +An immediate value outside these ranges will be taken modulo 16/32 +by the processor. + +If the destination operand is a memory location, then an immediate +bit offset follows the same rules as for a register. If the bit offset +is in a register, then it can be anything within the signed range of +the register used (ie, for a 32-bit operand, it can be (-2^31) to (2^31 - 1) + \H{insCALL} \i\c{CALL}: Call Subroutine @@ -6016,9 +6796,14 @@ call, i.e. a destination segment address is specified in the instruction. The forms involving two colon-separated arguments are far calls; so are the \c{CALL FAR mem} forms. -You can choose between the two immediate \i{far call} forms (\c{CALL -imm:imm}) by the use of the \c{WORD} and \c{DWORD} keywords: \c{CALL -WORD 0x1234:0x5678}) or \c{CALL DWORD 0x1234:0x56789abc}. +The immediate \i{near call} takes one of two forms (\c{call imm16/imm32}, +determined by the current segment size limit. For 16-bit operands, +you would use \c{CALL 0x1234}, and for 32-bit operands you would use +\c{CALL 0x12345678}. The value passed as an operand is a relative offset. + +You can choose between the two immediate \i{far call} forms +(\c{CALL imm:imm}) by the use of the \c{WORD} and \c{DWORD} keywords: +\c{CALL WORD 0x1234:0x5678}) or \c{CALL DWORD 0x1234:0x56789abc}. The \c{CALL FAR mem} forms execute a far call by loading the destination address out of memory. The address loaded consists of 16 @@ -6040,22 +6825,25 @@ The \c{CALL r/m} forms given above are near calls; NASM will accept the \c{NEAR} keyword (e.g. \c{CALL NEAR [address]}), even though it is not strictly necessary. + \H{insCBW} \i\c{CBW}, \i\c{CWD}, \i\c{CDQ}, \i\c{CWDE}: Sign Extensions \c CBW ; o16 98 [8086] +\c CWDE ; o32 98 [386] + \c CWD ; o16 99 [8086] \c CDQ ; o32 99 [386] -\c CWDE ; o32 98 [386] All these instructions sign-extend a short value into a longer one, by replicating the top bit of the original value to fill the extended one. \c{CBW} extends \c{AL} into \c{AX} by repeating the top bit of -\c{AL} in every bit of \c{AH}. \c{CWD} extends \c{AX} into \c{DX:AX} -by repeating the top bit of \c{AX} throughout \c{DX}. \c{CWDE} -extends \c{AX} into \c{EAX}, and \c{CDQ} extends \c{EAX} into -\c{EDX:EAX}. +\c{AL} in every bit of \c{AH}. \c{CWDE} extends \c{AX} into +\c{EAX}. \c{CWD} extends \c{AX} into \c{DX:AX} by repeating +the top bit of \c{AX} throughout \c{DX}, and \c{CDQ} extends +\c{EAX} into \c{EDX:EAX}. + \H{insCLC} \i\c{CLC}, \i\c{CLD}, \i\c{CLI}, \i\c{CLTS}: Clear Flags @@ -6073,6 +6861,24 @@ To set the carry, direction, or interrupt flags, use the \c{STC}, \c{STD} and \c{STI} instructions (\k{insSTC}). To invert the carry flag, use \c{CMC} (\k{insCMC}). + +\H{insCLFLUSH} \i\c{CLFLUSH}: Flush Cache Line + +\c CLFLUSH mem ; 0F AE /7 [WILLAMETTE,SSE2] + +\c{CLFLUSH} invlidates the cache line that contains the linear address +specified by the source operand from all levels of the processor cache +hierarchy (data and instruction). If, at any level of the cache +hierarchy, the line is inconsistent with memory (dirty) it is written +to memory before invalidation. The source operand points to a +byte-sized memory location. + +Although \c{CLFLUSH} is flagged \c{SSE2} and above, it may not be +present on all processors which have \c{SSE2} support, and it may be +supported on other processors; the \c{CPUID} instruction (\k{insCPUID}) +will return a bit which indicates support for the \c{CLFLUSH} instruction. + + \H{insCMC} \i\c{CMC}: Complement Carry Flag \c CMC ; F5 [8086] @@ -6080,6 +6886,7 @@ flag, use \c{CMC} (\k{insCMC}). \c{CMC} changes the value of the carry flag: if it was 0, it sets it to 1, and vice versa. + \H{insCMOVcc} \i\c{CMOVcc}: Conditional Move \c CMOVcc reg16,r/m16 ; o16 0F 40+cc /r [P6] @@ -6091,11 +6898,12 @@ it does nothing. For a list of condition codes, see \k{iref-cc}. -Although the \c{CMOV} instructions are flagged \c{P6} above, they +Although the \c{CMOV} instructions are flagged \c{P6} and above, they may not be supported by all Pentium Pro processors; the \c{CPUID} instruction (\k{insCPUID}) will return a bit which indicates whether conditional moves are supported. + \H{insCMP} \i\c{CMP}: Compare Integers \c CMP r/m8,reg8 ; 38 /r [8086] @@ -6128,100 +6936,95 @@ sign-extended to the length of the first operand. In these cases, the \c{BYTE} qualifier is necessary to force NASM to generate this form of the instruction. - -\H{insCMPEQPS} \i\c{CMPEQPS}: Packed Single FP Compare (CMPPS) - -\c CMPEQPS xmmreg,memory ; 0f c2 /r ib [KATMAI,SSE] -\c CMPEQPS xmmreg,xmmreg ; [KATMAI,SSE] - -\c{CMPPS} with condition set, re CMPPS. - -\H{insCMPEQSS} \i\c{CMPEQSS}: Scalar Single FP Compare (CMPSS) - -\c CMPEQSS xmmreg,memory ; ?? [KATMAI,SSE] -\c CMPEQSS xmmreg,xmmreg ; ?? [KATMAI,SSE] - -\c{CMPSS} with condition set, re CMPPS. - -\H{insCMPLEPS} \i\c{CMPLEPS}: Packed Single FP Compare (CMPPS) - -\c CMPLEPS xmmreg,memory ; ?? [KATMAI,SSE] -\c CMPLEPS xmmreg,xmmreg ; ?? [KATMAI,SSE] - - -\H{insCMPLESS} \i\c{CMPLESS}: Scalar Single FP Compare (CMPSS) - -\c CMPLESS xmmreg,memory ; ?? [KATMAI,SSE] -\c CMPLESS xmmreg,xmmreg ; ?? [KATMAI,SSE] - - -\H{insCMPLTPS} \i\c{CMPLTPS}: Packed Single FP Compare (CMPPS) - -\c CMPLTPS xmmreg,memory ; ?? [KATMAI,SSE] -\c CMPLTPS xmmreg,xmmreg ; ?? [KATMAI,SSE] - - -\H{insCMPLTSS} \i\c{CMPLTSS}: Scalar Single FP Compare (CMPSS) - -\c CMPLTSS xmmreg,memory ; ?? [KATMAI,SSE] -\c CMPLTSS xmmreg,xmmreg ; ?? [KATMAI,SSE] - - -\H{insCMPNEQPS} \i\c{CMPNEQPS}: Packed Single FP Compare (CMPPS) - -\c CMPNEQPS xmmreg,memory ; ?? [KATMAI,SSE] -\c CMPNEQPS xmmreg,xmmreg ; ?? [KATMAI,SSE] - - -\H{insCMPNEQSS} \i\c{CMPNEQSS}: Scalar Single FP Compare (CMPSS) - -\c CMPNEQSS xmmreg,memory ; ?? [KATMAI,SSE] -\c CMPNEQSS xmmreg,xmmreg ; ?? [KATMAI,SSE] - - -\H{insCMPNLEPS} \i\c{CMPNLEPS}: Packed Single FP Compare (CMPPS) - -\c CMPNLEPS xmmreg,memory ; ?? [KATMAI,SSE] -\c CMPNLEPS xmmreg,xmmreg ; ?? [KATMAI,SSE] - - -\H{insCMPNLESS} \i\c{CMPNLESS}: Scalar Single FP Compare (CMPSS) - -\c CMPNLESS xmmreg,memory ; ?? [KATMAI,SSE] -\c CMPNLESS xmmreg,xmmreg ; ?? [KATMAI,SSE] - - -\H{insCMPNLTPS} \i\c{CMPNLTPS}: Packed Single FP Compare (CMPPS) - -\c CMPNLTPS xmmreg,memory ; ?? [KATMAI,SSE] -\c CMPNLTPS xmmreg,xmmreg ; ?? [KATMAI,SSE] - - -\H{insCMPNLTSS} \i\c{CMPNLTSS}: Scalar Single FP Compare (CMPSS) - -\c CMPNLTSS xmmreg,memory ; ?? [KATMAI,SSE] -\c CMPNLTSS xmmreg,xmmreg ; ?? [KATMAI,SSE] - - -\H{insCMPORDPS} \i\c{CMPORDPS}: Packed Single FP Compare (CMPPS) - -\c CMPORDPS xmmreg,memory ; ?? [KATMAI,SSE] -\c CMPORDPS xmmreg,xmmreg ; ?? [KATMAI,SSE] - - -\H{insCMPORDSS} \i\c{CMPORDSS}: Scalar Single FP Compare (CMPSS) - -\c CMPORDSS xmmreg,memory ; ?? [KATMAI,SSE] -\c CMPORDSS xmmreg,xmmreg ; ?? [KATMAI,SSE] - - -\H{insCMPPS} \i\c{CMPPS}: Packed Single FP Compare - -\c CMPPS xmmreg,memory,immediate ; ?? [KATMAI,SSE,SB,AR2] -\c CMPPS xmmreg,xmmreg,immediate ; ?? [KATMAI,SSE,SB,AR2] - -\c{CMP(cc)PS} and \c{CMP(cc)SS} conditions (cc): -EQ, LT, LE, UNORD, NEQ, NLT, NLE, ORD +The destination operand can be a register or a memory location. The +source can be a register, memory location or an immediate value of +the same size as the destination. + + +\H{insCMPccPD} \i\c{CMPccPD}: Packed Double-Precision FP Compare +\I\c{CMPEQPD} \I\c{CMPLTPD} \I\c{CMPLEPD} \I\c{CMPUNORDPD} +\I\c{CMPNEQPD} \I\c{CMPNLTPD} \I\c{CMPNLEPD} \I\c{CMPORDPD} + +\c CMPPD xmm1,xmm2/mem128,imm8 ; 66 0F C2 /r ib [WILLAMETTE,SSE2] + +\c CMPEQPD xmm1,xmm2/mem128 ; 66 0F C2 /r 00 [WILLAMETTE,SSE2] +\c CMPLTPD xmm1,xmm2/mem128 ; 66 0F C2 /r 01 [WILLAMETTE,SSE2] +\c CMPLEPD xmm1,xmm2/mem128 ; 66 0F C2 /r 02 [WILLAMETTE,SSE2] +\c CMPUNORDPD xmm1,xmm2/mem128 ; 66 0F C2 /r 03 [WILLAMETTE,SSE2] +\c CMPNEQPD xmm1,xmm2/mem128 ; 66 0F C2 /r 04 [WILLAMETTE,SSE2] +\c CMPNLTPD xmm1,xmm2/mem128 ; 66 0F C2 /r 05 [WILLAMETTE,SSE2] +\c CMPNLEPD xmm1,xmm2/mem128 ; 66 0F C2 /r 06 [WILLAMETTE,SSE2] +\c CMPORDPD xmm1,xmm2/mem128 ; 66 0F C2 /r 07 [WILLAMETTE,SSE2] + +The \c{CMPccPD} instructions compare the two packed double-precision +FP values in the source and destination operands, and returns the +result of the comparison in the destination register. The result of +each comparison is a quadword mask of all 1s (comparison true) or +all 0s (comparison false). + +The destination is an \c{XMM} register. The source can be either an +\c{XMM} register or a 128-bit memory location. + +The third operand is an 8-bit immediate value, of which the low 3 +bits define the type of comparison. For ease of programming, the +8 two-operand pseudo-instructions are provided, with the third +operand already filled in. The \I{Condition Predicates} +\c{Condition Predicates} are: + +\c EQ 0 Equal +\c LT 1 Less-than +\c LE 2 Less-than-or-equal +\c UNORD 3 Unordered +\c NE 4 Not-equal +\c NLT 5 Not-less-than +\c NLE 6 Not-less-than-or-equal +\c ORD 7 Ordered + +For more details of the comparison predicates, and details of how +to emulate the "greater-than" equivalents, see \k{iref-SSE-cc} + + +\H{insCMPccPS} \i\c{CMPccPS}: Packed Single-Precision FP Compare +\I\c{CMPEQPS} \I\c{CMPLTPS} \I\c{CMPLEPS} \I\c{CMPUNORDPS} +\I\c{CMPNEQPS} \I\c{CMPNLTPS} \I\c{CMPNLEPS} \I\c{CMPORDPS} + +\c CMPPS xmm1,xmm2/mem128,imm8 ; 0F C2 /r ib [KATMAI,SSE] + +\c CMPEQPS xmm1,xmm2/mem128 ; 0F C2 /r 00 [KATMAI,SSE] +\c CMPLTPS xmm1,xmm2/mem128 ; 0F C2 /r 01 [KATMAI,SSE] +\c CMPLEPS xmm1,xmm2/mem128 ; 0F C2 /r 02 [KATMAI,SSE] +\c CMPUNORDPS xmm1,xmm2/mem128 ; 0F C2 /r 03 [KATMAI,SSE] +\c CMPNEQPS xmm1,xmm2/mem128 ; 0F C2 /r 04 [KATMAI,SSE] +\c CMPNLTPS xmm1,xmm2/mem128 ; 0F C2 /r 05 [KATMAI,SSE] +\c CMPNLEPS xmm1,xmm2/mem128 ; 0F C2 /r 06 [KATMAI,SSE] +\c CMPORDPS xmm1,xmm2/mem128 ; 0F C2 /r 07 [KATMAI,SSE] + +The \c{CMPccPS} instructions compare the two packed single-precision +FP values in the source and destination operands, and returns the +result of the comparison in the destination register. The result of +each comparison is a doubleword mask of all 1s (comparison true) or +all 0s (comparison false). + +The destination is an \c{XMM} register. The source can be either an +\c{XMM} register or a 128-bit memory location. + +The third operand is an 8-bit immediate value, of which the low 3 +bits define the type of comparison. For ease of programming, the +8 two-operand pseudo-instructions are provided, with the third +operand already filled in. The \I{Condition Predicates} +\c{Condition Predicates} are: + +\c EQ 0 Equal +\c LT 1 Less-than +\c LE 2 Less-than-or-equal +\c UNORD 3 Unordered +\c NE 4 Not-equal +\c NLT 5 Not-less-than +\c NLE 6 Not-less-than-or-equal +\c ORD 7 Ordered + +For more details of the comparison predicates, and details of how +to emulate the "greater-than" equivalents, see \k{iref-SSE-cc} \H{insCMPSB} \i\c{CMPSB}, \i\c{CMPSW}, \i\c{CMPSD}: Compare Strings @@ -6243,7 +7046,7 @@ use an explicit \i\c{a16} or \i\c{a32} prefix. The segment register used to load from \c{[SI]} or \c{[ESI]} can be overridden by using a segment register name as a prefix (for -example, \c{es cmpsb}). The use of \c{ES} for the load from \c{[DI]} +example, \c{ES CMPSB}). The use of \c{ES} for the load from \c{[DI]} or \c{[EDI]} cannot be overridden. \c{CMPSW} and \c{CMPSD} work in the same way, but they compare a @@ -6256,30 +7059,90 @@ The \c{REPE} and \c{REPNE} prefixes (equivalently, \c{REPZ} and first unequal or equal byte is found. - -\H{insCMPSS} \i\c{CMPSS}: Scalar Single FP Compare - -\c CMPSS xmmreg,memory,immediate ; ?? [KATMAI,SSE,SB,AR2] -\c CMPSS xmmreg,xmmreg,immediate ; ?? [KATMAI,SSE,SB,AR2] - -\c{CMP(cc)PS} and \c{CMP(cc)SS} conditions (cc): -EQ, LT, LE, UNORD, NEQ, NLT, NLE, ORD - - -\H{insCMPUNORDPS} \i\c{CMPUNORDPS}: Packed Single FP Compare - - (CMPPS) - -\c CMPUNORDPS xmmreg,memory ; ?? [KATMAI,SSE] -\c CMPUNORDPS xmmreg,xmmreg ; ?? [KATMAI,SSE] - - -\H{insCMPUNORDSS} \i\c{CMPUNORDSS}: Scalar Single FP Compare - - (CMPSS) - -\c CMPUNORDSS xmmreg,memory ; ?? [KATMAI,SSE] -\c CMPUNORDSS xmmreg,xmmreg ; ?? [KATMAI,SSE] +\H{insCMPccSD} \i\c{CMPccSD}: Scalar Double-Precision FP Compare +\I\c{CMPEQSD} \I\c{CMPLTSD} \I\c{CMPLESD} \I\c{CMPUNORDSD} +\I\c{CMPNEQSD} \I\c{CMPNLTSD} \I\c{CMPNLESD} \I\c{CMPORDSD} + +\c CMPSD xmm1,xmm2/mem64,imm8 ; F2 0F C2 /r ib [WILLAMETTE,SSE2] + +\c CMPEQSD xmm1,xmm2/mem64 ; F2 0F C2 /r 00 [WILLAMETTE,SSE2] +\c CMPLTSD xmm1,xmm2/mem64 ; F2 0F C2 /r 01 [WILLAMETTE,SSE2] +\c CMPLESD xmm1,xmm2/mem64 ; F2 0F C2 /r 02 [WILLAMETTE,SSE2] +\c CMPUNORDSD xmm1,xmm2/mem64 ; F2 0F C2 /r 03 [WILLAMETTE,SSE2] +\c CMPNEQSD xmm1,xmm2/mem64 ; F2 0F C2 /r 04 [WILLAMETTE,SSE2] +\c CMPNLTSD xmm1,xmm2/mem64 ; F2 0F C2 /r 05 [WILLAMETTE,SSE2] +\c CMPNLESD xmm1,xmm2/mem64 ; F2 0F C2 /r 06 [WILLAMETTE,SSE2] +\c CMPORDSD xmm1,xmm2/mem64 ; F2 0F C2 /r 07 [WILLAMETTE,SSE2] + +The \c{CMPccSD} instructions compare the low-order double-precision +FP values in the source and destination operands, and returns the +result of the comparison in the destination register. The result of +each comparison is a quadword mask of all 1s (comparison true) or +all 0s (comparison false). + +The destination is an \c{XMM} register. The source can be either an +\c{XMM} register or a 128-bit memory location. + +The third operand is an 8-bit immediate value, of which the low 3 +bits define the type of comparison. For ease of programming, the +8 two-operand pseudo-instructions are provided, with the third +operand already filled in. The \I{Condition Predicates} +\c{Condition Predicates} are: + +\c EQ 0 Equal +\c LT 1 Less-than +\c LE 2 Less-than-or-equal +\c UNORD 3 Unordered +\c NE 4 Not-equal +\c NLT 5 Not-less-than +\c NLE 6 Not-less-than-or-equal +\c ORD 7 Ordered + +For more details of the comparison predicates, and details of how +to emulate the "greater-than" equivalents, see \k{iref-SSE-cc} + + +\H{insCMPccSS} \i\c{CMPccSS}: Scalar Single-Precision FP Compare +\I\c{CMPEQSS} \I\c{CMPLTSS} \I\c{CMPLESS} \I\c{CMPUNORDSS} +\I\c{CMPNEQSS} \I\c{CMPNLTSS} \I\c{CMPNLESS} \I\c{CMPORDSS} + +\c CMPSS xmm1,xmm2/mem32,imm8 ; F3 0F C2 /r ib [KATMAI,SSE] + +\c CMPEQSS xmm1,xmm2/mem32 ; F3 0F C2 /r 00 [KATMAI,SSE] +\c CMPLTSS xmm1,xmm2/mem32 ; F3 0F C2 /r 01 [KATMAI,SSE] +\c CMPLESS xmm1,xmm2/mem32 ; F3 0F C2 /r 02 [KATMAI,SSE] +\c CMPUNORDSS xmm1,xmm2/mem32 ; F3 0F C2 /r 03 [KATMAI,SSE] +\c CMPNEQSS xmm1,xmm2/mem32 ; F3 0F C2 /r 04 [KATMAI,SSE] +\c CMPNLTSS xmm1,xmm2/mem32 ; F3 0F C2 /r 05 [KATMAI,SSE] +\c CMPNLESS xmm1,xmm2/mem32 ; F3 0F C2 /r 06 [KATMAI,SSE] +\c CMPORDSS xmm1,xmm2/mem32 ; F3 0F C2 /r 07 [KATMAI,SSE] + +The \c{CMPccSS} instructions compare the low-order single-precision +FP values in the source and destination operands, and returns the +result of the comparison in the destination register. The result of +each comparison is a doubleword mask of all 1s (comparison true) or +all 0s (comparison false). + +The destination is an \c{XMM} register. The source can be either an +\c{XMM} register or a 128-bit memory location. + +The third operand is an 8-bit immediate value, of which the low 3 +bits define the type of comparison. For ease of programming, the +8 two-operand pseudo-instructions are provided, with the third +operand already filled in. The \I{Condition Predicates} +\c{Condition Predicates} are: + +\c EQ 0 Equal +\c LT 1 Less-than +\c LE 2 Less-than-or-equal +\c UNORD 3 Unordered +\c NE 4 Not-equal +\c NLT 5 Not-less-than +\c NLE 6 Not-less-than-or-equal +\c ORD 7 Ordered + +For more details of the comparison predicates, and details of how +to emulate the "greater-than" equivalents, see \k{iref-SSE-cc} \H{insCMPXCHG} \i\c{CMPXCHG}, \i\c{CMPXCHG486}: Compare and Exchange @@ -6298,16 +7161,19 @@ non-standard opcode, so NASM provides the undocumented \c{CMPXCHG486} form to generate the non-standard opcode. \c{CMPXCHG} compares its destination (first) operand to the value in -\c{AL}, \c{AX} or \c{EAX} (depending on the size of the +\c{AL}, \c{AX} or \c{EAX} (depending on the operand size of the instruction). If they are equal, it copies its source (second) operand into the destination and sets the zero flag. Otherwise, it clears the zero flag and leaves the destination alone. +The destination can be either a register or a memory location. The +source is a register. + \c{CMPXCHG} is intended to be used for atomic operations in multitasking or multiprocessor environments. To safely update a value in shared memory, for example, you might load the value into \c{EAX}, load the updated value into \c{EBX}, and then execute the -instruction \c{lock cmpxchg [value],ebx}. If \c{value} has not +instruction \c{LOCK CMPXCHG [value],EBX}. If \c{value} has not changed since being loaded, it is updated with your desired new value, and the zero flag is set to let you know it has worked. (The \c{LOCK} prefix prevents another processor doing anything in the @@ -6317,6 +7183,7 @@ your attempted store, the store does not happen, and you are notified of the failure by a cleared zero flag, so you can go round and try again. + \H{insCMPXCHG8B} \i\c{CMPXCHG8B}: Compare and Exchange Eight Bytes \c CMPXCHG8B mem ; 0F C7 /1 [PENT] @@ -6327,13 +7194,54 @@ value in \c{EDX:EAX}. If they are equal, it sets the zero flag and stores \c{ECX:EBX} into the memory area. If they are unequal, it clears the zero flag and leaves the memory area untouched. -\H{insCOMISS} \i\c{COMISS}: Scalar Ordered Single-FP Compare and Set EFLAGS +\c{CMPXCHG8B} can be used with the \c{LOCK} prefix, to allow atomic +execution. This is useful in multi-processor and multi-tasking +environments. + + +\H{insCOMISD} \i\c{COMISD}: Scalar Ordered Double-Precision FP Compare and Set EFLAGS + +\c COMISD xmm1,xmm2/mem64 ; 66 0F 2F /r [WILLAMETTE,SSE2] + +\c{COMISD} compares the low-order double-precision FP value in the +two source operands. ZF, PF and CF are set according to the result. +OF, AF and AF are cleared. The unordered result is returned if either +source is a NaN (QNaN or SNaN). + +The destination operand is an \c{XMM} register. The source can be either +an \c{XMM} register or a memory location. + +The flags are set according to the following rules: + +\c Result Flags Values + +\c UNORDERED: ZF,PF,CF <-- 111; +\c GREATER_THAN: ZF,PF,CF <-- 000; +\c LESS_THAN: ZF,PF,CF <-- 001; +\c EQUAL: ZF,PF,CF <-- 100; + + +\H{insCOMISS} \i\c{COMISS}: Scalar Ordered Single-Precision FP Compare and Set EFLAGS + +\c COMISS xmm1,xmm2/mem32 ; 66 0F 2F /r [KATMAI,SSE] + +\c{COMISS} compares the low-order single-precision FP value in the +two source operands. ZF, PF and CF are set according to the result. +OF, AF and AF are cleared. The unordered result is returned if either +source is a NaN (QNaN or SNaN). -\c COMISS xmmreg,memory ; ?? [KATMAI,SSE] -\c COMISS xmmreg,xmmreg ; ?? [KATMAI,SSE] +The destination operand is an \c{XMM} register. The source can be either +an \c{XMM} register or a memory location. + +The flags are set according to the following rules: + +\c Result Flags Values + +\c UNORDERED: ZF,PF,CF <-- 111; +\c GREATER_THAN: ZF,PF,CF <-- 000; +\c LESS_THAN: ZF,PF,CF <-- 001; +\c EQUAL: ZF,PF,CF <-- 100; -Set Z, P, C according to comparison, clear O, S, A bits of EFLAGS. -Z=P=C=1 for "unordered" result (QNaN). \H{insCPUID} \i\c{CPUID}: Get CPU Identification Code @@ -6365,57 +7273,354 @@ feature flags, showing the presence and absence of various features. For example, bit 8 is set if the \c{CMPXCHG8B} instruction (\k{insCMPXCHG8B}) is supported, bit 15 is set if the conditional move instructions (\k{insCMOVcc} and \k{insFCMOVB}) are supported, -and bit 23 is set if MMX instructions are supported. +and bit 23 is set if \c{MMX} instructions are supported. \b If \c{EAX} is two on input, \c{EAX}, \c{EBX}, \c{ECX} and \c{EDX} all contain information about caches and TLBs (Translation Lookahead Buffers). For more information on the data returned from \c{CPUID}, see the -documentation on Intel's web site. +documentation from Intel and other processor manufacturers. + + +\H{insCVTDQ2PD} \i\c{CVTDQ2PD}: +Packed Signed INT32 to Packed Double-Precision FP Conversion + +\c CVTDQ2PD xmm1,xmm2/mem64 ; F3 0F E6 /r [WILLAMETTE,SSE2] + +\c{CVTDQ2PD} converts two packed signed doublewords from the source +operand to two packed double-precision FP values in the destination +operand. + +The destination operand is an \c{XMM} register. The source can be +either an \c{XMM} register or a 64-bit memory location. If the +source is a register, the packed integers are in the low quadword. + + +\H{insCVTDQ2PS} \i\c{CVTDQ2PS}: +Packed Signed INT32 to Packed Single-Precision FP Conversion + +\c CVTDQ2PS xmm1,xmm2/mem128 ; 0F 5B /r [WILLAMETTE,SSE2] + +\c{CVTDQ2PS} converts four packed signed doublewords from the source +operand to four packed single-precision FP values in the destination +operand. + +The destination operand is an \c{XMM} register. The source can be +either an \c{XMM} register or a 128-bit memory location. + +For more details of this instruction, see the Intel Processor manuals. + + +\H{insCVTPD2DQ} \i\c{CVTPD2DQ}: +Packed Double-Precision FP to Packed Signed INT32 Conversion + +\c CVTPD2DQ xmm1,xmm2/mem128 ; F2 0F E6 /r [WILLAMETTE,SSE2] + +\c{CVTPD2DQ} converts two packed double-precision FP values from the +source operand to two packed signed doublewords in the low quadword +of the destination operand. The high quadword of the destination is +set to all 0s. + +The destination operand is an \c{XMM} register. The source can be +either an \c{XMM} register or a 128-bit memory location. + +For more details of this instruction, see the Intel Processor manuals. + + +\H{insCVTPD2PI} \i\c{CVTPD2PI}: +Packed Double-Precision FP to Packed Signed INT32 Conversion + +\c CVTPD2PI mm,xmm/mem128 ; 66 0F 2D /r [WILLAMETTE,SSE2] + +\c{CVTPD2PI} converts two packed double-precision FP values from the +source operand to two packed signed doublewords in the destination +operand. + +The destination operand is an \c{MMX} register. The source can be +either an \c{XMM} register or a 128-bit memory location. + +For more details of this instruction, see the Intel Processor manuals. + + +\H{insCVTPD2PS} \i\c{CVTPD2PS}: +Packed Double-Precision FP to Packed Single-Precision FP Conversion + +\c CVTPD2PS xmm1,xmm2/mem128 ; 66 0F 5A /r [WILLAMETTE,SSE2] + +\c{CVTPD2PS} converts two packed double-precision FP values from the +source operand to two packed single-precision FP values in the low +quadword of the destination operand. The high quadword of the +destination is set to all 0s. + +The destination operand is an \c{XMM} register. The source can be +either an \c{XMM} register or a 128-bit memory location. + +For more details of this instruction, see the Intel Processor manuals. + + +\H{insCVTPI2PD} \i\c{CVTPI2PD}: +Packed Signed INT32 to Packed Double-Precision FP Conversion + +\c CVTPI2PD xmm,mm/mem64 ; 66 0F 2A /r [WILLAMETTE,SSE2] + +\c{CVTPI2PD} converts two packed signed doublewords from the source +operand to two packed double-precision FP values in the destination +operand. + +The destination operand is an \c{XMM} register. The source can be +either an \c{MMX} register or a 64-bit memory location. + +For more details of this instruction, see the Intel Processor manuals. \H{insCVTPI2PS} \i\c{CVTPI2PS}: Packed Signed INT32 to Packed Single-FP Conversion -\c CVTPI2PS xmmreg,mem64 ; ?? [KATMAI,SSE,MMX] -\c CVTPI2PS xmmreg,mmxreg ; ?? [KATMAI,SSE,MMX] +\c CVTPI2PS xmm,mm/mem64 ; 0F 2A /r [KATMAI,SSE] + +\c{CVTPI2PS} converts two packed signed doublewords from the source +operand to two packed single-precision FP values in the low quadword +of the destination operand. The high quadword of the destination +remains unchanged. + +The destination operand is an \c{XMM} register. The source can be +either an \c{MMX} register or a 64-bit memory location. + +For more details of this instruction, see the Intel Processor manuals. + + +\H{insCVTPS2DQ} \i\c{CVTPS2DQ}: +Packed Single-Precision FP to Packed Signed INT32 Conversion + +\c CVTPS2DQ xmm1,xmm2/mem128 ; 66 0F 5B /r [WILLAMETTE,SSE2] + +\c{CVTPS2DQ} converts four packed single-precision FP values from the +source operand to four packed signed doublewords in the destination operand. + +The destination operand is an \c{XMM} register. The source can be +either an \c{XMM} register or a 128-bit memory location. + +For more details of this instruction, see the Intel Processor manuals. + + +\H{insCVTPS2PD} \i\c{CVTPS2PD}: +Packed Single-Precision FP to Packed Double-Precision FP Conversion + +\c CVTPS2PD xmm1,xmm2/mem64 ; 0F 5A /r [WILLAMETTE,SSE2] + +\c{CVTPS2PD} converts two packed single-precision FP values from the +source operand to two packed double-precision FP values in the destination +operand. + +The destination operand is an \c{XMM} register. The source can be +either an \c{XMM} register or a 64-bit memory location. If the source +is a register, the input values are in the low quadword. + +For more details of this instruction, see the Intel Processor manuals. \H{insCVTPS2PI} \i\c{CVTPS2PI}: -Packed Single-FP to Packed INT32 Conversion +Packed Single-Precision FP to Packed Signed INT32 Conversion + +\c CVTPS2PI mm,xmm/mem64 ; 0F 2D /r [KATMAI,SSE] + +\c{CVTPS2PI} converts two packed single-precision FP values from +the source operand to two packed signed doublewords in the destination +operand. -\c CVTPS2PI mmxreg,mem64 ; ?? [KATMAI,SSE,MMX] -\c CVTPS2PI mmxreg,xmmreg ; ?? [KATMAI,SSE,MMX] +The destination operand is an \c{MMX} register. The source can be +either an \c{XMM} register or a 64-bit memory location. If the +source is a register, the input values are in the low quadword. + +For more details of this instruction, see the Intel Processor manuals. + + +\H{insCVTSD2SI} \i\c{CVTSD2SI}: +Scalar Double-Precision FP to Signed INT32 Conversion + +\c CVTSD2SI reg32,xmm/mem64 ; F2 0F 2D /r [WILLAMETTE,SSE2] + +\c{CVTSD2SI} converts a double-precision FP value from the source +operand to a signed doubleword in the destination operand. + +The destination operand is a general purpose register. The source can be +either an \c{XMM} register or a 64-bit memory location. If the +source is a register, the input value is in the low quadword. + +For more details of this instruction, see the Intel Processor manuals. + + +\H{insCVTSD2SS} \i\c{CVTSD2SS}: +Scalar Double-Precision FP to Scalar Single-Precision FP Conversion + +\c CVTSD2SS xmm1,xmm2/mem64 ; F2 0F 5A /r [KATMAI,SSE] + +\c{CVTSD2SS} converts a double-precision FP value from the source +operand to a single-precision FP value in the low doubleword of the +destination operand. The upper 3 doublewords are left unchanged. + +The destination operand is an \c{XMM} register. The source can be +either an \c{XMM} register or a 64-bit memory location. If the +source is a register, the input value is in the low quadword. + +For more details of this instruction, see the Intel Processor manuals. + + +\H{insCVTSI2SD} \i\c{CVTSI2SD}: +Signed INT32 to Scalar Double-Precision FP Conversion + +\c CVTSI2SD xmm,r/m32 ; F2 0F 2A /r [WILLAMETTE,SSE2] + +\c{CVTSI2SD} converts a signed doubleword from the source operand to +a double-precision FP value in the low quadword of the destination +operand. The high quadword is left unchanged. + +The destination operand is an \c{XMM} register. The source can be either +a general purpose register or a 32-bit memory location. + +For more details of this instruction, see the Intel Processor manuals. \H{insCVTSI2SS} \i\c{CVTSI2SS}: -Scalar Signed INT32 to Single-FP Conversion +Signed INT32 to Scalar Single-Precision FP Conversion + +\c CVTSI2SS xmm,r/m32 ; F3 0F 2A /r [KATMAI,SSE] -\c CVTSI2SS xmmreg,memory ; ?? [KATMAI,SSE,SD,AR1] -\c CVTSI2SS xmmreg,reg32 ; ?? [KATMAI,SSE] +\c{CVTSI2SS} converts a signed doubleword from the source operand to a +single-precision FP value in the low doubleword of the destination operand. +The upper 3 doublewords are left unchanged. +The destination operand is an \c{XMM} register. The source can be either +a general purpose register or a 32-bit memory location. + +For more details of this instruction, see the Intel Processor manuals. + + +\H{insCVTSS2SD} \i\c{CVTSS2SD}: +Scalar Single-Precision FP to Scalar Double-Precision FP Conversion + +\c CVTSS2SD xmm1,xmm2/mem32 ; F3 0F 5A /r [WILLAMETTE,SSE2] + +\c{CVTSS2SD} converts a single-precision FP value from the source operand +to a double-precision FP value in the low quadword of the destination +operand. The upper quadword is left unchanged. + +The destination operand is an \c{XMM} register. The source can be either +an \c{XMM} register or a 32-bit memory location. If the source is a +register, the input value is contained in the low doubleword. + +For more details of this instruction, see the Intel Processor manuals. \H{insCVTSS2SI} \i\c{CVTSS2SI}: -Scalar Single-FP to Signed INT32 Conversion +Scalar Single-Precision FP to Signed INT32 Conversion + +\c CVTSS2SI reg32,xmm/mem32 ; F3 0F 2D /r [KATMAI,SSE] + +\c{CVTSS2SI} converts a single-precision FP value from the source +operand to a signed doubleword in the destination operand. + +The destination operand is a general purpose register. The source can be +either an \c{XMM} register or a 32-bit memory location. If the +source is a register, the input value is in the low doubleword. + +For more details of this instruction, see the Intel Processor manuals. + + +\H{insCVTTPD2DQ} \i\c{CVTTPD2DQ}: +Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation + +\c CVTTPD2DQ xmm1,xmm2/mem128 ; 66 0F E6 /r [WILLAMETTE,SSE2] + +\c{CVTTPD2DQ} converts two packed double-precision FP values in the source +operand to two packed single-precision FP values in the destination operand. +If the result is inexact, it is truncated (rounded toward zero). The high +quadword is set to all 0s. + +The destination operand is an \c{XMM} register. The source can be +either an \c{XMM} register or a 128-bit memory location. + +For more details of this instruction, see the Intel Processor manuals. + + +\H{insCVTTPD2PI} \i\c{CVTTPD2PI}: +Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation + +\c CVTTPD2PI mm,xmm/mem128 ; 66 0F 2C /r [WILLAMETTE,SSE2] -\c CVTSS2SI reg32,memory ; ?? [KATMAI,SSE] -\c CVTSS2SI reg32,xmmreg ; ?? [KATMAI,SSE] +\c{CVTTPD2PI} converts two packed double-precision FP values in the source +operand to two packed single-precision FP values in the destination operand. +If the result is inexact, it is truncated (rounded toward zero). + +The destination operand is an \c{MMX} register. The source can be +either an \c{XMM} register or a 128-bit memory location. + +For more details of this instruction, see the Intel Processor manuals. + + +\H{insCVTTPS2DQ} \i\c{CVTTPS2DQ}: +Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation + +\c CVTTPS2DQ xmm1,xmm2/mem128 ; F3 0F 5B /r [WILLAMETTE,SSE2] + +\c{CVTTPS2DQ} converts four packed single-precision FP values in the source +operand to four packed signed doublewords in the destination operand. +If the result is inexact, it is truncated (rounded toward zero). + +The destination operand is an \c{XMM} register. The source can be +either an \c{XMM} register or a 128-bit memory location. + +For more details of this instruction, see the Intel Processor manuals. \H{insCVTTPS2PI} \i\c{CVTTPS2PI}: -Packed Single-FP to Packed INT32 Conversion +Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation + +\c CVTTPS2PI mm,xmm/mem64 ; 0F 2C /r [KATMAI,SSE] + +\c{CVTTPS2PI} converts two packed single-precision FP values in the source +operand to two packed signed doublewords in the destination operand. +If the result is inexact, it is truncated (rounded toward zero). If +the source is a register, the input values are in the low quadword. -\c CVTTPS2PI mmxreg,memory ; ?? [KATMAI,SSE,MMX] -\c CVTTPS2PI mmxreg,xmmreg ; ?? [KATMAI,SSE,MMX] +The destination operand is an \c{MMX} register. The source can be +either an \c{XMM} register or a 64-bit memory location. If the source +is a register, the input value is in the low quadword. + +For more details of this instruction, see the Intel Processor manuals. + + +\H{insCVTTSD2SI} \i\c{CVTTSD2SI}: +Scalar Double-Precision FP to Signed INT32 Conversion with Truncation + +\c CVTTSD2SI reg32,xmm/mem64 ; F2 0F 2C /r [WILLAMETTE,SSE2] + +\c{CVTTSD2SI} converts a double-precision FP value in the source operand +to a signed doubleword in the destination operand. If the result is +inexact, it is truncated (rounded toward zero). + +The destination operand is a general purpose register. The source can be +either an \c{XMM} register or a 64-bit memory location. If the source is a +register, the input value is in the low quadword. + +For more details of this instruction, see the Intel Processor manuals. \H{insCVTTSS2SI} \i\c{CVTTSS2SI}: -Scalr Single-FP to Signed INT32 Conversion +Scalar Single-Precision FP to Signed INT32 Conversion with Truncation + +\c CVTTSD2SI reg32,xmm/mem32 ; F3 0F 2C /r [KATMAI,SSE] + +\c{CVTTSS2SI} converts a single-precision FP value in the source operand +to a signed doubleword in the destination operand. If the result is +inexact, it is truncated (rounded toward zero). + +The destination operand is a general purpose register. The source can be +either an \c{XMM} register or a 32-bit memory location. If the source is a +register, the input value is in the low doubleword. -\c CVTTSS2SI reg32,memory ; ?? [KATMAI,SSE] -\c CVTTSS2SI reg32,xmmreg ; ?? [KATMAI,SSE] +For more details of this instruction, see the Intel Processor manuals. \H{insDAA} \i\c{DAA}, \i\c{DAS}: Decimal Adjustments @@ -6440,6 +7645,7 @@ of digits. \c{DAS} works similarly to \c{DAA}, but is for use after \c{SUB} instructions rather than \c{ADD}. + \H{insDEC} \i\c{DEC}: Decrement Integer \c DEC reg16 ; o16 48+r [8086] @@ -6450,7 +7656,13 @@ instructions rather than \c{ADD}. \c{DEC} subtracts 1 from its operand. It does \e{not} affect the carry flag: to affect the carry flag, use \c{SUB something,1} (see -\k{insSUB}). See also \c{INC} (\k{insINC}). +\k{insSUB}). \c{DEC} affects all the other flags according to the result. + +This instruction can be used with a \c{LOCK} prefix to allow atomic +execution. + +See also \c{INC} (\k{insINC}). + \H{insDIV} \i\c{DIV}: Unsigned Integer Divide @@ -6474,39 +7686,88 @@ the quotient is stored in \c{EAX} and the remainder in \c{EDX}. Signed integer division is performed by the \c{IDIV} instruction: see \k{insIDIV}. -\H{insDIVPS} \i\c{DIVPS}: Packed Single-FP Divide -\c DIVPS xmmreg,memory ; 0F,5E,/r [KATMAI,SSE] -\c DIVPS xmmreg,xmmreg ; ?? [KATMAI,SSE] +\H{insDIVPD} \i\c{DIVPD}: Packed Double-Precision FP Divide + +\c DIVPD xmm1,xmm2/mem128 ; 66 0F 5E /r [WILLAMETTE,SSE2] + +\c{DIVPD} divides the two packed double-precision FP values in +the destination operand by the two packed double-precision FP +values in the source operand, and stores the packed double-precision +results in the destination register. + +The destination is an \c{XMM} register. The source operand can be +either an \c{XMM} register or a 128-bit memory location. + +\c dst[0-63] := dst[0-63] / src[0-63], +\c dst[64-127] := dst[64-127] / src[64-127]. + + +\H{insDIVPS} \i\c{DIVPS}: Packed Single-Precision FP Divide + +\c DIVPS xmm1,xmm2/mem128 ; 0F 5E /r [KATMAI,SSE] + +\c{DIVPD} divides the four packed single-precision FP values in +the destination operand by the four packed single-precision FP +values in the source operand, and stores the packed single-precision +results in the destination register. + +The destination is an \c{XMM} register. The source operand can be +either an \c{XMM} register or a 128-bit memory location. + +\c dst[0-31] := dst[0-31] / src[0-31], +\c dst[32-63] := dst[32-63] / src[32-63], +\c dst[64-95] := dst[64-95] / src[64-95], +\c dst[96-127] := dst[96-127] / src[96-127]. + + +\H{insDIVSD} \i\c{DIVPD}: Scalar Double-Precision FP Divide + +\c DIVSD xmm1,xmm2/mem64 ; F2 0F 5E /r [WILLAMETTE,SSE2] + +\c{DIVSD} divides the low-order double-precision FP value in the +destination operand by the low-order double-precision FP value in +the source operand, and stores the double-precision result in the +destination register. + +The destination is an \c{XMM} register. The source operand can be +either an \c{XMM} register or a 64-bit memory location. + +\c dst[0-63] := dst[0-63] / src[0-63], +\c dst[64-127] remains unchanged. -\c{DIVPS}The DIVPS instruction divides the packed SP FP numbers -of both their operands. +\H{insDIVSS} \i\c{DIVSS}: Scalar Single-Precision FP Divide -\H{insDIVSS} \i\c{DIVSS}: Scalar Single-FP Divide +\c DIVSS xmm1,xmm2/mem32 ; F3 0F 5E /r [KATMAI,SSE] -\c DIVSS xmmreg,memory ; F3,0F,5E,/r [KATMAI,SSE] -\c DIVSS xmmreg,xmmreg ; ?? [KATMAI,SSE] +\c{DIVSS} divides the low-order single-precision FP value in the +destination operand by the low-order single-precision FP value in +the source operand, and stores the single-precision result in the +destination register. -\c{DIVSS}-The DIVSS instructions divide the lowest SP FP numbers -of both operands; the upper three fields are passed through from xmm1. +The destination is an \c{XMM} register. The source operand can be +either an \c{XMM} register or a 32-bit memory location. + +\c dst[0-31] := dst[0-31] / src[0-31], +\c dst[32-127] remains unchanged. \H{insEMMS} \i\c{EMMS}: Empty MMX State \c EMMS ; 0F 77 [PENT,MMX] -\c{EMMS} sets the FPU tag word (marking which floating-point -registers are available) to all ones, meaning all registers are -available for the FPU to use. It should be used after executing MMX -instructions and before executing any subsequent floating-point -operations. +\c{EMMS} sets the FPU tag word (marking which floating-point registers +are available) to all ones, meaning all registers are available for +the FPU to use. It should be used after executing \c{MMX} instructions +and before executing any subsequent floating-point operations. + \H{insENTER} \i\c{ENTER}: Create Stack Frame \c ENTER imm,imm ; C8 iw ib [186] -\c{ENTER} constructs a stack frame for a high-level language +\c{ENTER} constructs a \i\c{stack frame} for a high-level language procedure call. The first operand (the \c{iw} in the opcode definition above refers to the first operand) gives the amount of stack space to allocate for local variables; the second (the \c{ib} @@ -6540,20 +7801,23 @@ for nesting levels up to 31. Stack frames created by \c{ENTER} can be destroyed by the \c{LEAVE} instruction: see \k{insLEAVE}. + \H{insF2XM1} \i\c{F2XM1}: Calculate 2**X-1 \c F2XM1 ; D9 F0 [8086,FPU] \c{F2XM1} raises 2 to the power of \c{ST0}, subtracts one, and stores the result back into \c{ST0}. The initial contents of \c{ST0} -must be a number in the range -1 to +1. +must be a number in the range -1.0 to +1.0. + \H{insFABS} \i\c{FABS}: Floating-Point Absolute Value \c FABS ; D9 E1 [8086,FPU] -\c{FABS} computes the absolute value of \c{ST0}, storing the result -back in \c{ST0}. +\c{FABS} computes the absolute value of \c{ST0},by clearing the sign +bit, and stores the result back in \c{ST0}. + \H{insFADD} \i\c{FADD}, \i\c{FADDP}: Floating-Point Addition @@ -6569,15 +7833,19 @@ back in \c{ST0}. \c FADDP fpureg ; DE C0+r [8086,FPU] \c FADDP fpureg,ST0 ; DE C0+r [8086,FPU] -\c{FADD}, given one operand, adds the operand to \c{ST0} and stores +\b \c{FADD}, given one operand, adds the operand to \c{ST0} and stores the result back in \c{ST0}. If the operand has the \c{TO} modifier, the result is stored in the register given rather than in \c{ST0}. -\c{FADDP} performs the same function as \c{FADD TO}, but pops the +\b \c{FADDP} performs the same function as \c{FADD TO}, but pops the register stack after storing the result. The given two-operand forms are synonyms for the one-operand forms. +To add an integer value to \c{ST0}, use the c{FIADD} instruction +(\k{insFIADD}) + + \H{insFBLD} \i\c{FBLD}, \i\c{FBSTP}: BCD Floating-Point Load and Store \c FBLD mem80 ; DF /4 [8086,FPU] @@ -6589,12 +7857,14 @@ pushes it on the register stack. \c{FBSTP} stores the value of \c{ST0}, in packed BCD, at the given address and then pops the register stack. + \H{insFCHS} \i\c{FCHS}: Floating-Point Change Sign \c FCHS ; D9 E0 [8086,FPU] -\c{FCHS} negates the number in \c{ST0}: negative numbers become -positive, and vice versa. +\c{FCHS} negates the number in \c{ST0}, by inverting the sign bit: +negative numbers become positive, and vice versa. + \H{insFCLEX} \i\c{FCLEX}, \c{FNCLEX}: Clear Floating-Point Exceptions @@ -6606,32 +7876,33 @@ positive, and vice versa. floating-point operations (including the \e{handling} of pending exceptions) to finish first. + \H{insFCMOVB} \i\c{FCMOVcc}: Floating-Point Conditional Move \c FCMOVB fpureg ; DA C0+r [P6,FPU] \c FCMOVB ST0,fpureg ; DA C0+r [P6,FPU] +\c FCMOVE fpureg ; DA C8+r [P6,FPU] +\c FCMOVE ST0,fpureg ; DA C8+r [P6,FPU] + \c FCMOVBE fpureg ; DA D0+r [P6,FPU] \c FCMOVBE ST0,fpureg ; DA D0+r [P6,FPU] -\c FCMOVE fpureg ; DA C8+r [P6,FPU] -\c FCMOVE ST0,fpureg ; DA C8+r [P6,FPU] +\c FCMOVU fpureg ; DA D8+r [P6,FPU] +\c FCMOVU ST0,fpureg ; DA D8+r [P6,FPU] \c FCMOVNB fpureg ; DB C0+r [P6,FPU] \c FCMOVNB ST0,fpureg ; DB C0+r [P6,FPU] -\c FCMOVNBE fpureg ; DB D0+r [P6,FPU] -\c FCMOVNBE ST0,fpureg ; DB D0+r [P6,FPU] - \c FCMOVNE fpureg ; DB C8+r [P6,FPU] \c FCMOVNE ST0,fpureg ; DB C8+r [P6,FPU] +\c FCMOVNBE fpureg ; DB D0+r [P6,FPU] +\c FCMOVNBE ST0,fpureg ; DB D0+r [P6,FPU] + \c FCMOVNU fpureg ; DB D8+r [P6,FPU] \c FCMOVNU ST0,fpureg ; DB D8+r [P6,FPU] -\c FCMOVU fpureg ; DA D8+r [P6,FPU] -\c FCMOVU ST0,fpureg ; DA D8+r [P6,FPU] - The \c{FCMOV} instructions perform conditional move operations: each of them moves the contents of the given register into \c{ST0} if its condition is satisfied, and does nothing if not. @@ -6659,7 +7930,9 @@ may not be supported by all Pentium Pro processors; the \c{CPUID} instruction (\k{insCPUID}) will return a bit which indicates whether conditional moves are supported. -\H{insFCOM} \i\c{FCOM}, \i\c{FCOMP}, \i\c{FCOMPP}, \i\c{FCOMI}, \i\c{FCOMIP}: Floating-Point Compare + +\H{insFCOM} \i\c{FCOM}, \i\c{FCOMP}, \i\c{FCOMPP}, \i\c{FCOMI}, +\i\c{FCOMIP}: Floating-Point Compare \c FCOM mem32 ; D8 /2 [8086,FPU] \c FCOM mem64 ; DC /2 [8086,FPU] @@ -6699,12 +7972,16 @@ The \c{FCOM} instructions differ from the \c{FUCOM} instructions will handle them silently and set the condition code flags to an `unordered' result, whereas \c{FCOM} will generate an exception. + \H{insFCOS} \i\c{FCOS}: Cosine \c FCOS ; D9 FF [386,FPU] \c{FCOS} computes the cosine of \c{ST0} (in radians), and stores the -result in \c{ST0}. See also \c{FSINCOS} (\k{insFSIN}). +result in \c{ST0}. The absolute value of \c{ST0} must be less than 2**63. + +See also \c{FSINCOS} (\k{insFSIN}). + \H{insFDECSTP} \i\c{FDECSTP}: Decrement Floating-Point Stack Pointer @@ -6715,6 +7992,7 @@ word. This has the effect of rotating the FPU register stack by one, as if the contents of \c{ST7} had been pushed on the stack. See also \c{FINCSTP} (\k{insFINCSTP}). + \H{insFDISI} \i\c{FxDISI}, \i\c{FxENI}: Disable and Enable Floating-Point Interrupts \c FDISI ; 9B DB E1 [8086,FPU] @@ -6731,6 +8009,7 @@ the 287 and above treat them as no-operation instructions. respectively, but without waiting for the floating-point processor to finish what it was doing first. + \H{insFDIV} \i\c{FDIV}, \i\c{FDIVP}, \i\c{FDIVR}, \i\c{FDIVRP}: Floating-Point Division \c FDIV mem32 ; D8 /6 [8086,FPU] @@ -6757,35 +8036,49 @@ to finish what it was doing first. \c FDIVRP fpureg ; DE F0+r [8086,FPU] \c FDIVRP fpureg,ST0 ; DE F0+r [8086,FPU] -\c{FDIV} divides \c{ST0} by the given operand and stores the result +\b \c{FDIV} divides \c{ST0} by the given operand and stores the result back in \c{ST0}, unless the \c{TO} qualifier is given, in which case it divides the given operand by \c{ST0} and stores the result in the operand. -\c{FDIVR} does the same thing, but does the division the other way +\b \c{FDIVR} does the same thing, but does the division the other way up: so if \c{TO} is not given, it divides the given operand by \c{ST0} and stores the result in \c{ST0}, whereas if \c{TO} is given it divides \c{ST0} by its operand and stores the result in the operand. -\c{FDIVP} operates like \c{FDIV TO}, but pops the register stack -once it has finished. \c{FDIVRP} operates like \c{FDIVR TO}, but -pops the register stack once it has finished. +\b \c{FDIVP} operates like \c{FDIV TO}, but pops the register stack +once it has finished. + +\b \c{FDIVRP} operates like \c{FDIVR TO}, but pops the register stack +once it has finished. +For FP/Integer divisions, see \c{FIDIV} (\k{insFIDIV}). -\H{insFEMMS} \i\c{FEMMS}: 3dnow instruction (duh!) -\c FEMMS 0,0,0 ; ?? [PENT,3DNOW] +\H{insFEMMS} \i\c{FEMMS}: Faster Enter/Exit of the MMX or floating-point state -3dnow instruction (duh!) +\c FEMMS ; 0F 0E [PENT,3DNOW] + +\c{FEMMS} can be used in place of the \c{EMMS} instruction on +processors which support the 3DNow! instruction set. Following +execution of \c{FEMMS}, the state of the \c{MMX/FP} registers +is undefined, and this allows a faster context switch between +\c{FP} and \c{MMX} instructions. The \c{FEMMS} instruction can +also be used \e{before} executing \c{MMX} instructions \H{insFFREE} \i\c{FFREE}: Flag Floating-Point Register as Unused \c FFREE fpureg ; DD C0+r [8086,FPU] +\c FFREEP fpureg ; DF C0+r [286,FPU,UNDOC] \c{FFREE} marks the given register as being empty. +\c{FFREEP} marks the given register as being empty, and then +pops the register stack. + + \H{insFIADD} \i\c{FIADD}: Floating-Point/Integer Addition \c FIADD mem16 ; DE /0 [8086,FPU] @@ -6794,6 +8087,7 @@ pops the register stack once it has finished. \c{FIADD} adds the 16-bit or 32-bit integer stored in the given memory location to \c{ST0}, storing the result in \c{ST0}. + \H{insFICOM} \i\c{FICOM}, \i\c{FICOMP}: Floating-Point/Integer Compare \c FICOM mem16 ; DE /2 [8086,FPU] @@ -6806,19 +8100,21 @@ memory location to \c{ST0}, storing the result in \c{ST0}. in the given memory location, and sets the FPU flags accordingly. \c{FICOMP} does the same, but pops the register stack afterwards. + \H{insFIDIV} \i\c{FIDIV}, \i\c{FIDIVR}: Floating-Point/Integer Division \c FIDIV mem16 ; DE /6 [8086,FPU] \c FIDIV mem32 ; DA /6 [8086,FPU] -\c FIDIVR mem16 ; DE /0 [8086,FPU] -\c FIDIVR mem32 ; DA /0 [8086,FPU] +\c FIDIVR mem16 ; DE /7 [8086,FPU] +\c FIDIVR mem32 ; DA /7 [8086,FPU] \c{FIDIV} divides \c{ST0} by the 16-bit or 32-bit integer stored in the given memory location, and stores the result in \c{ST0}. \c{FIDIVR} does the division the other way up: it divides the integer by \c{ST0}, but still stores the result in \c{ST0}. + \H{insFILD} \i\c{FILD}, \i\c{FIST}, \i\c{FISTP}: Floating-Point/Integer Conversion \c FILD mem16 ; DF /0 [8086,FPU] @@ -6830,13 +8126,14 @@ integer by \c{ST0}, but still stores the result in \c{ST0}. \c FISTP mem16 ; DF /3 [8086,FPU] \c FISTP mem32 ; DB /3 [8086,FPU] -\c FISTP mem64 ; DF /0 [8086,FPU] +\c FISTP mem64 ; DF /7 [8086,FPU] \c{FILD} loads an integer out of a memory location, converts it to a real, and pushes it on the FPU register stack. \c{FIST} converts \c{ST0} to an integer and stores that in memory; \c{FISTP} does the same as \c{FIST}, but pops the register stack afterwards. + \H{insFIMUL} \i\c{FIMUL}: Floating-Point/Integer Multiplication \c FIMUL mem16 ; DE /1 [8086,FPU] @@ -6845,6 +8142,7 @@ same as \c{FIST}, but pops the register stack afterwards. \c{FIMUL} multiplies \c{ST0} by the 16-bit or 32-bit integer stored in the given memory location, and stores the result in \c{ST0}. + \H{insFINCSTP} \i\c{FINCSTP}: Increment Floating-Point Stack Pointer \c FINCSTP ; D9 F7 [8086,FPU] @@ -6856,15 +8154,17 @@ popping of the stack performed by many FPU instructions, it does not flag the new \c{ST7} (previously \c{ST0}) as empty. See also \c{FDECSTP} (\k{insFDECSTP}). + \H{insFINIT} \i\c{FINIT}, \i\c{FNINIT}: Initialise Floating-Point Unit \c FINIT ; 9B DB E3 [8086,FPU] \c FNINIT ; DB E3 [8086,FPU] \c{FINIT} initialises the FPU to its default state. It flags all -registers as empty, though it does not actually change their values. -\c{FNINIT} does the same, without first waiting for pending -exceptions to clear. +registers as empty, without actually change their values, clears +the top of stack pointer. \c{FNINIT} does the same, without first +waiting for pending exceptions to clear. + \H{insFISUB} \i\c{FISUB}: Floating-Point/Integer Subtraction @@ -6880,6 +8180,7 @@ memory location from \c{ST0}, and stores the result in \c{ST0}. subtracts \c{ST0} from the given integer, but still stores the result in \c{ST0}. + \H{insFLD} \i\c{FLD}: Floating-Point Load \c FLD mem32 ; D9 /0 [8086,FPU] @@ -6890,6 +8191,7 @@ result in \c{ST0}. \c{FLD} loads a floating-point value out of the given register or memory location, and pushes it on the FPU register stack. + \H{insFLD1} \i\c{FLDxx}: Floating-Point Load Constants \c FLD1 ; D9 E8 [8086,FPU] @@ -6901,10 +8203,18 @@ memory location, and pushes it on the FPU register stack. \c FLDZ ; D9 EE [8086,FPU] These instructions push specific standard constants on the FPU -register stack. \c{FLD1} pushes the value 1; \c{FLDL2E} pushes the -base-2 logarithm of e; \c{FLDL2T} pushes the base-2 log of 10; -\c{FLDLG2} pushes the base-10 log of 2; \c{FLDLN2} pushes the base-e -log of 2; \c{FLDPI} pushes pi; and \c{FLDZ} pushes zero. +register stack. + +\c Instruction Constant pushed + +\c FLD1 1 +\c FLDL2E base-2 logarithm of e +\c FLDL2T base-2 log of 10 +\c FLDLG2 base-10 log of 2 +\c FLDLN2 base-e log of 2 +\c FLDPI pi +\c FLDZ zero + \H{insFLDCW} \i\c{FLDCW}: Load Floating-Point Control Word @@ -6913,7 +8223,10 @@ log of 2; \c{FLDPI} pushes pi; and \c{FLDZ} pushes zero. \c{FLDCW} loads a 16-bit value out of memory and stores it into the FPU control word (governing things like the rounding mode, the precision, and the exception masks). See also \c{FSTCW} -(\k{insFSTCW}). +(\k{insFSTCW}). If exceptions are enabled and you don't want to +generate one, use \c{FCLEX} or \c{FNCLEX} (\k{insFCLEX}) before +loading the new control word. + \H{insFLDENV} \i\c{FLDENV}: Load Floating-Point Environment @@ -6924,6 +8237,7 @@ word, tag word, instruction pointer, data pointer and last opcode) from memory. The memory area is 14 or 28 bytes long, depending on the CPU mode at the time. See also \c{FSTENV} (\k{insFSTENV}). + \H{insFMUL} \i\c{FMUL}, \i\c{FMULP}: Floating-Point Multiply \c FMUL mem32 ; D8 /1 [8086,FPU] @@ -6943,12 +8257,14 @@ result in \c{ST0}, unless the \c{TO} qualifier is used in which case it stores the result in the operand. \c{FMULP} performs the same operation as \c{FMUL TO}, and then pops the register stack. + \H{insFNOP} \i\c{FNOP}: Floating-Point No Operation \c FNOP ; D9 D0 [8086,FPU] \c{FNOP} does nothing. + \H{insFPATAN} \i\c{FPATAN}, \i\c{FPTAN}: Arctangent and Tangent \c FPATAN ; D9 F3 [8086,FPU] @@ -6965,6 +8281,9 @@ the X coordinate, not merely an arctangent). \c{FPTAN} computes the tangent of the value in \c{ST0} (in radians), and stores the result back into \c{ST0}. +The absolute value of \c{ST0} must be less than 2**63. + + \H{insFPREM} \i\c{FPREM}, \i\c{FPREM1}: Floating-Point Partial Remainder \c FPREM ; D9 F8 [8086,FPU] @@ -6991,6 +8310,7 @@ set the C2 flag in the FPU status word; therefore, to calculate a remainder, you should repeatedly execute \c{FPREM} or \c{FPREM1} until C2 becomes clear. + \H{insFRNDINT} \i\c{FRNDINT}: Floating-Point Round to Integer \c FRNDINT ; D9 FC [8086,FPU] @@ -6999,6 +8319,7 @@ until C2 becomes clear. to the current rounding mode set in the FPU control word, and stores the result back in \c{ST0}. + \H{insFRSTOR} \i\c{FSAVE}, \i\c{FRSTOR}: Save/Restore Floating-Point State \c FSAVE mem ; 9B DD /6 [8086,FPU] @@ -7015,6 +8336,7 @@ state from the same area of memory. \c{FNSAVE} does the same as \c{FSAVE}, without first waiting for pending floating-point exceptions to clear. + \H{insFSCALE} \i\c{FSCALE}: Scale Floating-Point Value by Power of Two \c FSCALE ; D9 FD [8086,FPU] @@ -7023,6 +8345,7 @@ pending floating-point exceptions to clear. towards zero to obtain an integer, then multiplies \c{ST0} by two to the power of that integer, and stores the result in \c{ST0}. + \H{insFSETPM} \i\c{FSETPM}: Set Protected Mode \c FSETPM ; DB E4 [286,FPU] @@ -7031,6 +8354,7 @@ This instruction initalises protected mode on the 287 floating-point coprocessor. It is only meaningful on that processor: the 387 and above treat the instruction as a no-operation. + \H{insFSIN} \i\c{FSIN}, \i\c{FSINCOS}: Sine and Cosine \c FSIN ; D9 FE [386,FPU] @@ -7040,8 +8364,10 @@ above treat the instruction as a no-operation. result in \c{ST0}. \c{FSINCOS} does the same, but then pushes the cosine of the same value on the register stack, so that the sine ends up in \c{ST1} and the cosine in \c{ST0}. \c{FSINCOS} is faster -than executing \c{FSIN} and \c{FCOS} (see \k{insFCOS}) in -succession. +than executing \c{FSIN} and \c{FCOS} (see \k{insFCOS}) in succession. + +The absolute value of \c{ST0} must be less than 2**63. + \H{insFSQRT} \i\c{FSQRT}: Floating-Point Square Root @@ -7050,6 +8376,7 @@ succession. \c{FSQRT} calculates the square root of \c{ST0} and stores the result in \c{ST0}. + \H{insFST} \i\c{FST}, \i\c{FSTP}: Floating-Point Store \c FST mem32 ; D9 /2 [8086,FPU] @@ -7058,31 +8385,33 @@ result in \c{ST0}. \c FSTP mem32 ; D9 /3 [8086,FPU] \c FSTP mem64 ; DD /3 [8086,FPU] -\c FSTP mem80 ; DB /0 [8086,FPU] +\c FSTP mem80 ; DB /7 [8086,FPU] \c FSTP fpureg ; DD D8+r [8086,FPU] \c{FST} stores the value in \c{ST0} into the given memory location or other FPU register. \c{FSTP} does the same, but then pops the register stack. + \H{insFSTCW} \i\c{FSTCW}: Store Floating-Point Control Word -\c FSTCW mem16 ; 9B D9 /0 [8086,FPU] -\c FNSTCW mem16 ; D9 /0 [8086,FPU] +\c FSTCW mem16 ; 9B D9 /7 [8086,FPU] +\c FNSTCW mem16 ; D9 /7 [8086,FPU] -\c{FSTCW} stores the FPU control word (governing things like the +\c{FSTCW} stores the \c{FPU} control word (governing things like the rounding mode, the precision, and the exception masks) into a 2-byte memory area. See also \c{FLDCW} (\k{insFLDCW}). \c{FNSTCW} does the same thing as \c{FSTCW}, without first waiting for pending floating-point exceptions to clear. + \H{insFSTENV} \i\c{FSTENV}: Store Floating-Point Environment \c FSTENV mem ; 9B D9 /6 [8086,FPU] \c FNSTENV mem ; D9 /6 [8086,FPU] -\c{FSTENV} stores the FPU operating environment (control word, +\c{FSTENV} stores the \c{FPU} operating environment (control word, status word, tag word, instruction pointer, data pointer and last opcode) into memory. The memory area is 14 or 28 bytes long, depending on the CPU mode at the time. See also \c{FLDENV} @@ -7091,20 +8420,22 @@ depending on the CPU mode at the time. See also \c{FLDENV} \c{FNSTENV} does the same thing as \c{FSTENV}, without first waiting for pending floating-point exceptions to clear. + \H{insFSTSW} \i\c{FSTSW}: Store Floating-Point Status Word -\c FSTSW mem16 ; 9B DD /0 [8086,FPU] +\c FSTSW mem16 ; 9B DD /7 [8086,FPU] \c FSTSW AX ; 9B DF E0 [286,FPU] -\c FNSTSW mem16 ; DD /0 [8086,FPU] +\c FNSTSW mem16 ; DD /7 [8086,FPU] \c FNSTSW AX ; DF E0 [286,FPU] -\c{FSTSW} stores the FPU status word into \c{AX} or into a 2-byte +\c{FSTSW} stores the \c{FPU} status word into \c{AX} or into a 2-byte memory area. \c{FNSTSW} does the same thing as \c{FSTSW}, without first waiting for pending floating-point exceptions to clear. + \H{insFSUB} \i\c{FSUB}, \i\c{FSUBP}, \i\c{FSUBR}, \i\c{FSUBRP}: Floating-Point Subtract \c FSUB mem32 ; D8 /4 [8086,FPU] @@ -7131,20 +8462,23 @@ for pending floating-point exceptions to clear. \c FSUBRP fpureg ; DE E0+r [8086,FPU] \c FSUBRP fpureg,ST0 ; DE E0+r [8086,FPU] -\c{FSUB} subtracts the given operand from \c{ST0} and stores the +\b \c{FSUB} subtracts the given operand from \c{ST0} and stores the result back in \c{ST0}, unless the \c{TO} qualifier is given, in which case it subtracts \c{ST0} from the given operand and stores the result in the operand. -\c{FSUBR} does the same thing, but does the subtraction the other way -up: so if \c{TO} is not given, it subtracts \c{ST0} from the given +\b \c{FSUBR} does the same thing, but does the subtraction the other +way up: so if \c{TO} is not given, it subtracts \c{ST0} from the given operand and stores the result in \c{ST0}, whereas if \c{TO} is given it subtracts its operand from \c{ST0} and stores the result in the operand. -\c{FSUBP} operates like \c{FSUB TO}, but pops the register stack -once it has finished. \c{FSUBRP} operates like \c{FSUBR TO}, but -pops the register stack once it has finished. +\b \c{FSUBP} operates like \c{FSUB TO}, but pops the register stack +once it has finished. + +\b \c{FSUBRP} operates like \c{FSUBR TO}, but pops the register stack +once it has finished. + \H{insFTST} \i\c{FTST}: Test \c{ST0} Against Zero @@ -7155,6 +8489,7 @@ accordingly. \c{ST0} is treated as the left-hand side of the comparison, so that a `less-than' result is generated if \c{ST0} is negative. + \H{insFUCOM} \i\c{FUCOMxx}: Floating-Point Unordered Compare \c FUCOM fpureg ; DD E0+r [386,FPU] @@ -7171,16 +8506,16 @@ negative. \c FUCOMIP fpureg ; DF E8+r [P6,FPU] \c FUCOMIP ST0,fpureg ; DF E8+r [P6,FPU] -\c{FUCOM} compares \c{ST0} with the given operand, and sets the FPU -flags accordingly. \c{ST0} is treated as the left-hand side of the -comparison, so that the carry flag is set (for a `less-than' result) -if \c{ST0} is less than the given operand. +\b \c{FUCOM} compares \c{ST0} with the given operand, and sets the +FPU flags accordingly. \c{ST0} is treated as the left-hand side of +the comparison, so that the carry flag is set (for a `less-than' +result) if \c{ST0} is less than the given operand. -\c{FUCOMP} does the same as \c{FUCOM}, but pops the register stack +\b \c{FUCOMP} does the same as \c{FUCOM}, but pops the register stack afterwards. \c{FUCOMPP} compares \c{ST0} with \c{ST1} and then pops the register stack twice. -\c{FUCOMI} and \c{FUCOMIP} work like the corresponding forms of +\b \c{FUCOMI} and \c{FUCOMIP} work like the corresponding forms of \c{FUCOM} and \c{FUCOMP}, but write their results directly to the CPU flags register rather than the FPU status word, so they can be immediately followed by conditional jump or conditional move @@ -7191,15 +8526,26 @@ The \c{FUCOM} instructions differ from the \c{FCOM} instructions handle them silently and set the condition code flags to an `unordered' result, whereas \c{FCOM} will generate an exception. + \H{insFXAM} \i\c{FXAM}: Examine Class of Value in \c{ST0} \c FXAM ; D9 E5 [8086,FPU] -\c{FXAM} sets the FPU flags C3, C2 and C0 depending on the type of -value stored in \c{ST0}: 000 (respectively) for an unsupported -format, 001 for a NaN, 010 for a normal finite number, 011 for an -infinity, 100 for a zero, 101 for an empty register, and 110 for a -denormal. It also sets the C1 flag to the sign of the number. +\c{FXAM} sets the FPU flags \c{C3}, \c{C2} and \c{C0} depending on +the type of value stored in \c{ST0}: + +\c Register contents Flags + +\c Unsupported format 000 +\c NaN 001 +\c Finite number 010 +\c Infinity 011 +\c Zero 100 +\c Empty register 101 +\c Denormal 110 + +Additionally, the \c{C1} flag is set to the sign of the number. + \H{insFXCH} \i\c{FXCH}: Floating-Point Exchange @@ -7211,33 +8557,31 @@ denormal. It also sets the C1 flag to the sign of the number. \c{FXCH} exchanges \c{ST0} with a given FPU register. The no-operand form exchanges \c{ST0} with \c{ST1}. -\H{insFXRSTOR} \i\c{FXRSTOR}: Restore FP and MMXTM State and -Streaming SIMD Extension State -\c FXRSTOR memory ; 0F,AE,/1 [P6,SSE,FPU] +\H{insFXRSTOR} \i\c{FXRSTOR}: Restore \c{FP}, \c{MMX} and \c{SSE} State + +\c FXRSTOR memory ; 0F AE /1 [P6,SSE,FPU] -\c{FXRSTOR}The FXRSTOR instruction reloads the FP and MMXTM technology -state, and the Streaming SIMD Extension state (environment and registers), -from the memory area defined by m512byte. This data should have been -written by a previous FXSAVE. +The \c{FXRSTOR} instruction reloads the \c{FPU}, \c{MMX} and \c{SSE} +state (environment and registers), from the 512 byte memory area defined +by the source operand. This data should have been written by a previous +\c{FXSAVE}. -\H{insFXSAVE} \i\c{FXSAVE}: Store FP and MMXTM State - and Streaming SIMD +\H{insFXSAVE} \i\c{FXSAVE}: Store \c{FP}, \c{MMX} and \c{SSE} State -\c FXSAVE memory ; 0F,AE,/0 [P6,SSE,FPU] +\c FXSAVE memory ; 0F AE /0 [P6,SSE,FPU] +\c{FXSAVE}The FXSAVE instruction writes the current \c{FPU}, \c{MMX} +and \c{SSE} technology states (environment and registers), to the +512 byte memory area defined by the destination operand. It does this +without checking for pending unmasked floating-point exceptions +(similar to the operation of \c{FNSAVE}). -\c{FXSAVE}The FXSAVE instruction writes the current FP and - MMXTM technology state, and Streaming SIMD Extension state - (environment and registers), to the specified destination - defined by m512byte. It does this without checking for pending - unmasked floating-point exceptions (similar to the operation of - FNSAVE). Unlike the FSAVE/FNSAVE instructions, the processor -retains the contents of the FP and MMXTM technology state and - Streaming SIMD Extension state in the processor after the state - has been saved. This instruction has been optimized to maximize - floating-point save performance. +Unlike the \c{FSAVE/FNSAVE} instructions, the processor retains the +contents of the \c{FPU}, \c{MMX} and \c{SSE} state in the processor +after the state has been saved. This instruction has been optimized +to maximize floating-point save performance. \H{insFXTRACT} \i\c{FXTRACT}: Extract Exponent and Significand @@ -7249,6 +8593,7 @@ significand (mantissa), stores the exponent back into \c{ST0}, and then pushes the significand on the register stack (so that the significand ends up in \c{ST0}, and the exponent in \c{ST1}). + \H{insFYL2X} \i\c{FYL2X}, \i\c{FYL2XP1}: Compute Y times Log2(X) or Log2(X+1) \c FYL2X ; D9 F1 [8086,FPU] @@ -7263,25 +8608,42 @@ positive. \c{ST0} with that of \c{ST0} plus one. This time, \c{ST0} must have magnitude no greater than 1 minus half the square root of two. + \H{insHLT} \i\c{HLT}: Halt Processor -\c HLT ; F4 [8086] +\c HLT ; F4 [8086,PRIV] \c{HLT} puts the processor into a halted state, where it will perform no more operations until restarted by an interrupt or a reset. +On the 286 and later processors, this is a privileged instruction. + + \H{insIBTS} \i\c{IBTS}: Insert Bit String \c IBTS r/m16,reg16 ; o16 0F A7 /r [386,UNDOC] \c IBTS r/m32,reg32 ; o32 0F A7 /r [386,UNDOC] -No clear documentation seems to be available for this instruction: -the best I've been able to find reads `Takes a string of bits from -the second operand and puts them in the first operand'. It is -present only in early 386 processors, and conflicts with the opcodes -for \c{CMPXCHG486}. NASM supports it only for completeness. Its -counterpart is \c{XBTS} (see \k{insXBTS}). +The implied operation of this instruction is: + +\c IBTS r/m16,AX,CL,reg16 +\c IBTS r/m32,EAX,CL,reg32 + +Writes a bit string from the source operand to the destination. +\c{CL} indicates the number of bits to be copied, from the low bits +of the source. \c{(E)AX} indicates the low order bit offset in the +destination that is written to. For example, if \c{CL} is set to 4 +and \c{AX} (for 16-bit code) is set to 5, bits 0-3 of \c{src} will +be copied to bits 5-8 of \c{dst}. This instruction is very poorly +documented, and I have been unable to find any official source of +documentation on it. + +\c{IBTS} is supported only on the early Intel 386s, and conflicts +with the opcodes for \c{CMPXCHG486} (on early Intel 486s). NASM +supports it only for completeness. Its counterpart is \c{XBTS} +(see \k{insXBTS}). + \H{insIDIV} \i\c{IDIV}: Signed Integer Divide @@ -7290,14 +8652,14 @@ counterpart is \c{XBTS} (see \k{insXBTS}). \c IDIV r/m32 ; o32 F7 /7 [386] \c{IDIV} performs signed integer division. The explicit operand -provided is the divisor; the dividend and destination operands are -implicit, in the following way: +provided is the divisor; the dividend and destination operands +are implicit, in the following way: -\b For \c{IDIV r/m8}, \c{AX} is divided by the given operand; the -quotient is stored in \c{AL} and the remainder in \c{AH}. +\b For \c{IDIV r/m8}, \c{AX} is divided by the given operand; +the quotient is stored in \c{AL} and the remainder in \c{AH}. -\b For \c{IDIV r/m16}, \c{DX:AX} is divided by the given operand; the -quotient is stored in \c{AX} and the remainder in \c{DX}. +\b For \c{IDIV r/m16}, \c{DX:AX} is divided by the given operand; +the quotient is stored in \c{AX} and the remainder in \c{DX}. \b For \c{IDIV r/m32}, \c{EDX:EAX} is divided by the given operand; the quotient is stored in \c{EAX} and the remainder in \c{EDX}. @@ -7305,6 +8667,7 @@ the quotient is stored in \c{EAX} and the remainder in \c{EDX}. Unsigned integer division is performed by the \c{DIV} instruction: see \k{insDIV}. + \H{insIMUL} \i\c{IMUL}: Signed Integer Multiply \c IMUL r/m8 ; F6 /5 [8086] @@ -7325,11 +8688,11 @@ see \k{insDIV}. \c IMUL reg32,r/m32,imm32 ; o32 69 /r id [386] \c{IMUL} performs signed integer multiplication. For the -single-operand form, the other operand and destination are implicit, -in the following way: +single-operand form, the other operand and destination are +implicit, in the following way: -\b For \c{IMUL r/m8}, \c{AL} is multiplied by the given operand; the -product is stored in \c{AX}. +\b For \c{IMUL r/m8}, \c{AL} is multiplied by the given operand; +the product is stored in \c{AX}. \b For \c{IMUL r/m16}, \c{AX} is multiplied by the given operand; the product is stored in \c{DX:AX}. @@ -7338,24 +8701,26 @@ the product is stored in \c{DX:AX}. the product is stored in \c{EDX:EAX}. The two-operand form multiplies its two operands and stores the -result in the destination (first) operand. The three-operand form -multiplies its last two operands and stores the result in the first -operand. +result in the destination (first) operand. The three-operand +form multiplies its last two operands and stores the result in +the first operand. -The two-operand form is in fact a shorthand for the three-operand -form, as can be seen by examining the opcode descriptions: in the -two-operand form, the code \c{/r} takes both its register and -\c{r/m} parts from the same operand (the first one). +The two-operand form with an immediate second operand is in +fact a shorthand for the three-operand form, as can be seen by +examining the opcode descriptions: in the two-operand form, the +code \c{/r} takes both its register and \c{r/m} parts from the +same operand (the first one). In the forms with an 8-bit immediate operand and another longer source operand, the immediate operand is considered to be signed, -and is sign-extended to the length of the other source operand. In -these cases, the \c{BYTE} qualifier is necessary to force NASM to -generate this form of the instruction. +and is sign-extended to the length of the other source operand. +In these cases, the \c{BYTE} qualifier is necessary to force +NASM to generate this form of the instruction. Unsigned integer multiplication is performed by the \c{MUL} instruction: see \k{insMUL}. + \H{insIN} \i\c{IN}: Input from I/O Port \c IN AL,imm8 ; E4 ib [8086] @@ -7370,6 +8735,7 @@ and stores it in the given destination register. The port number may be specified as an immediate value if it is between 0 and 255, and otherwise must be stored in \c{DX}. See also \c{OUT} (\k{insOUT}). + \H{insINC} \i\c{INC}: Increment Integer \c INC reg16 ; o16 40+r [8086] @@ -7380,7 +8746,12 @@ otherwise must be stored in \c{DX}. See also \c{OUT} (\k{insOUT}). \c{INC} adds 1 to its operand. It does \e{not} affect the carry flag: to affect the carry flag, use \c{ADD something,1} (see -\k{insADD}). See also \c{DEC} (\k{insDEC}). +\k{insADD}). \c{INC} affects all the other flags according to the result. + +This instruction can be used with a \c{LOCK} prefix to allow atomic execution. + +See also \c{DEC} (\k{insDEC}). + \H{insINSB} \i\c{INSB}, \i\c{INSW}, \i\c{INSD}: Input String from I/O Port @@ -7411,6 +8782,7 @@ The \c{REP} prefix may be used to repeat the instruction \c{CX} (or See also \c{OUTSB}, \c{OUTSW} and \c{OUTSD} (\k{insOUTSB}). + \H{insINT} \i\c{INT}: Software Interrupt \c INT imm8 ; CD ib [8086] @@ -7424,6 +8796,7 @@ NASM does not generate them when it sees the \c{INT} mnemonic. In order to generate single-byte breakpoint instructions, use the \c{INT3} or \c{INT1} instructions (see \k{insINT1}) instead. + \H{insINT1} \i\c{INT3}, \i\c{INT1}, \i\c{ICEBP}, \i\c{INT01}: Breakpoints \c INT1 ; F1 [P6] @@ -7431,22 +8804,24 @@ order to generate single-byte breakpoint instructions, use the \c INT01 ; F1 [P6] \c INT3 ; CC [8086] +\c INT03 ; CC [8086] \c{INT1} and \c{INT3} are short one-byte forms of the instructions \c{INT 1} and \c{INT 3} (see \k{insINT}). They perform a similar function to their longer counterparts, but take up less code space. They are used as breakpoints by debuggers. -\c{INT1}, and its alternative synonyms \c{INT01} and \c{ICEBP}, is +\b \c{INT1}, and its alternative synonyms \c{INT01} and \c{ICEBP}, is an instruction used by in-circuit emulators (ICEs). It is present, though not documented, on some processors down to the 286, but is only documented for the Pentium Pro. \c{INT3} is the instruction normally used as a breakpoint by debuggers. -\c{INT3} is not precisely equivalent to \c{INT 3}: the short form, -since it is designed to be used as a breakpoint, bypasses the normal -IOPL checks in virtual-8086 mode, and also does not go through -interrupt redirection. +\b \c{INT3}, and its synonym \c{INT03}, is not precisely equivalent to +\c{INT 3}: the short form, since it is designed to be used as a +breakpoint, bypasses the normal \c{IOPL} checks in virtual-8086 mode, +and also does not go through interrupt redirection. + \H{insINTO} \i\c{INTO}: Interrupt if Overflow @@ -7455,6 +8830,7 @@ interrupt redirection. \c{INTO} performs an \c{INT 4} software interrupt (see \k{insINT}) if and only if the overflow flag is set. + \H{insINVD} \i\c{INVD}: Invalidate Internal Caches \c INVD ; 0F 08 [486] @@ -7465,13 +8841,15 @@ It does not write the contents of the caches back to memory first: any modified data held in the caches will be lost. To write the data back first, use \c{WBINVD} (\k{insWBINVD}). + \H{insINVLPG} \i\c{INVLPG}: Invalidate TLB Entry -\c INVLPG mem ; 0F 01 /0 [486] +\c INVLPG mem ; 0F 01 /7 [486] \c{INVLPG} invalidates the translation lookahead buffer (TLB) entry associated with the supplied memory address. + \H{insIRET} \i\c{IRET}, \i\c{IRETW}, \i\c{IRETD}: Return from Interrupt \c IRET ; CF [8086] @@ -7491,6 +8869,28 @@ taking 12 bytes off the stack. \c{IRET} is a shorthand for either \c{IRETW} or \c{IRETD}, depending on the default \c{BITS} setting at the time. + +\H{insJcc} \i\c{Jcc}: Conditional Branch + +\c Jcc imm ; 70+cc rb [8086] +\c Jcc NEAR imm ; 0F 80+cc rw/rd [386] + +The \i{conditional jump} instructions execute a near (same segment) +jump if and only if their conditions are satisfied. For example, +\c{JNZ} jumps only if the zero flag is not set. + +The ordinary form of the instructions has only a 128-byte range; the +\c{NEAR} form is a 386 extension to the instruction set, and can +span the full size of a segment. NASM will not override your choice +of jump instruction: if you want \c{Jcc NEAR}, you have to use the +\c{NEAR} keyword. + +The \c{SHORT} keyword is allowed on the first form of the +instruction, for clarity, but is not necessary. + +For details of the condition codes, see \k{iref-cc}. + + \H{insJCXZ} \i\c{JCXZ}, \i\c{JECXZ}: Jump if CX/ECX Zero \c JCXZ imm ; a16 E3 rb [8086] @@ -7500,6 +8900,7 @@ on the default \c{BITS} setting at the time. only if the contents of the \c{CX} register is 0. \c{JECXZ} does the same thing, but with \c{ECX}. + \H{insJMP} \i\c{JMP}: Jump \c JMP imm ; E9 rw/rd [8086] @@ -7544,30 +8945,20 @@ The \c{CALL r/m} forms given above are near calls; NASM will accept the \c{NEAR} keyword (e.g. \c{CALL NEAR [address]}), even though it is not strictly necessary. -\H{insJcc} \i\c{Jcc}: Conditional Branch -\c Jcc imm ; 70+cc rb [8086] -\c Jcc NEAR imm ; 0F 80+cc rw/rd [386] +\H{insLAHF} \i\c{LAHF}: Load AH from Flags -The \i{conditional jump} instructions execute a near (same segment) -jump if and only if their conditions are satisfied. For example, -\c{JNZ} jumps only if the zero flag is not set. +\c LAHF ; 9F [8086] -The ordinary form of the instructions has only a 128-byte range; the -\c{NEAR} form is a 386 extension to the instruction set, and can -span the full size of a segment. NASM will not override your choice -of jump instruction: if you want \c{Jcc NEAR}, you have to use the -\c{NEAR} keyword. +\c{LAHF} sets the \c{AH} register according to the contents of the +low byte of the flags word. -The \c{SHORT} keyword is allowed on the first form of the -instruction, for clarity, but is not necessary. +The operation of \c{LAHF} is: -\H{insLAHF} \i\c{LAHF}: Load AH from Flags +\c AH <-- SF:ZF:0:AF:0:PF:1:CF -\c LAHF ; 9F [8086] +See also \c{SAHF} (\k{insSAHF}). -\c{LAHF} sets the \c{AH} register according to the contents of the -low byte of the flags word. See also \c{SAHF} (\k{insSAHF}). \H{insLAR} \i\c{LAR}: Load Access Rights @@ -7579,13 +8970,29 @@ operand, finds the corresponding segment descriptor in the GDT or LDT, and loads the access-rights byte of the descriptor into its destination (first) operand. + +\H{insLDMXCSR} \i\c{LDMXCSR}: Load Streaming SIMD Extension + Control/Status + +\c LDMXCSR mem32 ; 0F AE /2 [KATMAI,SSE] + +\c{LDMXCSR} loads 32-bits of data from the specified memory location +into the \c{MXCSR} control/status register. \c{MXCSR} is used to +enable masked/unmasked exception handling, to set rounding modes, +to set flush-to-zero mode, and to view exception status flags. + +For details of the \c{MXCSR} register, see the Intel processor docs. + +See also \c{STMXCSR} (\k{insSTMXCSR} + + \H{insLDS} \i\c{LDS}, \i\c{LES}, \i\c{LFS}, \i\c{LGS}, \i\c{LSS}: Load Far Pointer \c LDS reg16,mem ; o16 C5 /r [8086] -\c LDS reg32,mem ; o32 C5 /r [8086] +\c LDS reg32,mem ; o32 C5 /r [386] \c LES reg16,mem ; o16 C4 /r [8086] -\c LES reg32,mem ; o32 C4 /r [8086] +\c LES reg32,mem ; o32 C4 /r [386] \c LFS reg16,mem ; o16 0F B4 /r [386] \c LFS reg32,mem ; o32 0F B4 /r [386] @@ -7605,20 +9012,10 @@ loads the \e{next} 16 bits from memory into \c{DS}. \c{LES}, segment registers. -\H{insLDMXCSR} \i\c{LDMXCSR}: Load Streaming SIMD Extension - Control/Status - -\c LDMXCSR memory ; 0F,AE,/2 [KATMAI,SSE,SD] - -\c{LDMXCSR} The MXCSR control/status register is used to enable - masked/unmasked exception handling, to set rounding modes, to - set flush-to-zero mode, and to view exception status flags. - - \H{insLEA} \i\c{LEA}: Load Effective Address \c LEA reg16,mem ; o16 8D /r [8086] -\c LEA reg32,mem ; o32 8D /r [8086] +\c LEA reg32,mem ; o32 8D /r [386] \c{LEA}, despite its syntax, does not access memory. It calculates the effective address specified by its second operand as if it were @@ -7631,6 +9028,13 @@ EAX,[EBX+ECX*4+100]}) in one instruction. accesses no memory, still requires square brackets around its second operand, as if it were a memory reference. +The size of the calculation is the current \e{address} size, and the +size that the result is stored as is the current \e{operand} size. +If the address and operand size are not the same, then if the +addressing mode was 32-bits, the low 16-bits are stored, and if the +address was 16-bits, it is zero-extended to 32-bits before storing. + + \H{insLEAVE} \i\c{LEAVE}: Destroy Stack Frame \c LEAVE ; C9 [186] @@ -7640,6 +9044,40 @@ operand, as if it were a memory reference. equivalent to \c{MOV ESP,EBP} followed by \c{POP EBP} (or \c{MOV SP,BP} followed by \c{POP BP} in 16-bit mode). + +\H{insLFENCE} \i\c{LFENCE}: Load Fence + +\c LFENCE ; 0F AE /5 [WILLAMETTE,SSE2] + +\c{LFENCE} performs a serialising operation on all loads from memory +that were issued before the \c{LFENCE} instruction. This guarantees that +all memory reads before the \c{LFENCE} instruction are visible before any +reads after the \c{LFENCE} instruction. + +\c{LFENCE} is ordered respective to other \c{LFENCE} instruction, \c{MFENCE}, +any memory read and any other serialising instruction (such as \c{CPUID}). + +Weakly ordered memory types can be used to achieve higher processor +performance through such techniques as out-of-order issue and +speculative reads. The degree to which a consumer of data recognizes +or knows that the data is weakly ordered varies among applications +and may be unknown to the producer of this data. The \c{LFENCE} +instruction provides a performance-efficient way of ensuring load +ordering between routines that produce weakly-ordered results and +routines that consume that data. + +\c{LFENCE} uses the following ModRM encoding: + +\c Mod (7:6) = 11B +\c Reg/Opcode (5:3) = 101B +\c R/M (2:0) = 000B + +All other ModRM encodings are defined to be reserved, and use +of these encodings risks incompatibility with future processors. + +See also \c{SFENCE} (\k{insSFENCE}) and \c{MFENCE} (\k{insMFENCE}). + + \H{insLGDT} \i\c{LGDT}, \i\c{LIDT}, \i\c{LLDT}: Load Descriptor Tables \c LGDT mem ; 0F 01 /2 [286,PRIV] @@ -7648,17 +9086,18 @@ SP,BP} followed by \c{POP BP} in 16-bit mode). \c{LGDT} and \c{LIDT} both take a 6-byte memory area as an operand: they load a 32-bit linear address and a 16-bit size limit from that -area (in the opposite order) into the GDTR (global descriptor table -register) or IDTR (interrupt descriptor table register). These are -the only instructions which directly use \e{linear} addresses, -rather than segment/offset pairs. +area (in the opposite order) into the \c{GDTR} (global descriptor table +register) or \c{IDTR} (interrupt descriptor table register). These are +the only instructions which directly use \e{linear} addresses, rather +than segment/offset pairs. \c{LLDT} takes a segment selector as an operand. The processor looks up that selector in the GDT and stores the limit and base address -given there into the LDTR (local descriptor table register). +given there into the \c{LDTR} (local descriptor table register). See also \c{SGDT}, \c{SIDT} and \c{SLDT} (\k{insSGDT}). + \H{insLMSW} \i\c{LMSW}: Load/Store Machine Status Word \c LMSW r/m16 ; 0F 01 /6 [286,PRIV] @@ -7667,6 +9106,7 @@ See also \c{SGDT}, \c{SIDT} and \c{SLDT} (\k{insSGDT}). bottom four bits of the \c{CR0} control register (or the Machine Status Word, on 286 processors). See also \c{SMSW} (\k{insSMSW}). + \H{insLOADALL} \i\c{LOADALL}, \i\c{LOADALL286}: Load Processor State \c LOADALL ; 0F 07 [386,UNDOC] @@ -7681,6 +9121,7 @@ to the state of the processor out of a block of memory: on the 286, this block is located implicitly at absolute address \c{0x800}, and on the 386 and 486 it is at \c{[ES:EDI]}. + \H{insLODSB} \i\c{LODSB}, \i\c{LODSW}, \i\c{LODSD}: Load from String \c LODSB ; AC [8086] @@ -7699,12 +9140,13 @@ equal to the current \c{BITS} setting, you can use an explicit The segment register used to load from \c{[SI]} or \c{[ESI]} can be overridden by using a segment register name as a prefix (for -example, \c{es lodsb}). +example, \c{ES LODSB}). \c{LODSW} and \c{LODSD} work in the same way, but they load a word or a doubleword instead of a byte, and increment or decrement the addressing registers by 2 or 4 instead of 1. + \H{insLOOP} \i\c{LOOP}, \i\c{LOOPE}, \i\c{LOOPZ}, \i\c{LOOPNE}, \i\c{LOOPNZ}: Loop with Counter \c LOOP imm ; E2 rb [8086] @@ -7736,6 +9178,7 @@ that it only jumps if the counter is nonzero \e{and} the zero flag is set. Similarly, \c{LOOPNE} (and \c{LOOPNZ}) jumps only if the counter is nonzero and the zero flag is clear. + \H{insLSL} \i\c{LSL}: Load Segment Limit \c LSL reg16,r/m16 ; o16 0F 03 /r [286,PRIV] @@ -7743,12 +9186,13 @@ counter is nonzero and the zero flag is clear. \c{LSL} is given a segment selector in its source (second) operand; it computes the segment limit value by loading the segment limit -field from the associated segment descriptor in the GDT or LDT. +field from the associated segment descriptor in the \c{GDT} or \c{LDT}. (This involves shifting left by 12 bits if the segment limit is page-granular, and not if it is byte-granular; so you end up with a byte limit in either case.) The segment limit obtained is then loaded into the destination (first) operand. + \H{insLTR} \i\c{LTR}: Load Task Register \c LTR r/m16 ; 0F 00 /3 [286,PRIV] @@ -7758,70 +9202,161 @@ descriptor specified by the segment selector given as its operand, and loads them into the Task Register. +\H{insMASKMOVDQU} \i\c{MASKMOVDQU}: Byte Mask Write + +\c MASKMOVDQU xmm1,xmm2 ; 66 0F F7 /r [WILLAMETTE,SSE2] + +\c{MASKMOVDQU} stores data from xmm1 to the location specified by +\c{ES:(E)DI}. The size of the store depends on the address-size +attribute. The most significant bit in each byte of the mask +register xmm2 is used to selectively write the data (0 = no write, +1 = write) on a per-byte basis. + + \H{insMASKMOVQ} \i\c{MASKMOVQ}: Byte Mask Write -\c MASKMOVQ mmxreg,mmxreg ; 0F,F7,/r [KATMAI,MMX] +\c MASKMOVQ mm1,mm2 ; 0F F7 /r [KATMAI,MMX] + +\c{MASKMOVQ} stores data from xmm1 to the location specified by +\c{ES:(E)DI}. The size of the store depends on the address-size +attribute. The most significant bit in each byte of the mask +register xmm2 is used to selectively write the data (0 = no write, +1 = write) on a per-byte basis. + + +\H{insMAXPD} \i\c{MAXPD}: Return Packed Double-Precision FP Maximum + +\c MAXPD xmm1,xmm2/m128 ; 66 0F 5F /r [WILLAMETTE,SSE2] + +\c{MAXPD} performs a SIMD compare of the packed double-precision +FP numbers from xmm1 and xmm2/mem, and stores the maximum values +of each pair of values in xmm1. If the values being compared are +both zeroes, source2 (xmm2/m128) would be returned. If source2 +(xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the +destination (i.e., a QNaN version of the SNaN is not returned). + + +\H{insMAXPS} \i\c{MAXPS}: Return Packed Single-Precision FP Maximum + +\c MAXPS xmm1,xmm2/m128 ; 0F 5F /r [KATMAI,SSE] + +\c{MAXPS} performs a SIMD compare of the packed single-precision +FP numbers from xmm1 and xmm2/mem, and stores the maximum values +of each pair of values in xmm1. If the values being compared are +both zeroes, source2 (xmm2/m128) would be returned. If source2 +(xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the +destination (i.e., a QNaN version of the SNaN is not returned). + + +\H{insMAXSD} \i\c{MAXSD}: Return Scalar Double-Precision FP Maximum + +\c MAXSD xmm1,xmm2/m64 ; F2 0F 5F /r [WILLAMETTE,SSE2] + +\c{MAXSD} compares the low-order double-precision FP numbers from +xmm1 and xmm2/mem, and stores the maximum value in xmm1. If the +values being compared are both zeroes, source2 (xmm2/m64) would +be returned. If source2 (xmm2/m64) is an SNaN, this SNaN is +forwarded unchanged to the destination (i.e., a QNaN version of +the SNaN is not returned). The high quadword of the destination +is left unchanged. + + +\H{insMAXSS} \i\c{MAXSD}: Return Scalar Single-Precision FP Maximum + +\c MAXSS xmm1,xmm2/m32 ; F3 0F 5F /r [KATMAI,SSE] -\c{MASKMOVQ} Data is stored from the mm1 register to the location - specified by the di/edi register (using DS segment). The size - of the store depends on the address-size attribute. The most - significant bit in each byte of the mask register mm2 is used - to selectively write the data (0 = no write, 1 = write) on a - per-byte basis. +\c{MAXSS} compares the low-order single-precision FP numbers from +xmm1 and xmm2/mem, and stores the maximum value in xmm1. If the +values being compared are both zeroes, source2 (xmm2/m32) would +be returned. If source2 (xmm2/m32) is an SNaN, this SNaN is +forwarded unchanged to the destination (i.e., a QNaN version of +the SNaN is not returned). The high three doublewords of the +destination are left unchanged. -\H{insMAXPS} \i\c{MAXPS}: Packed Single-FP Maximum +\H{insMFENCE} \i\c{MFENCE}: Memory Fence -\c MAXPS xmmreg,memory ; 0F,5F,/r [KATMAI,SSE] -\c MAXPS xmmreg,xmmreg ; ?? [KATMAI,SSE] +\c MFENCE ; 0F AE /6 [WILLAMETTE,SSE2] -\c{MAXPS}The MAXPS instruction returns the maximum SP FP numbers - from XMM1 and XMM2/Mem.If the values being compared are both - zeroes, source2 (xmm2/m128) would be returned. If source2 - (xmm2/m128) is an sNaN, this sNaN is forwarded unchanged - to the destination (i.e., a quieted version of the sNaN - is not returned). +\c{MFENCE} performs a serialising operation on all loads from memory +and writes to memory that were issued before the \c{MFENCE} instruction. +This guarantees that all memory reads and writes before the \c{MFENCE} +instruction are completed before any reads and writes after the +\c{MFENCE} instruction. +\c{MFENCE} is ordered respective to other \c{MFENCE} instructions, +\c{LFENCE}, \c{SFENCE}, any memory read and any other serialising +instruction (such as \c{CPUID}). -\H{insMAXSS} \i\c{MAXSS}: Scalar Single-FP Maximum +Weakly ordered memory types can be used to achieve higher processor +performance through such techniques as out-of-order issue, speculative +reads, write-combining, and write-collapsing. The degree to which a +consumer of data recognizes or knows that the data is weakly ordered +varies among applications and may be unknown to the producer of this +data. The \c{MFENCE} instruction provides a performance-efficient way +of ensuring load and store ordering between routines that produce +weakly-ordered results and routines that consume that data. -\c MAXSS xmmreg,memory ; F3,0F,5F,/r [KATMAI,SSE] -\c MAXSS xmmreg,xmmreg ; ?? [KATMAI,SSE] +\c{MFENCE} uses the following ModRM encoding: -\c{MAXSS}The MAXSS instruction returns the maximum SP FP number - from the lower SP FP numbers of XMM1 and XMM2/Mem; the upper - three fields are passed through from xmm1. If the values being - compared are both zeroes, source2 (xmm2/m128) will be returned. - If source2 (xmm2/m128) is an sNaN, this sNaN is forwarded - unchanged to the destination (i.e., a quieted version of the - sNaN is not returned). +\c Mod (7:6) = 11B +\c Reg/Opcode (5:3) = 110B +\c R/M (2:0) = 000B +All other ModRM encodings are defined to be reserved, and use +of these encodings risks incompatibility with future processors. -\H{insMINPS} \i\c{MINPS}: Packed Single-FP Minimum +See also \c{LFENCE} (\k{insLFENCE}) and \c{SFENCE} (\k{insSFENCE}). -\c MINPS xmmreg,memory ; 0F,5D,/r [KATMAI,SSE] -\c MINPS xmmreg,xmmreg ; ?? [KATMAI,SSE] -\c{MINPS} The MINPS instruction returns the minimum SP FP - numbers from XMM1 and XMM2/Mem. If the values being compared - are both zeroes, source2 (xmm2/m128) would be returned. If - source2 (xmm2/m128) is an sNaN, this sNaN is forwarded unchanged - to the destination (i.e., a quieted version of the sNaN is - not returned). +\H{insMINPD} \i\c{MINPD}: Return Packed Double-Precision FP Minimum +\c MINPD xmm1,xmm2/m128 ; 66 0F 5D /r [WILLAMETTE,SSE2] -\H{insMINSS} \i\c{MINSS}: Scalar Single-FP Minimum +\c{MINPD} performs a SIMD compare of the packed double-precision +FP numbers from xmm1 and xmm2/mem, and stores the minimum values +of each pair of values in xmm1. If the values being compared are +both zeroes, source2 (xmm2/m128) would be returned. If source2 +(xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the +destination (i.e., a QNaN version of the SNaN is not returned). -\c MINSS xmmreg,memory ; F3,0F,5D,/r [KATMAI,SSE] -\c MINSS xmmreg,xmmreg ; ?? [KATMAI,SSE] -\c{MINSS} The MINSS instruction returns the minimum SP FP number - from the lower SP FP numbers from XMM1 and XMM2/Mem; the upper - three fields are passed through from xmm1. If the values being - compared are both zeroes, source2 (xmm2/m128) would be returned. - If source2 (xmm2/m128) is an sNaN, this sNaN is forwarded - unchanged to the destination (i.e., a quieted version of the - sNaN is not returned). +\H{insMINPS} \i\c{MINPS}: Return Packed Single-Precision FP Minimum + +\c MINPS xmm1,xmm2/m128 ; 0F 5D /r [KATMAI,SSE] + +\c{MINPS} performs a SIMD compare of the packed single-precision +FP numbers from xmm1 and xmm2/mem, and stores the minimum values +of each pair of values in xmm1. If the values being compared are +both zeroes, source2 (xmm2/m128) would be returned. If source2 +(xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the +destination (i.e., a QNaN version of the SNaN is not returned). + + +\H{insMINSD} \i\c{MINSD}: Return Scalar Double-Precision FP Minimum + +\c MINSD xmm1,xmm2/m64 ; F2 0F 5D /r [WILLAMETTE,SSE2] + +\c{MINSD} compares the low-order double-precision FP numbers from +xmm1 and xmm2/mem, and stores the minimum value in xmm1. If the +values being compared are both zeroes, source2 (xmm2/m64) would +be returned. If source2 (xmm2/m64) is an SNaN, this SNaN is +forwarded unchanged to the destination (i.e., a QNaN version of +the SNaN is not returned). The high quadword of the destination +is left unchanged. + + +\H{insMINSS} \i\c{MINSD}: Return Scalar Single-Precision FP Minimum + +\c MINSS xmm1,xmm2/m32 ; F3 0F 5D /r [KATMAI,SSE] + +\c{MINSS} compares the low-order single-precision FP numbers from +xmm1 and xmm2/mem, and stores the minimum value in xmm1. If the +values being compared are both zeroes, source2 (xmm2/m32) would +be returned. If source2 (xmm2/m32) is an SNaN, this SNaN is +forwarded unchanged to the destination (i.e., a QNaN version of +the SNaN is not returned). The high three doublewords of the +destination are left unchanged. \H{insMOV} \i\c{MOV}: Move Data @@ -7875,89 +9410,272 @@ undefined. \c{CR4} is only a supported register on the Pentium and above. -\H{insMOVAPS} \i\c{MOVAPS}: Move Aligned Four Packed Single-FP +Test registers are supported on 386/486 processors and on some +non-Intel Pentium class processors. -\c MOVAPS xmmreg,memory ; 0F,28,/r [KATMAI,SSE] -\c MOVAPS memory,xmmreg ; 0F,29,/r [KATMAI,SSE] -\c MOVAPS xmmreg,xmmreg ; ?? [KATMAI,SSE] -\c MOVAPS xmmreg,xmmreg ; ?? [KATMAI,SSE] -\c{MOVAPS} The linear address corresponds to the address of the - least-significant byte of the referenced memory data. When a - memory address is indicated, the 16 bytes of data at memory - location m128 are loaded or stored. When the register-register - form of this operation is used, the content of the 128-bit - source register is copied into the 128-bit destination register. +\H{insMOVAPD} \i\c{MOVAPD}: Move Aligned Packed Double-Precision FP Values + +\c MOVAPD xmm1,xmm2/mem128 ; 66 0F 28 /r [WILLAMETTE,SSE2] +\c MOVAPD xmm1/mem128,xmm2 ; 66 0F 29 /r [WILLAMETTE,SSE2] + +\c{MOVAPS} moves a double quadword containing 2 packed double-precision +FP values from the source operand to the destination. When the source +or destination operand is a memory location, it must be aligned on a +16-byte boundary. + +To move data in and out of memory locations that are not known to be on +16-byte boundaries, use the \c{MOVUPD} instruction (\k{insMOVUPD}). + + +\H{insMOVAPS} \i\c{MOVAPS}: Move Aligned Packed Single-Precision FP Values + +\c MOVAPS xmm1,xmm2/mem128 ; 0F 28 /r [KATMAI,SSE] +\c MOVAPS xmm1/mem128,xmm2 ; 0F 29 /r [KATMAI,SSE] + +\c{MOVAPS} moves a double quadword containing 4 packed single-precision +FP values from the source operand to the destination. When the source +or destination operand is a memory location, it must be aligned on a +16-byte boundary. + +To move data in and out of memory locations that are not known to be on +16-byte boundaries, use the \c{MOVUPS} instruction (\k{insMOVUPS}). \H{insMOVD} \i\c{MOVD}: Move Doubleword to/from MMX Register -\c MOVD mmxreg,r/m32 ; 0F 6E /r [PENT,MMX] -\c MOVD r/m32,mmxreg ; 0F 7E /r [PENT,MMX] +\c MOVD mm,r/m32 ; 0F 6E /r [PENT,MMX] +\c MOVD r/m32,mm ; 0F 7E /r [PENT,MMX] +\c MOVD xmm,r/m32 ; 66 0F 6E /r [WILLAMETTE,SSE2] +\c MOVD r/m32,xmm ; 66 0F 7E /r [WILLAMETTE,SSE2] \c{MOVD} copies 32 bits from its source (second) operand into its -destination (first) operand. When the destination is a 64-bit MMX -register, the top 32 bits are set to zero. +destination (first) operand. When the destination is a 64-bit \c{MMX} +register or a 128-bit \c{XMM} register, the input value is zero-extended +to fill the destination register. + + +\H{insMOVDQ2Q} \i\c{MOVDQ2Q}: Move Quadword from XMM to MMX register. +\c MOVDQ2Q mm,xmm ; F2 OF D6 /r [WILLAMETTE,SSE2] -\H{insMOVHLPS} \i\c{MOVHLPS}: High to Low Packed Single-FP +\c{MOVDQ2Q} moves the low quadword from the source operand to the +destination operand. -\c MOVHLPS xmmreg,xmmreg ; OF,12,/r [KATMAI,SSE] -\c{MOVHLPS} The upper 64-bits of the source register xmm2 are - loaded into the lower 64-bits of the 128-bit register xmm1, - and the upper 64-bits of xmm1 are left unchanged. +\H{insMOVDQA} \i\c{MOVDQA}: Move Aligned Double Quadword +\c MOVDQA xmm1,xmm2/m128 ; 66 OF 6F /r [WILLAMETTE,SSE2] +\c MOVDQA xmm1/m128,xmm2 ; 66 OF 7F /r [WILLAMETTE,SSE2] -\H{insMOVHPS} \i\c{MOVHPS}: Move High Packed Single-FP +\c{MOVDQA} moves a double quadword from the source operand to the +destination operand. When the source or destination operand is a +memory location, it must be aligned to a 16-byte boundary. -\c MOVHPS xmmreg,memory ; 0F,16,/r [KATMAI,SSE] -\c MOVHPS memory,xmmreg ; 0F,17,/r [KATMAI,SSE] -\c MOVHPS xmmreg,xmmreg ; ?? [KATMAI,SSE,ND] +To move a double quadword to or from unaligned memory locations, +use the \c{MOVDQU} instruction (\k{insMOVDQU}). -\c{MOVHPS} The linear address corresponds to the address of the - least-significant byte of the referenced memory data. When the - load form of this operation is used, m64 is loaded into the - upper 64-bits of the 128-bit register xmm, and the lower 64-bits - are left unchanged. +\H{insMOVDQU} \i\c{MOVDQU}: Move Unaligned Double Quadword -\H{insMOVMSKPS} \i\c{MOVMSKPS}: Move Mask To Integer +\c MOVDQU xmm1,xmm2/m128 ; F3 OF 6F /r [WILLAMETTE,SSE2] +\c MOVDQU xmm1/m128,xmm2 ; F3 OF 7F /r [WILLAMETTE,SSE2] -\c MOVMSKPS reg32,xmmreg ; 0F,50,/r [KATMAI,SSE] +\c{MOVDQU} moves a double quadword from the source operand to the +destination operand. When the source or destination operand is a +memory location, the memory may be unaligned. -\c{MOVMSKPS} The MOVMSKPS instruction returns to the integer - register r32 a 4-bit mask formed of the most significant bits - of each SP FP number of its operand. +To move a double quadword to or from known aligned memory locations, +use the \c{MOVDQA} instruction (\k{insMOVDQA}). -\H{insMOVNTPS} \i\c{MOVNTPS}: Move Aligned Four Packed Single-FP - Non Temporal +\H{insMOVHLPS} \i\c{MOVHLPS}: Move Packed Single-Precision FP High to Low -\c MOVNTPS memory,xmmreg ; 0F,2B, /r [KATMAI,SSE] +\c MOVHLPS xmm1,xmm2 ; OF 12 /r [KATMAI,SSE] -\c{MOVNTPS} The linear address corresponds to the address of the - least-significant byte of the referenced memory data. This store - instruction minimizes cache pollution. +\c{MOVHLPS} moves the two packed single-precision FP values from the +high quadword of the source register xmm2 to the low quadword of the +destination register, xmm2. The upper quadword of xmm1 is left unchanged. +The operation of this instruction is: -\H{insMOVNTQ} \i\c{MOVNTQ}: Move 64 Bits Non Temporal +\c dst[0-63] := src[64-127], +\c dst[64-127] remains unchanged. -\c MOVNTQ memory,mmxreg ; 0F,E7,/r [KATMAI,MMX,SM] -\c{MOVNTQ} The linear address corresponds to the address of the - least-significant byte of the referenced memory data. This store - instruction minimizes cache pollution. +\H{insMOVHPD} \i\c{MOVHPD}: Move High Packed Double-Precision FP + +\c MOVHPD xmm,m64 ; 66 OF 16 /r [WILLAMETTE,SSE2] +\c MOVHPD m64,xmm ; 66 OF 17 /r [WILLAMETTE,SSE2] + +\c{MOVHPD} moves a double-precision FP value between the source and +destination operands. One of the operands is a 64-bit memory location, +the other is the high quadword of an \c{XMM} register. + +The operation of this instruction is: + +\c mem[0-63] := xmm[64-127]; + +or + +\c xmm[0-63] remains unchanged; +\c xmm[64-127] := mem[0-63]. + + +\H{insMOVHPS} \i\c{MOVHPS}: Move High Packed Single-Precision FP + +\c MOVHPS xmm,m64 ; 0F 16 /r [KATMAI,SSE] +\c MOVHPS m64,xmm ; 0F 17 /r [KATMAI,SSE] + +\c{MOVHPS} moves two packed single-precision FP values between the source +and destination operands. One of the operands is a 64-bit memory location, +the other is the high quadword of an \c{XMM} register. + +The operation of this instruction is: + +\c mem[0-63] := xmm[64-127]; + +or + +\c xmm[0-63] remains unchanged; +\c xmm[64-127] := mem[0-63]. + + +\H{insMOVLHPS} \i\c{MOVLHPS}: Move Packed Single-Precision FP Low to High + +\c MOVLHPS xmm1,xmm2 ; OF 16 /r [KATMAI,SSE] + +\c{MOVLHPS} moves the two packed single-precision FP values from the +low quadword of the source register xmm2 to the high quadword of the +destination register, xmm2. The low quadword of xmm1 is left unchanged. + +The operation of this instruction is: + +\c dst[0-63] remains unchanged; +\c dst[64-127] := src[0-63]. + +\H{insMOVLPD} \i\c{MOVLPD}: Move Low Packed Double-Precision FP + +\c MOVLPD xmm,m64 ; 66 OF 12 /r [WILLAMETTE,SSE2] +\c MOVLPD m64,xmm ; 66 OF 13 /r [WILLAMETTE,SSE2] + +\c{MOVLPD} moves a double-precision FP value between the source and +destination operands. One of the operands is a 64-bit memory location, +the other is the low quadword of an \c{XMM} register. + +The operation of this instruction is: + +\c mem(0-63) := xmm(0-63); + +or + +\c xmm(0-63) := mem(0-63); +\c xmm(64-127) remains unchanged. + +\H{insMOVLPS} \i\c{MOVLPS}: Move Low Packed Single-Precision FP + +\c MOVLPS xmm,m64 ; OF 12 /r [KATMAI,SSE] +\c MOVLPS m64,xmm ; OF 13 /r [KATMAI,SSE] + +\c{MOVLPS} moves two packed single-precision FP values between the source +and destination operands. One of the operands is a 64-bit memory location, +the other is the low quadword of an \c{XMM} register. + +The operation of this instruction is: + +\c mem(0-63) := xmm(0-63); + +or + +\c xmm(0-63) := mem(0-63); +\c xmm(64-127) remains unchanged. + + +\H{insMOVMSKPD} \i\c{MOVMSKPD}: Extract Packed Double-Precision FP Sign Mask + +\c MOVMSKPD reg32,xmm ; 66 0F 50 /r [WILLAMETTE,SSE2] + +\c{MOVMSKPD} inserts a 2-bit mask in r32, formed of the most significant +bits of each double-precision FP number of the source operand. + + +\H{insMOVMSKPS} \i\c{MOVMSKPS}: Extract Packed Single-Precision FP Sign Mask + +\c MOVMSKPS reg32,xmm ; 0F 50 /r [KATMAI,SSE] + +\c{MOVMSKPS} inserts a 4-bit mask in r32, formed of the most significant +bits of each single-precision FP number of the source operand. + + +\H{insMOVNTDQ} \i\c{MOVNTDQ}: Move Double Quadword Non Temporal + +\c MOVNTDQ m128,xmm ; 66 0F E7 /r [WILLAMETTE,SSE2] + +\c{MOVNTDQ} moves the double quadword from the \c{XMM} source +register to the destination memory location, using a non-temporal +hint. This store instruction minimizes cache pollution. + + +\H{insMOVNTI} \i\c{MOVNTI}: Move Doubleword Non Temporal + +\c MOVNTI m32,reg32 ; 0F C3 /r [WILLAMETTE,SSE2] + +\c{MOVNTI} moves the doubleword in the source register +to the destination memory location, using a non-temporal +hint. This store instruction minimizes cache pollution. + + +\H{insMOVNTPD} \i\c{MOVNTPD}: Move Aligned Four Packed Single-Precision +FP Values Non Temporal + +\c MOVNTPD m128,xmm ; 66 0F 2B /r [WILLAMETTE,SSE2] + +\c{MOVNTPD} moves the double quadword from the \c{XMM} source +register to the destination memory location, using a non-temporal +hint. This store instruction minimizes cache pollution. The memory +location must be aligned to a 16-byte boundary. + + +\H{insMOVNTPS} \i\c{MOVNTPS}: Move Aligned Four Packed Single-Precision +FP Values Non Temporal + +\c MOVNTPS m128,xmm ; 0F 2B /r [KATMAI,SSE] + +\c{MOVNTPS} moves the double quadword from the \c{XMM} source +register to the destination memory location, using a non-temporal +hint. This store instruction minimizes cache pollution. The memory +location must be aligned to a 16-byte boundary. + + +\H{insMOVNTQ} \i\c{MOVNTQ}: Move Quadword Non Temporal + +\c MOVNTQ m64,mm ; 0F E7 /r [KATMAI,MMX] + +\c{MOVNTQ} moves the quadword in the \c{MMX} source register +to the destination memory location, using a non-temporal +hint. This store instruction minimizes cache pollution. \H{insMOVQ} \i\c{MOVQ}: Move Quadword to/from MMX Register -\c MOVQ mmxreg,r/m64 ; 0F 6F /r [PENT,MMX] -\c MOVQ r/m64,mmxreg ; 0F 7F /r [PENT,MMX] +\c MOVQ mm1,mm2/m64 ; 0F 6F /r [PENT,MMX] +\c MOVQ mm1/m64,mm2 ; 0F 7F /r [PENT,MMX] + +\c MOVQ xmm1,xmm2/m64 ; F3 0F 7E /r [WILLAMETTE,SSE2] +\c MOVQ xmm1/m64,xmm2 ; 66 0F D6 /r [WILLAMETTE,SSE2] \c{MOVQ} copies 64 bits from its source (second) operand into its -destination (first) operand. +destination (first) operand. When the source is an \c{XMM} register, +the low quadword is moved. When the destination is an \c{XMM} register, +the destination is the low quadword, and the high quadword is cleared. + + +\H{insMOVQ2DQ} \i\c{MOVQ2DQ}: Move Quadword from MMX to XMM register. +\c MOVQ2DQ xmm,mm ; F3 OF D6 /r [WILLAMETTE,SSE2] + +\c{MOVQ2DQ} moves the quadword from the source operand to the low +quadword of the destination operand, and clears the high quadword. \H{insMOVSB} \i\c{MOVSB}, \i\c{MOVSW}, \i\c{MOVSD}: Move String @@ -7988,20 +9706,25 @@ addressing registers by 2 or 4 instead of 1. The \c{REP} prefix may be used to repeat the instruction \c{CX} (or \c{ECX} - again, the address size chooses which) times. -\H{insMOVSS} \i\c{MOVSS}: Move Scalar Single-FP -\c MOVSS xmmreg,memory ; F3,0F,10,/r [KATMAI,SSE] -\c MOVSS memory,xmmreg ; F3,0F,11,/r [KATMAI,SSE] -\c MOVSS xmmreg,xmmreg ; ?? [KATMAI,SSE] -\c MOVSS xmmreg,xmmreg ; ?? [KATMAI,SSE] +\H{insMOVSD} \i\c{MOVSD}: Move Scalar Double-Precision FP Value + +\c MOVSD xmm1,xmm2/m64 ; F2 0F 10 /r [WILLAMETTE,SSE2] +\c MOVSD xmm1/m64,xmm2 ; F2 0F 11 /r [WILLAMETTE,SSE2] + +\c{MOVDS} moves a double-precision FP value from the source operand +to the destination operand. When the source or destination is a +register, the low-order FP value is read or written. + + +\H{insMOVSS} \i\c{MOVSS}: Move Scalar Single-Precision FP Value -\c{MOVSS} The linear address corresponds to the address of - the least-significant byte of the referenced memory data. - When a memory address is indicated, the four bytes of data - at memory location m32 are loaded or stored. When the load - form of this operation is used, the 32 bits from memory are - copied into the lower 32 bits of the 128-bit register xmm, - the 96 most significant bits being cleared. +\c MOVSS xmm1,xmm2/m32 ; F3 0F 10 /r [KATMAI,SSE] +\c MOVSS xmm1/m32,xmm2 ; F3 0F 11 /r [KATMAI,SSE] + +\c{MOVSS} moves a single-precision FP value from the source operand +to the destination operand. When the source or destination is a +register, the low-order FP value is read or written. \H{insMOVSX} \i\c{MOVSX}, \i\c{MOVZX}: Move Data with Sign or Zero Extend @@ -8020,21 +9743,30 @@ destination operand. \c{MOVZX} does the same, but zero-extends rather than sign-extending. -\H{insMOVUPS} \i\c{MOVUPS}: Move Unaligned Four Packed Single-FP +\H{insMOVUPD} \i\c{MOVUPD}: Move Unaligned Packed Double-Precision FP Values + +\c MOVUPD xmm1,xmm2/mem128 ; 66 0F 10 /r [WILLAMETTE,SSE2] +\c MOVUPD xmm1/mem128,xmm2 ; 66 0F 11 /r [WILLAMETTE,SSE2] + +\c{MOVUPD} moves a double quadword containing 2 packed double-precision +FP values from the source operand to the destination. This instruction +makes no assumptions about alignment of memory operands. + +To move data in and out of memory locations that are known to be on 16-byte +boundaries, use the \c{MOVAPD} instruction (\k{insMOVAPD}). + -\c MOVUPS xmmreg,memory ; 0F,10,/r [KATMAI,SSE] -\c MOVUPS memory,xmmreg ; 0F,11,/r [KATMAI,SSE] -\c MOVUPS xmmreg,xmmreg ; ?? [KATMAI,SSE] -\c MOVUPS xmmreg,xmmreg ; ?? [KATMAI,SSE] +\H{insMOVUPS} \i\c{MOVUPS}: Move Unaligned Packed Single-Precision FP Values -\c{MOVUPS} The linear address corresponds to the address of the - least-significant byte of the referenced memory data. When a - memory address is indicated, the 16 bytes of data at memory - location m128 are loaded to the 128-bit multimedia register - xmm or stored from the 128-bit multimedia register xmm. When - the register-register form of this operation is used, the content - of the 128-bit source register is copied into 128-bit register - xmm. No assumption is made about alignment. +\c MOVUPS xmm1,xmm2/mem128 ; 0F 10 /r [KATMAI,SSE] +\c MOVUPS xmm1/mem128,xmm2 ; 0F 11 /r [KATMAI,SSE] + +\c{MOVUPS} moves a double quadword containing 4 packed single-precision +FP values from the source operand to the destination. This instruction +makes no assumptions about alignment of memory operands. + +To move data in and out of memory locations that are known to be on 16-byte +boundaries, use the \c{MOVAPS} instruction (\k{insMOVAPS}). \H{insMUL} \i\c{MUL}: Unsigned Integer Multiply @@ -8059,25 +9791,37 @@ the product is stored in \c{EDX:EAX}. Signed integer multiplication is performed by the \c{IMUL} instruction: see \k{insIMUL}. + +\H{insMULPD} \i\c{MULPD}: Packed Single-FP Multiply + +\c MULPD xmm1,xmm2/mem128 ; 66 0F 59 /r [WILLAMETTE,SSE2] + +\c{MULPD} performs a SIMD multiply of the packed double-precision FP +values in both operands, and stores the results in the destination register. + + \H{insMULPS} \i\c{MULPS}: Packed Single-FP Multiply -\c MULPS xmmreg,memory ; 0F,59,/r [KATMAI,SSE] -\c MULPS xmmreg,xmmreg ; ?? [KATMAI,SSE] +\c MULPS xmm1,xmm2/mem128 ; 0F 59 /r [KATMAI,SSE] +\c{MULPS} performs a SIMD multiply of the packed single-precision FP +values in both operands, and stores the results in the destination register. -\c{MULPS} The MULPS instructions multiply the packed SP FP - numbers of both their operands. +\H{insMULSD} \i\c{MULSD}: Scalar Single-FP Multiply + +\c MULSD xmm1,xmm2/mem32 ; F2 0F 59 /r [WILLAMETTE,SSE2] + +\c{MULSD} multiplies the lowest double-precision FP values of both +operands, and stores the result in the low quadword of xmm1. -\H{insMULSS} \i\c{MULSS}: Scalar Single-FP Multiply +\H{insMULSS} \i\c{MULSS}: Scalar Single-FP Multiply -\c MULSS xmmreg,memory ; F3,0F,59,/r [KATMAI,SSE] -\c MULSS xmmreg,xmmreg ; ?? [KATMAI,SSE] +\c MULSS xmm1,xmm2/mem32 ; F3 0F 59 /r [KATMAI,SSE] -\c{MULSS}The MULSS instructions multiply the lowest SP FP - numbers of both their operands; the upper three fields - are passed through from xmm1. +\c{MULSS} multiplies the lowest single-precision FP values of both +operands, and stores the result in the low doubleword of xmm1. \H{insNEG} \i\c{NEG}, \i\c{NOT}: Two's and One's Complement @@ -8095,6 +9839,7 @@ negation (invert all the bits and then add one) of the original value. \c{NOT}, similarly, performs one's complement (inverts all the bits). + \H{insNOP} \i\c{NOP}: No Operation \c NOP ; 90 [8086] @@ -8103,6 +9848,7 @@ the bits). generated by \c{XCHG AX,AX} or \c{XCHG EAX,EAX} (depending on the processor mode; see \k{insXCHG}). + \H{insOR} \i\c{OR}: Bitwise OR \c OR r/m8,reg8 ; 08 /r [8086] @@ -8138,13 +9884,23 @@ form of the instruction. The MMX instruction \c{POR} (see \k{insPOR}) performs the same operation on the 64-bit MMX registers. -\H{insORPS} \i\c{ORPS}: Bit-wise Logical OR for Single-FP Data -\c ORPS xmmreg,memory ; 0F,56,/r [KATMAI,SSE] -\c ORPS xmmreg,xmmreg ; ?? [KATMAI,SSE] +\H{insORPD} \i\c{ORPD}: Bit-wise Logical OR of Double-Precision FP Data + +\c ORPD xmm1,xmm2/m128 ; 66 0F 56 /r [WILLAMETTE,SSE2] + +\c{ORPD} return a bit-wise logical OR between xmm1 and xmm2/mem, +and stores the result in xmm1. If the source operand is a memory +location, it must be aligned to a 16-byte boundary. -\c{ORPS} The ORPS instructions return a bit-wise logical - OR between xmm1 and xmm2/mem. + +\H{insORPS} \i\c{ORPS}: Bit-wise Logical OR of Single-Precision FP Data + +\c ORPS xmm1,xmm2/m128 ; 0F 56 /r [KATMAI,SSE] + +\c{ORPS} return a bit-wise logical OR between xmm1 and xmm2/mem, +and stores the result in xmm1. If the source operand is a memory +location, it must be aligned to a 16-byte boundary. \H{insOUT} \i\c{OUT}: Output Data to I/O Port @@ -8161,6 +9917,7 @@ specified I/O port. The port number may be specified as an immediate value if it is between 0 and 255, and otherwise must be stored in \c{DX}. See also \c{IN} (\k{insIN}). + \H{insOUTSB} \i\c{OUTSB}, \i\c{OUTSW}, \i\c{OUTSD}: Output String to I/O Port \c OUTSB ; 6E [186] @@ -8190,74 +9947,139 @@ the addressing registers by 2 or 4 instead of 1. The \c{REP} prefix may be used to repeat the instruction \c{CX} (or \c{ECX} - again, the address size chooses which) times. + \H{insPACKSSDW} \i\c{PACKSSDW}, \i\c{PACKSSWB}, \i\c{PACKUSWB}: Pack Data -\c PACKSSDW mmxreg,r/m64 ; 0F 6B /r [PENT,MMX] -\c PACKSSWB mmxreg,r/m64 ; 0F 63 /r [PENT,MMX] -\c PACKUSWB mmxreg,r/m64 ; 0F 67 /r [PENT,MMX] - -All these instructions start by forming a notional 128-bit word by -placing the source (second) operand on the left of the destination -(first) operand. \c{PACKSSDW} then splits this 128-bit word into -four doublewords, converts each to a word, and loads them side by -side into the destination register; \c{PACKSSWB} and \c{PACKUSWB} -both split the 128-bit word into eight words, converts each to a -byte, and loads \e{those} side by side into the destination +\c PACKSSDW mm1,mm2/m64 ; 0F 6B /r [PENT,MMX] +\c PACKSSWB mm1,mm2/m64 ; 0F 63 /r [PENT,MMX] +\c PACKUSWB mm1,mm2/m64 ; 0F 67 /r [PENT,MMX] + +\c PACKSSDW xmm1,xmm2/m128 ; 66 0F 6B /r [WILLAMETTE,SSE2] +\c PACKSSWB xmm1,xmm2/m128 ; 66 0F 63 /r [WILLAMETTE,SSE2] +\c PACKUSWB xmm1,xmm2/m128 ; 66 0F 67 /r [WILLAMETTE,SSE2] + +All these instructions start by combining the source and destination +operands, and then splitting the result in smaller sections which it +then packs into the destination register. The \c{MMX} versions pack +two 64-bit operands into one 64-bit register, while the \c{SSE} +versions pack two 128-bit operands into one 128-bit register. + +\b \c{PACKSSWB} splits the combined value into words, and then reduces +the words to btes, using signed saturation. It then packs the bytes +into the destination register in the same order the words were in. + +\b \c{PACKSSDW} performs the same operation as \c{PACKSSWB}, except that +it reduces doublewords to words, then packs them into the destination register. -\c{PACKSSDW} and \c{PACKSSWB} perform signed saturation when -reducing the length of numbers: if the number is too large to fit -into the reduced space, they replace it by the largest signed number -(\c{7FFFh} or \c{7Fh}) that \e{will} fit, and if it is too small -then they replace it by the smallest signed number (\c{8000h} or -\c{80h}) that will fit. \c{PACKUSWB} performs unsigned saturation: -it treats its input as unsigned, and replaces it by the largest -unsigned number that will fit. - -\H{insPADDB} \i\c{PADDxx}: MMX Packed Addition - -\c PADDB mmxreg,r/m64 ; 0F FC /r [PENT,MMX] -\c PADDW mmxreg,r/m64 ; 0F FD /r [PENT,MMX] -\c PADDD mmxreg,r/m64 ; 0F FE /r [PENT,MMX] - -\c PADDSB mmxreg,r/m64 ; 0F EC /r [PENT,MMX] -\c PADDSW mmxreg,r/m64 ; 0F ED /r [PENT,MMX] - -\c PADDUSB mmxreg,r/m64 ; 0F DC /r [PENT,MMX] -\c PADDUSW mmxreg,r/m64 ; 0F DD /r [PENT,MMX] - -\c{PADDxx} all perform packed addition between their two 64-bit -operands, storing the result in the destination (first) operand. The -\c{PADDxB} forms treat the 64-bit operands as vectors of eight -bytes, and add each byte individually; \c{PADDxW} treat the operands -as vectors of four words; and \c{PADDD} treats its operands as -vectors of two doublewords. - -\c{PADDSB} and \c{PADDSW} perform signed saturation on the sum of -each pair of bytes or words: if the result of an addition is too -large or too small to fit into a signed byte or word result, it is -clipped (saturated) to the largest or smallest value which \e{will} -fit. \c{PADDUSB} and \c{PADDUSW} similarly perform unsigned -saturation, clipping to \c{0FFh} or \c{0FFFFh} if the result is -larger than that. - -\H{insPADDSIW} \i\c{PADDSIW}: MMX Packed Addition to Implicit -Destination +\b \c{PACKUSWB} performs the same operation as \c{PACKSSWB}, except that +it uses unsigned saturation when reducing the size of the elements. + +To perform signed saturation on a number, it is replaced by the largest +signed number (\c{7FFFh} or \c{7Fh}) that \e{will} fit, and if it is too +small it is replaced by the smallest signed number (\c{8000h} or +\c{80h}) that will fit. To perform unsigned saturation, the input is +treated as unsigned, and the input is replaced by the largest unsigned +number that will fit. + + +\H{insPADDB} \i\c{PADDB}, \i\c{PADDW}, \i\c{PADDD}: Add Packed Integers + +\c PADDB mm1,mm2/m64 ; 0F FC /r [PENT,MMX] +\c PADDW mm1,mm2/m64 ; 0F FD /r [PENT,MMX] +\c PADDD mm1,mm2/m64 ; 0F FE /r [PENT,MMX] + +\c PADDB xmm1,xmm2/m128 ; 66 0F FC /r [WILLAMETTE,SSE2] +\c PADDW xmm1,xmm2/m128 ; 66 0F FD /r [WILLAMETTE,SSE2] +\c PADDD xmm1,xmm2/m128 ; 66 0F FE /r [WILLAMETTE,SSE2] + +\c{PADDx} performs packed addition of the two operands, storing the +result in the destination (first) operand. + +\b \c{PADDB} treats the operands as packed bytes, and adds each byte +individually; + +\b \c{PADDW} treats the operands as packed words; + +\b \c{PADDD} treats its operands as packed doublewords. + +When an individual result is too large to fit in its destination, it +is wrapped around and the low bits are stored, with the carry bit +discarded. + + +\H{insPADDQ} \i\c{PADDQ}: Add Packed Quadword Integers + +\c PADDQ mm1,mm2/m64 ; 0F D4 /r [PENT,MMX] + +\c PADDQ xmm1,xmm2/m128 ; 66 0F D4 /r [WILLAMETTE,SSE2] + +\c{PADDQ} adds the quadwords in the source and destination operands, and +stores the result in the destination register. + +When an individual result is too large to fit in its destination, it +is wrapped around and the low bits are stored, with the carry bit +discarded. + + +\H{insPADDSB} \i\c{PADDSB}, \i\c{PADDSW}: Add Packed Signed Integers With Saturation + +\c PADDSB mm1,mm2/m64 ; 0F EC /r [PENT,MMX] +\c PADDSW mm1,mm2/m64 ; 0F ED /r [PENT,MMX] + +\c PADDSB xmm1,xmm2/m128 ; 66 0F EC /r [WILLAMETTE,SSE2] +\c PADDSW xmm1,xmm2/m128 ; 66 0F ED /r [WILLAMETTE,SSE2] + +\c{PADDSx} performs packed addition of the two operands, storing the +result in the destination (first) operand. +\c{PADDSB} treats the operands as packed bytes, and adds each byte +individually; and \c{PADDSW} treats the operands as packed words. + +When an individual result is too large to fit in its destination, a +saturated value is stored. The resulting value is the value with the +largest magnitude of the same sign as the result which will fit in +the available space. + + +\H{insPADDSIW} \i\c{PADDSIW}: MMX Packed Addition to Implicit Destination \c PADDSIW mmxreg,r/m64 ; 0F 51 /r [CYRIX,MMX] \c{PADDSIW}, specific to the Cyrix extensions to the MMX instruction -set, performs the same function as \c{PADDSW}, except that the -result is not placed in the register specified by the first operand, -but instead in the register whose number differs from the first -operand only in the last bit. So \c{PADDSIW MM0,MM2} would put the -result in \c{MM1}, but \c{PADDSIW MM1,MM2} would put the result in -\c{MM0}. +set, performs the same function as \c{PADDSW}, except that the result +is placed in an implied register. + +To work out the implied register, invert the lowest bit in the register +number. So \c{PADDSIW MM0,MM2} would put the result in \c{MM1}, but +\c{PADDSIW MM1,MM2} would put the result in \c{MM0}. + + +\H{insPADDUSB} \i\c{PADDUSB}, \i\c{PADDUSW}: Add Packed Unsigned Integers With Saturation + +\c PADDUSB mm1,mm2/m64 ; 0F DC /r [PENT,MMX] +\c PADDUSW mm1,mm2/m64 ; 0F DD /r [PENT,MMX] + +\c PADDUSB xmm1,xmm2/m128 ; 66 0F DC /r [WILLAMETTE,SSE2] +\c PADDUSW xmm1,xmm2/m128 ; 66 0F DD /r [WILLAMETTE,SSE2] + +\c{PADDUSx} performs packed addition of the two operands, storing the +result in the destination (first) operand. +\c{PADDUSB} treats the operands as packed bytes, and adds each byte +individually; and \c{PADDUSW} treats the operands as packed words. + +When an individual result is too large to fit in its destination, a +saturated value is stored. The resulting value is the maximum value +that will fit in the available space. + \H{insPAND} \i\c{PAND}, \i\c{PANDN}: MMX Bitwise AND and AND-NOT -\c PAND mmxreg,r/m64 ; 0F DB /r [PENT,MMX] -\c PANDN mmxreg,r/m64 ; 0F DF /r [PENT,MMX] +\c PAND mm1,mm2/m64 ; 0F DB /r [PENT,MMX] +\c PANDN mm1,mm2/m64 ; 0F DF /r [PENT,MMX] + +\c PAND xmm1,xmm2/m128 ; 66 0F DB /r [WILLAMETTE,SSE2] +\c PANDN xmm1,xmm2/m128 ; 66 0F DF /r [WILLAMETTE,SSE2] + \c{PAND} performs a bitwise AND operation between its two operands (i.e. each bit of the result is 1 if and only if the corresponding @@ -8267,6 +10089,17 @@ destination (first) operand. \c{PANDN} performs the same operation, but performs a one's complement operation on the destination (first) operand first. + +\H{insPAUSE} \i\c{PAUSE}: Spin Loop Hint + +\c PAUSE ; F3 90 [WILLAMETTE,SSE2] + +\c{PAUSE} provides a hint to the processor that the following code +is a spin loop. This improves processor performance by bypassing +possible memory order violations. On older processors, this instruction +operates as a \c{NOP}. + + \H{insPAVEB} \i\c{PAVEB}: MMX Packed Average \c PAVEB mmxreg,r/m64 ; 0F 50 /r [CYRIX,MMX] @@ -8276,47 +10109,62 @@ operands as vectors of eight unsigned bytes, and calculates the average of the corresponding bytes in the operands. The resulting vector of eight averages is stored in the first operand. +This opcode maps to \c{MOVMSKPS r32, xmm} on processors that support +the SSE instruction set. + -\H{insPAVGB} \i\c{PAVGB}: Packed Average +\H{insPAVGB} \i\c{PAVGB} \i\c{PAVGW}: Average Packed Integers -\c PAVGB mmxreg,mmxreg ; 0F,E0, /r [KATMAI,MMX] -\c PAVGB mmxreg,memory ; 0F,E3, /r [KATMAI,MMX,SM] +\c PAVGB mm1,mm2/m64 ; 0F E0 /r [KATMAI,MMX] +\c PAVGW mm1,mm2/m64 ; 0F E3 /r [KATMAI,MMX,SM] +\c PAVGB xmm1,xmm2/m128 ; 66 0F E0 /r [WILLAMETTE,SSE2] +\c PAVGW xmm1,xmm2/m128 ; 66 0F E3 /r [WILLAMETTE,SSE2] -\H{insPAVGW} \i\c{PAVGW}: Packed Average +\c{PAVGB} and \c{PAVGW} add the unsigned data elements of the source +operand to the unsigned data elements of the destination register, +then adds 1 to the temporary results. The results of the add are then +each independently right-shifted by one bit position. The high order +bits of each element are filled with the carry bits of the corresponding +sum. -\c PAVGW mmxreg,mmxreg ; ?? [KATMAI,MMX] -\c PAVGW mmxreg,memory ; ?? [KATMAI,MMX,SM] +\b \c{PAVGB} operates on packed unsigned bytes, and -\c{PAVGB} The PAVG instructions add the unsigned data elements - of the source operand to the unsigned data elements of the - destination register, along with a carry-in. The results of - the add are then each independently right-shifted by one bit - position. The high order bits of each element are filled with - the carry bits of the corresponding sum. The destination operand - is an MMXTM technology register. The source operand can either - be an MMXTM technology register or a 64-bit memory operand. - The PAVGB instruction operates on packed unsigned bytes, and - the PAVGW instruction operates on packed unsigned words. +\b \c{PAVGW} operates on packed unsigned words. -\H{insPAVGUSB} \i\c{PAVGUSB}: 3dnow instruction (duh!) +\H{insPAVGUSB} \i\c{PAVGUSB}: Average of unsigned packed 8-bit values -\c PAVGUSB mmxreg,memory ; ?? [PENT,3DNOW,SM] -\c PAVGUSB mmxreg,mmxreg ; ?? [PENT,3DNOW] +\c PAVGUSB mm1,mm2/m64 ; 0F 0F /r BF [PENT,3DNOW] -3dnow instruction (duh!) +\c{PAVGUSB} adds the unsigned data elements of the source operand to +the unsigned data elements of the destination register, then adds 1 +to the temporary results. The results of the add are then each +independently right-shifted by one bit position. The high order bits +of each element are filled with the carry bits of the corresponding +sum. +This instruction performs exactly the same operations as the \c{PAVGB} +\c{MMX} instruction (\k{insPAVGB}). -\H{insPCMPEQB} \i\c{PCMPxx}: MMX Packed Comparison -\c PCMPEQB mmxreg,r/m64 ; 0F 74 /r [PENT,MMX] -\c PCMPEQW mmxreg,r/m64 ; 0F 75 /r [PENT,MMX] -\c PCMPEQD mmxreg,r/m64 ; 0F 76 /r [PENT,MMX] +\H{insPCMPEQB} \i\c{PCMPxx}: Compare Packed Integers. -\c PCMPGTB mmxreg,r/m64 ; 0F 64 /r [PENT,MMX] -\c PCMPGTW mmxreg,r/m64 ; 0F 65 /r [PENT,MMX] -\c PCMPGTD mmxreg,r/m64 ; 0F 66 /r [PENT,MMX] +\c PCMPEQB mm1,mm2/m64 ; 0F 74 /r [PENT,MMX] +\c PCMPEQW mm1,mm2/m64 ; 0F 75 /r [PENT,MMX] +\c PCMPEQD mm1,mm2/m64 ; 0F 76 /r [PENT,MMX] + +\c PCMPGTB mm1,mm2/m64 ; 0F 64 /r [PENT,MMX] +\c PCMPGTW mm1,mm2/m64 ; 0F 65 /r [PENT,MMX] +\c PCMPGTD mm1,mm2/m64 ; 0F 66 /r [PENT,MMX] + +\c PCMPEQB xmm1,xmm2/m128 ; 66 0F 74 /r [WILLAMETTE,SSE2] +\c PCMPEQW xmm1,xmm2/m128 ; 66 0F 75 /r [WILLAMETTE,SSE2] +\c PCMPEQD xmm1,xmm2/m128 ; 66 0F 76 /r [WILLAMETTE,SSE2] + +\c PCMPGTB xmm1,xmm2/m128 ; 66 0F 64 /r [WILLAMETTE,SSE2] +\c PCMPGTW xmm1,xmm2/m128 ; 66 0F 65 /r [WILLAMETTE,SSE2] +\c PCMPGTD xmm1,xmm2/m128 ; 66 0F 66 /r [WILLAMETTE,SSE2] The \c{PCMPxx} instructions all treat their operands as vectors of bytes, words, or doublewords; corresponding elements of the source @@ -8324,20 +10172,24 @@ and destination are compared, and the corresponding element of the destination (first) operand is set to all zeros or all ones depending on the result of the comparison. -\c{PCMPxxB} treats the operands as vectors of eight bytes, -\c{PCMPxxW} treats them as vectors of four words, and \c{PCMPxxD} as -two doublewords. +\b \c{PCMPxxB} treats the operands as vectors of bytes; + +\b \c{PCMPxxW} treats the operands as vectors of words; + +\b \c{PCMPxxD} treats the operands as vectors of doublewords; -\c{PCMPEQx} sets the corresponding element of the destination +\b \c{PCMPEQx} sets the corresponding element of the destination operand to all ones if the two elements compared are equal; -\c{PCMPGTx} sets the destination element to all ones if the element + +\b \c{PCMPGTx} sets the destination element to all ones if the element of the first (destination) operand is greater (treated as a signed integer) than that of the second (source) operand. + \H{insPDISTIB} \i\c{PDISTIB}: MMX Packed Distance and Accumulate with Implied Register -\c PDISTIB mmxreg,mem64 ; 0F 54 /r [CYRIX,MMX] +\c PDISTIB mm,m64 ; 0F 54 /r [CYRIX,MMX] \c{PDISTIB}, specific to the Cyrix MMX extensions, treats its two input operands as vectors of eight unsigned bytes. For each byte @@ -8346,200 +10198,356 @@ position in the two input operands, and adds that value to the byte in the same position in the implied output register. The addition is saturated to an unsigned byte in the same way as \c{PADDUSB}. -The implied output register is found in the same way as \c{PADDSIW} -(\k{insPADDSIW}). +To work out the implied register, invert the lowest bit in the register +number. So \c{PDISTIB MM0,M64} would put the result in \c{MM1}, but +\c{PDISTIB MM1,M64} would put the result in \c{MM0}. Note that \c{PDISTIB} cannot take a register as its second source operand. +Opration: + +\c dstI[0-7] := dstI[0-7] + ABS(src0[0-7] - src1[0-7]), +\c dstI[8-15] := dstI[8-15] + ABS(src0[8-15] - src1[8-15]), +\c ....... +\c ....... +\c dstI[56-63] := dstI[56-63] + ABS(src0[56-63] - src1[56-63]). + \H{insPEXTRW} \i\c{PEXTRW}: Extract Word -\c PEXTRW reg32,mmxreg,immediate ; 0F,C5,/r,ib [KATMAI,MMX,SB,AR2] +\c PEXTRW reg32,mm,imm8 ; 0F C5 /r ib [KATMAI,MMX] +\c PEXTRW reg32,xmm,imm8 ; 66 0F C5 /r ib [WILLAMETTE,SSE2] + +\c{PEXTRW} moves the word in the source register (second operand) +that is pointed to by the count operand (third operand), into the +lower half of a 32-bit general purpose register. The upper half of +the register is cleared to all 0s. + +When the source operand is an \c{MMX} register, the two least +significant bits of the count specify the source word. When it is +an \c{SSE} register, the three least significant bits specify the +word location. + + +\H{insPF2ID} \i\c{PF2ID}: Packed Single-Precision FP to Integer Convert + +\c PF2ID mm1,mm2/m64 ; 0F 0F /r 1D [PENT,3DNOW] + +\c{PF2ID} converts two single-precision FP values in the source operand +to signed 32-bit integers, using truncation, and stores them in the +destination operand. Source values that are outside the range supported +by the destination are saturated to the largest absolute value of the +same sign. + + +\H{insPF2IW} \i\c{PF2IW}: Packed Single-Precision FP to Integer Word Convert + +\c PF2IW mm1,mm2/m64 ; 0F 0F /r 1C [PENT,3DNOW] + +\c{PF2IW} converts two single-precision FP values in the source operand +to signed 16-bit integers, using truncation, and stores them in the +destination operand. Source values that are outside the range supported +by the destination are saturated to the largest absolute value of the +same sign. + +\b In the K6-2 and K6-III, the 16-bit value is zero-extended to 32-bits +before storing. -\c{PEXTRW}PEXTRW instruction moves the word in MM (selected by the - two least significant bits of imm8) to the lower half of a 32-bit - integer register. +\b In the K6-2+, K6-III+ and Athlon processors, the value is sign-extended +to 32-bits before storing. -\H{insPF2ID} \i\c{PF2ID}: 3dnow instruction (duh!) +\H{insPFACC} \i\c{PFACC}: Packed Single-Precision FP Accumulate -\c PF2ID mmxreg,memory ; ?? [PENT,3DNOW,SM] -\c PF2ID mmxreg,mmxreg ; ?? [PENT,3DNOW] +\c PFACC mm1,mm2/m64 ; 0F 0F /r AE [PENT,3DNOW] -3dnow instruction (duh!) +\c{PFACC} adds the two single-precision FP values from the destination +operand together, then adds the two single-precision FP values from the +source operand, and places the results in the low and high doublewords +of the destination operand. +The operation is: -\H{insPFACC} \i\c{PFACC}: 3dnow instruction (duh!) +\c dst[0-31] := dst[0-31] + dst[32-63], +\c dst[32-63] := src[0-31] + src[32-63]. -\c PFACC mmxreg,memory ; ?? [PENT,3DNOW,SM] -\c PFACC mmxreg,mmxreg ; ?? [PENT,3DNOW] -3dnow instruction (duh!) +\H{insPFADD} \i\c{PFADD}: Packed Single-Precision FP Addition +\c PFADD mm1,mm2/m64 ; 0F 0F /r 9E [PENT,3DNOW] -\H{insPFADD} \i\c{PFADD}: 3dnow instruction (duh!) +\c{PFADD} performs addition on each of two packed single-precision +FP value pairs. -\c PFADD mmxreg,memory ; ?? [PENT,3DNOW,SM] -\c PFADD mmxreg,mmxreg ; ?? [PENT,3DNOW] +\c dst[0-31] := dst[0-31] + src[0-31], +\c dst[32-63] := dst[32-63] + src[32-63]. -3dnow instruction (duh!) +\H{insPFCMP} \i\c{PFCMPxx}: Packed Single-Precision FP Compare +\I\c{PFCMPEQ} \I\c{PFCMPGE} \I\c{PFCMPGT} -\H{insPFCMPEQ} \i\c{PFCMPEQ}: 3dnow instruction (duh!) +\c PFCMPEQ mm1,mm2/m64 ; 0F 0F /r B0 [PENT,3DNOW] +\c PFCMPGE mm1,mm2/m64 ; 0F 0F /r 90 [PENT,3DNOW] +\c PFCMPGT mm1,mm2/m64 ; 0F 0F /r A0 [PENT,3DNOW] -\c PFCMPEQ mmxreg,memory ; ?? [PENT,3DNOW,SM] -\c PFCMPEQ mmxreg,mmxreg ; ?? [PENT,3DNOW] +The \c{PFCMPxx} instructions compare the packed single-point FP values +in the source and destination operands, and set the destination +according to the result. If the condition is true, the destination is +set to all 1s, otherwise it's set to all 0s. -3dnow instruction (duh!) +\b \c{PFCMPEQ} tests whether dst == src; +\b \c{PFCMPGE} tests whether dst >= src; -\H{insPFCMPGE} \i\c{PFCMPGE}: 3dnow instruction (duh!) +\b \c{PFCMPGT} tests whether dst > src. -\c PFCMPGE mmxreg,memory ; ?? [PENT,3DNOW,SM] -\c PFCMPGE mmxreg,mmxreg ; ?? [PENT,3DNOW] -3dnow instruction (duh!) +\H{insPFMAX} \i\c{PFMAX}: Packed Single-Precision FP Maximum +\c PFMAX mm1,mm2/m64 ; 0F 0F /r A4 [PENT,3DNOW] -\H{insPFCMPGT} \i\c{PFCMPGT}: 3dnow instruction (duh!) +\c{PFMAX} returns the higher of each pair of single-precision FP values. +If the higher value is zero, it is returned as positive zero. -\c PFCMPGT mmxreg,memory ; ?? [PENT,3DNOW,SM] -\c PFCMPGT mmxreg,mmxreg ; ?? [PENT,3DNOW] -3dnow instruction (duh!) +\H{insPFMIN} \i\c{PFMIN}: Packed Single-Precision FP Minimum +\c PFMIN mm1,mm2/m64 ; 0F 0F /r 94 [PENT,3DNOW] -\H{insPFMAX} \i\c{PFMAX}: 3dnow instruction (duh!) +\c{PFMIN} returns the lower of each pair of single-precision FP values. +If the lower value is zero, it is returned as positive zero. -\c PFMAX mmxreg,memory ; ?? [PENT,3DNOW,SM] -\c PFMAX mmxreg,mmxreg ; ?? [PENT,3DNOW] -3dnow instruction (duh!) +\H{insPFMUL} \i\c{PFMUL}: Packed Single-Precision FP Multiply +\c PFMUL mm1,mm2/m64 ; 0F 0F /r B4 [PENT,3DNOW] -\H{insPFMIN} \i\c{PFMIN}: 3dnow instruction (duh!) +\c{PFMUL} returns the product of each pair of single-precision FP values. -\c PFMIN mmxreg,memory ; ?? [PENT,3DNOW,SM] -\c PFMIN mmxreg,mmxreg ; ?? [PENT,3DNOW] +\c dst[0-31] := dst[0-31] * src[0-31], +\c dst[32-63] := dst[32-63] * src[32-63]. -3dnow instruction (duh!) +\H{insPFNACC} \i\c{PFNACC}: Packed Single-Precision FP Negative Accumulate -\H{insPFMUL} \i\c{PFMUL}: 3dnow instruction (duh!) +\c PFNACC mm1,mm2/m64 ; 0F 0F /r 8A [PENT,3DNOW] -\c PFMUL mmxreg,memory ; ?? [PENT,3DNOW,SM] -\c PFMUL mmxreg,mmxreg ; ?? [PENT,3DNOW] +\c{PFACC} performs a negative accumulate of the two single-precision +FP values in the source and destination registers. The result of the +accumulate from the destination register is stored in the low doubleword +of the destination, and the result of the source accumulate is stored in +the high doubleword of the destination register. -3dnow instruction (duh!) +The operation is: +\c dst[0-31] := dst[0-31] - dst[32-63], +\c dst[32-63] := src[0-31] - src[32-63]. -\H{insPFRCP} \i\c{PFRCP}: 3dnow instruction (duh!) -\c PFRCP mmxreg,memory ; ?? [PENT,3DNOW,SM] -\c PFRCP mmxreg,mmxreg ; ?? [PENT,3DNOW] +\H{insPFNACC} \i\c{PFNACC}: Packed Single-Precision FP Mixed Accumulate -3dnow instruction (duh!) +\c PFNACC mm1,mm2/m64 ; 0F 0F /r 8E [PENT,3DNOW] +\c{PFACC} performs a positive accumulate of the two single-precision +FP values in the source register and a negative accumulate of the +destination register. The result of the accumulate from the destination +register is stored in the low doubleword of the destination, and the +result of the source accumulate is stored in the high doubleword of the +destination register. -\H{insPFRCPIT1} \i\c{PFRCPIT1}: 3dnow instruction (duh!) +The operation is: -\c PFRCPIT1 mmxreg,memory ; ?? [PENT,3DNOW,SM] -\c PFRCPIT1 mmxreg,mmxreg ; ?? [PENT,3DNOW] +\c dst[0-31] := dst[0-31] - dst[32-63], +\c dst[32-63] := src[0-31] + src[32-63]. -3dnow instruction (duh!) +\H{insPFRCP} \i\c{PFRCP}: Packed Single-Precision FP Reciprocal Approximation -\H{insPFRCPIT2} \i\c{PFRCPIT2}: 3dnow instruction (duh!) +\c PFRCP mm1,mm2/m64 ; 0F 0F /r 96 [PENT,3DNOW] -\c PFRCPIT2 mmxreg,memory ; ?? [PENT,3DNOW,SM] -\c PFRCPIT2 mmxreg,mmxreg ; ?? [PENT,3DNOW] +\c{PFRCP} performs a low precision estimate of the reciprocal of the +low-order single-precision FP value in the source operand, storing the +result in both halves of the destination register. The result is accurate +to 14 bits. -3dnow instruction (duh!) +For higher precision reciprocals, this instruction should be followed by +two more instructions: \c{PFRCPIT1} (\k{insPFRCPIT1}) and \c{PFRCPIT2} +(\k{insPFRCPIT1}). This will result in a 24-bit accuracy. For more details, +see the AMD 3DNow! technology manual. -\H{insPFRSQIT1} \i\c{PFRSQIT1}: 3dnow instruction (duh!) +\H{insPFRCPIT1} \i\c{PFRCPIT1}: Packed Single-Precision FP Reciprocal, +First Iteration Step -\c PFRSQIT1 mmxreg,memory ; ?? [PENT,3DNOW,SM] -\c PFRSQIT1 mmxreg,mmxreg ; ?? [PENT,3DNOW] +\c PFRCPIT1 mm1,mm2/m64 ; 0F 0F /r A6 [PENT,3DNOW] -3dnow instruction (duh!) +\c{PFRCPIT1} performs the first intermediate step in the calculation of +the reciprocal of a single-precision FP value. The first source value +(\c{mm1} is the original value, and the second source value (\c{mm2/m64} +is the result of a \c{PFRCP} instruction. +For the final step in a reciprocal, returning the full 24-bit accuracy +of a single-precision FP value, see \c{PFRCPIT2} (\k{insPFRCPIT2}). For +more details, see the AMD 3DNow! technology manual. -\H{insPFRSQRT} \i\c{PFRSQRT}: 3dnow instruction (duh!) -\c PFRSQRT mmxreg,memory ; ?? [PENT,3DNOW,SM] -\c PFRSQRT mmxreg,mmxreg ; ?? [PENT,3DNOW] +\H{insPFRCPIT2} \i\c{PFRCPIT2}: Packed Single-Precision FP +Reciprocal/ Reciprocal Square Root, Second Iteration Step -3dnow instruction (duh!) +\c PFRCPIT2 mm1,mm2/m64 ; 0F 0F /r B6 [PENT,3DNOW] +\c{PFRCPIT2} performs the second and final intermediate step in the +calculation of a reciprocal or reciprocal square root, refining the +values returned by the \c{PFRCP} and \c{PFRSQRT} instructions, +respectively. -\H{insPFSUB} \i\c{PFSUB}: 3dnow instruction (duh!) +The first source value (\c{mm1}) is the output of either a \c{PFRCPIT1} +or a \c{PFRSQIT1} instruction, and the second source is the output of +either the \c{PFRCP} or the \c{PFRSQRT} instruction. For more details, +see the AMD 3DNow! technology manual. -\c PFSUB mmxreg,memory ; ?? [PENT,3DNOW,SM] -\c PFSUB mmxreg,mmxreg ; ?? [PENT,3DNOW] -3dnow instruction (duh!) +\H{insPFRSQIT1} \i\c{PFRSQIT1}: Packed Single-Precision FP Reciprocal +Square Root, First Iteration Step +\c PFRSQIT1 mm1,mm2/m64 ; 0F 0F /r A7 [PENT,3DNOW] -\H{insPFSUBR} \i\c{PFSUBR}: 3dnow instruction (duh!) +\c{PFRSQIT1} performs the first intermediate step in the calculation of +the reciprocal square root of a single-precision FP value. The first +source value (\c{mm1} is the square of the result of a \c{PFRSQRT} +instruction, and the second source value (\c{mm2/m64} is the original +value. -\c PFSUBR mmxreg,memory ; ?? [PENT,3DNOW,SM] -\c PFSUBR mmxreg,mmxreg ; ?? [PENT,3DNOW] +For the final step in a calculation, returning the full 24-bit accuracy +of a single-precision FP value, see \c{PFRCPIT2} (\k{insPFRCPIT2}). For +more details, see the AMD 3DNow! technology manual. -3dnow instruction (duh!) +\H{insPFRSQRT} \i\c{PFRSQRT}: Packed Single-Precision FP Reciprocal +Square Root Approximation -\H{insPI2FD} \i\c{PI2FD}: 3dnow instruction (duh!) +\c PFRSQRT mm1,mm2/m64 ; 0F 0F /r 97 [PENT,3DNOW] -\c PI2FD mmxreg,memory ; ?? [PENT,3DNOW,SM] -\c PI2FD mmxreg,mmxreg ; ?? [PENT,3DNOW] +\c{PFRSQRT} performs a low precision estimate of the reciprocal square +root of the low-order single-precision FP value in the source operand, +storing the result in both halves of the destination register. The result +is accurate to 15 bits. -3dnow instruction (duh!) +For higher precision reciprocals, this instruction should be followed by +two more instructions: \c{PFRSQIT1} (\k{insPFRSQIT1}) and \c{PFRCPIT2} +(\k{insPFRCPIT1}). This will result in a 24-bit accuracy. For more details, +see the AMD 3DNow! technology manual. + + +\H{insPFSUB} \i\c{PFSUB}: Packed Single-Precision FP Subtract + +\c PFSUB mm1,mm2/m64 ; 0F 0F /r 9A [PENT,3DNOW] + +\c{PFSUB} subtracts the single-precision FP values in the source from +those in the destination, and stores the result in the destination +operand. + +\c dst[0-31] := dst[0-31] - src[0-31], +\c dst[32-63] := dst[32-63] - src[32-63]. + + +\H{insPFSUBR} \i\c{PFSUBR}: Packed Single-Precision FP Reverse Subtract + +\c PFSUBR mm1,mm2/m64 ; 0F 0F /r AA [PENT,3DNOW] + +\c{PFSUBR} subtracts the single-precision FP values in the destination +from those in the source, and stores the result in the destination +operand. + +\c dst[0-31] := src[0-31] - dst[0-31], +\c dst[32-63] := src[32-63] - dst[32-63]. + + +\H{insPI2FD} \i\c{PI2FD}: Packed Doubleword Integer to Single-Precision FP Convert + +\c PI2FD mm1,mm2/m64 ; 0F 0F /r 0D [PENT,3DNOW] + +\c{PF2ID} converts two signed 32-bit integers in the source operand +to single-precision FP values, using truncation of significant digits, +and stores them in the destination operand. + + +\H{insPF2IW} \i\c{PF2IW}: Packed Word Integer to Single-Precision FP Convert + +\c PI2FW mm1,mm2/m64 ; 0F 0F /r 0C [PENT,3DNOW] + +\c{PF2IW} converts two signed 16-bit integers in the source operand +to single-precision FP values, and stores them in the destination +operand. The input values are in the low word of each doubleword. \H{insPINSRW} \i\c{PINSRW}: Insert Word -\c PINSRW mmxreg,reg16,immediate ;0F,C4,/r,ib [KATMAI,MMX,SB,AR2] -\c PINSRW mmxreg,reg32,immediate ; ?? [KATMAI,MMX,SB,AR2,ND] -\c PINSRW mmxreg,memory,immediate ; ?? [KATMAI,MMX,SB,AR2] -\c PINSRW mmxreg,memory|bits16,immediate ; ?? [KATMAI,MMX,SB,AR2,ND] +\c PINSRW mm,r16/r32/m16,imm8 ;0F C4 /r ib [KATMAI,MMX] +\c PINSRW xmm,r16/r32/m16,imm8 ;66 0F C4 /r ib [WILLAMETTE,SSE2] + +\c{PINSRW} loads a word from a 16-bit register (or the low half of a +32-bit register), or from memory, and loads it to the word position +in the destination register, pointed at by the count operand (third +operand). If the destination is an \c{MMX} register, the low two bits +of the count byte are used, if it is an \c{XMM} register the low 3 +bits are used. The insertion is done in such a way that the other +words from the destination register are left untouched. -\c{PINSRW} The PINSRW instruction loads a word from the lower half - of a 32-bit integer register (or from memory) and inserts it in - the MM destination register, at a position defined by the two - least significant bits of the imm8 constant. The insertion is - done in such a way that the three other words from the - destination register are left untouched. +\H{insPMACHRIW} \i\c{PMACHRIW}: Packed Multiply and Accumulate with Rounding -\H{insPMACHRIW} \i\c{PMACHRIW}: MMX Packed Multiply and Accumulate -with Rounding +\c PMACHRIW mm,m64 ; 0F 5E /r [CYRIX,MMX] -\c PMACHRIW mmxreg,mem64 ; 0F 5E /r [CYRIX,MMX] +\c{PMACHRIW} takes two packed 16-bit integer inputs, multiplies the +values in the inputs, rounds on bit 15 of each result, then adds bits +15-30 of each result to the corresponding position of the \e{implied} +destination register. -\c{PMACHRIW} acts almost identically to \c{PMULHRIW} -(\k{insPMULHRW}), but instead of \e{storing} its result in the -implied destination register, it \e{adds} its result, as four packed -words, to the implied destination register. No saturation is done: -the addition can wrap around. +The operation of this instruction is: + +\c dstI[0-15] := dstI[0-15] + (mm[0-15] *m64[0-15] +\c + 0x00004000)[15-30], +\c dstI[16-31] := dstI[16-31] + (mm[16-31]*m64[16-31] +\c + 0x00004000)[15-30], +\c dstI[32-47] := dstI[32-47] + (mm[32-47]*m64[32-47] +\c + 0x00004000)[15-30], +\c dstI[48-63] := dstI[48-63] + (mm[48-63]*m64[48-63] +\c + 0x00004000)[15-30]. Note that \c{PMACHRIW} cannot take a register as its second source operand. + \H{insPMADDWD} \i\c{PMADDWD}: MMX Packed Multiply and Add -\c PMADDWD mmxreg,r/m64 ; 0F F5 /r [PENT,MMX] +\c PMADDWD mm1,mm2/m64 ; 0F F5 /r [PENT,MMX] +\c PMADDWD xmm1,xmm2/m128 ; 66 0F F5 /r [WILLAMETTE,SSE2] + +\c{PMADDWD} treats its two inputs as vectors of signed words. It +multiplies corresponding elements of the two operands, giving doubleword +results. These are then added together in pairs and stored in the +destination operand. + +The operation of this instruction is: + +\c dst[0-31] := (dst[0-15] * src[0-15]) +\c + (dst[16-31] * src[16-31]); +\c dst[32-63] := (dst[32-47] * src[32-47]) +\c + (dst[48-63] * src[48-63]); + +The following apply to the \c{SSE} version of the instruction: + +\c dst[64-95] := (dst[64-79] * src[64-79]) +\c + (dst[80-95] * src[80-95]); +\c dst[96-127] := (dst[96-111] * src[96-111]) +\c + (dst[112-127] * src[112-127]). -\c{PMADDWD} treats its two inputs as vectors of four signed words. -It multiplies corresponding elements of the two operands, giving -four signed doubleword results. The top two of these are added and -placed in the top 32 bits of the destination (first) operand; the -bottom two are added and placed in the bottom 32 bits. \H{insPMAGW} \i\c{PMAGW}: MMX Packed Magnitude -\c PMAGW mmxreg,r/m64 ; 0F 52 /r [CYRIX,MMX] +\c PMAGW mm1,mm2/m64 ; 0F 52 /r [CYRIX,MMX] \c{PMAGW}, specific to the Cyrix MMX extensions, treats both its operands as vectors of four signed words. It compares the absolute @@ -8547,102 +10555,149 @@ values of the words in corresponding positions, and sets each word of the destination (first) operand to whichever of the two words in that position had the larger absolute value. + \H{insPMAXSW} \i\c{PMAXSW}: Packed Signed Integer Word Maximum -\c PMAXSW mmxreg,mmxreg ; 0F,EE, /r [KATMAI,MMX] -\c PMAXSW mmxreg,memory ; ?? [KATMAI,MMX,SM] +\c PMAXSW mm1,mm2/m64 ; 0F EE /r [KATMAI,MMX] +\c PMAXSW xmm1,xmm2/m128 ; 66 0F EE /r [WILLAMETTE,SSE2] -\c{PMAXSW} The PMAXSW instruction returns the maximum between - the four signed words in MM1 and MM2/Mem. +\c{PMAXSW} compares each pair of words in the two source operands, and +for each pair it stores the maximum value in the destination register. \H{insPMAXUB} \i\c{PMAXUB}: Packed Unsigned Integer Byte Maximum -\c PMAXUB mmxreg,mmxreg ; 0F,DE, /r [KATMAI,MMX] -\c PMAXUB mmxreg,memory ; ?? [KATMAI,MMX,SM] +\c PMAXUB mm1,mm2/m64 ; 0F DE /r [KATMAI,MMX] +\c PMAXUB xmm1,xmm2/m128 ; 66 0F DE /r [WILLAMETTE,SSE2] -\c{PMAXUB} The PMAXUB instruction returns the maximum between - the eight unsigned words in MM1 and MM2/Mem. +\c{PMAXUB} compares each pair of bytes in the two source operands, and +for each pair it stores the maximum value in the destination register. \H{insPMINSW} \i\c{PMINSW}: Packed Signed Integer Word Minimum -\c PMINSW mmxreg,mmxreg ; 0F,EA, /r [KATMAI,MMX] -\c PMINSW mmxreg,memory ; ?? [KATMAI,MMX,SM] +\c PMINSW mm1,mm2/m64 ; 0F EA /r [KATMAI,MMX] +\c PMINSW xmm1,xmm2/m128 ; 66 0F EA /r [WILLAMETTE,SSE2] -\c{PMINSW} The PMINSW instruction returns the minimum between - the four signed words in MM1 and MM2/Mem. +\c{PMINSW} compares each pair of words in the two source operands, and +for each pair it stores the minimum value in the destination register. \H{insPMINUB} \i\c{PMINUB}: Packed Unsigned Integer Byte Minimum -\c PMINUB mmxreg,mmxreg ; 0F,DA, /r [KATMAI,MMX] -\c PMINUB mmxreg,memory ; ?? [KATMAI,MMX,SM] +\c PMINUB mm1,mm2/m64 ; 0F DA /r [KATMAI,MMX] +\c PMINUB xmm1,xmm2/m128 ; 66 0F DA /r [WILLAMETTE,SSE2] -\c{PMINUB}The PMINUB instruction returns the minimum between - the eight unsigned words in MM1 and MM2/Mem. +\c{PMINUB} compares each pair of bytes in the two source operands, and +for each pair it stores the minimum value in the destination register. \H{insPMOVMSKB} \i\c{PMOVMSKB}: Move Byte Mask To Integer -\c PMOVMSKB reg32,mmxreg ; 0F,D7,/r [KATMAI,MMX] +\c PMOVMSKB reg32,mm ; 0F D7 /r [KATMAI,MMX] +\c PMOVMSKB reg32,xmm ; 66 0F D7 /r [WILLAMETTE,SSE2] + +\c{PMOVMSKB} returns an 8-bit or 16-bit mask formed of the most +significant bits of each byte of source operand (8-bits for an +\c{MMX} register, 16-bits for an \c{XMM} register). + -\c{PMOVMSKB} The PMOVMSKB instruction returns an 8-bit mask - formed of the most significant bits of each byte of its - source operand. +\H{insPMULHRW} \i\c{PMULHRWC}, \i\c{PMULHRIW}: Multiply Packed 16-bit Integers +With Rounding, and Store High Word +\c PMULHRWC mm1,mm2/m64 ; 0F 59 /r [CYRIX,MMX] +\c PMULHRIW mm1,mm2/m64 ; 0F 5D /r [CYRIX,MMX] -\H{insPMULHRW} \i\c{PMULHRW}, \i\c{PMULHRIW}: MMX Packed Multiply -High with Rounding +These instructions take two packed 16-bit integer inputs, multiply the +values in the inputs, round on bit 15 of each result, then store bits +15-30 of each result to the corresponding position of the destination +register. + +\b For \c{PMULHRWC}, the destination is the first source operand. + +\b For \c{PMULHRIW}, the destination is an implied register (worked out +as described for \c{PADDSIW} (\k{insPADDSIW})). + +The operation of this instruction is: + +\c dst[0-15] := (src1[0-15] *src2[0-15] + 0x00004000)[15-30] +\c dst[16-31] := (src1[16-31]*src2[16-31] + 0x00004000)[15-30] +\c dst[32-47] := (src1[32-47]*src2[32-47] + 0x00004000)[15-30] +\c dst[48-63] := (src1[48-63]*src2[48-63] + 0x00004000)[15-30] -\c PMULHRW mmxreg,r/m64 ; 0F 59 /r [CYRIX,MMX] -\c PMULHRIW mmxreg,r/m64 ; 0F 5D /r [CYRIX,MMX] +See also \c{PMULHRWA} (\k{insPMULHRWA}) for a 3DNow! version of this +instruction. + + +\H{insPMULHRWA} \i\c{PMULHRWA}: Multiply Packed 16-bit Integers +With Rounding, and Store High Word -These instructions, specific to the Cyrix MMX extensions, treat -their operands as vectors of four signed words. Words in -corresponding positions are multiplied, to give a 32-bit value in -which bits 30 and 31 are guaranteed equal. Bits 30 to 15 of this -value (bit mask \c{0x7FFF8000}) are taken and stored in the -corresponding position of the destination operand, after first -rounding the low bit (equivalent to adding \c{0x4000} before -extracting bits 30 to 15). +\c PMULHRWA mm1,mm2/m64 ; 0F 0F /r B7 [PENT,3DNOW] -For \c{PMULHRW}, the destination operand is the first operand; for -\c{PMULHRIW} the destination operand is implied by the first operand -in the manner of \c{PADDSIW} (\k{insPADDSIW}). +\c{PMULHRWA} takes two packed 16-bit integer inputs, multiplies +the values in the inputs, rounds on bit 16 of each result, then +stores bits 16-31 of each result to the corresponding position +of the destination register. +The operation of this instruction is: -\H{insPMULHRWA} \i\c{PMULHRWA}: 3dnow instruction (duh!) +\c dst[0-15] := (src1[0-15] *src2[0-15] + 0x00008000)[16-31]; +\c dst[16-31] := (src1[16-31]*src2[16-31] + 0x00008000)[16-31]; +\c dst[32-47] := (src1[32-47]*src2[32-47] + 0x00008000)[16-31]; +\c dst[48-63] := (src1[48-63]*src2[48-63] + 0x00008000)[16-31]. + +See also \c{PMULHRWC} (\k{insPMULHRW}) for a Cyrix version of this +instruction. -\c PMULHRWA mmxreg,memory ; ?? [PENT,3DNOW,SM] -\c PMULHRWA mmxreg,mmxreg ; ?? [PENT,3DNOW] -3dnow instruction (duh!) +\H{insPMULHUW} \i\c{PMULHUW}: Multiply Packed 16-bit Integers, +and Store High Word +\c PMULHUW mm1,mm2/m64 ; 0F E4 /r [KATMAI,MMX] +\c PMULHUW xmm1,xmm2/m128 ; 66 0F E4 /r [WILLAMETTE,SSE2] -\H{insPMULHUW} \i\c{PMULHUW}: Packed Multiply High Unsigned +\c{PMULHUW} takes two packed unsigned 16-bit integer inputs, multiplies +the values in the inputs, then stores bits 16-31 of each result to the +corresponding position of the destination register. -\c PMULHUW mmxreg,mmxreg ; 0F,E4,/r [KATMAI,MMX] -\c PMULHUW mmxreg,memory ; ?? [KATMAI,MMX,SM] -\c{PMULHUW} The PMULHUW instruction multiplies the four unsigned - words in the destination operand with the four unsigned words - in the source operand. The high-order 16 bits of the 32-bit - intermediate results are written to the destination operand. +\H{insPMULHW} \i\c{PMULHW}, \i\c{PMULLW}: Multiply Packed 16-bit Integers, +and Store +\c PMULHW mm1,mm2/m64 ; 0F E5 /r [PENT,MMX] +\c PMULLW mm1,mm2/m64 ; 0F D5 /r [PENT,MMX] -\H{insPMULHW} \i\c{PMULHW}, \i\c{PMULLW}: MMX Packed Multiply +\c PMULHW xmm1,xmm2/m128 ; 66 0F E5 /r [WILLAMETTE,SSE2] +\c PMULLW xmm1,xmm2/m128 ; 66 0F D5 /r [WILLAMETTE,SSE2] -\c PMULHW mmxreg,r/m64 ; 0F E5 /r [PENT,MMX] -\c PMULLW mmxreg,r/m64 ; 0F D5 /r [PENT,MMX] +\c{PMULxW} takes two packed unsigned 16-bit integer inputs, and +multiplies the values in the inputs, forming doubleword results. -\c{PMULxW} treats its two inputs as vectors of four signed words. It -multiplies corresponding elements of the two operands, giving four -signed doubleword results. +\b \c{PMULHW} then stores the top 16 bits of each doubleword in the +destination (first) operand; -\c{PMULHW} then stores the top 16 bits of each doubleword in the -destination (first) operand; \c{PMULLW} stores the bottom 16 bits of -each doubleword in the destination operand. +\b \c{PMULLW} stores the bottom 16 bits of each doubleword in the +destination operand. + + +\H{insPMULUDQ} \i\c{PMULUDQ}: Multiply Packed Unsigned +32-bit Integers, and Store. + +\c PMULUDQ mm1,mm2/m64 ; 0F F4 /r [WILLAMETTE,SSE2] +\c PMULUDQ xmm1,xmm2/m128 ; 66 0F F4 /r [WILLAMETTE,SSE2] + +\c{PMULUDQ} takes two packed unsigned 32-bit integer inputs, and +multiplies the values in the inputs, forming quadword results. The +source is either an unsigned doubleword in the low doubleword of a +64-bit operand, or it's two unsigned doublewords in the first and +third doublewords of a 128-bit operand. This produces either one or +two 64-bit results, which are stored in the respective quadword +locations of the destination register. + +The operation is: + +\c dst[0-63] := dst[0-31] * src[0-31]; +\c dst[64-127] := dst[64-95] * src[64-95]. \H{insPMVccZB} \i\c{PMVccZB}: MMX Packed Conditional Move @@ -8660,14 +10715,19 @@ operand, or left alone, depending on the value of the byte in the \e{implied} operand (specified in the same way as \c{PADDSIW}, in \k{insPADDSIW}). -\c{PMVZB} performs each move if the corresponding byte in the -implied operand is zero. \c{PMVNZB} moves if the byte is non-zero. -\c{PMVLZB} moves if the byte is less than zero, and \c{PMVGEZB} -moves if the byte is greater than or equal to zero. +\b \c{PMVZB} performs each move if the corresponding byte in the +implied operand is zero; + +\b \c{PMVNZB} moves if the byte is non-zero; + +\b \c{PMVLZB} moves if the byte is less than zero; + +\b \c{PMVGEZB} moves if the byte is greater than or equal to zero. Note that these instructions cannot take a register as their second source operand. + \H{insPOP} \i\c{POP}: Pop Data from Stack \c POP reg16 ; o16 58+r [8086] @@ -8676,7 +10736,7 @@ source operand. \c POP r/m16 ; o16 8F /0 [8086] \c POP r/m32 ; o32 8F /0 [386] -\c POP CS ; 0F [8086,UNDOC] +\c POP CS ; 0F [8086,UNDOC] \c POP DS ; 1F [8086] \c POP ES ; 07 [8086] \c POP SS ; 17 [8086] @@ -8707,20 +10767,21 @@ any processor above the 8086 (since they use \c{0Fh} as an opcode prefix for instruction set extensions). However, at least some 8086 processors do support it, and so NASM generates it for completeness. + \H{insPOPA} \i\c{POPAx}: Pop All General-Purpose Registers \c POPA ; 61 [186] \c POPAW ; o16 61 [186] \c POPAD ; o32 61 [386] -\c{POPAW} pops a word from the stack into each of, successively, +\b \c{POPAW} pops a word from the stack into each of, successively, \c{DI}, \c{SI}, \c{BP}, nothing (it discards a word from the stack which was a placeholder for \c{SP}), \c{BX}, \c{DX}, \c{CX} and \c{AX}. It is intended to reverse the operation of \c{PUSHAW} (see \k{insPUSHA}), but it ignores the value for \c{SP} that was pushed on the stack by \c{PUSHAW}. -\c{POPAD} pops twice as much data, and places the results in +\b \c{POPAD} pops twice as much data, and places the results in \c{EDI}, \c{ESI}, \c{EBP}, nothing (placeholder for \c{ESP}), \c{EBX}, \c{EDX}, \c{ECX} and \c{EAX}. It reverses the operation of \c{PUSHAD}. @@ -8731,25 +10792,29 @@ depending on the current \c{BITS} setting. Note that the registers are popped in reverse order of their numeric values in opcodes (see \k{iref-rv}). + \H{insPOPF} \i\c{POPFx}: Pop Flags Register \c POPF ; 9D [186] \c POPFW ; o16 9D [186] \c POPFD ; o32 9D [386] -\c{POPFW} pops a word from the stack and stores it in the bottom 16 +\b \c{POPFW} pops a word from the stack and stores it in the bottom 16 bits of the flags register (or the whole flags register, on -processors below a 386). \c{POPFD} pops a doubleword and stores it -in the entire flags register. +processors below a 386). + +\b \c{POPFD} pops a doubleword and stores it in the entire flags register. \c{POPF} is an alias mnemonic for either \c{POPFW} or \c{POPFD}, depending on the current \c{BITS} setting. See also \c{PUSHF} (\k{insPUSHF}). + \H{insPOR} \i\c{POR}: MMX Bitwise OR -\c POR mmxreg,r/m64 ; 0F EB /r [PENT,MMX] +\c POR mm1,mm2/m64 ; 0F EB /r [PENT,MMX] +\c POR xmm1,xmm2/m128 ; 66 0F EB /r [WILLAMETTE,SSE2] \c{POR} performs a bitwise OR operation between its two operands (i.e. each bit of the result is 1 if and only if at least one of the @@ -8757,161 +10822,283 @@ corresponding bits of the two inputs was 1), and stores the result in the destination (first) operand. -\H{insPREFETCHNTA} \i\c{PREFETCHNTA}: Prefetch +\H{insPREFETCH} \i\c{PREFETCH}: Prefetch Data Into Caches + +\c PREFETCH mem8 ; 0F 0D /0 [PENT,3DNOW] +\c PREFETCHW mem8 ; 0F 0D /1 [PENT,3DNOW] -\c PREFETCHNTA memory ; 0F,18,/0 [KATMAI] +\c{PREFETCH} and \c{PREFETCHW} fetch the line of data from memory that +contains the specified byte. \c{PREFETCHW} performs differently on the +Athlon to earlier processors. -\c{PREFETCHNTA} Move data specified by address closer to the - processor using the nta hint. +For more details, see the 3DNow! Technology Manual. -\H{insPREFETCHT0} \i\c{PREFETCHT0}: Prefetch +\H{insPREFETCHh} \i\c{PREFETCHh}: Prefetch Data Into Caches +\I\c{PREFETCHNTA} \I\c{PREFETCHT0} \I\c{PREFETCHT1} \I\c{PREFETCHT2} -\c PREFETCHT0 memory ; 0F,18,/1 [KATMAI] +\c PREFETCHNTA m8 ; 0F 18 /0 [KATMAI] +\c PREFETCHT0 m8 ; 0F 18 /1 [KATMAI] +\c PREFETCHT1 m8 ; 0F 18 /2 [KATMAI] +\c PREFETCHT2 m8 ; 0F 18 /3 [KATMAI] -\c{PREFETCHT0} Move data specified by address closer to the - processor using the t0 hint. +The \c{PREFETCHh} instructions fetch the line of data from memory +that contains the specified byte. It is placed in the cache +according to rules specified by locality hints \c{h}: +The hints are: -\H{insPREFETCHT1} \i\c{PREFETCHT1}: Prefetch +\b \c{T0} (temporal data) - prefetch data into all levels of the +cache hierarchy. -\c PREFETCHT1 memory ; 0F,18,/2 [KATMAI] +\b \c{T1} (temporal data with respect to first level cache) - +prefetch data into level 2 cache and higher. -\c{PREFETCHT1}Move data specified by address closer to the - processor using the t1 hint. +\b \c{T2} (temporal data with respect to second level cache) - +prefetch data into level 2 cache and higher. +\b \c{NTA} (non-temporal data with respect to all cache levels) — +prefetch data into non-temporal cache structure and into a +location close to the processor, minimizing cache pollution. -\H{insPREFETCHT2} \i\c{PREFETCHT2}: Prefetch +Note that this group of instructions doesn't provide a guarantee +that the data will be in the cache when it is needed. For more +details, see the Intel IA32 Software Developer Manual, Volume 2. -\c PREFETCHT2 memory ; 0F,18,/3 [KATMAI] -\c{PREFETCHT2} Move data specified by address closer to the - processor using the t2 hint. +\H{insPSADBW} \i\c{PSADBW}: Packed Sum of Absolute Differences +\c PSADBW mm1,mm2/m64 ; 0F F6 /r [KATMAI,MMX] +\c PSADBW xmm1,xmm2/m128 ; 66 0F F6 /r [WILLAMETTE,SSE2] -\H{insPREFETCH} \i\c{PREFETCH}: 3dnow instruction (duh!) +\c{PSADBW} The PSADBW instruction computes the absolute value of the +difference of the packed unsigned bytes in the two source operands. +These differences are then summed to produce a word result in the lower +16-bit field of the destination register; the rest of the register is +cleared. The destination operand is an \c{MMX} or an \c{XMM} register. +The source operand can either be a register or a memory operand. -\c PREFETCH memory ; ?? [PENT,3DNOW,SM] -3dnow instruction (duh!) +\H{insPSHUFD} \i\c{PSHUFD}: Shuffle Packed Doublewords +\c PSHUFD xmm1,xmm2/m128,imm8 ; 66 0F 70 /r ib [WILLAMETTE,SSE2] -\H{insPREFETCHW} \i\c{PREFETCHW}: 3dnow instruction (duh!) +\c{PSHUFD} shuffles the doublewords in the source (second) operand +according to the encoding specified by imm8, and stores the result +in the destination (first) operand. -\c PREFETCHW memory ; ?? [PENT,3DNOW,SM] +Bits 0 and 1 of imm8 encode the source position of the doubleword to +be copied to position 0 in the destination operand. Bits 2 and 3 +encode for position 1, bits 4 and 5 encode for position 2, and bits +6 and 7 encode for position 3. For example, an encoding of 10 in +bits 0 and 1 of imm8 indicates that the doubleword at bits 64-95 of +the source operand will be copied to bits 0-31 of the destination. -3dnow instruction (duh!) +\H{insPSHUFHW} \i\c{PSHUFHW}: Shuffle Packed High Words +\c PSHUFHW xmm1,xmm2/m128,imm8 ; F3 0F 70 /r ib [WILLAMETTE,SSE2] +\c{PSHUFW} shuffles the words in the high quadword of the source +(second) operand according to the encoding specified by imm8, and +stores the result in the high quadword of the destination (first) +operand. +The operation of this instruction is similar to the \c{PSHUFW} +instruction, except that the source and destination are the top +quadword of a 128-bit operand, instead of being 64-bit operands. +The low quadword is copied from the source to the destination +without any changes. -\H{insPSADBW} \i\c{PSADBW}: Packed Sum of Absolute Differences -\c PSADBW mmxreg,mmxreg ; 0F,F6, /r [KATMAI,MMX] -\c PSADBW mmxreg,memory ; ?? [KATMAI,MMX,SM] +\H{insPSHUFLW} \i\c{PSHUFLW}: Shuffle Packed Low Words + +\c PSHUFLW xmm1,xmm2/m128,imm8 ; F2 0F 70 /r ib [WILLAMETTE,SSE2] + +\c{PSHUFW} shuffles the words in the low quadword of the source +(second) operand according to the encoding specified by imm8, and +stores the result in the low quadword of the destination (first) +operand. + +The operation of this instruction is similar to the \c{PSHUFW} +instruction, except that the source and destination are the low +quadword of a 128-bit operand, instead of being 64-bit operands. +The high quadword is copied from the source to the destination +without any changes. + + +\H{insPSHUFW} \i\c{PSHUFW}: Shuffle Packed Words + +\c PSHUFW mm1,mm2/m64,imm8 ; 0F 70 /r ib [KATMAI,MMX] + +\c{PSHUFW} shuffles the words in the source (second) operand +according to the encoding specified by imm8, and stores the result +in the destination (first) operand. + +Bits 0 and 1 of imm8 encode the source position of the word to be +copied to position 0 in the destination operand. Bits 2 and 3 encode +for position 1, bits 4 and 5 encode for position 2, and bits 6 and 7 +encode for position 3. For example, an encoding of 10 in bits 0 and 1 +of imm8 indicates that the word at bits 32-47 of the source operand +will be copied to bits 0-15 of the destination. + + +\H{insPSLLD} \i\c{PSLLx}: Packed Data Bit Shift Left Logical + +\c PSLLW mm1,mm2/m64 ; 0F F1 /r [PENT,MMX] +\c PSLLW mm,imm8 ; 0F 71 /6 ib [PENT,MMX] + +\c PSLLW xmm1,xmm2/m128 ; 66 0F F1 /r [WILLAMETTE,SSE2] +\c PSLLW xmm,imm8 ; 66 0F 71 /6 ib [WILLAMETTE,SSE2] + +\c PSLLD mm1,mm2/m64 ; 0F F2 /r [PENT,MMX] +\c PSLLD mm,imm8 ; 0F 72 /6 ib [PENT,MMX] + +\c PSLLD xmm1,xmm2/m128 ; 66 0F F2 /r [WILLAMETTE,SSE2] +\c PSLLD xmm,imm8 ; 66 0F 72 /6 ib [WILLAMETTE,SSE2] + +\c PSLLQ mm1,mm2/m64 ; 0F F3 /r [PENT,MMX] +\c PSLLQ mm,imm8 ; 0F 73 /6 ib [PENT,MMX] + +\c PSLLQ xmm1,xmm2/m128 ; 66 0F F3 /r [WILLAMETTE,SSE2] +\c PSLLQ xmm,imm8 ; 66 0F 73 /6 ib [WILLAMETTE,SSE2] + +\c PSLLDQ xmm1,imm8 ; 66 0F 73 /7 ib [PENT,MMX] + +\c{PSLLx} performs logical left shifts of the data elements in the +destination (first) operand, moving each bit in the separate elements +left by the number of bits specified in the source (second) operand, +clearing the low-order bits as they are vacated. + +\b \c{PSLLW} shifts word sized elements. -\c{PSADBW} The PSADBW instruction computes the absolute value of - the difference of unsigned bytes for mm1 and mm2/m64. These - differences are then summed to produce a word result in the lower - 16-bit field; the upper three words are cleared. The destination - operand is an MMXTM technology register. The source operand can - either be an MMXTM technology register or a 64-bit memory operand. +\b \c{PSLLD} shifts doubleword sized elements. +\b \c{PSLLQ} shifts quadword sized elements. -\H{insPSHUFW} \i\c{PSHUFW}: Packed Shuffle Word +\b \c{PSLLDQ} shifts double quadword sized elements. -\c PSHUFW mmxreg,mmxreg,immediate ; 0F,70,/r,ib [KATMAI,MMX,SB,AR2] -\c PSHUFW mmxreg,memory,immediate ; ?? [KATMAI,MMX,SM2,SB,AR2] -\c{PSHUFW} The PSHUF instruction uses the imm8 operand to select - which of the four words in MM2/Mem will be placed in each of the - words in MM1. Bits 1 and 0 of imm8 encode the source for - destination word 0 (MM1[15-0]), bits 3 and 2 encode for word 1, - bits 5 and 4 encode for word 2, and bits 7 and 6 encode for - word 3 (MM1[63-48]). Similarly, the two-bit encoding represents - which source word is to be used, e.g., a binary encoding of 10 - indicates that source word 2 (MM2/Mem[47-32]) will be used. +\H{insPSRAD} \i\c{PSRAx}: Packed Data Bit Shift Right Arithmetic +\c PSRAW mm1,mm2/m64 ; 0F E1 /r [PENT,MMX] +\c PSRAW mm,imm8 ; 0F 71 /4 ib [PENT,MMX] -\H{insPSLLD} \i\c{PSLLx}, \i\c{PSRLx}, \i\c{PSRAx}: MMX Bit Shifts +\c PSRAW xmm1,xmm2/m128 ; 66 0F E1 /r [WILLAMETTE,SSE2] +\c PSRAW xmm,imm8 ; 66 0F 71 /4 ib [WILLAMETTE,SSE2] -\c PSLLW mmxreg,r/m64 ; 0F F1 /r [PENT,MMX] -\c PSLLW mmxreg,imm8 ; 0F 71 /6 ib [PENT,MMX] +\c PSRAD mm1,mm2/m64 ; 0F E2 /r [PENT,MMX] +\c PSRAD mm,imm8 ; 0F 72 /4 ib [PENT,MMX] -\c PSLLD mmxreg,r/m64 ; 0F F2 /r [PENT,MMX] -\c PSLLD mmxreg,imm8 ; 0F 72 /6 ib [PENT,MMX] +\c PSRAD xmm1,xmm2/m128 ; 66 0F E2 /r [WILLAMETTE,SSE2] +\c PSRAD xmm,imm8 ; 66 0F 72 /4 ib [WILLAMETTE,SSE2] -\c PSLLQ mmxreg,r/m64 ; 0F F3 /r [PENT,MMX] -\c PSLLQ mmxreg,imm8 ; 0F 73 /6 ib [PENT,MMX] +\c{PSRAx} performs arithmetic right shifts of the data elements in the +destination (first) operand, moving each bit in the separate elements +right by the number of bits specified in the source (second) operand, +setting the high-order bits to the value of the original sign bit. -\c PSRAW mmxreg,r/m64 ; 0F E1 /r [PENT,MMX] -\c PSRAW mmxreg,imm8 ; 0F 71 /4 ib [PENT,MMX] +\b \c{PSRAW} shifts word sized elements. -\c PSRAD mmxreg,r/m64 ; 0F E2 /r [PENT,MMX] -\c PSRAD mmxreg,imm8 ; 0F 72 /4 ib [PENT,MMX] +\b \c{PSRAD} shifts doubleword sized elements. -\c PSRLW mmxreg,r/m64 ; 0F D1 /r [PENT,MMX] -\c PSRLW mmxreg,imm8 ; 0F 71 /2 ib [PENT,MMX] -\c PSRLD mmxreg,r/m64 ; 0F D2 /r [PENT,MMX] -\c PSRLD mmxreg,imm8 ; 0F 72 /2 ib [PENT,MMX] +\H{insPSRLD} \i\c{PSRLx}: Packed Data Bit Shift Right Logical -\c PSRLQ mmxreg,r/m64 ; 0F D3 /r [PENT,MMX] -\c PSRLQ mmxreg,imm8 ; 0F 73 /2 ib [PENT,MMX] +\c PSRLW mm1,mm2/m64 ; 0F D1 /r [PENT,MMX] +\c PSRLW mm,imm8 ; 0F 71 /2 ib [PENT,MMX] -\c{PSxxQ} perform simple bit shifts on the 64-bit MMX registers: the -destination (first) operand is shifted left or right by the number of -bits given in the source (second) operand, and the vacated bits are -filled in with zeros (for a logical shift) or copies of the original -sign bit (for an arithmetic right shift). +\c PSRLW xmm1,xmm2/m128 ; 66 0F D1 /r [WILLAMETTE,SSE2] +\c PSRLW xmm,imm8 ; 66 0F 71 /2 ib [WILLAMETTE,SSE2] -\c{PSxxW} and \c{PSxxD} perform packed bit shifts: the destination -operand is treated as a vector of four words or two doublewords, and -each element is shifted individually, so bits shifted out of one -element do not interfere with empty bits coming into the next. +\c PSRLD mm1,mm2/m64 ; 0F D2 /r [PENT,MMX] +\c PSRLD mm,imm8 ; 0F 72 /2 ib [PENT,MMX] -\c{PSLLx} and \c{PSRLx} perform logical shifts: the vacated bits at -one end of the shifted number are filled with zeros. \c{PSRAx} -performs an arithmetic right shift: the vacated bits at the top of -the shifted number are filled with copies of the original top (sign) -bit. +\c PSRLD xmm1,xmm2/m128 ; 66 0F D2 /r [WILLAMETTE,SSE2] +\c PSRLD xmm,imm8 ; 66 0F 72 /2 ib [WILLAMETTE,SSE2] -\H{insPSUBB} \i\c{PSUBxx}: MMX Packed Subtraction +\c PSRLQ mm1,mm2/m64 ; 0F D3 /r [PENT,MMX] +\c PSRLQ mm,imm8 ; 0F 73 /2 ib [PENT,MMX] -\c PSUBB mmxreg,r/m64 ; 0F F8 /r [PENT,MMX] -\c PSUBW mmxreg,r/m64 ; 0F F9 /r [PENT,MMX] -\c PSUBD mmxreg,r/m64 ; 0F FA /r [PENT,MMX] +\c PSRLQ xmm1,xmm2/m128 ; 66 0F D3 /r [WILLAMETTE,SSE2] +\c PSRLQ xmm,imm8 ; 66 0F 73 /2 ib [WILLAMETTE,SSE2] -\c PSUBSB mmxreg,r/m64 ; 0F E8 /r [PENT,MMX] -\c PSUBSW mmxreg,r/m64 ; 0F E9 /r [PENT,MMX] +\c PSRLDQ xmm1,imm8 ; 66 0F 73 /3 ib [WILLAMETTE,SSE2] -\c PSUBUSB mmxreg,r/m64 ; 0F D8 /r [PENT,MMX] -\c PSUBUSW mmxreg,r/m64 ; 0F D9 /r [PENT,MMX] +\c{PSRLx} performs logical right shifts of the data elements in the +destination (first) operand, moving each bit in the separate elements +right by the number of bits specified in the source (second) operand, +clearing the high-order bits as they are vacated. -\c{PSUBxx} all perform packed subtraction between their two 64-bit -operands, storing the result in the destination (first) operand. The -\c{PSUBxB} forms treat the 64-bit operands as vectors of eight -bytes, and subtract each byte individually; \c{PSUBxW} treat the operands -as vectors of four words; and \c{PSUBD} treats its operands as -vectors of two doublewords. +\b \c{PSRLW} shifts word sized elements. -In all cases, the elements of the operand on the right are -subtracted from the corresponding elements of the operand on the -left, not the other way round. +\b \c{PSRLD} shifts doubleword sized elements. + +\b \c{PSRLQ} shifts quadword sized elements. + +\b \c{PSRLDQ} shifts double quadword sized elements. + + +\H{insPSUBB} \i\c{PSUBx}: Subtract Packed Integers + +\c PSUBB mm1,mm2/m64 ; 0F F8 /r [PENT,MMX] +\c PSUBW mm1,mm2/m64 ; 0F F9 /r [PENT,MMX] +\c PSUBD mm1,mm2/m64 ; 0F FA /r [PENT,MMX] +\c PSUBQ mm1,mm2/m64 ; 0F FB /r [WILLAMETTE,SSE2] + +\c PSUBB xmm1,xmm2/m128 ; 66 0F F8 /r [WILLAMETTE,SSE2] +\c PSUBW xmm1,xmm2/m128 ; 66 0F F9 /r [WILLAMETTE,SSE2] +\c PSUBD xmm1,xmm2/m128 ; 66 0F FA /r [WILLAMETTE,SSE2] +\c PSUBQ xmm1,xmm2/m128 ; 66 0F FB /r [WILLAMETTE,SSE2] + +\c{PSUBx} subtracts packed integers in the source operand from those +in the destination operand. It doesn't differentiate between signed +and unsigned integers, and doesn't set any of the flags. + +\b \c{PSUBB} operates on byte sized elements. + +\b \c{PSUBW} operates on word sized elements. + +\b \c{PSUBD} operates on doubleword sized elements. + +\b \c{PSUBQ} operates on quadword sized elements. + + +\H{insPSUBSB} \i\c{PSUBSxx}, \i\c{PSUBUSx}: Subtract Packed Integers With Saturation + +\c PSUBSB mm1,mm2/m64 ; 0F E8 /r [PENT,MMX] +\c PSUBSW mm1,mm2/m64 ; 0F E9 /r [PENT,MMX] + +\c PSUBSB xmm1,xmm2/m128 ; 66 0F E8 /r [WILLAMETTE,SSE2] +\c PSUBSW xmm1,xmm2/m128 ; 66 0F E9 /r [WILLAMETTE,SSE2] + +\c PSUBUSB mm1,mm2/m64 ; 0F D8 /r [PENT,MMX] +\c PSUBUSW mm1,mm2/m64 ; 0F D9 /r [PENT,MMX] + +\c PSUBUSB xmm1,xmm2/m128 ; 66 0F D8 /r [WILLAMETTE,SSE2] +\c PSUBUSW xmm1,xmm2/m128 ; 66 0F D9 /r [WILLAMETTE,SSE2] + +\c{PSUBSx} and \c{PSUBUSx} subtracts packed integers in the source +operand from those in the destination operand, and use saturation for +results that are outide the range supported by the destination operand. + +\b \c{PSUBSB} operates on signed bytes, and uses signed saturation on the +results. + +\b \c{PSUBSW} operates on signed words, and uses signed saturation on the +results. + +\b \c{PSUBUSB} operates on unsigned bytes, and uses signed saturation on +the results. + +\b \c{PSUBUSW} operates on unsigned words, and uses signed saturation on +the results. -\c{PSUBSB} and \c{PSUBSW} perform signed saturation on the sum of -each pair of bytes or words: if the result of a subtraction is too -large or too small to fit into a signed byte or word result, it is -clipped (saturated) to the largest or smallest value which \e{will} -fit. \c{PSUBUSB} and \c{PSUBUSW} similarly perform unsigned -saturation, clipping to \c{0FFh} or \c{0FFFFh} if the result is -larger than that. \H{insPSUBSIW} \i\c{PSUBSIW}: MMX Packed Subtract with Saturation to Implied Destination -\c PSUBSIW mmxreg,r/m64 ; 0F 55 /r [CYRIX,MMX] +\c PSUBSIW mm1,mm2/m64 ; 0F 55 /r [CYRIX,MMX] \c{PSUBSIW}, specific to the Cyrix extensions to the MMX instruction set, performs the same function as \c{PSUBSW}, except that the @@ -8919,15 +11106,51 @@ result is not placed in the register specified by the first operand, but instead in the implied destination register, specified as for \c{PADDSIW} (\k{insPADDSIW}). -\H{insPUNPCKHBW} \i\c{PUNPCKxxx}: Unpack Data -\c PUNPCKHBW mmxreg,r/m64 ; 0F 68 /r [PENT,MMX] -\c PUNPCKHWD mmxreg,r/m64 ; 0F 69 /r [PENT,MMX] -\c PUNPCKHDQ mmxreg,r/m64 ; 0F 6A /r [PENT,MMX] +\H{insPSWAPD} \i\c{PSWAPD}: Swap Packed Data +\I\c{PSWAPW} + +\c PSWAPD mm1,mm2/m64 ; 0F 0F /r BB [PENT,3DNOW] + +\c{PSWAPD} swaps the packed doublewords in the source operand, and +stores the result in the destination operand. + +In the \c{K6-2} and \c{K6-III} processors, this opcode uses the +mnemonic \c{PSWAPW}, and it swaps the order of words when copying +from the source to the destination. + +The operation in the \c{K6-2} and \c{K6-III} processors is + +\c dst[0-15] = src[48-63]; +\c dst[16-31] = src[32-47]; +\c dst[32-47] = src[16-31]; +\c dst[48-63] = src[0-15]. + +The operation in the \c{K6-x+}, \c{ATHLON} and later processors is: + +\c dst[0-31] = src[32-63]; +\c dst[32-63] = src[0-31]. + -\c PUNPCKLBW mmxreg,r/m64 ; 0F 60 /r [PENT,MMX] -\c PUNPCKLWD mmxreg,r/m64 ; 0F 61 /r [PENT,MMX] -\c PUNPCKLDQ mmxreg,r/m64 ; 0F 62 /r [PENT,MMX] +\H{insPUNPCKHBW} \i\c{PUNPCKxxx}: Unpack and Interleave Data + +\c PUNPCKHBW mm1,mm2/m64 ; 0F 68 /r [PENT,MMX] +\c PUNPCKHWD mm1,mm2/m64 ; 0F 69 /r [PENT,MMX] +\c PUNPCKHDQ mm1,mm2/m64 ; 0F 6A /r [PENT,MMX] + +\c PUNPCKHBW xmm1,xmm2/m128 ; 66 0F 68 /r [WILLAMETTE,SSE2] +\c PUNPCKHWD xmm1,xmm2/m128 ; 66 0F 69 /r [WILLAMETTE,SSE2] +\c PUNPCKHDQ xmm1,xmm2/m128 ; 66 0F 6A /r [WILLAMETTE,SSE2] +\c PUNPCKHQDQ xmm1,xmm2/m128 ; 66 0F 6D /r [WILLAMETTE,SSE2] + +\c PUNPCKLBW mm1,mm2/m32 ; 0F 60 /r [PENT,MMX] +\c PUNPCKLWD mm1,mm2/m32 ; 0F 61 /r [PENT,MMX] +\c PUNPCKLDQ mm1,mm2/m32 ; 0F 62 /r [PENT,MMX] + +\c PUNPCKLBW xmm1,xmm2/m128 ; 66 0F 60 /r [WILLAMETTE,SSE2] +\c PUNPCKLWD xmm1,xmm2/m128 ; 66 0F 61 /r [WILLAMETTE,SSE2] +\c PUNPCKLDQ xmm1,xmm2/m128 ; 66 0F 62 /r [WILLAMETTE,SSE2] +\c PUNPCKLQDQ xmm1,xmm2/m128 ; 66 0F 6C /r [WILLAMETTE,SSE2] \c{PUNPCKxx} all treat their operands as vectors, and produce a new vector generated by interleaving elements from the two inputs. The @@ -8935,17 +11158,27 @@ vector generated by interleaving elements from the two inputs. The each input operand, and the \c{PUNPCKLxx} instructions throw away the top half. -The remaining elements, totalling 64 bits, are then interleaved into -the destination, alternating elements from the second (source) -operand and the first (destination) operand: so the leftmost element -in the result always comes from the second operand, and the -rightmost from the destination. +The remaining elements, are then interleaved into the destination, +alternating elements from the second (source) operand and the first +(destination) operand: so the leftmost part of each element in the +result always comes from the second operand, and the rightmost from +the destination. + +\b \c{PUNPCKxBW} works a byte at a time, producing word sized output +elements. -\c{PUNPCKxBW} works a byte at a time, \c{PUNPCKxWD} a word at a -time, and \c{PUNPCKxDQ} a doubleword at a time. +\b \c{PUNPCKxWD} works a word at a time, producing doubleword sized +output elements. -So, for example, if the first operand held \c{0x7A6A5A4A3A2A1A0A} -and the second held \c{0x7B6B5B4B3B2B1B0B}, then: +\b \c{PUNPCKxDQ} works a doubleword at a time, producing quadword sized +output elements. + +\b \c{PUNPCKxQDQ} works a quadword at a time, producing double quadword +sized output elements. + +So, for example, for \c{MMX} operands, if the first operand held +\c{0x7A6A5A4A3A2A1A0A} and the second held \c{0x7B6B5B4B3B2B1B0B}, +then: \b \c{PUNPCKHBW} would return \c{0x7B7A6B6A5B5A4B4A}. @@ -8959,6 +11192,7 @@ and the second held \c{0x7B6B5B4B3B2B1B0B}, then: \b \c{PUNPCKLDQ} would return \c{0x3B2B1B0B3A2A1A0A}. + \H{insPUSH} \i\c{PUSH}: Push Data on Stack \c PUSH reg16 ; o16 50+r [8086] @@ -9006,6 +11240,7 @@ later processors: on an 8086, the value of \c{SP} stored is the value it has \e{after} the push instruction, whereas on later processors it is the value \e{before} the push instruction. + \H{insPUSHA} \i\c{PUSHAx}: Push All General-Purpose Registers \c PUSHA ; 60 [186] @@ -9031,31 +11266,37 @@ in opcodes (see \k{iref-rv}). See also \c{POPA} (\k{insPOPA}). + \H{insPUSHF} \i\c{PUSHFx}: Push Flags Register \c PUSHF ; 9C [186] \c PUSHFD ; o32 9C [386] \c PUSHFW ; o16 9C [186] -\c{PUSHFW} pops a word from the stack and stores it in the bottom 16 -bits of the flags register (or the whole flags register, on -processors below a 386). \c{PUSHFD} pops a doubleword and stores it -in the entire flags register. +\b \c{PUSHFW} pops a word from the stack and stores it in the +bottom 16 bits of the flags register (or the whole flags register, +on processors below a 386). + +\b \c{PUSHFD} pops a doubleword and stores it in the entire flags +register. \c{PUSHF} is an alias mnemonic for either \c{PUSHFW} or \c{PUSHFD}, depending on the current \c{BITS} setting. See also \c{POPF} (\k{insPOPF}). + \H{insPXOR} \i\c{PXOR}: MMX Bitwise XOR -\c PXOR mmxreg,r/m64 ; 0F EF /r [PENT,MMX] +\c PXOR mm1,mm2/m64 ; 0F EF /r [PENT,MMX] +\c PXOR xmm1,xmm2/m128 ; 66 0F EF /r [WILLAMETTE,SSE2] \c{PXOR} performs a bitwise XOR operation between its two operands (i.e. each bit of the result is 1 if and only if exactly one of the corresponding bits of the two inputs was 1), and stores the result in the destination (first) operand. + \H{insRCL} \i\c{RCL}, \i\c{RCR}: Bitwise Rotate through Carry Bit \c RCL r/m8,1 ; D0 /2 [8086] @@ -9081,7 +11322,7 @@ in the destination (first) operand. \c{RCL} and \c{RCR} perform a 9-bit, 17-bit or 33-bit bitwise rotation operation, involving the given source/destination (first) operand and the carry bit. Thus, for example, in the operation -\c{RCR AL,1}, a 9-bit rotation is performed in which \c{AL} is +\c{RCL AL,1}, a 9-bit rotation is performed in which \c{AL} is shifted left by 1, the top bit of \c{AL} moves into the carry flag, and the original value of the carry flag is placed in the low bit of \c{AL}. @@ -9095,35 +11336,34 @@ byte) form of \c{RCL foo,1} by using a \c{BYTE} prefix: \c{RCL foo,BYTE 1}. Similarly with \c{RCR}. -\H{insRCPPS} \i\c{RCPPS}: Packed Single-FP Reciprocal +\H{insRCPPS} \i\c{RCPPS}: Packed Single-Precision FP Reciprocal -\c RCPPS xmmreg,memory ; 0F,53,/r [KATMAI,SSE] -\c RCPPS xmmreg,xmmreg ; ?? [KATMAI,SSE] +\c RCPPS xmm1,xmm2/m128 ; 0F 53 /r [KATMAI,SSE] -\c{RCPPS}RCPPS returns an approximation of the reciprocal of the - SP FP numbers from xmm2/m128. The maximum error for this - approximation is: Error <=1.5x2-12 +\c{RCPPS} returns an approximation of the reciprocal of the packed +single-precision FP values from xmm2/m128. The maximum error for this +approximation is: |Error| <= 1.5 x 2^-12 -\H{insRCPSS} \i\c{RCPSS}: Scalar Single-FP Reciprocal +\H{insRCPSS} \i\c{RCPSS}: Scalar Single-Precision FP Reciprocal -\c RCPSS xmmreg,memory ; F3,0F,53,/r [KATMAI,SSE] -\c RCPSS xmmreg,xmmreg ; ?? [KATMAI,SSE] +\c RCPSS xmm1,xmm2/m128 ; F3 0F 53 /r [KATMAI,SSE] -\c{RCPSS}RCPSS returns an approximation of the reciprocal of the - lower SP FP number from xmm2/m32; the upper three fields are - passed through from xmm1. The maximum error for this - approximation is: |Error| <= 1.5x2-12 +\c{RCPSS} returns an approximation of the reciprocal of the lower +single-precision FP value from xmm2/m32; the upper three fields are +passed through from xmm1. The maximum error for this approximation is: +|Error| <= 1.5 x 2^-12 \H{insRDMSR} \i\c{RDMSR}: Read Model-Specific Registers -\c RDMSR ; 0F 32 [PENT] +\c RDMSR ; 0F 32 [PENT,PRIV] \c{RDMSR} reads the processor Model-Specific Register (MSR) whose index is stored in \c{ECX}, and stores the result in \c{EDX:EAX}. See also \c{WRMSR} (\k{insWRMSR}). + \H{insRDPMC} \i\c{RDPMC}: Read Performance-Monitoring Counters \c RDPMC ; 0F 33 [P6] @@ -9131,12 +11371,28 @@ See also \c{WRMSR} (\k{insWRMSR}). \c{RDPMC} reads the processor performance-monitoring counter whose index is stored in \c{ECX}, and stores the result in \c{EDX:EAX}. +This instruction is available on P6 and later processors and on MMX +class processors. + + +\H{insRDSHR} \i\c{RDSHR}: Read SMM Header Pointer Register + +\c RDSHR r/m32 ; 0F 36 /0 [386,CYRIX,SMM] + +\c{RDSHR} reads the contents of the SMM header pointer register and +saves it to the destination operand, which can be either a 32 bit +memory location or a 32 bit register. + +See also \c{WRSHR} (\k{insWRSHR}). + + \H{insRDTSC} \i\c{RDTSC}: Read Time-Stamp Counter \c RDTSC ; 0F 31 [PENT] \c{RDTSC} reads the processor's time-stamp counter into \c{EDX:EAX}. + \H{insRET} \i\c{RET}, \i\c{RETF}, \i\c{RETN}: Return from Procedure Call \c RET ; C3 [8086] @@ -9148,15 +11404,16 @@ index is stored in \c{ECX}, and stores the result in \c{EDX:EAX}. \c RETN ; C3 [8086] \c RETN imm16 ; C2 iw [8086] -\c{RET}, and its exact synonym \c{RETN}, pop \c{IP} or \c{EIP} from +\b \c{RET}, and its exact synonym \c{RETN}, pop \c{IP} or \c{EIP} from the stack and transfer control to the new address. Optionally, if a numeric second operand is provided, they increment the stack pointer by a further \c{imm16} bytes after popping the return address. -\c{RETF} executes a far return: after popping \c{IP}/\c{EIP}, it +\b \c{RETF} executes a far return: after popping \c{IP}/\c{EIP}, it then pops \c{CS}, and \e{then} increments the stack pointer by the optional argument if present. + \H{insROL} \i\c{ROL}, \i\c{ROR}: Bitwise Rotate \c ROL r/m8,1 ; D0 /0 [8086] @@ -9181,18 +11438,34 @@ optional argument if present. \c{ROL} and \c{ROR} perform a bitwise rotation operation on the given source/destination (first) operand. Thus, for example, in the -operation \c{ROR AL,1}, an 8-bit rotation is performed in which +operation \c{ROL AL,1}, an 8-bit rotation is performed in which \c{AL} is shifted left by 1 and the original top bit of \c{AL} moves round into the low bit. The number of bits to rotate by is given by the second operand. Only -the bottom 3, 4 or 5 bits (depending on the source operand size) of -the rotation count are considered by processors above the 8086. +the bottom five bits of the rotation count are considered by processors +above the 8086. You can force the longer (286 and upwards, beginning with a \c{C1} byte) form of \c{ROL foo,1} by using a \c{BYTE} prefix: \c{ROL foo,BYTE 1}. Similarly with \c{ROR}. + +\H{insRSDC} \i\c{RSDC}: Restore Segment Register and Descriptor + +\c RSDC segreg,m80 ; 0F 79 /r [486,CYRIX,SMM] + +\c{RSDC} restores a segment register (DS, ES, FS, GS, or SS) from mem80, +and sets up its descriptor. + + +\H{insRSLDT} \i\c{RSLDT}: Restore Segment Register and Descriptor + +\c RSLDT m80 ; 0F 7B /0 [486,CYRIX,SMM] + +\c{RSLDT} restores the Local Descriptor Table (LDTR) from mem80. + + \H{insRSM} \i\c{RSM}: Resume from System-Management Mode \c RSM ; 0F AA [PENT] @@ -9201,25 +11474,32 @@ foo,BYTE 1}. Similarly with \c{ROR}. was in System-Management Mode. -\H{insRSQRTPS} \i\c{RSQRTPS}:Packed Single-FP Square Root Reciprocal +\H{insRSQRTPS} \i\c{RSQRTPS}: Packed Single-Precision FP Square Root Reciprocal + +\c RSQRTPS xmm1,xmm2/m128 ; 0F 52 /r [KATMAI,SSE] -\c RSQRTPS xmmreg,memory ; 0F,52,/r [KATMAI,SSE] -\c RSQRTPS xmmreg,xmmreg ; ?? [KATMAI,SSE] +\c{RSQRTPS} computes the approximate reciprocals of the square +roots of the packed single-precision floating-point values in the +source and stores the results in xmm1. The maximum error for this +approximation is: |Error| <= 1.5 x 2^-12 -\c{RSQRTPS} RSQRTPS returns an approximation of the reciprocal - of the square root of the SP FP numbers rom xmm2/m128. The - maximum error for this approximation is: Error| <= 1.5x2-12 +\H{insRSQRTSS} \i\c{RSQRTSS}: Scalar Single-Precision FP Square Root Reciprocal -\H{insRSQRTSS} \i\c{RSQRTSS}:Scalar Single-FP Square Root Reciprocal +\c RSQRTSS xmm1,xmm2/m128 ; F3 0F 52 /r [KATMAI,SSE] -\c RSQRTSS xmmreg,memory ; F3,0F,52,/r [KATMAI,SSE] -\c RSQRTSS xmmreg,xmmreg ; ?? [KATMAI,SSE] +\c{RSQRTSS} returns an approximation of the reciprocal of the +square root of the lowest order single-precision FP value from +the source, and stores it in the low doubleword of the destination +register. The upper three fields of xmm1 are preserved. The maximum +error for this approximation is: |Error| <= 1.5 x 2^-12 -\c{RSQRTSS} RSQRTSS returns an approximation of the reciprocal - of the square root of the lowest SP FP number from xmm2/m32; - the upper three fields are passed through from xmm1. The maximum - error for this approximation is: |Error| <= 1.5x2-12 + +\H{insRSTS} \i\c{RSTS}: Restore TSR and Descriptor + +\c RSTS m80 ; 0F 7D /0 [486,CYRIX,SMM] + +\c{RSTS} restores Task State Register (TSR) from mem80. \H{insSAHF} \i\c{SAHF}: Store AH to Flags @@ -9227,7 +11507,14 @@ was in System-Management Mode. \c SAHF ; 9E [8086] \c{SAHF} sets the low byte of the flags word according to the -contents of the \c{AH} register. See also \c{LAHF} (\k{insLAHF}). +contents of the \c{AH} register. + +The operation of \c{SAHF} is: + +\c AH --> SF:ZF:0:AF:0:PF:1:CF + +See also \c{LAHF} (\k{insLAHF}). + \H{insSAL} \i\c{SAL}, \i\c{SAR}: Bitwise Arithmetic Shifts @@ -9241,15 +11528,15 @@ contents of the \c{AH} register. See also \c{LAHF} (\k{insLAHF}). \c SAL r/m32,CL ; o32 D3 /4 [386] \c SAL r/m32,imm8 ; o32 C1 /4 ib [386] -\c SAR r/m8,1 ; D0 /0 [8086] -\c SAR r/m8,CL ; D2 /0 [8086] -\c SAR r/m8,imm8 ; C0 /0 ib [286] -\c SAR r/m16,1 ; o16 D1 /0 [8086] -\c SAR r/m16,CL ; o16 D3 /0 [8086] -\c SAR r/m16,imm8 ; o16 C1 /0 ib [286] -\c SAR r/m32,1 ; o32 D1 /0 [386] -\c SAR r/m32,CL ; o32 D3 /0 [386] -\c SAR r/m32,imm8 ; o32 C1 /0 ib [386] +\c SAR r/m8,1 ; D0 /7 [8086] +\c SAR r/m8,CL ; D2 /7 [8086] +\c SAR r/m8,imm8 ; C0 /7 ib [286] +\c SAR r/m16,1 ; o16 D1 /7 [8086] +\c SAR r/m16,CL ; o16 D3 /7 [8086] +\c SAR r/m16,imm8 ; o16 C1 /7 ib [286] +\c SAR r/m32,1 ; o32 D1 /7 [386] +\c SAR r/m32,CL ; o32 D3 /7 [386] +\c SAR r/m32,imm8 ; o32 C1 /7 ib [386] \c{SAL} and \c{SAR} perform an arithmetic shift operation on the given source/destination (first) operand. The vacated bits are filled with @@ -9261,13 +11548,14 @@ assemble either one to the same code, but NDISASM will always disassemble that code as \c{SHL}. The number of bits to shift by is given by the second operand. Only -the bottom 3, 4 or 5 bits (depending on the source operand size) of -the shift count are considered by processors above the 8086. +the bottom five bits of the shift count are considered by processors +above the 8086. You can force the longer (286 and upwards, beginning with a \c{C1} byte) form of \c{SAL foo,1} by using a \c{BYTE} prefix: \c{SAL foo,BYTE 1}. Similarly with \c{SAR}. + \H{insSALC} \i\c{SALC}: Set AL from Carry Flag \c SALC ; D6 [8086,UNDOC] @@ -9276,6 +11564,7 @@ foo,BYTE 1}. Similarly with \c{SAR}. \c{SETcc} (\k{insSETcc}). Its function is to set \c{AL} to zero if the carry flag is clear, or to \c{0xFF} if it is set. + \H{insSBB} \i\c{SBB}: Subtract with Borrow \c SBB r/m8,reg8 ; 18 /r [8086] @@ -9313,6 +11602,7 @@ form of the instruction. To subtract one number from another without also subtracting the contents of the carry flag, use \c{SUB} (\k{insSUB}). + \H{insSCASB} \i\c{SCASB}, \i\c{SCASW}, \i\c{SCASD}: Scan String \c SCASB ; AE [8086] @@ -9343,6 +11633,7 @@ The \c{REPE} and \c{REPNE} prefixes (equivalently, \c{REPZ} and \c{ECX} - again, the address size chooses which) times until the first unequal or equal byte is found. + \H{insSETcc} \i\c{SETcc}: Set Register from Condition \c SETcc r/m8 ; 0F 90+cc /2 [386] @@ -9353,31 +11644,35 @@ not satisfied, and to 1 if it is. \H{insSFENCE} \i\c{SFENCE}: Store Fence -\c SFENCE 0,0,0 ; 0F AE /7 [KATMAI] - -\c{SFENCE} Weakly ordered memory types can enable higher - performance through such techniques as out-of-order issue, - write-combining, and write-collapsing. Memory ordering issues - can arise between a producer and a consumer of data and there - are a number of common usage models which may be affected by - weakly ordered stores: - 1. library functions, which use weakly ordered memory - to write results - 2. compiler-generated code, which also benefit from writing - weakly-ordered results - 3. hand-written code - The degree to which a consumer of data knows that the data is - weakly ordered can vary for these cases. As a result, the SFENCE - instruction provides a performance-efficient way of ensuring - ordering between routines that produce weakly-ordered results - and routines that consume this data. The SFENCE is ordered with - respect to stores and other SFENCE instructions. - SFENCE uses the following ModRM encoding: - Mod (7:6) = 11B - Reg/Opcode (5:3) = 111B - R/M (2:0) = 000B - All other ModRM encodings are defined to be reserved, and use - of these encodings risks incompatibility with future processors. +\c SFENCE ; 0F AE /7 [KATMAI] + +\c{SFENCE} performs a serialising operation on all writes to memory +that were issued before the \c{SFENCE} instruction. This guarantees that +all memory writes before the \c{SFENCE} instruction are visible before any +writes after the \c{SFENCE} instruction. + +\c{SFENCE} is ordered respective to other \c{SFENCE} instruction, \c{MFENCE}, +any memory write and any other serialising instruction (such as \c{CPUID}). + +Weakly ordered memory types can be used to achieve higher processor +performance through such techniques as out-of-order issue, +write-combining, and write-collapsing. The degree to which a consumer +of data recognizes or knows that the data is weakly ordered varies +among applications and may be unknown to the producer of this data. +The \c{SFENCE} instruction provides a performance-efficient way of +insuring store ordering between routines that produce weakly-ordered +results and routines that consume this data. + +\c{SFENCE} uses the following ModRM encoding: + +\c Mod (7:6) = 11B +\c Reg/Opcode (5:3) = 111B +\c R/M (2:0) = 000B + +All other ModRM encodings are defined to be reserved, and use +of these encodings risks incompatibility with future processors. + +See also \c{LFENCE} (\k{insLFENCE}) and \c{MFENCE} (\k{insMFENCE}). \H{insSGDT} \i\c{SGDT}, \i\c{SIDT}, \i\c{SLDT}: Store Descriptor Table Pointers @@ -9398,6 +11693,7 @@ descriptor table) into the given operand. See also \c{LGDT}, \c{LIDT} and \c{LLDT} (\k{insLGDT}). + \H{insSHL} \i\c{SHL}, \i\c{SHR}: Bitwise Logical Shifts \c SHL r/m8,1 ; D0 /4 [8086] @@ -9429,13 +11725,14 @@ assemble either one to the same code, but NDISASM will always disassemble that code as \c{SHL}. The number of bits to shift by is given by the second operand. Only -the bottom 3, 4 or 5 bits (depending on the source operand size) of -the shift count are considered by processors above the 8086. +the bottom five bits of the shift count are considered by processors +above the 8086. You can force the longer (286 and upwards, beginning with a \c{C1} byte) form of \c{SHL foo,1} by using a \c{BYTE} prefix: \c{SHL foo,BYTE 1}. Similarly with \c{SHR}. + \H{insSHLD} \i\c{SHLD}, \i\c{SHRD}: Bitwise Double-Precision Shifts \c SHLD r/m16,reg16,imm8 ; o16 0F A4 /r ib [386] @@ -9448,13 +11745,14 @@ foo,BYTE 1}. Similarly with \c{SHR}. \c SHRD r/m16,reg16,CL ; o16 0F AD /r [386] \c SHRD r/m32,reg32,CL ; o32 0F AD /r [386] -\c{SHLD} performs a double-precision left shift. It notionally places -its second operand to the right of its first, then shifts the entire -bit string thus generated to the left by a number of bits specified -in the third operand. It then updates only the \e{first} operand -according to the result of this. The second operand is not modified. +\b \c{SHLD} performs a double-precision left shift. It notionally +places its second operand to the right of its first, then shifts +the entire bit string thus generated to the left by a number of +bits specified in the third operand. It then updates only the +\e{first} operand according to the result of this. The second +operand is not modified. -\c{SHRD} performs the corresponding right shift: it notionally +\b \c{SHRD} performs the corresponding right shift: it notionally places the second operand to the \e{left} of the first, shifts the whole bit string right, and updates only the first operand. @@ -9464,27 +11762,70 @@ For example, if \c{EAX} holds \c{0x01234567} and \c{EBX} holds EAX,EBX,4} would update \c{EAX} to hold \c{0xF0123456}. The number of bits to shift by is given by the third operand. Only -the bottom 5 bits of the shift count are considered. +the bottom five bits of the shift count are considered. + + +\H{insSHUFPD} \i\c{SHUFPD}: Shuffle Packed Double-Precision FP Values + +\c SHUFPD xmm1,xmm2/m128,imm8 ; 66 0F C6 /r ib [WILLAMETTE,SSE2] + +\c{SHUFPD} moves one of the packed double-precision FP values from +the destination operand into the low quadword of the destination +operand; the upper quadword is generated by moving one of the +double-precision FP values from the source operand into the +destination. The select (third) operand selects which of the values +are moved to the destination register. + +The select operand is an 8-bit immediate: bit 0 selects which value +is moved from the destination operand to the result (where 0 selects +the low quadword and 1 selects the high quadword) and bit 1 selects +which value is moved from the source operand to the result. +Bits 2 through 7 of the shuffle operand are reserved. + +\H{insSHUFPS} \i\c{SHUFPS}: Shuffle Packed Single-Precision FP Values -\H{insSHUFPS} \i\c{SHUFPS}: Shuffle Single-FP +\c SHUFPS xmm1,xmm2/m128,imm8 ; 0F C6 /r ib [KATMAI,SSE] -\c SHUFPS xmmreg,memory,immediate ; 0F,C6,/r, ib [KATMAI,SSE,SB,AR2] -\c SHUFPS xmmreg,xmmreg,immediate ; ?? [KATMAI,SSE,SB,AR2] +\c{SHUFPD} moves two of the packed single-precision FP values from +the destination operand into the low quadword of the destination +operand; the upper quadword is generated by moving two of the +single-precision FP values from the source operand into the +destination. The select (third) operand selects which of the +values are moved to the destination register. -\c{SHUFPS} The SHUFPS instruction is able to shuffle any of the - four SP FP numbers from xmm1 to the lower two destination fields; - the upper two destination fields are generated from a shuffle of - any of the four SP FP numbers from xmm2/m128. +The select operand is an 8-bit immediate: bits 0 and 1 select the +value to be moved from the destination operand the low doubleword of +the result, bits 2 and 3 select the value to be moved from the +destination operand the second doubleword of the result, bits 4 and +5 select the value to be moved from the source operand the third +doubleword of the result, and bits 6 and 7 select the value to be +moved from the source operand to the high doubleword of the result. \H{insSMI} \i\c{SMI}: System Management Interrupt \c SMI ; F1 [386,UNDOC] -This is an opcode apparently supported by some AMD processors (which -is why it can generate the same opcode as \c{INT1}), and places the -machine into system-management mode, a special debugging mode. +\c{SMI} puts some AMD processors into SMM mode. It is available on some +386 and 486 processors, and is only available when DR7 bit 12 is set, +otherwise it generates an Int 1. + + +\H{insSMINT} \i\c{SMINT}, \i\c{SMINTOLD}: Software SMM Entry (CYRIX) + +\c SMINT ; 0F 38 [PENT,CYRIX] +\c SMINTOLD ; 0F 7E [486,CYRIX] + +\c{SMINT} puts the processor into SMM mode. The CPU state information is +saved in the SMM memory header, and then execution begins at the SMM base +address. + +\c{SMINTOLD} is the same as \c{SMINT}, but was the opcode used on the 486. + +This pair of opcodes are specific to the Cyrix and compatible range of +processors (Cyrix, IBM, Via). + \H{insSMSW} \i\c{SMSW}: Store Machine Status Word @@ -9494,23 +11835,46 @@ machine into system-management mode, a special debugging mode. the Machine Status Word, on 286 processors) into the destination operand. See also \c{LMSW} (\k{insLMSW}). +For 32-bit code, this would use the low 16-bits of the specified +register (or a 16bit memory location), without needing an operand +size override byte. + + +\H{insSQRTPD} \i\c{SQRTPD}: Packed Double-Precision FP Square Root + +\c SQRTPD xmm1,xmm2/m128 ; 66 0F 51 /r [WILLAMETTE,SSE2] -\H{insSQRTPS} \i\c{SQRTPS}: Packed Single-FP Square Root +\c{SQRTPD} calculates the square root of the packed double-precision +FP value from the source operand, and stores the double-precision +results in the destination register. -\c SQRTPS xmmreg,memory ; 0F,51,/r [KATMAI,SSE] -\c SQRTPS xmmreg,xmmreg ; ?? [KATMAI,SSE] -\c{SQRTPS} The SQRTPS instruction returns the square root of - the packed SP FP numbers from xmm2/m128. +\H{insSQRTPS} \i\c{SQRTPS}: Packed Single-Precision FP Square Root +\c SQRTPS xmm1,xmm2/m128 ; 0F 51 /r [KATMAI,SSE] -\H{insSQRTSS} \i\c{SQRTSS}: Scalar Single-FP Square Root +\c{SQRTPS} calculates the square root of the packed single-precision +FP value from the source operand, and stores the single-precision +results in the destination register. -\c SQRTSS xmmreg,memory ; F3,0F,51,/r [KATMAI,SSE] -\c SQRTSS xmmreg,xmmreg ; ?? [KATMAI,SSE] -\c{SQRTSS} The SQRTSS instructions return the square root of - the lowest SP FP numbers of their operand. +\H{insSQRTSD} \i\c{SQRTSD}: Scalar Double-Precision FP Square Root + +\c SQRTSD xmm1,xmm2/m128 ; F2 0F 51 /r [WILLAMETTE,SSE2] + +\c{SQRTSD} calculates the square root of the low-order double-precision +FP value from the source operand, and stores the double-precision +result in the destination register. The high-quadword remains unchanged. + + +\H{insSQRTSS} \i\c{SQRTSS}: Scalar Single-Precision FP Square Root + +\c SQRTSS xmm1,xmm2/m128 ; F3 0F 51 /r [KATMAI,SSE] + +\c{SQRTSS} calculates the square root of the low-order single-precision +FP value from the source operand, and stores the single-precision +result in the destination register. The three high doublewords remain +unchanged. \H{insSTC} \i\c{STC}, \i\c{STD}, \i\c{STI}: Set Flags @@ -9531,15 +11895,17 @@ flag, use \c{CMC} (\k{insCMC}). \H{insSTMXCSR} \i\c{STMXCSR}: Store Streaming SIMD Extension Control/Status -\c STMXCSR memory ; 0F,AE,/3 [KATMAI,SSE,SD] +\c STMXCSR m32 ; 0F AE /3 [KATMAI,SSE] + +\c{STMXCSR} stores the contents of the \c{MXCSR} control/status +register to the specified memory location. \c{MXCSR} is used to +enable masked/unmasked exception handling, to set rounding modes, +to set flush-to-zero mode, and to view exception status flags. +The reserved bits in the \c{MXCSR} register are stored as 0s. + +For details of the \c{MXCSR} register, see the Intel processor docs. -\c{STMXCSR} The MXCSR control/status register is used to enable - masked/unmasked exception handling, to set rounding modes, - to set flush-to-zero mode, and to view exception status flags. - Refer to LDMXCSR for a description of the format of MXCSR. - The linear address corresponds to the address of the - least-significant byte of the referenced memory data. - The reserved bits in the MXCSR are stored as zeroes. +See also \c{LDMXCSR} (\k{insLDMXCSR}). \H{insSTOSB} \i\c{STOSB}, \i\c{STOSW}, \i\c{STOSD}: Store Byte to String @@ -9570,12 +11936,17 @@ word in \c{AX} or the doubleword in \c{EAX} instead of the byte in The \c{REP} prefix may be used to repeat the instruction \c{CX} (or \c{ECX} - again, the address size chooses which) times. + \H{insSTR} \i\c{STR}: Store Task Register \c STR r/m16 ; 0F 00 /1 [286,PRIV] \c{STR} stores the segment selector corresponding to the contents of -the Task Register into its operand. +the Task Register into its operand. When the operand size is a 16-bit +register, the upper 16-bits are cleared to 0s. When the destination +operand is a memory location, 16 bits are written regardless of the +operand size. + \H{insSUB} \i\c{SUB}: Subtract Integers @@ -9610,22 +11981,210 @@ sign-extended to the length of the first operand. In these cases, the \c{BYTE} qualifier is necessary to force NASM to generate this form of the instruction. -\H{insSUBPS} \i\c{SUBPS}: Packed Single-FP Subtract -\c SUBPS xmmreg,memory ; 0F,5C,/r [KATMAI,SSE] -\c SUBPS xmmreg,xmmreg ; ?? [KATMAI,SSE] +\H{insSUBPD} \i\c{SUBPD}: Packed Double-Precision FP Subtract -\c{SUBPS}T he SUBPS instruction subtracts the packed SP FP - numbers of both their operands. +\c SUBPD xmm1,xmm2/m128 ; 66 0F 5C /r [WILLAMETTE,SSE2] + +\c{SUBPD} subtracts the packed double-precision FP values of +the source operand from those of the destination operand, and +stores the result in the destination operation. + + +\H{insSUBPS} \i\c{SUBPS}: Packed Single-Precision FP Subtract + +\c SUBPS xmm1,xmm2/m128 ; 0F 5C /r [KATMAI,SSE] + +\c{SUBPS} subtracts the packed single-precision FP values of +the source operand from those of the destination operand, and +stores the result in the destination operation. + + +\H{insSUBSD} \i\c{SUBSD}: Scalar Single-FP Subtract + +\c SUBSD xmm1,xmm2/m128 ; F2 0F 5C /r [WILLAMETTE,SSE2] + +\c{SUBSD} subtracts the low-order double-precision FP value of +the source operand from that of the destination operand, and +stores the result in the destination operation. The high +quadword is unchanged. \H{insSUBSS} \i\c{SUBSS}: Scalar Single-FP Subtract -\c SUBSS xmmreg,memory ; F3,0F,5C, /r [KATMAI,SSE] -\c SUBSS xmmreg,xmmreg ; ?? [KATMAI,SSE] +\c SUBSS xmm1,xmm2/m128 ; F3 0F 5C /r [KATMAI,SSE] + +\c{SUBSS} subtracts the low-order single-precision FP value of +the source operand from that of the destination operand, and +stores the result in the destination operation. The three high +doublewords are unchanged. + + +\H{insSVDC} \i\c{SVDC}: Save Segment Register and Descriptor + +\c SVDC m80,segreg ; 0F 78 /r [486,CYRIX,SMM] + +\c{SVDC} saves a segment register (DS, ES, FS, GS, or SS) and its +descriptor to mem80. + + +\H{insSVLDT} \i\c{SVLDT}: Save LDTR and Descriptor + +\c SVLDT m80 ; 0F 7A /0 [486,CYRIX,SMM] + +\c{SVLDT} saves the Local Descriptor Table (LDTR) to mem80. + + +\H{insSVTS} \i\c{SVTS}: Save TSR and Descriptor + +\c SVTS m80 ; 0F 7C /0 [486,CYRIX,SMM] + +\c{SVTS} saves the Task State Register (TSR) to mem80. + + +\H{insSYSCALL} \i\c{SYSCALL}: Call Operating System + +\c SYSCALL ; 0F 05 [P6,AMD] + +\c{SYSCALL} provides a fast method of transfering control to a fixed +entry point in an operating system. + +\b The \c{EIP} register is copied into the \c{ECX} register. + +\b Bits [31–0] of the 64-bit SYSCALL/SYSRET Target Address Register +(\c{STAR}) are copied into the \c{EIP} register. + +\b Bits [47–32] of the \c{STAR} register specify the selector that is +copied into the \c{CS} register. + +\b Bits [47–32]+1000b of the \c{STAR} register specify the selector that +is copied into the SS register. + +The \c{CS} and \c{SS} registers should not be modified by the operating +system between the execution of the \c{SYSCALL} instruction and its +corresponding \c{SYSRET} instruction. + +For more information, see the \c{SYSCALL and SYSRET Instruction Specification} +(AMD document number 21086.pdf). + + +\H{insSYSENTER} \i\c{SYSENTER}: Fast System Call + +\c SYSENTER ; 0F 34 [P6] + +\c{SYSENTER} executes a fast call to a level 0 system procedure or +routine. Before using this instruction, various MSRs need to be set +up: + +\b \c{SYSENTER_CS_MSR} contains the 32-bit segment selector for the +privilege level 0 code segment. (This value is also used to compute +the segment selector of the privilege level 0 stack segment.) + +\b \c{SYSENTER_EIP_MSR} contains the 32-bit offset into the privilege +level 0 code segment to the first instruction of the selected operating +procedure or routine. + +\b \c{SYSENTER_ESP_MSR} contains the 32-bit stack pointer for the +privilege level 0 stack. + +\c{SYSENTER} performs the following sequence of operations: + +\b Loads the segment selector from the \c{SYSENTER_CS_MSR} into the +\c{CS} register. + +\b Loads the instruction pointer from the \c{SYSENTER_EIP_MSR} into +the \c{EIP} register. + +\b Adds 8 to the value in \c{SYSENTER_CS_MSR} and loads it into the +\c{SS} register. + +\b Loads the stack pointer from the \c{SYSENTER_ESP_MSR} into the +\c{ESP} register. + +\b Switches to privilege level 0. + +\b Clears the \c{VM} flag in the \c{EFLAGS} register, if the flag +is set. + +\b Begins executing the selected system procedure. + +In particular, note that this instruction des not save the values of +\c{CS} or \c{(E)IP}. If you need to return to the calling code, you +need to write your code to cater for this. + +For more information, see the Intel Architecture Software Developer’s +Manual, Volume 2. + -\c{SUBSS} The SUBSS instruction subtracts the lower SP FP - numbers of both their operands. +\H{insSYSEXIT} \i\c{SYSEXIT}: Fast Return From System Call + +\c SYSEXIT ; 0F 35 [P6,PRIV] + +\c{SYSEXIT} executes a fast return to privilege level 3 user code. +This instruction is a companion instruction to the \c{SYSENTER} +instruction, and can only be executed by privelege level 0 code. +Various registers need to be set up before calling this instruction: + +\b \c{SYSENTER_CS_MSR} contains the 32-bit segment selector for the +privilege level 0 code segment in which the processor is currently +executing. (This value is used to compute the segment selectors for +the privilege level 3 code and stack segments.) + +\b \c{EDX} contains the 32-bit offset into the privilege level 3 code +segment to the first instruction to be executed in the user code. + +\b \c{ECX} contains the 32-bit stack pointer for the privilege level 3 +stack. + +\c{SYSEXIT} performs the following sequence of operations: + +\b Adds 16 to the value in \c{SYSENTER_CS_MSR} and loads the sum into +the \c{CS} selector register. + +\b Loads the instruction pointer from the \c{EDX} register into the +\c{EIP} register. + +\b Adds 24 to the value in \c{SYSENTER_CS_MSR} and loads the sum +into the \c{SS} selector register. + +\b Loads the stack pointer from the \c{ECX} register into the \c{ESP} +register. + +\b Switches to privilege level 3. + +\b Begins executing the user code at the \c{EIP} address. + +For more information on the use of the \c{SYSENTER} and \c{SYSEXIT} +instructions, see the Intel Architecture Software Developer’s +Manual, Volume 2. + + +\H{insSYSRET} \i\c{SYSRET}: Return From Operating System + +\c SYSRET ; 0F 07 [P6,AMD,PRIV] + +\c{SYSRET} is the return instruction used in conjunction with the +\c{SYSCALL} instruction to provide fast entry/exit to an operating system. + +\b The \c{ECX} register, which points to the next sequential instruction +after the corresponding \c{SYSCALL} instruction, is copied into the \c{EIP} +register. + +\b Bits [63–48] of the \c{STAR} register specify the selector that is copied +into the \c{CS} register. + +\b Bits [63–48]+1000b of the \c{STAR} register specify the selector that is +copied into the \c{SS} register. + +\b Bits [1–0] of the \c{SS} register are set to 11b (RPL of 3) regardless of +the value of bits [49–48] of the \c{STAR} register. + +The \c{CS} and \c{SS} registers should not be modified by the operating +system between the execution of the \c{SYSCALL} instruction and its +corresponding \c{SYSRET} instruction. + +For more information, see the \c{SYSCALL and SYSRET Instruction Specification} +(AMD document number 21086.pdf). \H{insTEST} \i\c{TEST}: Test Bits (notional bitwise AND) @@ -9634,9 +12193,9 @@ form of the instruction. \c TEST r/m16,reg16 ; o16 85 /r [8086] \c TEST r/m32,reg32 ; o32 85 /r [386] -\c TEST r/m8,imm8 ; F6 /7 ib [8086] -\c TEST r/m16,imm16 ; o16 F7 /7 iw [8086] -\c TEST r/m32,imm32 ; o32 F7 /7 id [386] +\c TEST r/m8,imm8 ; F6 /0 ib [8086] +\c TEST r/m16,imm16 ; o16 F7 /0 iw [8086] +\c TEST r/m32,imm32 ; o32 F7 /0 id [386] \c TEST AL,imm8 ; A8 ib [8086] \c TEST AX,imm16 ; o16 A9 iw [8086] @@ -9646,17 +12205,53 @@ form of the instruction. affects the flags as if the operation had taken place, but does not store the result of the operation anywhere. -\H{insUCOMISS} \i\c{UCOMISS}: Unordered Scalar Single-FP compare - and set EFLAGS -\c UCOMISS xmmreg,memory ; 0F,2E,/r [KATMAI,SSE] -\c UCOMISS xmmreg,xmmreg ; ?? [KATMAI,SSE] +\H{insUCOMISD} \i\c{UCOMISD}: Unordered Scalar Double-Precision FP +compare and set EFLAGS + +\c UCOMISD xmm1,xmm2/m128 ; 66 0F 2E /r [WILLAMETTE,SSE2] + +\c{UCOMISD} compares the low-order double-precision FP numbers in the +two operands, and sets the \c{ZF}, \c{PF} and \c{CF} bits in the +\c{EFLAGS} register. In addition, the \c{OF}, \c{SF} and \c{AF} bits +in the \c{EFLAGS} register are zeroed out. The unordered predicate +(\c{ZF}, \c{PF} and \c{CF} all set) is returned if either source +operand is a \c{NaN} (\c{qNaN} or \c{sNaN}). + + +\H{insUCOMISS} \i\c{UCOMISS}: Unordered Scalar Single-Precision FP +compare and set EFLAGS + +\c UCOMISS xmm1,xmm2/m128 ; 0F 2E /r [KATMAI,SSE] -\c{UCOMISS} The UCOMISS instructions compare the two lowest scalar - SP FP numbers, and set the ZF,PF,CF bits in the EFLAGS register - as described above. In addition, the OF, SF, and AF bits in the - EFLAGS register are zeroed out. The unordered predicate is - returned if either source operand is a NaN (qNaN or sNaN). +\c{UCOMISS} compares the low-order single-precision FP numbers in the +two operands, and sets the \c{ZF}, \c{PF} and \c{CF} bits in the +\c{EFLAGS} register. In addition, the \c{OF}, \c{SF} and \c{AF} bits +in the \c{EFLAGS} register are zeroed out. The unordered predicate +(\c{ZF}, \c{PF} and \c{CF} all set) is returned if either source +operand is a \c{NaN} (\c{qNaN} or \c{sNaN}). + + +\H{insUD2} \i\c{UD0}, \i\c{UD1}, \i\c{UD2}: Undefined Instruction + +\c UD0 ; 0F FF [186,UNDOC] +\c UD1 ; 0F B9 [186,UNDOC] +\c UD2 ; 0F 0B [186] + +\c{UDx} can be used to generate an invalid opcode exception, for testing +purposes. + +\c{UD0} is specifically documented by AMD as being reserved for this +purpose. + +\c{UD1} is specifically documented by Intel as being reserved for this +purpose. + +\c{UD2} is mentioned by Intel as being available, but is not mentioned +as reserved. + +All these opcodes can be used to generate invalid opcode exceptions on +all processors that are available at the current time. \H{insUMOV} \i\c{UMOV}: User Move Data @@ -9674,25 +12269,72 @@ access user memory (as opposed to host memory). It is used just like an ordinary memory/register or register/register \c{MOV} instruction, but accesses user space. +This instruction is only available on some AMD and IBM 386 and 486 +processors. + -\H{insUNPCKHPS} \i\c{UNPCKHPS}: Unpack High Packed Single-FP Data +\H{insUNPCKHPD} \i\c{UNPCKHPD}: Unpack and Interleave High Packed +Double-Precision FP Values -\c UNPCKHPS xmmreg,memory ; 0F,15,/r [KATMAI,SSE] -\c UNPCKHPS xmmreg,xmmreg ; ?? [KATMAI,SSE] +\c UNPCKHPD xmm1,xmm2/m128 ; 66 0F 15 /r [WILLAMETTE,SSE2] -\c{UNPCKHPS} The UNPCKHPS instruction performs an interleaved - unpack of the high-order data elements of XMM1 and XMM2/Mem. - It ignores the lower half of the sources. +\c{UNPCKHPD} performs an interleaved unpack of the high-order data +elements of the source and destination operands, saving the result +in \c{xmm1}. It ignores the lower half of the sources. +The operation of this instruction is: -\H{insUNPCKLPS} \i\c{UNPCKLPS}: Unpack Low Packed Single-FP Data +\c dst[63-0] := dst[127-64]; +\c dst[127-64] := src[127-64]. -\c UNPCKLPS xmmreg,memory ; 0F,14,/r [KATMAI,SSE] -\c UNPCKLPS xmmreg,xmmreg ; ?? [KATMAI,SSE] -\c{UNPCKLPS} The UNPCKLPS instruction performs an interleaved - unpack of the low-order data elements of XMM1 and XMM2/Mem. - It ignores the upper half part of the sources. +\H{insUNPCKHPS} \i\c{UNPCKHPS}: Unpack and Interleave High Packed +Single-Precision FP Values + +\c UNPCKHPS xmm1,xmm2/m128 ; 0F 15 /r [KATMAI,SSE] + +\c{UNPCKHPS} performs an interleaved unpack of the high-order data +elements of the source and destination operands, saving the result +in \c{xmm1}. It ignores the lower half of the sources. + +The operation of this instruction is: + +\c dst[31-0] := dst[95-64]; +\c dst[63-32] := src[95-64]; +\c dst[95-64] := dst[127-96]; +\c dst[127-96] := src[127-96]. + + +\H{insUNPCKLPD} \i\c{UNPCKLPD}: Unpack and Interleave Low Packed +Double-Precision FP Data + +\c UNPCKLPD xmm1,xmm2/m128 ; 66 0F 14 /r [WILLAMETTE,SSE2] + +\c{UNPCKLPD} performs an interleaved unpack of the low-order data +elements of the source and destination operands, saving the result +in \c{xmm1}. It ignores the lower half of the sources. + +The operation of this instruction is: + +\c dst[63-0] := dst[63-0]; +\c dst[127-64] := src[63-0]. + + +\H{insUNPCKLPS} \i\c{UNPCKLPS}: Unpack and Interleave Low Packed +Single-Precision FP Data + +\c UNPCKLPS xmm1,xmm2/m128 ; 0F 14 /r [KATMAI,SSE] + +\c{UNPCKLPS} performs an interleaved unpack of the low-order data +elements of the source and destination operands, saving the result +in \c{xmm1}. It ignores the lower half of the sources. + +The operation of this instruction is: + +\c dst[31-0] := dst[31-0]; +\c dst[63-32] := src[31-0]; +\c dst[95-64] := dst[63-32]; +\c dst[127-96] := src[63-32]. \H{insVERR} \i\c{VERR}, \i\c{VERW}: Verify Segment Readability/Writability @@ -9701,13 +12343,17 @@ instruction, but accesses user space. \c VERW r/m16 ; 0F 00 /5 [286,PRIV] -\c{VERR} sets the zero flag if the segment specified by the selector +\b \c{VERR} sets the zero flag if the segment specified by the selector in its operand can be read from at the current privilege level. -\c{VERW} sets the zero flag if the segment can be written. +Otherwise it is cleared. + +\b \c{VERW} sets the zero flag if the segment can be written. + \H{insWAIT} \i\c{WAIT}: Wait for Floating-Point Processor \c WAIT ; 9B [8086] +\c FWAIT ; 9B [8086] \c{WAIT}, on 8086 systems with a separate 8087 FPU, waits for the FPU to have finished any operation it is engaged in before @@ -9719,6 +12365,7 @@ On higher processors, \c{WAIT} is unnecessary for this purpose, and it has the alternative purpose of ensuring that any pending unmasked FPU exceptions have happened before execution continues. + \H{insWBINVD} \i\c{WBINVD}: Write Back and Invalidate Cache \c WBINVD ; 0F 09 [486] @@ -9729,13 +12376,25 @@ It writes the contents of the caches back to memory first, so no data is lost. To flush the caches quickly without bothering to write the data back first, use \c{INVD} (\k{insINVD}). + \H{insWRMSR} \i\c{WRMSR}: Write Model-Specific Registers \c WRMSR ; 0F 30 [PENT] \c{WRMSR} writes the value in \c{EDX:EAX} to the processor -Model-Specific Register (MSR) whose index is stored in \c{ECX}. See -also \c{RDMSR} (\k{insRDMSR}). +Model-Specific Register (MSR) whose index is stored in \c{ECX}. +See also \c{RDMSR} (\k{insRDMSR}). + + +\H{insWRSHR} \i\c{WRSHR}: Write SMM Header Pointer Register + +\c WRSHR r/m32 ; 0F 37 /0 [386,CYRIX,SMM] + +\c{WRSHR} loads the contents of either a 32-bit memory location or a +32-bit register into the SMM header pointer register. + +See also \c{RDSHR} (\k{insRDSHR}). + \H{insXADD} \i\c{XADD}: Exchange and Add @@ -9748,17 +12407,30 @@ them together and writes the result into the destination (first) operand. This instruction can be used with a \c{LOCK} prefix for multi-processor synchronisation purposes. + \H{insXBTS} \i\c{XBTS}: Extract Bit String \c XBTS reg16,r/m16 ; o16 0F A6 /r [386,UNDOC] \c XBTS reg32,r/m32 ; o32 0F A6 /r [386,UNDOC] -No clear documentation seems to be available for this instruction: -the best I've been able to find reads `Takes a string of bits from -the first operand and puts them in the second operand'. It is -present only in early 386 processors, and conflicts with the opcodes -for \c{CMPXCHG486}. NASM supports it only for completeness. Its -counterpart is \c{IBTS} (see \k{insIBTS}). +The implied operation of this instruction is: + +\c XBTS r/m16,reg16,AX,CL +\c XBTS r/m32,reg32,EAX,CL + +Writes a bit string from the source operand to the destination. \c{CL} +indicates the number of bits to be copied, and \c{(E)AX} indicates the +low order bit offset in the source. The bist are written to the low +order bits of the destination register. For example, if \c{CL} is set +to 4 and \c{AX} (for 16-bit code) is set to 5, bits 5-8 of \c{src} will +be copied to bits 0-3 of \c{dst}. This instruction is very poorly +documented, and I have been unable to find any official source of +documentation on it. + +\c{XBTS} is supported only on the early Intel 386s, and conflicts with +the opcodes for \c{CMPXCHG486} (on early Intel 486s). NASM supports it +only for completeness. Its counterpart is \c{IBTS} (see \k{insIBTS}). + \H{insXCHG} \i\c{XCHG}: Exchange @@ -9783,8 +12455,10 @@ synchronisation. setting) generates the opcode \c{90h}, and so is a synonym for \c{NOP} (\k{insNOP}). + \H{insXLATB} \i\c{XLATB}: Translate Byte in Lookup Table +\c XLAT ; D7 [8086] \c XLATB ; D7 [8086] \c{XLATB} adds the value in \c{AL}, treated as an unsigned byte, to @@ -9800,6 +12474,7 @@ The segment register used to load from \c{[BX+AL]} or \c{[EBX+AL]} can be overridden by using a segment register name as a prefix (for example, \c{es xlatb}). + \H{insXOR} \i\c{XOR}: Bitwise Exclusive OR \c XOR r/m8,reg8 ; 30 /r [8086] @@ -9832,14 +12507,23 @@ sign-extended to the length of the first operand. In these cases, the \c{BYTE} qualifier is necessary to force NASM to generate this form of the instruction. -The MMX instruction \c{PXOR} (see \k{insPXOR}) performs the same -operation on the 64-bit MMX registers. +The \c{MMX} instruction \c{PXOR} (see \k{insPXOR}) performs the same +operation on the 64-bit \c{MMX} registers. + + +\H{insXORPD} \i\c{XORPD}: Bitwise Logical XOR of Double-Precision FP Values + +\c XORPD xmm1,xmm2/m128 ; 66 0F 57 /r [WILLAMETTE,SSE2] + +\c{XORPD} returns a bit-wise logical XOR between the source and +destination operands, storing the result in the destination operand. + + +\H{insXORPS} \i\c{XORPS}: Bitwise Logical XOR of Single-Precision FP Values +\c XORPS xmm1,xmm2/m128 ; 0F 57 /r [KATMAI,SSE] -\H{insXORPS} \i\c{XORPS}: Bit-wise Logical Xor for Single-FP Data +\c{XORPS} returns a bit-wise logical XOR between the source and +destination operands, storing the result in the destination operand. -\c XORPS xmmreg,memory ; 0F,57,/r [KATMAI,SSE] -\c XORPS xmmreg,xmmreg ; ?? [KATMAI,SSE] -\c{XORPS} The XORPS instruction returns a bit-wise logical XOR - between XMM1 and XMM2/Mem. @@ -13,7 +13,7 @@ #define NASM_MAJOR_VER 0 #define NASM_MINOR_VER 98 -#define NASM_VER "0.98.23" +#define NASM_VER "0.98.24" #ifndef NULL #define NULL 0 |