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author | H. Peter Anvin <hpa@linux.intel.com> | 2018-02-07 11:16:20 -0800 |
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committer | H. Peter Anvin <hpa@linux.intel.com> | 2018-02-07 11:16:20 -0800 |
commit | f53c9778cdb45c4ad5f2d5eb3b4b2a5df7d12df2 (patch) | |
tree | 1ad29c9cf3379f008261e333352f91e4d7663c90 | |
parent | 22d3a2b6015b54d45d3ff5c0359754df0e947b06 (diff) | |
download | nasm-f53c9778cdb45c4ad5f2d5eb3b4b2a5df7d12df2.tar.gz |
doc: add a bit more text about 64-bit immediates and pointers
There are some gotchas in how immediates and pointers are loaded in
64-bit mode and how they interact with optimization. Document those
cases.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
-rw-r--r-- | doc/nasmdoc.src | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/doc/nasmdoc.src b/doc/nasmdoc.src index f998cc60..35e48001 100644 --- a/doc/nasmdoc.src +++ b/doc/nasmdoc.src @@ -1,6 +1,6 @@ \# -------------------------------------------------------------------------- \# -\# Copyright 1996-2017 The NASM Authors - All Rights Reserved +\# Copyright 1996-2018 The NASM Authors - All Rights Reserved \# See the file AUTHORS included with the NASM distribution for \# the specific copyright holders. \# @@ -7755,6 +7755,24 @@ immediate as \c{DWORD}: The length of these instructions are 10, 5 and 7 bytes, respectively. +If optimization is enabled and NASM can determine at assembly time +that a shorter instruction will suffice, the shorter instruction will +be emitted unless of course \c{STRICT QWORD} or \c{STRICT DWORD} is +specified (see \k{strict}): + +\c mov rax,1 ; Assembles as "mov eax,1" (5 bytes) +\c mov rax,strict qword 1 ; Full 10-byte instruction +\c mov rax,strict dword 1 ; 7-byte instruction +\c mov rax,symbol ; 10 bytes, not known at assembly time +\c lea rax,[rel symbol] ; 7 bytes, usually preferred by the ABI + +Note that \c{lea rax,[rel symbol]} is position-independent, whereas +\c{mov rax,symbol} is not. Most ABIs prefer or even require +position-independent code in 64-bit mode. However, the \c{MOV} +instruction is able to reference a symbol anywhere in the 64-bit +address space, whereas \c{LEA} is only able to access a symbol within +within 2 GB of the instruction itself (see below.) + The only instructions which take a full \I{64-bit displacement}64-bit \e{displacement} is loading or storing, using \c{MOV}, \c{AL}, \c{AX}, \c{EAX} or \c{RAX} (but no other registers) to an absolute 64-bit address. |