diff options
| author | Keith Kanios <keith@kanios.net> | 2009-07-07 23:21:15 -0500 |
|---|---|---|
| committer | Keith Kanios <keith@kanios.net> | 2009-07-07 23:21:15 -0500 |
| commit | da1cba1023f10224ad41cde39a5bf158667af5da (patch) | |
| tree | f8eaffbfa45a399c646d3b14a08be83d5f17fa48 | |
| parent | 8b36baa5b6fb5108bf7ca30138a6aaf08e271879 (diff) | |
| download | nasm-da1cba1023f10224ad41cde39a5bf158667af5da.tar.gz | |
Push to synchronize macho64 branch with latest master/2.07 source
186 files changed, 8608 insertions, 15121 deletions
@@ -7,6 +7,7 @@ N: Name Here E: Email Here D: Description Here D: Additional Description Here.... and so on +C: Copyright information Such is life. -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= @@ -51,7 +52,8 @@ D: RDOFF support N: H. Peter Anvin E: hpa@zytor.com -D: Organized 0.98 release and Linux binaries; new CVS tree. +D: Primary maintainer for the 0.98, late 0.98.x and 2.x releases. +C: Contributions since 2008-12-15 are Copyright Intel Corporation. N: John Fine E: johnfine@earthlink.net @@ -129,3 +131,7 @@ D: Website Maintenance @ http://nasm.sourceforge.net/ N: Chuck Crayne E: ccrayne@users.sourceforge.net D: elf64 (x86_64) output format + +N: Cyrill Gorcunov +E: gorcunov@gmail.com +D: AMD XOP/FMA4/CVT16 instructions diff --git a/COPYING b/COPYING deleted file mode 100644 index 5ab7695a..00000000 --- a/COPYING +++ /dev/null @@ -1,504 +0,0 @@ - GNU LESSER GENERAL PUBLIC LICENSE - Version 2.1, February 1999 - - Copyright (C) 1991, 1999 Free Software Foundation, Inc. - 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - -[This is the first released version of the Lesser GPL. It also counts - as the successor of the GNU Library Public License, version 2, hence - the version number 2.1.] - - Preamble - - The licenses for most software are designed to take away your -freedom to share and change it. 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See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - -Also add information on how to contact you by electronic and paper mail. - -You should also get your employer (if you work as a programmer) or your -school, if any, to sign a "copyright disclaimer" for the library, if -necessary. Here is a sample; alter the names: - - Yoyodyne, Inc., hereby disclaims all copyright interest in the - library `Frob' (a library for tweaking knobs) written by James Random Hacker. - - <signature of Ty Coon>, 1 April 1990 - Ty Coon, President of Vice - -That's all there is to it! - - @@ -1,4 +1,29 @@ -NASM is licensed under the GNU Lesser General Public License (LGPL). +NASM is now licensed under the 2-clause BSD license, also known as the +simplified BSD license. -Please read the "COPYING" file in the archive root, or visit -http://www.gnu.org/licenses/lgpl.html, for information about the LGPL. + Copyright 1996-2009 the NASM Authors - All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following + conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials provided + with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/Makefile.in b/Makefile.in index de13adcc..92f91925 100644 --- a/Makefile.in +++ b/Makefile.in @@ -59,20 +59,20 @@ X = @EXEEXT@ $(NROFF) -man $< > $@ #-- Begin File Lists --# -NASM = nasm.$(O) nasmlib.$(O) raa.$(O) saa.$(O) \ +NASM = nasm.$(O) nasmlib.$(O) ver.$(O) \ + raa.$(O) saa.$(O) rbtree.$(O) \ float.$(O) insnsa.$(O) insnsb.$(O) \ assemble.$(O) labels.$(O) hashtbl.$(O) crc64.$(O) parser.$(O) \ - outform.$(O) output/outbin.$(O) \ - output/outaout.$(O) output/outcoff.$(O) \ - output/outelf32.$(O) output/outelf64.$(O) \ + output/outform.$(O) output/outlib.$(O) output/nulldbg.$(O) \ + output/outbin.$(O) output/outaout.$(O) output/outcoff.$(O) \ + output/outelf.$(O) output/outelf32.$(O) output/outelf64.$(O) \ output/outobj.$(O) output/outas86.$(O) output/outrdf2.$(O) \ - output/outdbg.$(O) output/outieee.$(O) \ - output/outmacho32.$(O) output/outmacho64.$(O) \ + output/outdbg.$(O) output/outieee.$(O) output/outmacho.$(O) \ preproc.$(O) quote.$(O) pptok.$(O) macros.$(O) \ listing.$(O) eval.$(O) exprlib.$(O) stdscan.$(O) strfunc.$(O) \ tokhash.$(O) regvals.$(O) regflags.$(O) -NDISASM = ndisasm.$(O) disasm.$(O) sync.$(O) nasmlib.$(O) \ +NDISASM = ndisasm.$(O) disasm.$(O) sync.$(O) nasmlib.$(O) ver.$(O) \ insnsd.$(O) insnsb.$(O) insnsn.$(O) regs.$(O) regdis.$(O) #-- End File Lists --# @@ -111,6 +111,8 @@ version.sed: version version.pl $(PERL) $(srcdir)/version.pl sed < $(srcdir)/version > version.sed version.mak: version version.pl $(PERL) $(srcdir)/version.pl make < $(srcdir)/version > version.mak +version.nsh: version version.pl + $(PERL) $(srcdir)/version.pl nsis < $(srcdir)/version > version.nsh # This source file is generated from the standard macros file # `standard.mac' by another Perl script. Again, it's part of the @@ -158,7 +160,7 @@ pptok.ph: pptok.dat pptok.pl perllib/phash.ph PERLREQ = macros.c insnsb.c insnsa.c insnsd.c insnsi.h insnsn.c \ regs.c regs.h regflags.c regdis.c regdis.h regvals.c \ tokhash.c tokens.h pptok.h pptok.c pptok.ph \ - version.h version.mac version.mak + version.h version.mac version.mak version.nsh perlreq: $(PERLREQ) install: nasm$(X) ndisasm$(X) @@ -243,93 +245,106 @@ alldeps: perlreq # @path-separator: "/" #-- Everything below is generated by mkdep.pl - do not edit --# assemble.$(O): assemble.c assemble.h compiler.h config.h insns.h insnsi.h \ - nasm.h nasmlib.h pptok.h preproc.h regs.h tables.h tokens.h version.h + nasm.h nasmlib.h pptok.h preproc.h regs.h tables.h tokens.h crc64.$(O): crc64.c compiler.h config.h nasmlib.h disasm.$(O): disasm.c compiler.h config.h disasm.h insns.h insnsi.h nasm.h \ - nasmlib.h pptok.h preproc.h regdis.h regs.h sync.h tables.h tokens.h \ - version.h + nasmlib.h pptok.h preproc.h regdis.h regs.h sync.h tables.h tokens.h eval.$(O): eval.c compiler.h config.h eval.h float.h insnsi.h labels.h \ - nasm.h nasmlib.h pptok.h preproc.h regs.h version.h + nasm.h nasmlib.h pptok.h preproc.h regs.h exprlib.$(O): exprlib.c compiler.h config.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h regs.h version.h + pptok.h preproc.h regs.h float.$(O): float.c compiler.h config.h float.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h regs.h version.h + pptok.h preproc.h regs.h hashtbl.$(O): hashtbl.c compiler.h config.h hashtbl.h insnsi.h nasm.h \ - nasmlib.h pptok.h preproc.h regs.h version.h + nasmlib.h pptok.h preproc.h regs.h insnsa.$(O): insnsa.c compiler.h config.h insns.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h regs.h tokens.h version.h + pptok.h preproc.h regs.h tokens.h insnsb.$(O): insnsb.c compiler.h config.h insns.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h regs.h tokens.h version.h + pptok.h preproc.h regs.h tokens.h insnsd.$(O): insnsd.c compiler.h config.h insns.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h regs.h tokens.h version.h + pptok.h preproc.h regs.h tokens.h insnsn.$(O): insnsn.c compiler.h config.h insnsi.h tables.h labels.$(O): labels.c compiler.h config.h hashtbl.h insnsi.h nasm.h \ - nasmlib.h pptok.h preproc.h regs.h version.h + nasmlib.h pptok.h preproc.h regs.h lib/snprintf.$(O): lib/snprintf.c compiler.h config.h nasmlib.h lib/vsnprintf.$(O): lib/vsnprintf.c compiler.h config.h nasmlib.h listing.$(O): listing.c compiler.h config.h insnsi.h listing.h nasm.h \ - nasmlib.h pptok.h preproc.h regs.h version.h + nasmlib.h pptok.h preproc.h regs.h macros.$(O): macros.c compiler.h config.h hashtbl.h insnsi.h nasm.h \ - nasmlib.h outform.h pptok.h preproc.h regs.h tables.h version.h + nasmlib.h output/outform.h pptok.h preproc.h regs.h tables.h nasm.$(O): nasm.c assemble.h compiler.h config.h eval.h float.h insns.h \ - insnsi.h labels.h listing.h nasm.h nasmlib.h outform.h parser.h pptok.h \ - preproc.h raa.h regs.h saa.h stdscan.h tokens.h version.h + insnsi.h labels.h listing.h nasm.h nasmlib.h output/outform.h parser.h \ + pptok.h preproc.h raa.h regs.h saa.h stdscan.h tokens.h nasmlib.$(O): nasmlib.c compiler.h config.h insns.h insnsi.h nasm.h \ - nasmlib.h pptok.h preproc.h regs.h tokens.h version.h + nasmlib.h pptok.h preproc.h regs.h tokens.h ndisasm.$(O): ndisasm.c compiler.h config.h disasm.h insns.h insnsi.h nasm.h \ - nasmlib.h pptok.h preproc.h regs.h sync.h tokens.h version.h -outform.$(O): outform.c compiler.h config.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h regs.h version.h + nasmlib.h pptok.h preproc.h regs.h sync.h tokens.h +output/nulldbg.$(O): output/nulldbg.c compiler.h config.h insnsi.h nasm.h \ + nasmlib.h pptok.h preproc.h regs.h output/outaout.$(O): output/outaout.c compiler.h config.h insnsi.h nasm.h \ - nasmlib.h outform.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h \ - version.h + nasmlib.h output/outform.h output/outlib.h pptok.h preproc.h raa.h regs.h \ + saa.h stdscan.h output/outas86.$(O): output/outas86.c compiler.h config.h insnsi.h nasm.h \ - nasmlib.h outform.h pptok.h preproc.h raa.h regs.h saa.h version.h + nasmlib.h output/outform.h output/outlib.h pptok.h preproc.h raa.h regs.h \ + saa.h output/outbin.$(O): output/outbin.c compiler.h config.h eval.h insnsi.h \ - labels.h nasm.h nasmlib.h outform.h pptok.h preproc.h regs.h saa.h \ - stdscan.h version.h + labels.h nasm.h nasmlib.h output/outform.h output/outlib.h pptok.h \ + preproc.h regs.h saa.h stdscan.h output/outcoff.$(O): output/outcoff.c compiler.h config.h insnsi.h nasm.h \ - nasmlib.h outform.h pptok.h preproc.h raa.h regs.h saa.h version.h + nasmlib.h output/outform.h output/outlib.h pptok.h preproc.h raa.h regs.h \ + saa.h output/outdbg.$(O): output/outdbg.c compiler.h config.h insnsi.h nasm.h \ - nasmlib.h outform.h pptok.h preproc.h regs.h version.h + nasmlib.h output/outform.h pptok.h preproc.h regs.h +output/outelf.$(O): output/outelf.c compiler.h config.h insnsi.h nasm.h \ + nasmlib.h output/dwarf.h output/elfcommon.h output/outelf.h \ + output/outform.h pptok.h preproc.h regs.h output/outelf32.$(O): output/outelf32.c compiler.h config.h insnsi.h nasm.h \ - nasmlib.h outform.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h \ - version.h + nasmlib.h output/dwarf.h output/elf32.h output/elfcommon.h output/outelf.h \ + output/outform.h output/outlib.h pptok.h preproc.h raa.h rbtree.h regs.h \ + saa.h stdscan.h output/outelf64.$(O): output/outelf64.c compiler.h config.h insnsi.h nasm.h \ - nasmlib.h outform.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h \ - version.h + nasmlib.h output/dwarf.h output/elf64.h output/elfcommon.h output/outelf.h \ + output/outform.h output/outlib.h pptok.h preproc.h raa.h rbtree.h regs.h \ + saa.h stdscan.h +output/outform.$(O): output/outform.c compiler.h config.h insnsi.h nasm.h \ + nasmlib.h output/outform.h pptok.h preproc.h regs.h output/outieee.$(O): output/outieee.c compiler.h config.h insnsi.h nasm.h \ - nasmlib.h outform.h pptok.h preproc.h regs.h version.h -output/outmacho32.$(O): output/outmacho32.c compiler.h config.h insnsi.h \ - nasm.h nasmlib.h outform.h pptok.h preproc.h raa.h regs.h saa.h version.h -output/outmacho64.$(O): output/outmacho64.c compiler.h config.h insnsi.h \ - nasm.h nasmlib.h outform.h pptok.h preproc.h raa.h regs.h saa.h version.h + nasmlib.h output/outform.h output/outlib.h pptok.h preproc.h regs.h +output/outlib.$(O): output/outlib.c compiler.h config.h insnsi.h nasm.h \ + nasmlib.h output/outlib.h pptok.h preproc.h regs.h +output/outmacho.$(O): output/outmacho.c compiler.h config.h insnsi.h nasm.h \ + nasmlib.h output/outform.h output/outlib.h pptok.h preproc.h raa.h regs.h \ + saa.h output/outobj.$(O): output/outobj.c compiler.h config.h insnsi.h nasm.h \ - nasmlib.h outform.h pptok.h preproc.h regs.h stdscan.h version.h + nasmlib.h output/outform.h output/outlib.h pptok.h preproc.h regs.h \ + stdscan.h output/outrdf.$(O): output/outrdf.c compiler.h config.h insnsi.h nasm.h \ - nasmlib.h outform.h pptok.h preproc.h regs.h version.h + nasmlib.h output/outform.h pptok.h preproc.h regs.h output/outrdf2.$(O): output/outrdf2.c compiler.h config.h insnsi.h nasm.h \ - nasmlib.h outform.h pptok.h preproc.h rdoff/rdoff.h regs.h saa.h version.h + nasmlib.h output/outform.h output/outlib.h pptok.h preproc.h rdoff/rdoff.h \ + regs.h saa.h +owtest.$(O): owtest.c parser.$(O): parser.c compiler.h config.h float.h insns.h insnsi.h nasm.h \ - nasmlib.h parser.h pptok.h preproc.h regs.h stdscan.h tables.h tokens.h \ - version.h + nasmlib.h parser.h pptok.h preproc.h regs.h stdscan.h tables.h tokens.h pptok.$(O): pptok.c compiler.h config.h hashtbl.h nasmlib.h pptok.h \ preproc.h preproc.$(O): preproc.c compiler.h config.h hashtbl.h insnsi.h nasm.h \ - nasmlib.h pptok.h preproc.h quote.h regs.h stdscan.h tables.h tokens.h \ - version.h + nasmlib.h pptok.h preproc.h quote.h regs.h stdscan.h tables.h tokens.h quote.$(O): quote.c compiler.h config.h nasmlib.h quote.h raa.$(O): raa.c compiler.h config.h nasmlib.h raa.h +rbtree.$(O): rbtree.c compiler.h config.h rbtree.h regdis.$(O): regdis.c regdis.h regs.h regflags.$(O): regflags.c compiler.h config.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h regs.h tables.h version.h + pptok.h preproc.h regs.h tables.h regs.$(O): regs.c compiler.h config.h insnsi.h tables.h regvals.$(O): regvals.c compiler.h config.h insnsi.h tables.h saa.$(O): saa.c compiler.h config.h nasmlib.h saa.h stdscan.$(O): stdscan.c compiler.h config.h insns.h insnsi.h nasm.h \ - nasmlib.h pptok.h preproc.h quote.h regs.h stdscan.h tokens.h version.h + nasmlib.h pptok.h preproc.h quote.h regs.h stdscan.h tokens.h strfunc.$(O): strfunc.c compiler.h config.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h regs.h version.h + pptok.h preproc.h regs.h sync.$(O): sync.c compiler.h config.h nasmlib.h sync.h tokhash.$(O): tokhash.c compiler.h config.h hashtbl.h insns.h insnsi.h \ - nasm.h nasmlib.h pptok.h preproc.h regs.h tokens.h version.h + nasm.h nasmlib.h pptok.h preproc.h regs.h tokens.h +ver.$(O): ver.c compiler.h config.h insnsi.h nasm.h nasmlib.h pptok.h \ + preproc.h regs.h version.h diff --git a/Mkfiles/msvc.mak b/Mkfiles/msvc.mak index 6e57e420..8dcb5daf 100644 --- a/Mkfiles/msvc.mak +++ b/Mkfiles/msvc.mak @@ -34,20 +34,20 @@ X = .exe #-- Begin File Lists --# # Edit in Makefile.in, not here! -NASM = nasm.$(O) nasmlib.$(O) raa.$(O) saa.$(O) \ +NASM = nasm.$(O) nasmlib.$(O) ver.$(O) \ + raa.$(O) saa.$(O) rbtree.$(O) \ float.$(O) insnsa.$(O) insnsb.$(O) \ assemble.$(O) labels.$(O) hashtbl.$(O) crc64.$(O) parser.$(O) \ - outform.$(O) output/outbin.$(O) \ - output/outaout.$(O) output/outcoff.$(O) \ - output/outelf32.$(O) output/outelf64.$(O) \ + output/outform.$(O) output/outlib.$(O) output/nulldbg.$(O) \ + output/outbin.$(O) output/outaout.$(O) output/outcoff.$(O) \ + output/outelf.$(O) output/outelf32.$(O) output/outelf64.$(O) \ output/outobj.$(O) output/outas86.$(O) output/outrdf2.$(O) \ - output/outdbg.$(O) output/outieee.$(O) \ - output/outmacho32.$(O) output/outmacho64.$(O) \ + output/outdbg.$(O) output/outieee.$(O) output/outmacho.$(O) \ preproc.$(O) quote.$(O) pptok.$(O) macros.$(O) \ listing.$(O) eval.$(O) exprlib.$(O) stdscan.$(O) strfunc.$(O) \ tokhash.$(O) regvals.$(O) regflags.$(O) -NDISASM = ndisasm.$(O) disasm.$(O) sync.$(O) nasmlib.$(O) \ +NDISASM = ndisasm.$(O) disasm.$(O) sync.$(O) nasmlib.$(O) ver.$(O) \ insnsd.$(O) insnsb.$(O) insnsn.$(O) regs.$(O) regdis.$(O) #-- End File Lists --# @@ -183,86 +183,101 @@ everything: all doc rdf # @exclude: "config.h" #-- Everything below is generated by mkdep.pl - do not edit --# assemble.$(O): assemble.c assemble.h compiler.h insns.h insnsi.h nasm.h \ - nasmlib.h pptok.h preproc.h regs.h tables.h tokens.h version.h + nasmlib.h pptok.h preproc.h regs.h tables.h tokens.h crc64.$(O): crc64.c compiler.h nasmlib.h disasm.$(O): disasm.c compiler.h disasm.h insns.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h regdis.h regs.h sync.h tables.h tokens.h version.h + pptok.h preproc.h regdis.h regs.h sync.h tables.h tokens.h eval.$(O): eval.c compiler.h eval.h float.h insnsi.h labels.h nasm.h \ - nasmlib.h pptok.h preproc.h regs.h version.h + nasmlib.h pptok.h preproc.h regs.h exprlib.$(O): exprlib.c compiler.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h regs.h version.h + preproc.h regs.h float.$(O): float.c compiler.h float.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h regs.h version.h + preproc.h regs.h hashtbl.$(O): hashtbl.c compiler.h hashtbl.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h regs.h version.h + pptok.h preproc.h regs.h insnsa.$(O): insnsa.c compiler.h insns.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h regs.h tokens.h version.h + preproc.h regs.h tokens.h insnsb.$(O): insnsb.c compiler.h insns.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h regs.h tokens.h version.h + preproc.h regs.h tokens.h insnsd.$(O): insnsd.c compiler.h insns.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h regs.h tokens.h version.h + preproc.h regs.h tokens.h insnsn.$(O): insnsn.c compiler.h insnsi.h tables.h labels.$(O): labels.c compiler.h hashtbl.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h regs.h version.h + preproc.h regs.h lib/snprintf.$(O): lib/snprintf.c compiler.h nasmlib.h lib/vsnprintf.$(O): lib/vsnprintf.c compiler.h nasmlib.h listing.$(O): listing.c compiler.h insnsi.h listing.h nasm.h nasmlib.h \ - pptok.h preproc.h regs.h version.h + pptok.h preproc.h regs.h macros.$(O): macros.c compiler.h hashtbl.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h regs.h tables.h version.h + output/outform.h pptok.h preproc.h regs.h tables.h nasm.$(O): nasm.c assemble.h compiler.h eval.h float.h insns.h insnsi.h \ - labels.h listing.h nasm.h nasmlib.h outform.h parser.h pptok.h preproc.h \ - raa.h regs.h saa.h stdscan.h tokens.h version.h + labels.h listing.h nasm.h nasmlib.h output/outform.h parser.h pptok.h \ + preproc.h raa.h regs.h saa.h stdscan.h tokens.h nasmlib.$(O): nasmlib.c compiler.h insns.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h regs.h tokens.h version.h + preproc.h regs.h tokens.h ndisasm.$(O): ndisasm.c compiler.h disasm.h insns.h insnsi.h nasm.h \ - nasmlib.h pptok.h preproc.h regs.h sync.h tokens.h version.h -outform.$(O): outform.c compiler.h insnsi.h nasm.h nasmlib.h outform.h \ - pptok.h preproc.h regs.h version.h + nasmlib.h pptok.h preproc.h regs.h sync.h tokens.h +output/nulldbg.$(O): output/nulldbg.c compiler.h insnsi.h nasm.h nasmlib.h \ + pptok.h preproc.h regs.h output/outaout.$(O): output/outaout.c compiler.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h version.h + output/outform.h output/outlib.h pptok.h preproc.h raa.h regs.h saa.h \ + stdscan.h output/outas86.$(O): output/outas86.c compiler.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h raa.h regs.h saa.h version.h + output/outform.h output/outlib.h pptok.h preproc.h raa.h regs.h saa.h output/outbin.$(O): output/outbin.c compiler.h eval.h insnsi.h labels.h \ - nasm.h nasmlib.h outform.h pptok.h preproc.h regs.h saa.h stdscan.h \ - version.h + nasm.h nasmlib.h output/outform.h output/outlib.h pptok.h preproc.h regs.h \ + saa.h stdscan.h output/outcoff.$(O): output/outcoff.c compiler.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h raa.h regs.h saa.h version.h + output/outform.h output/outlib.h pptok.h preproc.h raa.h regs.h saa.h output/outdbg.$(O): output/outdbg.c compiler.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h regs.h version.h + output/outform.h pptok.h preproc.h regs.h +output/outelf.$(O): output/outelf.c compiler.h insnsi.h nasm.h nasmlib.h \ + output/dwarf.h output/elfcommon.h output/outelf.h output/outform.h pptok.h \ + preproc.h regs.h output/outelf32.$(O): output/outelf32.c compiler.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h version.h + output/dwarf.h output/elf32.h output/elfcommon.h output/outelf.h \ + output/outform.h output/outlib.h pptok.h preproc.h raa.h rbtree.h regs.h \ + saa.h stdscan.h output/outelf64.$(O): output/outelf64.c compiler.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h version.h + output/dwarf.h output/elf64.h output/elfcommon.h output/outelf.h \ + output/outform.h output/outlib.h pptok.h preproc.h raa.h rbtree.h regs.h \ + saa.h stdscan.h +output/outform.$(O): output/outform.c compiler.h insnsi.h nasm.h nasmlib.h \ + output/outform.h pptok.h preproc.h regs.h output/outieee.$(O): output/outieee.c compiler.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h regs.h version.h -output/outmacho32.$(O): output/outmacho32.c compiler.h insnsi.h nasm.h \ - nasmlib.h outform.h pptok.h preproc.h raa.h regs.h saa.h version.h -output/outmacho64.$(O): output/outmacho64.c compiler.h insnsi.h nasm.h \ - nasmlib.h outform.h pptok.h preproc.h raa.h regs.h saa.h version.h + output/outform.h output/outlib.h pptok.h preproc.h regs.h +output/outlib.$(O): output/outlib.c compiler.h insnsi.h nasm.h nasmlib.h \ + output/outlib.h pptok.h preproc.h regs.h +output/outmacho.$(O): output/outmacho.c compiler.h insnsi.h nasm.h nasmlib.h \ + output/outform.h output/outlib.h pptok.h preproc.h raa.h regs.h saa.h output/outobj.$(O): output/outobj.c compiler.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h regs.h stdscan.h version.h + output/outform.h output/outlib.h pptok.h preproc.h regs.h stdscan.h output/outrdf.$(O): output/outrdf.c compiler.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h regs.h version.h + output/outform.h pptok.h preproc.h regs.h output/outrdf2.$(O): output/outrdf2.c compiler.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h rdoff/rdoff.h regs.h saa.h version.h + output/outform.h output/outlib.h pptok.h preproc.h rdoff/rdoff.h regs.h \ + saa.h +owtest.$(O): owtest.c parser.$(O): parser.c compiler.h float.h insns.h insnsi.h nasm.h nasmlib.h \ - parser.h pptok.h preproc.h regs.h stdscan.h tables.h tokens.h version.h + parser.h pptok.h preproc.h regs.h stdscan.h tables.h tokens.h pptok.$(O): pptok.c compiler.h hashtbl.h nasmlib.h pptok.h preproc.h preproc.$(O): preproc.c compiler.h hashtbl.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h quote.h regs.h stdscan.h tables.h tokens.h version.h + pptok.h preproc.h quote.h regs.h stdscan.h tables.h tokens.h quote.$(O): quote.c compiler.h nasmlib.h quote.h raa.$(O): raa.c compiler.h nasmlib.h raa.h +rbtree.$(O): rbtree.c compiler.h rbtree.h regdis.$(O): regdis.c regdis.h regs.h regflags.$(O): regflags.c compiler.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h regs.h tables.h version.h + preproc.h regs.h tables.h regs.$(O): regs.c compiler.h insnsi.h tables.h regvals.$(O): regvals.c compiler.h insnsi.h tables.h saa.$(O): saa.c compiler.h nasmlib.h saa.h stdscan.$(O): stdscan.c compiler.h insns.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h quote.h regs.h stdscan.h tokens.h version.h + preproc.h quote.h regs.h stdscan.h tokens.h strfunc.$(O): strfunc.c compiler.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h regs.h version.h + preproc.h regs.h sync.$(O): sync.c compiler.h nasmlib.h sync.h tokhash.$(O): tokhash.c compiler.h hashtbl.h insns.h insnsi.h nasm.h \ - nasmlib.h pptok.h preproc.h regs.h tokens.h version.h + nasmlib.h pptok.h preproc.h regs.h tokens.h +ver.$(O): ver.c compiler.h insnsi.h nasm.h nasmlib.h pptok.h preproc.h \ + regs.h version.h diff --git a/Mkfiles/netware.mak b/Mkfiles/netware.mak index 3a01e79f..9309cd52 100644 --- a/Mkfiles/netware.mak +++ b/Mkfiles/netware.mak @@ -3,7 +3,7 @@ PROOT=. OBJDIR=release --include $(OBJDIR)/version.inc +-include $(OBJDIR)/version.mak TARGETS=nasm.nlm ndisasm.nlm @@ -30,20 +30,20 @@ O = o #-- Begin File Lists --# # Edit in Makefile.in, not here! -NASM = nasm.o nasmlib.o raa.o saa.o \ +NASM = nasm.o nasmlib.o ver.o \ + raa.o saa.o rbtree.o \ float.o insnsa.o insnsb.o \ assemble.o labels.o hashtbl.o crc64.o parser.o \ - outform.o outbin.o \ - outaout.o outcoff.o \ - outelf32.o outelf64.o \ + outform.o outlib.o nulldbg.o \ + outbin.o outaout.o outcoff.o \ + outelf.o outelf32.o outelf64.o \ outobj.o outas86.o outrdf2.o \ - outdbg.o outieee.o \ - outmacho32.o outmacho64.o \ + outdbg.o outieee.o outmacho.o \ preproc.o quote.o pptok.o macros.o \ listing.o eval.o exprlib.o stdscan.o strfunc.o \ tokhash.o regvals.o regflags.o -NDISASM = ndisasm.o disasm.o sync.o nasmlib.o \ +NDISASM = ndisasm.o disasm.o sync.o nasmlib.o ver.o \ insnsd.o insnsb.o insnsn.o regs.o regdis.o #-- End File Lists --# @@ -114,7 +114,7 @@ clean: distclean: clean -$(RM) $(TARGETS) -$(OBJDIR)/version.inc: $(PROOT)/version $(PROOT)/version.pl $(OBJDIR) +$(OBJDIR)/version.mak: $(PROOT)/version $(PROOT)/version.pl $(OBJDIR) @$(PERL) $(PROOT)/version.pl make < $< > $@ #-- Magic hints to mkdep.pl --# @@ -123,87 +123,95 @@ $(OBJDIR)/version.inc: $(PROOT)/version $(PROOT)/version.pl $(OBJDIR) # @continuation: "\" #-- Everything below is generated by mkdep.pl - do not edit --# assemble.o: assemble.c assemble.h compiler.h config.h insns.h insnsi.h \ - nasm.h nasmlib.h pptok.h preproc.h regs.h tables.h tokens.h version.h + nasm.h nasmlib.h pptok.h preproc.h regs.h tables.h tokens.h crc64.o: crc64.c compiler.h config.h nasmlib.h disasm.o: disasm.c compiler.h config.h disasm.h insns.h insnsi.h nasm.h \ - nasmlib.h pptok.h preproc.h regdis.h regs.h sync.h tables.h tokens.h \ - version.h + nasmlib.h pptok.h preproc.h regdis.h regs.h sync.h tables.h tokens.h eval.o: eval.c compiler.h config.h eval.h float.h insnsi.h labels.h nasm.h \ - nasmlib.h pptok.h preproc.h regs.h version.h + nasmlib.h pptok.h preproc.h regs.h exprlib.o: exprlib.c compiler.h config.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h regs.h version.h + preproc.h regs.h float.o: float.c compiler.h config.h float.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h regs.h version.h + pptok.h preproc.h regs.h hashtbl.o: hashtbl.c compiler.h config.h hashtbl.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h regs.h version.h + pptok.h preproc.h regs.h insnsa.o: insnsa.c compiler.h config.h insns.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h regs.h tokens.h version.h + pptok.h preproc.h regs.h tokens.h insnsb.o: insnsb.c compiler.h config.h insns.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h regs.h tokens.h version.h + pptok.h preproc.h regs.h tokens.h insnsd.o: insnsd.c compiler.h config.h insns.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h regs.h tokens.h version.h + pptok.h preproc.h regs.h tokens.h insnsn.o: insnsn.c compiler.h config.h insnsi.h tables.h labels.o: labels.c compiler.h config.h hashtbl.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h regs.h version.h + pptok.h preproc.h regs.h snprintf.o: snprintf.c compiler.h config.h nasmlib.h vsnprintf.o: vsnprintf.c compiler.h config.h nasmlib.h listing.o: listing.c compiler.h config.h insnsi.h listing.h nasm.h nasmlib.h \ - pptok.h preproc.h regs.h version.h + pptok.h preproc.h regs.h macros.o: macros.c compiler.h config.h hashtbl.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h regs.h tables.h version.h + outform.h pptok.h preproc.h regs.h tables.h nasm.o: nasm.c assemble.h compiler.h config.h eval.h float.h insns.h \ insnsi.h labels.h listing.h nasm.h nasmlib.h outform.h parser.h pptok.h \ - preproc.h raa.h regs.h saa.h stdscan.h tokens.h version.h + preproc.h raa.h regs.h saa.h stdscan.h tokens.h nasmlib.o: nasmlib.c compiler.h config.h insns.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h regs.h tokens.h version.h + pptok.h preproc.h regs.h tokens.h ndisasm.o: ndisasm.c compiler.h config.h disasm.h insns.h insnsi.h nasm.h \ - nasmlib.h pptok.h preproc.h regs.h sync.h tokens.h version.h -outform.o: outform.c compiler.h config.h insnsi.h nasm.h nasmlib.h outform.h \ - pptok.h preproc.h regs.h version.h + nasmlib.h pptok.h preproc.h regs.h sync.h tokens.h +nulldbg.o: nulldbg.c compiler.h config.h insnsi.h nasm.h nasmlib.h pptok.h \ + preproc.h regs.h outaout.o: outaout.c compiler.h config.h insnsi.h nasm.h nasmlib.h outform.h \ - pptok.h preproc.h raa.h regs.h saa.h stdscan.h version.h + outlib.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h outas86.o: outas86.c compiler.h config.h insnsi.h nasm.h nasmlib.h outform.h \ - pptok.h preproc.h raa.h regs.h saa.h version.h + outlib.h pptok.h preproc.h raa.h regs.h saa.h outbin.o: outbin.c compiler.h config.h eval.h insnsi.h labels.h nasm.h \ - nasmlib.h outform.h pptok.h preproc.h regs.h saa.h stdscan.h version.h + nasmlib.h outform.h outlib.h pptok.h preproc.h regs.h saa.h stdscan.h outcoff.o: outcoff.c compiler.h config.h insnsi.h nasm.h nasmlib.h outform.h \ - pptok.h preproc.h raa.h regs.h saa.h version.h + outlib.h pptok.h preproc.h raa.h regs.h saa.h outdbg.o: outdbg.c compiler.h config.h insnsi.h nasm.h nasmlib.h outform.h \ - pptok.h preproc.h regs.h version.h -outelf32.o: outelf32.c compiler.h config.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h version.h -outelf64.o: outelf64.c compiler.h config.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h version.h + pptok.h preproc.h regs.h +outelf.o: outelf.c compiler.h config.h insnsi.h nasm.h nasmlib.h dwarf.h \ + elfcommon.h outelf.h outform.h pptok.h preproc.h regs.h +outelf32.o: outelf32.c compiler.h config.h insnsi.h nasm.h nasmlib.h dwarf.h \ + elf32.h elfcommon.h outelf.h outform.h outlib.h pptok.h preproc.h raa.h \ + rbtree.h regs.h saa.h stdscan.h +outelf64.o: outelf64.c compiler.h config.h insnsi.h nasm.h nasmlib.h dwarf.h \ + elf64.h elfcommon.h outelf.h outform.h outlib.h pptok.h preproc.h raa.h \ + rbtree.h regs.h saa.h stdscan.h +outform.o: outform.c compiler.h config.h insnsi.h nasm.h nasmlib.h outform.h \ + pptok.h preproc.h regs.h outieee.o: outieee.c compiler.h config.h insnsi.h nasm.h nasmlib.h outform.h \ - pptok.h preproc.h regs.h version.h -outmacho32.o: outmacho32.c compiler.h config.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h raa.h regs.h saa.h version.h -outmacho64.o: outmacho64.c compiler.h config.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h raa.h regs.h saa.h version.h + outlib.h pptok.h preproc.h regs.h +outlib.o: outlib.c compiler.h config.h insnsi.h nasm.h nasmlib.h outlib.h \ + pptok.h preproc.h regs.h +outmacho.o: outmacho.c compiler.h config.h insnsi.h nasm.h nasmlib.h \ + outform.h outlib.h pptok.h preproc.h raa.h regs.h saa.h outobj.o: outobj.c compiler.h config.h insnsi.h nasm.h nasmlib.h outform.h \ - pptok.h preproc.h regs.h stdscan.h version.h + outlib.h pptok.h preproc.h regs.h stdscan.h outrdf.o: outrdf.c compiler.h config.h insnsi.h nasm.h nasmlib.h outform.h \ - pptok.h preproc.h regs.h version.h + pptok.h preproc.h regs.h outrdf2.o: outrdf2.c compiler.h config.h insnsi.h nasm.h nasmlib.h outform.h \ - pptok.h preproc.h rdoff.h regs.h saa.h version.h + outlib.h pptok.h preproc.h rdoff.h regs.h saa.h +owtest.o: owtest.c parser.o: parser.c compiler.h config.h float.h insns.h insnsi.h nasm.h \ - nasmlib.h parser.h pptok.h preproc.h regs.h stdscan.h tables.h tokens.h \ - version.h + nasmlib.h parser.h pptok.h preproc.h regs.h stdscan.h tables.h tokens.h pptok.o: pptok.c compiler.h config.h hashtbl.h nasmlib.h pptok.h preproc.h preproc.o: preproc.c compiler.h config.h hashtbl.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h quote.h regs.h stdscan.h tables.h tokens.h version.h + pptok.h preproc.h quote.h regs.h stdscan.h tables.h tokens.h quote.o: quote.c compiler.h config.h nasmlib.h quote.h raa.o: raa.c compiler.h config.h nasmlib.h raa.h +rbtree.o: rbtree.c compiler.h config.h rbtree.h regdis.o: regdis.c regdis.h regs.h regflags.o: regflags.c compiler.h config.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h regs.h tables.h version.h + preproc.h regs.h tables.h regs.o: regs.c compiler.h config.h insnsi.h tables.h regvals.o: regvals.c compiler.h config.h insnsi.h tables.h saa.o: saa.c compiler.h config.h nasmlib.h saa.h stdscan.o: stdscan.c compiler.h config.h insns.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h quote.h regs.h stdscan.h tokens.h version.h + pptok.h preproc.h quote.h regs.h stdscan.h tokens.h strfunc.o: strfunc.c compiler.h config.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h regs.h version.h + preproc.h regs.h sync.o: sync.c compiler.h config.h nasmlib.h sync.h tokhash.o: tokhash.c compiler.h config.h hashtbl.h insns.h insnsi.h nasm.h \ - nasmlib.h pptok.h preproc.h regs.h tokens.h version.h + nasmlib.h pptok.h preproc.h regs.h tokens.h +ver.o: ver.c compiler.h config.h insnsi.h nasm.h nasmlib.h pptok.h preproc.h \ + regs.h version.h diff --git a/Mkfiles/openwcom.mak b/Mkfiles/openwcom.mak index 32b61348..a25ba669 100644 --- a/Mkfiles/openwcom.mak +++ b/Mkfiles/openwcom.mak @@ -46,20 +46,20 @@ X = .exe # Note: wcl386 is broken if forward slashes are used as path separators. #-- Begin File Lists --# # Edit in Makefile.in, not here! -NASM = nasm.$(O) nasmlib.$(O) raa.$(O) saa.$(O) & +NASM = nasm.$(O) nasmlib.$(O) ver.$(O) & + raa.$(O) saa.$(O) rbtree.$(O) & float.$(O) insnsa.$(O) insnsb.$(O) & assemble.$(O) labels.$(O) hashtbl.$(O) crc64.$(O) parser.$(O) & - outform.$(O) output\outbin.$(O) & - output\outaout.$(O) output\outcoff.$(O) & - output\outelf32.$(O) output\outelf64.$(O) & + output\outform.$(O) output\outlib.$(O) output\nulldbg.$(O) & + output\outbin.$(O) output\outaout.$(O) output\outcoff.$(O) & + output\outelf.$(O) output\outelf32.$(O) output\outelf64.$(O) & output\outobj.$(O) output\outas86.$(O) output\outrdf2.$(O) & - output\outdbg.$(O) output\outieee.$(O) & - output\outmacho32.$(O) output\outmacho64.$(O) & + output\outdbg.$(O) output\outieee.$(O) output\outmacho.$(O) & preproc.$(O) quote.$(O) pptok.$(O) macros.$(O) & listing.$(O) eval.$(O) exprlib.$(O) stdscan.$(O) strfunc.$(O) & tokhash.$(O) regvals.$(O) regflags.$(O) -NDISASM = ndisasm.$(O) disasm.$(O) sync.$(O) nasmlib.$(O) & +NDISASM = ndisasm.$(O) disasm.$(O) sync.$(O) nasmlib.$(O) ver.$(O) & insnsd.$(O) insnsb.$(O) insnsn.$(O) regs.$(O) regdis.$(O) #-- End File Lists --# @@ -212,86 +212,101 @@ everything: all doc rdf # @continuation: "&" #-- Everything below is generated by mkdep.pl - do not edit --# assemble.$(O): assemble.c assemble.h compiler.h insns.h insnsi.h nasm.h & - nasmlib.h pptok.h preproc.h regs.h tables.h tokens.h version.h + nasmlib.h pptok.h preproc.h regs.h tables.h tokens.h crc64.$(O): crc64.c compiler.h nasmlib.h disasm.$(O): disasm.c compiler.h disasm.h insns.h insnsi.h nasm.h nasmlib.h & - pptok.h preproc.h regdis.h regs.h sync.h tables.h tokens.h version.h + pptok.h preproc.h regdis.h regs.h sync.h tables.h tokens.h eval.$(O): eval.c compiler.h eval.h float.h insnsi.h labels.h nasm.h & - nasmlib.h pptok.h preproc.h regs.h version.h + nasmlib.h pptok.h preproc.h regs.h exprlib.$(O): exprlib.c compiler.h insnsi.h nasm.h nasmlib.h pptok.h & - preproc.h regs.h version.h + preproc.h regs.h float.$(O): float.c compiler.h float.h insnsi.h nasm.h nasmlib.h pptok.h & - preproc.h regs.h version.h + preproc.h regs.h hashtbl.$(O): hashtbl.c compiler.h hashtbl.h insnsi.h nasm.h nasmlib.h & - pptok.h preproc.h regs.h version.h + pptok.h preproc.h regs.h insnsa.$(O): insnsa.c compiler.h insns.h insnsi.h nasm.h nasmlib.h pptok.h & - preproc.h regs.h tokens.h version.h + preproc.h regs.h tokens.h insnsb.$(O): insnsb.c compiler.h insns.h insnsi.h nasm.h nasmlib.h pptok.h & - preproc.h regs.h tokens.h version.h + preproc.h regs.h tokens.h insnsd.$(O): insnsd.c compiler.h insns.h insnsi.h nasm.h nasmlib.h pptok.h & - preproc.h regs.h tokens.h version.h + preproc.h regs.h tokens.h insnsn.$(O): insnsn.c compiler.h insnsi.h tables.h labels.$(O): labels.c compiler.h hashtbl.h insnsi.h nasm.h nasmlib.h pptok.h & - preproc.h regs.h version.h + preproc.h regs.h lib\snprintf.$(O): lib\snprintf.c compiler.h nasmlib.h lib\vsnprintf.$(O): lib\vsnprintf.c compiler.h nasmlib.h listing.$(O): listing.c compiler.h insnsi.h listing.h nasm.h nasmlib.h & - pptok.h preproc.h regs.h version.h + pptok.h preproc.h regs.h macros.$(O): macros.c compiler.h hashtbl.h insnsi.h nasm.h nasmlib.h & - outform.h pptok.h preproc.h regs.h tables.h version.h + output\outform.h pptok.h preproc.h regs.h tables.h nasm.$(O): nasm.c assemble.h compiler.h eval.h float.h insns.h insnsi.h & - labels.h listing.h nasm.h nasmlib.h outform.h parser.h pptok.h preproc.h & - raa.h regs.h saa.h stdscan.h tokens.h version.h + labels.h listing.h nasm.h nasmlib.h output\outform.h parser.h pptok.h & + preproc.h raa.h regs.h saa.h stdscan.h tokens.h nasmlib.$(O): nasmlib.c compiler.h insns.h insnsi.h nasm.h nasmlib.h pptok.h & - preproc.h regs.h tokens.h version.h + preproc.h regs.h tokens.h ndisasm.$(O): ndisasm.c compiler.h disasm.h insns.h insnsi.h nasm.h & - nasmlib.h pptok.h preproc.h regs.h sync.h tokens.h version.h -outform.$(O): outform.c compiler.h insnsi.h nasm.h nasmlib.h outform.h & - pptok.h preproc.h regs.h version.h + nasmlib.h pptok.h preproc.h regs.h sync.h tokens.h +output\nulldbg.$(O): output\nulldbg.c compiler.h insnsi.h nasm.h nasmlib.h & + pptok.h preproc.h regs.h output\outaout.$(O): output\outaout.c compiler.h insnsi.h nasm.h nasmlib.h & - outform.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h version.h + output\outform.h output\outlib.h pptok.h preproc.h raa.h regs.h saa.h & + stdscan.h output\outas86.$(O): output\outas86.c compiler.h insnsi.h nasm.h nasmlib.h & - outform.h pptok.h preproc.h raa.h regs.h saa.h version.h + output\outform.h output\outlib.h pptok.h preproc.h raa.h regs.h saa.h output\outbin.$(O): output\outbin.c compiler.h eval.h insnsi.h labels.h & - nasm.h nasmlib.h outform.h pptok.h preproc.h regs.h saa.h stdscan.h & - version.h + nasm.h nasmlib.h output\outform.h output\outlib.h pptok.h preproc.h regs.h & + saa.h stdscan.h output\outcoff.$(O): output\outcoff.c compiler.h insnsi.h nasm.h nasmlib.h & - outform.h pptok.h preproc.h raa.h regs.h saa.h version.h + output\outform.h output\outlib.h pptok.h preproc.h raa.h regs.h saa.h output\outdbg.$(O): output\outdbg.c compiler.h insnsi.h nasm.h nasmlib.h & - outform.h pptok.h preproc.h regs.h version.h + output\outform.h pptok.h preproc.h regs.h +output\outelf.$(O): output\outelf.c compiler.h insnsi.h nasm.h nasmlib.h & + output\dwarf.h output\elfcommon.h output\outelf.h output\outform.h pptok.h & + preproc.h regs.h output\outelf32.$(O): output\outelf32.c compiler.h insnsi.h nasm.h nasmlib.h & - outform.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h version.h + output\dwarf.h output\elf32.h output\elfcommon.h output\outelf.h & + output\outform.h output\outlib.h pptok.h preproc.h raa.h rbtree.h regs.h & + saa.h stdscan.h output\outelf64.$(O): output\outelf64.c compiler.h insnsi.h nasm.h nasmlib.h & - outform.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h version.h + output\dwarf.h output\elf64.h output\elfcommon.h output\outelf.h & + output\outform.h output\outlib.h pptok.h preproc.h raa.h rbtree.h regs.h & + saa.h stdscan.h +output\outform.$(O): output\outform.c compiler.h insnsi.h nasm.h nasmlib.h & + output\outform.h pptok.h preproc.h regs.h output\outieee.$(O): output\outieee.c compiler.h insnsi.h nasm.h nasmlib.h & - outform.h pptok.h preproc.h regs.h version.h -output\outmacho32.$(O): output\outmacho32.c compiler.h insnsi.h nasm.h & - nasmlib.h outform.h pptok.h preproc.h raa.h regs.h saa.h version.h -output\outmacho64.$(O): output\outmacho64.c compiler.h insnsi.h nasm.h & - nasmlib.h outform.h pptok.h preproc.h raa.h regs.h saa.h version.h + output\outform.h output\outlib.h pptok.h preproc.h regs.h +output\outlib.$(O): output\outlib.c compiler.h insnsi.h nasm.h nasmlib.h & + output\outlib.h pptok.h preproc.h regs.h +output\outmacho.$(O): output\outmacho.c compiler.h insnsi.h nasm.h nasmlib.h & + output\outform.h output\outlib.h pptok.h preproc.h raa.h regs.h saa.h output\outobj.$(O): output\outobj.c compiler.h insnsi.h nasm.h nasmlib.h & - outform.h pptok.h preproc.h regs.h stdscan.h version.h + output\outform.h output\outlib.h pptok.h preproc.h regs.h stdscan.h output\outrdf.$(O): output\outrdf.c compiler.h insnsi.h nasm.h nasmlib.h & - outform.h pptok.h preproc.h regs.h version.h + output\outform.h pptok.h preproc.h regs.h output\outrdf2.$(O): output\outrdf2.c compiler.h insnsi.h nasm.h nasmlib.h & - outform.h pptok.h preproc.h rdoff\rdoff.h regs.h saa.h version.h + output\outform.h output\outlib.h pptok.h preproc.h rdoff\rdoff.h regs.h & + saa.h +owtest.$(O): owtest.c parser.$(O): parser.c compiler.h float.h insns.h insnsi.h nasm.h nasmlib.h & - parser.h pptok.h preproc.h regs.h stdscan.h tables.h tokens.h version.h + parser.h pptok.h preproc.h regs.h stdscan.h tables.h tokens.h pptok.$(O): pptok.c compiler.h hashtbl.h nasmlib.h pptok.h preproc.h preproc.$(O): preproc.c compiler.h hashtbl.h insnsi.h nasm.h nasmlib.h & - pptok.h preproc.h quote.h regs.h stdscan.h tables.h tokens.h version.h + pptok.h preproc.h quote.h regs.h stdscan.h tables.h tokens.h quote.$(O): quote.c compiler.h nasmlib.h quote.h raa.$(O): raa.c compiler.h nasmlib.h raa.h +rbtree.$(O): rbtree.c compiler.h rbtree.h regdis.$(O): regdis.c regdis.h regs.h regflags.$(O): regflags.c compiler.h insnsi.h nasm.h nasmlib.h pptok.h & - preproc.h regs.h tables.h version.h + preproc.h regs.h tables.h regs.$(O): regs.c compiler.h insnsi.h tables.h regvals.$(O): regvals.c compiler.h insnsi.h tables.h saa.$(O): saa.c compiler.h nasmlib.h saa.h stdscan.$(O): stdscan.c compiler.h insns.h insnsi.h nasm.h nasmlib.h pptok.h & - preproc.h quote.h regs.h stdscan.h tokens.h version.h + preproc.h quote.h regs.h stdscan.h tokens.h strfunc.$(O): strfunc.c compiler.h insnsi.h nasm.h nasmlib.h pptok.h & - preproc.h regs.h version.h + preproc.h regs.h sync.$(O): sync.c compiler.h nasmlib.h sync.h tokhash.$(O): tokhash.c compiler.h hashtbl.h insns.h insnsi.h nasm.h & - nasmlib.h pptok.h preproc.h regs.h tokens.h version.h + nasmlib.h pptok.h preproc.h regs.h tokens.h +ver.$(O): ver.c compiler.h insnsi.h nasm.h nasmlib.h pptok.h preproc.h & + regs.h version.h diff --git a/Mkfiles/owlinux.mak b/Mkfiles/owlinux.mak index 7eb82577..72998924 100644 --- a/Mkfiles/owlinux.mak +++ b/Mkfiles/owlinux.mak @@ -57,20 +57,20 @@ X = .exe #-- Begin File Lists --# # Edit in Makefile.in, not here! -NASM = nasm.$(O) nasmlib.$(O) raa.$(O) saa.$(O) \ +NASM = nasm.$(O) nasmlib.$(O) ver.$(O) \ + raa.$(O) saa.$(O) rbtree.$(O) \ float.$(O) insnsa.$(O) insnsb.$(O) \ assemble.$(O) labels.$(O) hashtbl.$(O) crc64.$(O) parser.$(O) \ - outform.$(O) output/outbin.$(O) \ - output/outaout.$(O) output/outcoff.$(O) \ - output/outelf32.$(O) output/outelf64.$(O) \ + output/outform.$(O) output/outlib.$(O) output/nulldbg.$(O) \ + output/outbin.$(O) output/outaout.$(O) output/outcoff.$(O) \ + output/outelf.$(O) output/outelf32.$(O) output/outelf64.$(O) \ output/outobj.$(O) output/outas86.$(O) output/outrdf2.$(O) \ - output/outdbg.$(O) output/outieee.$(O) \ - output/outmacho32.$(O) output/outmacho64.$(O) \ + output/outdbg.$(O) output/outieee.$(O) output/outmacho.$(O) \ preproc.$(O) quote.$(O) pptok.$(O) macros.$(O) \ listing.$(O) eval.$(O) exprlib.$(O) stdscan.$(O) strfunc.$(O) \ tokhash.$(O) regvals.$(O) regflags.$(O) -NDISASM = ndisasm.$(O) disasm.$(O) sync.$(O) nasmlib.$(O) \ +NDISASM = ndisasm.$(O) disasm.$(O) sync.$(O) nasmlib.$(O) ver.$(O) \ insnsd.$(O) insnsb.$(O) insnsn.$(O) regs.$(O) regdis.$(O) #-- End File Lists --# @@ -222,86 +222,101 @@ everything: all doc rdf # @continuation: "\" #-- Everything below is generated by mkdep.pl - do not edit --# assemble.$(O): assemble.c assemble.h compiler.h insns.h insnsi.h nasm.h \ - nasmlib.h pptok.h preproc.h regs.h tables.h tokens.h version.h + nasmlib.h pptok.h preproc.h regs.h tables.h tokens.h crc64.$(O): crc64.c compiler.h nasmlib.h disasm.$(O): disasm.c compiler.h disasm.h insns.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h regdis.h regs.h sync.h tables.h tokens.h version.h + pptok.h preproc.h regdis.h regs.h sync.h tables.h tokens.h eval.$(O): eval.c compiler.h eval.h float.h insnsi.h labels.h nasm.h \ - nasmlib.h pptok.h preproc.h regs.h version.h + nasmlib.h pptok.h preproc.h regs.h exprlib.$(O): exprlib.c compiler.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h regs.h version.h + preproc.h regs.h float.$(O): float.c compiler.h float.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h regs.h version.h + preproc.h regs.h hashtbl.$(O): hashtbl.c compiler.h hashtbl.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h regs.h version.h + pptok.h preproc.h regs.h insnsa.$(O): insnsa.c compiler.h insns.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h regs.h tokens.h version.h + preproc.h regs.h tokens.h insnsb.$(O): insnsb.c compiler.h insns.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h regs.h tokens.h version.h + preproc.h regs.h tokens.h insnsd.$(O): insnsd.c compiler.h insns.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h regs.h tokens.h version.h + preproc.h regs.h tokens.h insnsn.$(O): insnsn.c compiler.h insnsi.h tables.h labels.$(O): labels.c compiler.h hashtbl.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h regs.h version.h + preproc.h regs.h lib/snprintf.$(O): lib/snprintf.c compiler.h nasmlib.h lib/vsnprintf.$(O): lib/vsnprintf.c compiler.h nasmlib.h listing.$(O): listing.c compiler.h insnsi.h listing.h nasm.h nasmlib.h \ - pptok.h preproc.h regs.h version.h + pptok.h preproc.h regs.h macros.$(O): macros.c compiler.h hashtbl.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h regs.h tables.h version.h + output/outform.h pptok.h preproc.h regs.h tables.h nasm.$(O): nasm.c assemble.h compiler.h eval.h float.h insns.h insnsi.h \ - labels.h listing.h nasm.h nasmlib.h outform.h parser.h pptok.h preproc.h \ - raa.h regs.h saa.h stdscan.h tokens.h version.h + labels.h listing.h nasm.h nasmlib.h output/outform.h parser.h pptok.h \ + preproc.h raa.h regs.h saa.h stdscan.h tokens.h nasmlib.$(O): nasmlib.c compiler.h insns.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h regs.h tokens.h version.h + preproc.h regs.h tokens.h ndisasm.$(O): ndisasm.c compiler.h disasm.h insns.h insnsi.h nasm.h \ - nasmlib.h pptok.h preproc.h regs.h sync.h tokens.h version.h -outform.$(O): outform.c compiler.h insnsi.h nasm.h nasmlib.h outform.h \ - pptok.h preproc.h regs.h version.h + nasmlib.h pptok.h preproc.h regs.h sync.h tokens.h +output/nulldbg.$(O): output/nulldbg.c compiler.h insnsi.h nasm.h nasmlib.h \ + pptok.h preproc.h regs.h output/outaout.$(O): output/outaout.c compiler.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h version.h + output/outform.h output/outlib.h pptok.h preproc.h raa.h regs.h saa.h \ + stdscan.h output/outas86.$(O): output/outas86.c compiler.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h raa.h regs.h saa.h version.h + output/outform.h output/outlib.h pptok.h preproc.h raa.h regs.h saa.h output/outbin.$(O): output/outbin.c compiler.h eval.h insnsi.h labels.h \ - nasm.h nasmlib.h outform.h pptok.h preproc.h regs.h saa.h stdscan.h \ - version.h + nasm.h nasmlib.h output/outform.h output/outlib.h pptok.h preproc.h regs.h \ + saa.h stdscan.h output/outcoff.$(O): output/outcoff.c compiler.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h raa.h regs.h saa.h version.h + output/outform.h output/outlib.h pptok.h preproc.h raa.h regs.h saa.h output/outdbg.$(O): output/outdbg.c compiler.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h regs.h version.h + output/outform.h pptok.h preproc.h regs.h +output/outelf.$(O): output/outelf.c compiler.h insnsi.h nasm.h nasmlib.h \ + output/dwarf.h output/elfcommon.h output/outelf.h output/outform.h pptok.h \ + preproc.h regs.h output/outelf32.$(O): output/outelf32.c compiler.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h version.h + output/dwarf.h output/elf32.h output/elfcommon.h output/outelf.h \ + output/outform.h output/outlib.h pptok.h preproc.h raa.h rbtree.h regs.h \ + saa.h stdscan.h output/outelf64.$(O): output/outelf64.c compiler.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h raa.h regs.h saa.h stdscan.h version.h + output/dwarf.h output/elf64.h output/elfcommon.h output/outelf.h \ + output/outform.h output/outlib.h pptok.h preproc.h raa.h rbtree.h regs.h \ + saa.h stdscan.h +output/outform.$(O): output/outform.c compiler.h insnsi.h nasm.h nasmlib.h \ + output/outform.h pptok.h preproc.h regs.h output/outieee.$(O): output/outieee.c compiler.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h regs.h version.h -output/outmacho32.$(O): output/outmacho32.c compiler.h insnsi.h nasm.h \ - nasmlib.h outform.h pptok.h preproc.h raa.h regs.h saa.h version.h -output/outmacho64.$(O): output/outmacho64.c compiler.h insnsi.h nasm.h \ - nasmlib.h outform.h pptok.h preproc.h raa.h regs.h saa.h version.h + output/outform.h output/outlib.h pptok.h preproc.h regs.h +output/outlib.$(O): output/outlib.c compiler.h insnsi.h nasm.h nasmlib.h \ + output/outlib.h pptok.h preproc.h regs.h +output/outmacho.$(O): output/outmacho.c compiler.h insnsi.h nasm.h nasmlib.h \ + output/outform.h output/outlib.h pptok.h preproc.h raa.h regs.h saa.h output/outobj.$(O): output/outobj.c compiler.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h regs.h stdscan.h version.h + output/outform.h output/outlib.h pptok.h preproc.h regs.h stdscan.h output/outrdf.$(O): output/outrdf.c compiler.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h regs.h version.h + output/outform.h pptok.h preproc.h regs.h output/outrdf2.$(O): output/outrdf2.c compiler.h insnsi.h nasm.h nasmlib.h \ - outform.h pptok.h preproc.h rdoff/rdoff.h regs.h saa.h version.h + output/outform.h output/outlib.h pptok.h preproc.h rdoff/rdoff.h regs.h \ + saa.h +owtest.$(O): owtest.c parser.$(O): parser.c compiler.h float.h insns.h insnsi.h nasm.h nasmlib.h \ - parser.h pptok.h preproc.h regs.h stdscan.h tables.h tokens.h version.h + parser.h pptok.h preproc.h regs.h stdscan.h tables.h tokens.h pptok.$(O): pptok.c compiler.h hashtbl.h nasmlib.h pptok.h preproc.h preproc.$(O): preproc.c compiler.h hashtbl.h insnsi.h nasm.h nasmlib.h \ - pptok.h preproc.h quote.h regs.h stdscan.h tables.h tokens.h version.h + pptok.h preproc.h quote.h regs.h stdscan.h tables.h tokens.h quote.$(O): quote.c compiler.h nasmlib.h quote.h raa.$(O): raa.c compiler.h nasmlib.h raa.h +rbtree.$(O): rbtree.c compiler.h rbtree.h regdis.$(O): regdis.c regdis.h regs.h regflags.$(O): regflags.c compiler.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h regs.h tables.h version.h + preproc.h regs.h tables.h regs.$(O): regs.c compiler.h insnsi.h tables.h regvals.$(O): regvals.c compiler.h insnsi.h tables.h saa.$(O): saa.c compiler.h nasmlib.h saa.h stdscan.$(O): stdscan.c compiler.h insns.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h quote.h regs.h stdscan.h tokens.h version.h + preproc.h quote.h regs.h stdscan.h tokens.h strfunc.$(O): strfunc.c compiler.h insnsi.h nasm.h nasmlib.h pptok.h \ - preproc.h regs.h version.h + preproc.h regs.h sync.$(O): sync.c compiler.h nasmlib.h sync.h tokhash.$(O): tokhash.c compiler.h hashtbl.h insns.h insnsi.h nasm.h \ - nasmlib.h pptok.h preproc.h regs.h tokens.h version.h + nasmlib.h pptok.h preproc.h regs.h tokens.h +ver.$(O): ver.c compiler.h insnsi.h nasm.h nasmlib.h pptok.h preproc.h \ + regs.h version.h @@ -13,3 +13,27 @@ AC_DEFUN(PA_ADD_CFLAGS, AC_MSG_RESULT([no]) CFLAGS="$pa_add_cflags__old_cflags")]) +dnl -------------------------------------------------------------------------- +dnl PA_WORKING_STDBOOL +dnl +dnl See if we have a working <stdbool.h> and bool support; in particular, +dnl OpenWatcom 1.8 has a broken _Bool type that we don't want to use. +dnl -------------------------------------------------------------------------- +AC_DEFUN(PA_WORKING_BOOL, +[AC_MSG_CHECKING([if $CC has a working bool type]) + AC_COMPILE_IFELSE( + [ +#ifndef __cplusplus +#include <stdbool.h> +#endif +int foo(bool x, int y) +{ + return x+y; +} + ], + [AC_MSG_RESULT([yes]) + AC_DEFINE(HAVE_WORKING_BOOL, 1, + [Define to 1 if your compiler has a correct implementation of bool])], + [AC_MSG_RESULT([no])]) +]) + @@ -1,17 +1,45 @@ -/* assemble.c code generation for the Netwide Assembler +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * assemble.c code generation for the Netwide Assembler * * the actual codes (C syntax, i.e. octal): * \0 - terminates the code. (Unless it's a literal of course.) - * \1, \2, \3 - that many literal bytes follow in the code stream - * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS - * (POP is never used for CS) depending on operand 0 - * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending - * on operand 0 + * \1..\4 - that many literal bytes follow in the code stream + * \5 - add 4 to the primary operand number (b, low octdigit) + * \6 - add 4 to the secondary operand number (a, middle octdigit) + * \7 - add 4 to both the primary and the secondary operand number * \10..\13 - a literal byte follows in the code stream, to be added * to the register value of operand 0..3 * \14..\17 - a signed byte immediate operand, from operand 0..3 @@ -29,13 +57,13 @@ * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit * assembly mode or the operand-size override on the operand * \70..\73 - a long relative operand, from operand 0..3 - * \74..\77 - a word constant, from the _segment_ part of operand 0..3 + * \74..\77 - a word constant, from the _segment_ part of operand 0..3 * \1ab - a ModRM, calculated on EA in operand a, with the spare * field the register value of operand b. * \140..\143 - an immediate word or signed byte for operand 0..3 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3 * is a signed byte rather than a word. Opcode byte follows. - * \150..\153 - an immediate dword or signed byte for operand 0..3 + * \150..\153 - an immediate dword or signed byte for operand 0..3 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3 * is a signed byte rather than a dword. Opcode byte follows. * \160..\163 - this instruction uses DREX rather than REX, with the @@ -56,23 +84,27 @@ * \250..\253 - same as \150..\153, except warn if the 64-bit operand * is not equal to the truncated and sign-extended 32-bit * operand; used for 32-bit immediates in 64-bit mode. - * \260..\263 - this instruction uses VEX rather than REX, with the + * \254..\257 - a signed 32-bit operand to be extended to 64 bits. + * \260..\263 - this instruction uses VEX/XOP rather than REX, with the * V field taken from operand 0..3. - * \270 - this instruction uses VEX rather than REX, with the + * \270 - this instruction uses VEX/XOP rather than REX, with the * V field set to 1111b. * - * VEX prefixes are followed by the sequence: - * \mm\wlp where mm is the M field; and wlp is: + * VEX/XOP prefixes are followed by the sequence: + * \tmm\wlp where mm is the M field; and wlp is: * 00 0ww lpp * [w0] ww = 0 for W = 0 * [w1] ww = 1 for W = 1 * [wx] ww = 2 for W don't care (always assembled as 0) * [ww] ww = 3 for W used as REX.W * + * t = 0 for VEX (C4/C5), t = 1 for XOP (8F). * + * \274..\277 - a signed byte immediate operand, from operand 0..3, + * which is to be extended to the operand size. * \310 - indicates fixed 16-bit address size, i.e. optional 0x67. * \311 - indicates fixed 32-bit address size, i.e. optional 0x67. - * \312 - (disassembler only) marker on LOOP, LOOPxx instructions. + * \312 - (disassembler only) invalid with non-default address size. * \313 - indicates fixed 64-bit address size, 0x67 invalid. * \314 - (disassembler only) invalid with REX.B * \315 - (disassembler only) invalid with REX.X @@ -85,19 +117,25 @@ * generates no code in the assembler) * \323 - indicates fixed 64-bit operand size, REX on extensions only. * \324 - indicates 64-bit operand size requiring REX prefix. + * \325 - instruction which always uses spl/bpl/sil/dil * \330 - a literal byte follows in the code stream, to be added * to the condition code value of the instruction. * \331 - instruction not valid with REP prefix. Hint for * disassembler only; for SSE instructions. * \332 - REP prefix (0xF2 byte) used as opcode extension. * \333 - REP prefix (0xF3 byte) used as opcode extension. - * \334 - LOCK prefix used instead of REX.R + * \334 - LOCK prefix used as REX.R (used in non-64-bit mode) * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep. * \336 - force a REP(E) prefix (0xF2) even if not specified. * \337 - force a REPNE prefix (0xF3) even if not specified. * \336-\337 are still listed as prefixes in the disassembler. * \340 - reserve <operand 0> bytes of uninitialized storage. * Operand 0 had better be a segmentless constant. + * \341 - this instruction needs a WAIT "prefix" + * \344,\345 - the PUSH/POP (respectively) codes for CS, DS, ES, SS + * (POP is never used for CS) depending on operand 0 + * \346,\347 - the second byte of PUSH/POP codes for FS, GS, depending + * on operand 0 * \360 - no SSE prefix (== \364\331) * \361 - 66 SSE prefix (== \366\331) * \362 - F2 SSE prefix (== \364\332) @@ -124,9 +162,6 @@ #include "insns.h" #include "tables.h" -/* Initialized to zero by the C standard */ -static const uint8_t const_zero_buf[256]; - typedef struct { int sib_present; /* is a SIB byte necessary? */ int bytes; /* # of bytes of offset needed */ @@ -140,7 +175,9 @@ static struct ofmt *outfmt; static ListGen *list; static int64_t calcsize(int32_t, int64_t, int, insn *, const uint8_t *); -static void gencode(int32_t, int64_t, int, insn *, const uint8_t *, int64_t); +static void gencode(int32_t segment, int64_t offset, int bits, + insn * ins, const struct itemplate *temp, + int64_t insn_end); static int matches(const struct itemplate *, insn *, int bits); static int32_t regflag(const operand *); static int32_t regval(const operand *); @@ -183,13 +220,14 @@ static const char *size_name(int size) } } -static void warn_overflow(int size, int64_t data) +static void warn_overflow(int size, const struct operand *o) { - if (size < 8) { + if (size < 8 && o->wrt == NO_SEG && o->segment == NO_SEG) { int64_t lim = ((int64_t)1 << (size*8))-1; + int64_t data = o->offset; if (data < ~lim || data > lim) - errfunc(ERR_WARNING | ERR_WARN_NOV, + errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV, "%s data exceeds bounds", size_name(size)); } } @@ -241,29 +279,30 @@ static void out(int64_t offset, int32_t segto, const void *data, outfmt->output(segto, data, type, size, segment, wrt); } -static int jmp_match(int32_t segment, int64_t offset, int bits, +static bool jmp_match(int32_t segment, int64_t offset, int bits, insn * ins, const uint8_t *code) { int64_t isize; uint8_t c = code[0]; - if (c != 0370 && c != 0371) - return 0; - if (ins->oprs[0].opflags & OPFLAG_FORWARD) { - if ((optimizing < 0 || (ins->oprs[0].type & STRICT)) - && c == 0370) - return 1; - else - return (pass0 == 0); /* match a forward reference */ - } + if ((c != 0370 && c != 0371) || (ins->oprs[0].type & STRICT)) + return false; + if (!optimizing) + return false; + if (optimizing < 0 && c == 0371) + return false; + isize = calcsize(segment, offset, bits, ins, code); + + if (ins->oprs[0].opflags & OPFLAG_UNKNOWN) + /* Be optimistic in pass 1 */ + return true; + if (ins->oprs[0].segment != segment) - return 0; - isize = ins->oprs[0].offset - offset - isize; /* isize is now the delta */ - if (isize >= -128L && isize <= 127L) - return 1; /* it is byte size */ + return false; - return 0; + isize = ins->oprs[0].offset - offset - isize; /* isize is delta */ + return (isize >= -128 && isize <= 127); /* is it byte size? */ } int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp, @@ -348,7 +387,7 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp, if (align) { align = wsize - align; - out(offset, segment, const_zero_buf, + out(offset, segment, zero_buffer, OUT_RAWDATA, align, NO_SEG, NO_SEG); } offset += e->stringlen + align; @@ -405,9 +444,8 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp, fseek(fp, base, SEEK_SET); l = len; while (l > 0) { - int32_t m = - fread(buf, 1, (l > (int32_t) sizeof(buf) ? (int32_t) sizeof(buf) : l), - fp); + int32_t m; + m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp); if (!m) { /* * This shouldn't happen unless the file @@ -444,18 +482,16 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp, /* Check to see if we need an address-size prefix */ add_asp(instruction, bits); - size_prob = false; + size_prob = 0; for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++){ int m = matches(temp, instruction, bits); - - if (m == 99) - m += jmp_match(segment, offset, bits, instruction, temp->code); - - if (m == 100) { /* matches! */ - const uint8_t *codes = temp->code; + if (m == 100 || + (m == 99 && jmp_match(segment, offset, bits, + instruction, temp->code))) { + /* Matches! */ int64_t insn_size = calcsize(segment, offset, bits, - instruction, codes); + instruction, temp->code); itimes = instruction->times; if (insn_size < 0) /* shouldn't be, on pass two */ error(ERR_PANIC, "errors made it through from pass one"); @@ -464,6 +500,9 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp, for (j = 0; j < MAXPREFIX; j++) { uint8_t c = 0; switch (instruction->prefixes[j]) { + case P_WAIT: + c = 0x9B; + break; case P_LOCK: c = 0xF0; break; @@ -478,21 +517,21 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp, break; case R_CS: if (bits == 64) { - error(ERR_WARNING, + error(ERR_WARNING | ERR_PASS2, "cs segment base generated, but will be ignored in 64-bit mode"); } c = 0x2E; break; case R_DS: if (bits == 64) { - error(ERR_WARNING, + error(ERR_WARNING | ERR_PASS2, "ds segment base generated, but will be ignored in 64-bit mode"); } c = 0x3E; break; case R_ES: if (bits == 64) { - error(ERR_WARNING, + error(ERR_WARNING | ERR_PASS2, "es segment base generated, but will be ignored in 64-bit mode"); } c = 0x26; @@ -505,7 +544,7 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp, break; case R_SS: if (bits == 64) { - error(ERR_WARNING, + error(ERR_WARNING | ERR_PASS2, "ss segment base generated, but will be ignored in 64-bit mode"); } c = 0x36; @@ -563,8 +602,8 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp, } } insn_end = offset + insn_size; - gencode(segment, offset, bits, instruction, codes, - insn_end); + gencode(segment, offset, bits, instruction, + temp, insn_end); offset += insn_size; if (itimes > 0 && itimes == instruction->times - 1) { /* @@ -581,7 +620,6 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp, } else if (m > 0 && m > size_prob) { size_prob = m; } -// temp++; } if (temp->opcode == -1) { /* didn't match any instruction */ @@ -596,7 +634,8 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp, error(ERR_NONFATAL, "no instruction for this cpu level"); break; case 4: - error(ERR_NONFATAL, "instruction not supported in 64-bit mode"); + error(ERR_NONFATAL, "instruction not supported in %d-bit mode", + bits); break; default: error(ERR_NONFATAL, @@ -702,10 +741,9 @@ int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp, for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++) { int m = matches(temp, instruction, bits); - if (m == 99) - m += jmp_match(segment, offset, bits, instruction, temp->code); - - if (m == 100) { + if (m == 100 || + (m == 99 && jmp_match(segment, offset, bits, + instruction, temp->code))) { /* we've matched an instruction. */ int64_t isize; const uint8_t *codes = temp->code; @@ -749,9 +787,9 @@ int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp, static bool possible_sbyte(operand *o) { - return !(o->opflags & OPFLAG_FORWARD) && - optimizing >= 0 && !(o->type & STRICT) && - o->wrt == NO_SEG && o->segment == NO_SEG; + return o->wrt == NO_SEG && o->segment == NO_SEG && + !(o->opflags & OPFLAG_UNKNOWN) && + optimizing >= 0 && !(o->type & STRICT); } /* check that opn[op] is a signed byte of size 16 or 32 */ @@ -777,31 +815,18 @@ static bool is_sbyte32(operand *o) return v >= -128 && v <= 127; } -/* check that opn[op] is a signed byte of size 32; warn if this is not - the original value when extended to 64 bits */ -static bool is_sbyte64(operand *o) -{ - int64_t v64; - int32_t v32; - - /* dead in the water on forward reference or External */ - if (!possible_sbyte(o)) - return false; +/* Common construct */ +#define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3 - v64 = o->offset; - v32 = (int32_t)v64; - - warn_overflow(32, v64); - - return v32 >= -128 && v32 <= 127; -} static int64_t calcsize(int32_t segment, int64_t offset, int bits, - insn * ins, const uint8_t *codes) + insn * ins, const uint8_t *codes) { int64_t length = 0; uint8_t c; int rex_mask = ~0; + int op1, op2; struct operand *opx; + uint8_t opex = 0; ins->rex = 0; /* Ensure REX is reset */ @@ -813,243 +838,226 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits, while (*codes) { c = *codes++; - opx = &ins->oprs[c & 3]; + op1 = (c & 3) + ((opex & 1) << 2); + op2 = ((c >> 3) & 3) + ((opex & 2) << 1); + opx = &ins->oprs[op1]; + opex = 0; /* For the next iteration */ + switch (c) { case 01: case 02: case 03: + case 04: codes += c, length += c; break; - case 04: - case 05: - case 06: - case 07: - length++; - break; - case 010: - case 011: - case 012: - case 013: + + case 05: + case 06: + case 07: + opex = c; + break; + + case4(010): ins->rex |= op_rexflags(opx, REX_B|REX_H|REX_P|REX_W); codes++, length++; break; - case 014: - case 015: - case 016: - case 017: - length++; - break; - case 020: - case 021: - case 022: - case 023: - length++; - break; - case 024: - case 025: - case 026: - case 027: + + case4(014): + case4(020): + case4(024): length++; break; - case 030: - case 031: - case 032: - case 033: + + case4(030): length += 2; break; - case 034: - case 035: - case 036: - case 037: + + case4(034): if (opx->type & (BITS16 | BITS32 | BITS64)) length += (opx->type & BITS16) ? 2 : 4; else length += (bits == 16) ? 2 : 4; break; - case 040: - case 041: - case 042: - case 043: + + case4(040): length += 4; break; - case 044: - case 045: - case 046: - case 047: + + case4(044): length += ins->addr_size >> 3; break; - case 050: - case 051: - case 052: - case 053: + + case4(050): length++; break; - case 054: - case 055: - case 056: - case 057: + + case4(054): length += 8; /* MOV reg64/imm */ break; - case 060: - case 061: - case 062: - case 063: + + case4(060): length += 2; break; - case 064: - case 065: - case 066: - case 067: + + case4(064): if (opx->type & (BITS16 | BITS32 | BITS64)) length += (opx->type & BITS16) ? 2 : 4; else length += (bits == 16) ? 2 : 4; break; - case 070: - case 071: - case 072: - case 073: + + case4(070): length += 4; break; - case 074: - case 075: - case 076: - case 077: + + case4(074): length += 2; break; - case 0140: - case 0141: - case 0142: - case 0143: + + case4(0140): length += is_sbyte16(opx) ? 1 : 2; break; - case 0144: - case 0145: - case 0146: - case 0147: + + case4(0144): codes++; length++; break; - case 0150: - case 0151: - case 0152: - case 0153: + + case4(0150): length += is_sbyte32(opx) ? 1 : 4; break; - case 0154: - case 0155: - case 0156: - case 0157: + + case4(0154): codes++; length++; break; - case 0160: - case 0161: - case 0162: - case 0163: + + case4(0160): length++; ins->rex |= REX_D; ins->drexdst = regval(opx); break; - case 0164: - case 0165: - case 0166: - case 0167: + + case4(0164): length++; ins->rex |= REX_D|REX_OC; ins->drexdst = regval(opx); break; + case 0171: break; + case 0172: case 0173: case 0174: codes++; length++; break; - case 0250: - case 0251: - case 0252: - case 0253: - length += is_sbyte64(opx) ? 1 : 4; + + case4(0250): + length += is_sbyte32(opx) ? 1 : 4; break; - case 0260: - case 0261: - case 0262: - case 0263: + + case4(0254): + length += 4; + break; + + case4(0260): ins->rex |= REX_V; ins->drexdst = regval(opx); - ins->vex_m = *codes++; + ins->vex_cm = *codes++; ins->vex_wlp = *codes++; break; + case 0270: ins->rex |= REX_V; ins->drexdst = 0; - ins->vex_m = *codes++; + ins->vex_cm = *codes++; ins->vex_wlp = *codes++; break; - case 0300: - case 0301: - case 0302: - case 0303: + + case4(0274): + length++; + break; + + case4(0300): break; + case 0310: if (bits == 64) return -1; length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16); break; + case 0311: length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32); break; + case 0312: break; + case 0313: if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) || has_prefix(ins, PPS_ASIZE, P_A32)) return -1; break; - case 0314: - case 0315: - case 0316: - case 0317: + + case4(0314): break; + case 0320: length += (bits != 16); break; + case 0321: length += (bits == 16); break; + case 0322: break; + case 0323: rex_mask &= ~REX_W; break; + case 0324: ins->rex |= REX_W; break; + + case 0325: + ins->rex |= REX_NH; + break; + case 0330: codes++, length++; break; + case 0331: break; + case 0332: case 0333: length++; break; + case 0334: ins->rex |= REX_L; break; + case 0335: break; + case 0336: if (!ins->prefixes[PPS_LREP]) ins->prefixes[PPS_LREP] = P_REP; break; + case 0337: if (!ins->prefixes[PPS_LREP]) ins->prefixes[PPS_LREP] = P_REPNE; break; + case 0340: if (ins->oprs[0].segment != NO_SEG) errfunc(ERR_NONFATAL, "attempt to reserve non-constant" @@ -1057,61 +1065,99 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits, else length += ins->oprs[0].offset; break; + + case 0341: + if (!ins->prefixes[PPS_WAIT]) + ins->prefixes[PPS_WAIT] = P_WAIT; + break; + + case4(0344): + length++; + break; + case 0360: break; + case 0361: case 0362: case 0363: length++; break; + case 0364: case 0365: break; + case 0366: case 0367: length++; break; + case 0370: case 0371: case 0372: break; + case 0373: length++; break; - default: /* can't do it by 'case' statements */ - if (c >= 0100 && c <= 0277) { /* it's an EA */ + + case4(0100): + case4(0110): + case4(0120): + case4(0130): + case4(0200): + case4(0204): + case4(0210): + case4(0214): + case4(0220): + case4(0224): + case4(0230): + case4(0234): + { ea ea_data; int rfield; int32_t rflags; + struct operand *opy = &ins->oprs[op2]; + ea_data.rex = 0; /* Ensure ea.REX is initially 0 */ if (c <= 0177) { - /* pick rfield from operand b */ - rflags = regflag(&ins->oprs[c & 7]); - rfield = nasm_regvals[ins->oprs[c & 7].basereg]; + /* pick rfield from operand b (opx) */ + rflags = regflag(opx); + rfield = nasm_regvals[opx->basereg]; } else { rflags = 0; rfield = c & 7; } - - if (!process_ea - (&ins->oprs[(c >> 3) & 7], &ea_data, bits, - ins->addr_size, rfield, rflags)) { + if (!process_ea(opy, &ea_data, bits, + ins->addr_size, rfield, rflags)) { errfunc(ERR_NONFATAL, "invalid effective address"); return -1; } else { ins->rex |= ea_data.rex; length += ea_data.size; } - } else { - errfunc(ERR_PANIC, "internal instruction table corrupt" - ": instruction code 0x%02X given", c); } - } + break; + + default: + errfunc(ERR_PANIC, "internal instruction table corrupt" + ": instruction code \\%o (0x%02X) given", c, c); + break; + } } ins->rex &= rex_mask; + if (ins->rex & REX_NH) { + if (ins->rex & REX_H) { + errfunc(ERR_NONFATAL, "instruction cannot use high registers"); + return -1; + } + ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */ + } + if (ins->rex & REX_V) { int bad32 = REX_R|REX_W|REX_X|REX_B; @@ -1137,7 +1183,7 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits, errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode"); return -1; } - if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_R|REX_B))) + if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_R|REX_B))) length += 3; else length += 2; @@ -1182,7 +1228,8 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits, } static void gencode(int32_t segment, int64_t offset, int bits, - insn * ins, const uint8_t *codes, int64_t insn_end) + insn * ins, const struct itemplate *temp, + int64_t insn_end) { static char condval[] = { /* conditional opcodes */ 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2, @@ -1193,81 +1240,53 @@ static void gencode(int32_t segment, int64_t offset, int bits, uint8_t bytes[4]; int64_t size; int64_t data; + int op1, op2; struct operand *opx; + const uint8_t *codes = temp->code; + uint8_t opex = 0; while (*codes) { c = *codes++; - opx = &ins->oprs[c & 3]; + op1 = (c & 3) + ((opex & 1) << 2); + op2 = ((c >> 3) & 3) + ((opex & 2) << 1); + opx = &ins->oprs[op1]; + opex = 0; /* For the next iteration */ + switch (c) { case 01: case 02: case 03: + case 04: EMIT_REX(); out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG); codes += c; offset += c; break; - case 04: - case 06: - switch (ins->oprs[0].basereg) { - case R_CS: - bytes[0] = 0x0E + (c == 0x04 ? 1 : 0); - break; - case R_DS: - bytes[0] = 0x1E + (c == 0x04 ? 1 : 0); - break; - case R_ES: - bytes[0] = 0x06 + (c == 0x04 ? 1 : 0); - break; - case R_SS: - bytes[0] = 0x16 + (c == 0x04 ? 1 : 0); - break; - default: - errfunc(ERR_PANIC, - "bizarre 8086 segment register received"); - } - out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG); - offset++; - break; - - case 05: - case 07: - switch (ins->oprs[0].basereg) { - case R_FS: - bytes[0] = 0xA0 + (c == 0x05 ? 1 : 0); - break; - case R_GS: - bytes[0] = 0xA8 + (c == 0x05 ? 1 : 0); - break; - default: - errfunc(ERR_PANIC, - "bizarre 386 segment register received"); - } - out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG); - offset++; - break; + case 05: + case 06: + case 07: + opex = c; + break; - case 010: - case 011: - case 012: - case 013: + case4(010): EMIT_REX(); - bytes[0] = *codes++ + ((regval(opx)) & 7); + bytes[0] = *codes++ + (regval(opx) & 7); out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG); offset += 1; break; - case 014: - case 015: - case 016: - case 017: - /* XXX: warns for legitimate optimizer actions */ - if (opx->offset < -128 || opx->offset > 127) { - errfunc(ERR_WARNING | ERR_WARN_NOV, + case4(014): + /* The test for BITS8 and SBYTE here is intended to avoid + warning on optimizer actions due to SBYTE, while still + warn on explicit BYTE directives. Also warn, obviously, + if the optimizer isn't enabled. */ + if (((opx->type & BITS8) || + !(opx->type & temp->opd[op1] & BYTENESS)) && + (opx->offset < -128 || opx->offset > 127)) { + errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV, "signed byte value exceeds bounds"); - } - + } if (opx->segment != NO_SEG) { data = opx->offset; out(offset, segment, &data, OUT_ADDRESS, 1, @@ -1280,12 +1299,9 @@ static void gencode(int32_t segment, int64_t offset, int bits, offset += 1; break; - case 020: - case 021: - case 022: - case 023: + case4(020): if (opx->offset < -256 || opx->offset > 255) { - errfunc(ERR_WARNING | ERR_WARN_NOV, + errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV, "byte value exceeds bounds"); } if (opx->segment != NO_SEG) { @@ -1300,12 +1316,9 @@ static void gencode(int32_t segment, int64_t offset, int bits, offset += 1; break; - case 024: - case 025: - case 026: - case 027: + case4(024): if (opx->offset < 0 || opx->offset > 255) - errfunc(ERR_WARNING | ERR_WARN_NOV, + errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV, "unsigned byte value exceeds bounds"); if (opx->segment != NO_SEG) { data = opx->offset; @@ -1319,64 +1332,44 @@ static void gencode(int32_t segment, int64_t offset, int bits, offset += 1; break; - case 030: - case 031: - case 032: - case 033: + case4(030): + warn_overflow(2, opx); data = opx->offset; - if (opx->segment == NO_SEG && opx->wrt == NO_SEG) - warn_overflow(2, data); out(offset, segment, &data, OUT_ADDRESS, 2, opx->segment, opx->wrt); offset += 2; break; - case 034: - case 035: - case 036: - case 037: + case4(034): if (opx->type & (BITS16 | BITS32)) size = (opx->type & BITS16) ? 2 : 4; else size = (bits == 16) ? 2 : 4; + warn_overflow(size, opx); data = opx->offset; - if (opx->segment == NO_SEG && opx->wrt == NO_SEG) - warn_overflow(size, data); out(offset, segment, &data, OUT_ADDRESS, size, opx->segment, opx->wrt); offset += size; break; - case 040: - case 041: - case 042: - case 043: + case4(040): + warn_overflow(4, opx); data = opx->offset; - if (opx->segment == NO_SEG && opx->wrt == NO_SEG) - warn_overflow(4, data); out(offset, segment, &data, OUT_ADDRESS, 4, opx->segment, opx->wrt); offset += 4; break; - case 044: - case 045: - case 046: - case 047: + case4(044): data = opx->offset; size = ins->addr_size >> 3; - if (opx->segment == NO_SEG && - opx->wrt == NO_SEG) - warn_overflow(size, data); + warn_overflow(size, opx); out(offset, segment, &data, OUT_ADDRESS, size, opx->segment, opx->wrt); offset += size; break; - case 050: - case 051: - case 052: - case 053: + case4(050): if (opx->segment != segment) errfunc(ERR_NONFATAL, "short relative jump outside segment"); @@ -1388,20 +1381,14 @@ static void gencode(int32_t segment, int64_t offset, int bits, offset += 1; break; - case 054: - case 055: - case 056: - case 057: + case4(054): data = (int64_t)opx->offset; out(offset, segment, &data, OUT_ADDRESS, 8, opx->segment, opx->wrt); offset += 8; break; - case 060: - case 061: - case 062: - case 063: + case4(060): if (opx->segment != segment) { data = opx->offset; out(offset, segment, &data, @@ -1415,10 +1402,7 @@ static void gencode(int32_t segment, int64_t offset, int bits, offset += 2; break; - case 064: - case 065: - case 066: - case 067: + case4(064): if (opx->type & (BITS16 | BITS32 | BITS64)) size = (opx->type & BITS16) ? 2 : 4; else @@ -1436,10 +1420,7 @@ static void gencode(int32_t segment, int64_t offset, int bits, offset += size; break; - case 070: - case 071: - case 072: - case 073: + case4(070): if (opx->segment != segment) { data = opx->offset; out(offset, segment, &data, @@ -1453,10 +1434,7 @@ static void gencode(int32_t segment, int64_t offset, int bits, offset += 4; break; - case 074: - case 075: - case 076: - case 077: + case4(074): if (opx->segment == NO_SEG) errfunc(ERR_NONFATAL, "value referenced by FAR is not" " relocatable"); @@ -1467,30 +1445,22 @@ static void gencode(int32_t segment, int64_t offset, int bits, offset += 2; break; - case 0140: - case 0141: - case 0142: - case 0143: + case4(0140): data = opx->offset; + warn_overflow(2, opx); if (is_sbyte16(opx)) { bytes[0] = data; out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG); offset++; } else { - if (opx->segment == NO_SEG && - opx->wrt == NO_SEG) - warn_overflow(2, data); out(offset, segment, &data, OUT_ADDRESS, 2, opx->segment, opx->wrt); offset += 2; } break; - case 0144: - case 0145: - case 0146: - case 0147: + case4(0144): EMIT_REX(); bytes[0] = *codes++; if (is_sbyte16(opx)) @@ -1499,11 +1469,9 @@ static void gencode(int32_t segment, int64_t offset, int bits, offset++; break; - case 0150: - case 0151: - case 0152: - case 0153: + case4(0150): data = opx->offset; + warn_overflow(4, opx); if (is_sbyte32(opx)) { bytes[0] = data; out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, @@ -1516,10 +1484,7 @@ static void gencode(int32_t segment, int64_t offset, int bits, } break; - case 0154: - case 0155: - case 0156: - case 0157: + case4(0154): EMIT_REX(); bytes[0] = *codes++; if (is_sbyte32(opx)) @@ -1528,14 +1493,8 @@ static void gencode(int32_t segment, int64_t offset, int bits, offset++; break; - case 0160: - case 0161: - case 0162: - case 0163: - case 0164: - case 0165: - case 0166: - case 0167: + case4(0160): + case4(0164): break; case 0171: @@ -1559,7 +1518,7 @@ static void gencode(int32_t segment, int64_t offset, int bits, c & 7); } else { if (opx->offset & ~15) { - errfunc(ERR_WARNING | ERR_WARN_NOV, + errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV, "four-bit argument exceeds bounds"); } bytes[0] |= opx->offset & 15; @@ -1585,12 +1544,13 @@ static void gencode(int32_t segment, int64_t offset, int bits, offset++; break; - case 0250: - case 0251: - case 0252: - case 0253: + case4(0250): data = opx->offset; - /* is_sbyte32() is right here, we have already warned */ + if (opx->wrt == NO_SEG && opx->segment == NO_SEG && + (int32_t)data != (int64_t)data) { + errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV, + "signed dword immediate exceeds bounds"); + } if (is_sbyte32(opx)) { bytes[0] = data; out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, @@ -1603,15 +1563,24 @@ static void gencode(int32_t segment, int64_t offset, int bits, } break; - case 0260: - case 0261: - case 0262: - case 0263: + case4(0254): + data = opx->offset; + if (opx->wrt == NO_SEG && opx->segment == NO_SEG && + (int32_t)data != (int64_t)data) { + errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV, + "signed dword immediate exceeds bounds"); + } + out(offset, segment, &data, OUT_ADDRESS, 4, + opx->segment, opx->wrt); + offset += 4; + break; + + case4(0260): case 0270: codes += 2; - if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_X|REX_B))) { - bytes[0] = 0xc4; - bytes[1] = ins->vex_m | ((~ins->rex & 7) << 5); + if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) { + bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4; + bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5); bytes[2] = ((ins->rex & REX_W) << (7-3)) | ((~ins->drexdst & 15)<< 3) | (ins->vex_wlp & 07); out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG); @@ -1625,10 +1594,42 @@ static void gencode(int32_t segment, int64_t offset, int bits, } break; - case 0300: - case 0301: - case 0302: - case 0303: + case4(0274): + { + uint64_t uv, um; + int s; + + if (ins->rex & REX_W) + s = 64; + else if (ins->prefixes[PPS_OSIZE] == P_O16) + s = 16; + else if (ins->prefixes[PPS_OSIZE] == P_O32) + s = 32; + else + s = bits; + + um = (uint64_t)2 << (s-1); + uv = opx->offset; + + if (uv > 127 && uv < (uint64_t)-128 && + (uv < um-128 || uv > um-1)) { + errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV, + "signed byte value exceeds bounds"); + } + if (opx->segment != NO_SEG) { + data = uv; + out(offset, segment, &data, OUT_ADDRESS, 1, + opx->segment, opx->wrt); + } else { + bytes[0] = uv; + out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, + NO_SEG); + } + offset += 1; + break; + } + + case4(0300): break; case 0310: @@ -1656,10 +1657,7 @@ static void gencode(int32_t segment, int64_t offset, int bits, ins->rex = 0; break; - case 0314: - case 0315: - case 0316: - case 0317: + case4(0314): break; case 0320: @@ -1688,6 +1686,9 @@ static void gencode(int32_t segment, int64_t offset, int bits, ins->rex |= REX_W; break; + case 0325: + break; + case 0330: *bytes = *codes++ ^ condval[ins->condition]; out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG); @@ -1732,6 +1733,51 @@ static void gencode(int32_t segment, int64_t offset, int bits, } break; + case 0341: + break; + + case 0344: + case 0345: + bytes[0] = c & 1; + switch (ins->oprs[0].basereg) { + case R_CS: + bytes[0] += 0x0E; + break; + case R_DS: + bytes[0] += 0x1E; + break; + case R_ES: + bytes[0] += 0x06; + break; + case R_SS: + bytes[0] += 0x16; + break; + default: + errfunc(ERR_PANIC, + "bizarre 8086 segment register received"); + } + out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG); + offset++; + break; + + case 0346: + case 0347: + bytes[0] = c & 1; + switch (ins->oprs[0].basereg) { + case R_FS: + bytes[0] += 0xA0; + break; + case R_GS: + bytes[0] += 0xA8; + break; + default: + errfunc(ERR_PANIC, + "bizarre 386 segment register received"); + } + out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG); + offset++; + break; + case 0360: break; @@ -1770,27 +1816,39 @@ static void gencode(int32_t segment, int64_t offset, int bits, offset += 1; break; - default: /* can't do it by 'case' statements */ - if (c >= 0100 && c <= 0277) { /* it's an EA */ + case4(0100): + case4(0110): + case4(0120): + case4(0130): + case4(0200): + case4(0204): + case4(0210): + case4(0214): + case4(0220): + case4(0224): + case4(0230): + case4(0234): + { ea ea_data; int rfield; int32_t rflags; uint8_t *p; int32_t s; + enum out_type type; + struct operand *opy = &ins->oprs[op2]; if (c <= 0177) { - /* pick rfield from operand b */ - rflags = regflag(&ins->oprs[c & 7]); - rfield = nasm_regvals[ins->oprs[c & 7].basereg]; + /* pick rfield from operand b (opx) */ + rflags = regflag(opx); + rfield = nasm_regvals[opx->basereg]; } else { /* rfield is constant */ rflags = 0; rfield = c & 7; } - if (!process_ea - (&ins->oprs[(c >> 3) & 7], &ea_data, bits, - ins->addr_size, rfield, rflags)) { + if (!process_ea(opy, &ea_data, bits, ins->addr_size, + rfield, rflags)) { errfunc(ERR_NONFATAL, "invalid effective address"); } @@ -1802,50 +1860,62 @@ static void gencode(int32_t segment, int64_t offset, int bits, /* DREX suffixes come between the SIB and the displacement */ if (ins->rex & REX_D) { - *p++ = - (ins->drexdst << 4) | - (ins->rex & REX_OC ? 0x08 : 0) | - (ins->rex & (REX_R|REX_X|REX_B)); + *p++ = (ins->drexdst << 4) | + (ins->rex & REX_OC ? 0x08 : 0) | + (ins->rex & (REX_R|REX_X|REX_B)); ins->rex = 0; } s = p - bytes; out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG); + /* + * Make sure the address gets the right offset in case + * the line breaks in the .lst file (BR 1197827) + */ + offset += s; + s = 0; + switch (ea_data.bytes) { case 0: break; case 1: - if (ins->oprs[(c >> 3) & 7].segment != NO_SEG) { - data = ins->oprs[(c >> 3) & 7].offset; - out(offset, segment, &data, OUT_ADDRESS, 1, - ins->oprs[(c >> 3) & 7].segment, - ins->oprs[(c >> 3) & 7].wrt); - } else { - *bytes = ins->oprs[(c >> 3) & 7].offset; - out(offset, segment, bytes, OUT_RAWDATA, 1, - NO_SEG, NO_SEG); - } - s++; - break; - case 8: case 2: case 4: - data = ins->oprs[(c >> 3) & 7].offset; - warn_overflow(ea_data.bytes, data); - out(offset, segment, &data, - ea_data.rip ? OUT_REL4ADR : OUT_ADDRESS, - ea_data.bytes, - ins->oprs[(c >> 3) & 7].segment, - ins->oprs[(c >> 3) & 7].wrt); + case 8: + data = opy->offset; + warn_overflow(ea_data.bytes, opy); s += ea_data.bytes; + if (ea_data.rip) { + if (opy->segment == segment) { + data -= insn_end; + out(offset, segment, &data, OUT_ADDRESS, + ea_data.bytes, NO_SEG, NO_SEG); + } else { + out(offset, segment, &data, OUT_REL4ADR, + insn_end - offset, opy->segment, opy->wrt); + } + } else { + type = OUT_ADDRESS; + out(offset, segment, &data, OUT_ADDRESS, + ea_data.bytes, opy->segment, opy->wrt); + } + break; + default: + /* Impossible! */ + errfunc(ERR_PANIC, + "Invalid amount of bytes (%d) for offset?!", + ea_data.bytes); break; } offset += s; - } else { - errfunc(ERR_PANIC, "internal instruction table corrupt" - ": instruction code 0x%02X given", c); } + break; + + default: + errfunc(ERR_PANIC, "internal instruction table corrupt" + ": instruction code \\%o (0x%02X) given", c, c); + break; } } } @@ -2061,9 +2131,9 @@ static int matches(const struct itemplate *itemp, insn * instruction, int bits) return 3; /* - * Check if instruction is available in long mode + * Verify the appropriate long mode flag. */ - if ((itemp->flags & IF_NOLONG) && (bits == 64)) + if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG))) return 4; /* @@ -2078,7 +2148,7 @@ static int matches(const struct itemplate *itemp, insn * instruction, int bits) static ea *process_ea(operand * input, ea * output, int bits, int addrbits, int rfield, int32_t rflags) { - bool forw_ref = !!(input->opflags & OPFLAG_FORWARD); + bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN); output->rip = false; @@ -1,9 +1,38 @@ -/* assemble.h header file for assemble.c +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * assemble.h header file for assemble.c */ #ifndef NASM_ASSEMBLE_H @@ -1,10 +1,33 @@ /* ----------------------------------------------------------------------- * + * + * Copyright 2007-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * Copyright 2007 The NASM Authors - All Rights Reserved + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the license given in the file "LICENSE" - * distributed in the NASM archive. + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * ----------------------------------------------------------------------- */ @@ -78,7 +101,7 @@ int vsnprintf(char *, size_t, const char *, va_list); #endif #ifndef __cplusplus /* C++ has false, true, bool as keywords */ -# ifdef HAVE_STDBOOL_H +# if defined(HAVE_STDBOOL_H) && defined(HAVE_WORKING_BOOL) # include <stdbool.h> # else /* This is sort of dangerous, since casts will behave different than @@ -87,6 +110,19 @@ typedef enum bool { false, true } bool; # endif #endif +/* Provide a substitute for offsetof() if we don't have one. This + variant works on most (but not *all*) systems... */ +#ifndef offsetof +# define offsetof(t,m) ((size_t)&(((t *)0)->m)) +#endif + +/* The container_of construct: if p is a pointer to member m of + container class c, then return a pointer to the container of which + *p is a member. */ +#ifndef container_of +# define container_of(p, c, m) ((c *)((char *)(p) - offsetof(c,m))) +#endif + /* Some misguided platforms hide the defs for these */ #if defined(HAVE_STRCASECMP) && !HAVE_DECL_STRCASECMP int strcasecmp(const char *, const char *); @@ -134,4 +170,13 @@ char *strsep(char **, const char *); # define unlikely(x) (!!(x)) #endif +/* + * How to tell the compiler that a function doesn't return + */ +#ifdef __GNUC__ +# define no_return void __attribute__((noreturn)) +#else +# define no_return void +#endif + #endif /* NASM_COMPILER_H */ diff --git a/configure.in b/configure.in index 0d536533..b47675be 100644 --- a/configure.in +++ b/configure.in @@ -97,6 +97,7 @@ AC_C_CONST AC_C_INLINE AC_C_RESTRICT AC_TYPE_SIZE_T +PA_WORKING_BOOL AC_C_BIGENDIAN(AC_DEFINE(WORDS_BIGENDIAN),AC_DEFINE(WORDS_LITTLEENDIAN)) AH_TEMPLATE(WORDS_BIGENDIAN, [Define to 1 if your processor stores words with the most significant @@ -1,3 +1,36 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + #include "compiler.h" #include "nasmlib.h" @@ -1,11 +1,38 @@ -/* disasm.c where all the _work_ gets done in the Netwide Disassembler +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: * - * initial version 27/iii/95 by Simon Tatham + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * disasm.c where all the _work_ gets done in the Netwide Disassembler */ #include "compiler.h" @@ -46,8 +73,10 @@ struct prefix_info { uint8_t asp; /* Address size prefix present */ uint8_t rep; /* Rep prefix present */ uint8_t seg; /* Segment override prefix present */ + uint8_t wait; /* WAIT "prefix" present */ uint8_t lock; /* Lock prefix present */ uint8_t vex[3]; /* VEX prefix present */ + uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */ uint8_t vex_m; /* VEX.M field */ uint8_t vex_v; uint8_t vex_lp; /* VEX.LP fields */ @@ -133,7 +162,7 @@ static enum reg_enum whichreg(int32_t regflags, int regval, int rex) return 0; if (!(REG8 & ~regflags)) { - if (rex & REX_P) + if (rex & (REX_P|REX_NH)) return nasm_rd_reg8_rex[regval]; else return nasm_rd_reg8[regval]; @@ -151,7 +180,7 @@ static enum reg_enum whichreg(int32_t regflags, int regval, int rex) if (!(REG_DREG & ~regflags)) return nasm_rd_dreg[regval]; if (!(REG_TREG & ~regflags)) { - if (rex & REX_P) + if (regval > 7) return 0; /* TR registers are ill-defined with rex */ return nasm_rd_treg[regval]; } @@ -370,11 +399,14 @@ static int matches(const struct itemplate *t, uint8_t *data, uint8_t *origdata = data; bool a_used = false, o_used = false; enum prefixes drep = 0; + enum prefixes dwait = 0; uint8_t lock = prefix->lock; int osize = prefix->osize; int asize = prefix->asize; int i, c; - struct operand *opx; + int op1, op2; + struct operand *opx, *opy; + uint8_t opex = 0; int s_field_for = -1; /* No 144/154 series code encountered */ bool vex_ok = false; int regmask = (segsize == 64) ? 15 : 7; @@ -395,77 +427,29 @@ static int matches(const struct itemplate *t, uint8_t *data, else if (prefix->rep == 0xF3) drep = P_REP; + dwait = prefix->wait ? P_WAIT : 0; + while ((c = *r++) != 0) { - opx = &ins->oprs[c & 3]; + op1 = (c & 3) + ((opex & 1) << 2); + op2 = ((c >> 3) & 3) + ((opex & 2) << 1); + opx = &ins->oprs[op1]; + opy = &ins->oprs[op2]; + opex = 0; switch (c) { case 01: case 02: case 03: + case 04: while (c--) if (*r++ != *data++) return false; break; - case 04: - switch (*data++) { - case 0x07: - ins->oprs[0].basereg = 0; - break; - case 0x17: - ins->oprs[0].basereg = 2; - break; - case 0x1F: - ins->oprs[0].basereg = 3; - break; - default: - return false; - } - break; - case 05: - switch (*data++) { - case 0xA1: - ins->oprs[0].basereg = 4; - break; - case 0xA9: - ins->oprs[0].basereg = 5; - break; - default: - return false; - } - break; - case 06: - switch (*data++) { - case 0x06: - ins->oprs[0].basereg = 0; - break; - case 0x0E: - ins->oprs[0].basereg = 1; - break; - case 0x16: - ins->oprs[0].basereg = 2; - break; - case 0x1E: - ins->oprs[0].basereg = 3; - break; - default: - return false; - } - break; - case 07: - switch (*data++) { - case 0xA0: - ins->oprs[0].basereg = 4; - break; - case 0xA8: - ins->oprs[0].basereg = 5; - break; - default: - return false; - } + opex = c; break; case4(010): @@ -482,6 +466,7 @@ static int matches(const struct itemplate *t, uint8_t *data, } case4(014): + case4(0274): opx->offset = (int8_t)*data++; opx->segment |= SEG_SIGNED; break; @@ -512,6 +497,7 @@ static int matches(const struct itemplate *t, uint8_t *data, break; case4(040): + case4(0254): opx->offset = getu32(data); data += 4; break; @@ -587,17 +573,15 @@ static int matches(const struct itemplate *t, uint8_t *data, { int modrm = *data++; opx->segment |= SEG_RMREG; - data = do_ea(data, modrm, asize, segsize, - &ins->oprs[(c >> 3) & 3], ins); + data = do_ea(data, modrm, asize, segsize, opy, ins); if (!data) return false; - opx->basereg = ((modrm >> 3)&7)+ - (ins->rex & REX_R ? 8 : 0); + opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0); break; } case4(0140): - if (s_field_for == (c & 3)) { + if (s_field_for == op1) { opx->offset = gets8(data); data++; } else { @@ -608,13 +592,13 @@ static int matches(const struct itemplate *t, uint8_t *data, case4(0144): case4(0154): - s_field_for = (*data & 0x02) ? c & 3 : -1; + s_field_for = (*data & 0x02) ? op1 : -1; if ((*data++ & ~0x02) != *r++) return false; break; case4(0150): - if (s_field_for == (c & 3)) { + if (s_field_for == op1) { opx->offset = gets8(data); data++; } else { @@ -625,12 +609,12 @@ static int matches(const struct itemplate *t, uint8_t *data, case4(0160): ins->rex |= REX_D; - ins->drexdst = c & 3; + ins->drexdst = op1; break; case4(0164): ins->rex |= REX_D|REX_OC; - ins->drexdst = c & 3; + ins->drexdst = op1; break; case 0171: @@ -684,8 +668,7 @@ static int matches(const struct itemplate *t, uint8_t *data, int modrm = *data++; if (((modrm >> 3) & 07) != (c & 07)) return false; /* spare field doesn't match up */ - data = do_ea(data, modrm, asize, segsize, - &ins->oprs[(c >> 3) & 07], ins); + data = do_ea(data, modrm, asize, segsize, opy, ins); if (!data) return false; break; @@ -770,7 +753,7 @@ static int matches(const struct itemplate *t, uint8_t *data, break; case 0311: - if (asize == 16) + if (asize != 32) return false; else a_used = true; @@ -843,6 +826,10 @@ static int matches(const struct itemplate *t, uint8_t *data, o_used = true; break; + case 0325: + ins->rex |= REX_NH; + break; + case 0330: { int t = *r++, d = *data++; @@ -889,6 +876,16 @@ static int matches(const struct itemplate *t, uint8_t *data, case 0340: return false; + case 0341: + if (prefix->wait != 0x9B) + return false; + dwait = 0; + break; + + case4(0344): + ins->oprs[0].basereg = (*data++ >> 3) & 7; + break; + case 0360: if (prefix->osp || prefix->rep) return false; @@ -964,6 +961,7 @@ static int matches(const struct itemplate *t, uint8_t *data, return false; ins->prefixes[PPS_LREP] = drep; } + ins->prefixes[PPS_WAIT] = dwait; if (!o_used) { if (osize != ((segsize == 16) ? 16 : 32)) { enum prefixes pfx = 0; @@ -1040,6 +1038,10 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, prefix.rep = *data++; break; + case 0x9B: + prefix.wait = *data++; + break; + case 0xF0: prefix.lock = *data++; break; @@ -1079,6 +1081,7 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, prefix.vex[1] = *data++; prefix.rex = REX_V; + prefix.vex_c = RV_VEX; if (prefix.vex[0] == 0xc4) { prefix.vex[2] = *data++; @@ -1094,7 +1097,28 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, prefix.vex_lp = prefix.vex[1] & 7; } - ix = itable_VEX[prefix.vex_m][prefix.vex_lp]; + ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp]; + } + end_prefix = true; + break; + + case 0x8F: + if ((data[1] & 030) != 0 && + (segsize == 64 || (data[1] & 0xc0) == 0xc0)) { + prefix.vex[0] = *data++; + prefix.vex[1] = *data++; + prefix.vex[2] = *data++; + + prefix.rex = REX_V; + prefix.vex_c = RV_XOP; + + prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */ + prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W; + prefix.vex_m = prefix.vex[1] & 0x1f; + prefix.vex_v = (~prefix.vex[2] >> 3) & 15; + prefix.vex_lp = prefix.vex[2] & 7; + + ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp]; } end_prefix = true; break; @@ -1218,41 +1242,11 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, * the return value is "sane." Maybe a macro wrapper could * be used for that purpose. */ - for (i = 0; i < MAXPREFIX; i++) - switch (ins.prefixes[i]) { - case P_LOCK: - slen += snprintf(output + slen, outbufsize - slen, "lock "); - break; - case P_REP: - slen += snprintf(output + slen, outbufsize - slen, "rep "); - break; - case P_REPE: - slen += snprintf(output + slen, outbufsize - slen, "repe "); - break; - case P_REPNE: - slen += snprintf(output + slen, outbufsize - slen, "repne "); - break; - case P_A16: - slen += snprintf(output + slen, outbufsize - slen, "a16 "); - break; - case P_A32: - slen += snprintf(output + slen, outbufsize - slen, "a32 "); - break; - case P_A64: - slen += snprintf(output + slen, outbufsize - slen, "a64 "); - break; - case P_O16: - slen += snprintf(output + slen, outbufsize - slen, "o16 "); - break; - case P_O32: - slen += snprintf(output + slen, outbufsize - slen, "o32 "); - break; - case P_O64: - slen += snprintf(output + slen, outbufsize - slen, "o64 "); - break; - default: - break; - } + for (i = 0; i < MAXPREFIX; i++) { + const char *prefix = prefix_name(ins.prefixes[i]); + if (prefix) + slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix); + } i = (*p)->opcode; if (i >= FIRST_COND_OPCODE) @@ -1480,8 +1474,86 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, return length; } -int32_t eatbyte(uint8_t *data, char *output, int outbufsize) +/* + * This is called when we don't have a complete instruction. If it + * is a standalone *single-byte* prefix show it as such, otherwise + * print it as a literal. + */ +int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize) { - snprintf(output, outbufsize, "db 0x%02X", *data); + uint8_t byte = *data; + const char *str = NULL; + + switch (byte) { + case 0xF2: + str = "repne"; + break; + case 0xF3: + str = "rep"; + break; + case 0x9B: + str = "wait"; + break; + case 0xF0: + str = "lock"; + break; + case 0x2E: + str = "cs"; + break; + case 0x36: + str = "ss"; + break; + case 0x3E: + str = "ss"; + break; + case 0x26: + str = "es"; + break; + case 0x64: + str = "fs"; + break; + case 0x65: + str = "gs"; + break; + case 0x66: + str = (segsize == 16) ? "o32" : "o16"; + break; + case 0x67: + str = (segsize == 32) ? "a16" : "a32"; + break; + case REX_P + 0x0: + case REX_P + 0x1: + case REX_P + 0x2: + case REX_P + 0x3: + case REX_P + 0x4: + case REX_P + 0x5: + case REX_P + 0x6: + case REX_P + 0x7: + case REX_P + 0x8: + case REX_P + 0x9: + case REX_P + 0xA: + case REX_P + 0xB: + case REX_P + 0xC: + case REX_P + 0xD: + case REX_P + 0xE: + case REX_P + 0xF: + if (segsize == 64) { + snprintf(output, outbufsize, "rex%s%s%s%s%s", + (byte == REX_P) ? "" : ".", + (byte & REX_W) ? "w" : "", + (byte & REX_R) ? "r" : "", + (byte & REX_X) ? "x" : "", + (byte & REX_B) ? "b" : ""); + break; + } + /* else fall through */ + default: + snprintf(output, outbufsize, "db 0x%02x", byte); + break; + } + + if (str) + strcpy(output, str); + return 1; } @@ -1,9 +1,38 @@ -/* disasm.h header file for disasm.c +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * disasm.h header file for disasm.c */ #ifndef NASM_DISASM_H @@ -13,6 +42,6 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize, int32_t offset, int autosync, uint32_t prefer); -int32_t eatbyte(uint8_t *data, char *output, int outbufsize); +int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize); #endif diff --git a/doc/Makefile.in b/doc/Makefile.in index f704f03e..a2ef4e31 100644 --- a/doc/Makefile.in +++ b/doc/Makefile.in @@ -95,6 +95,7 @@ spotless: clean -rm -f nasmdoc*.ps inslist.src install: all + mkdir -p $(INSTALLROOT)$(infodir) $(INSTALL_DATA) info/* $(INSTALLROOT)$(infodir) mkdir -p $(INSTALLROOT)$(docdir)/html $(INSTALL_DATA) html/* $(INSTALLROOT)$(docdir)/html diff --git a/doc/afmmetrics.pl b/doc/afmmetrics.pl index b93d22e9..6d7bfc23 100755 --- a/doc/afmmetrics.pl +++ b/doc/afmmetrics.pl @@ -1,4 +1,37 @@ #!/usr/bin/perl +## -------------------------------------------------------------------------- +## +## Copyright 1996-2009 The NASM Authors - All Rights Reserved +## See the file AUTHORS included with the NASM distribution for +## the specific copyright holders. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following +## conditions are met: +## +## * Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above +## copyright notice, this list of conditions and the following +## disclaimer in the documentation and/or other materials provided +## with the distribution. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## -------------------------------------------------------------------------- + # # Parse AFM metric files # diff --git a/doc/changes.src b/doc/changes.src index d0abb5b1..1920b5bf 100644 --- a/doc/changes.src +++ b/doc/changes.src @@ -8,37 +8,182 @@ The NASM 2 series support x86-64, and is the production version of NASM since 2007. +\S{cl-2.07} Version 2.07 + +\b NASM is now under the 2-clause BSD license. See \k{legal}. + +\b Fix the section type for the \c{.strtab} section in the \c{elf64} + output format. + +\b Fix the handling of \c{COMMON} directives in the \c{obj} output format. + +\b New \c{ith} and \c{srec} output formats; these are variants of the + \c{bin} output format which output Intel hex and Motorola S-records, + respectively. See \k{ithfmt} and \k{srecfmt}. + +\b \c{rdf2ihx} replaced with an enhanced \c{rdf2bin}, which can output + binary, COM, Intel hex or Motorola S-records. + +\b The Windows installer now puts the NASM directory first in the + \c{PATH} of the "NASM Shell". + +\b Revert the early expansion behavior of \c{%+} to pre-2.06 behavior: + \c{%+} is only expanded late. + +\b Yet another Mach-O alignment fix. + +\b Don't delete the list file on errors. Also, include error and + warning information in the list file. + + +\S{cl-2.06} Version 2.06 + +\b This release is dedicated to the memory of Charles A. Crayne, long + time NASM developer as well as moderator of \c{comp.lang.asm.x86} and + author of the book \e{Serious Assembler}. We miss you, Chuck. + +\b Support for indirect macro expansion (\c{%[...]}). See \k{indmacro}. + +\b \c{%pop} can now take an argument, see \k{pushpop}. + +\b The argument to \c{%use} is no longer macro-expanded. Use + \c{%[...]} if macro expansion is desired. + +\b Support for thread-local storage in ELF32 and ELF64. See \k{elftls}. + +\b Fix crash on \c{%ifmacro} without an argument. + +\b Correct the arguments to the \c{POPCNT} instruction. + +\b Fix section alignment in the Mach-O format. + +\b Update AVX support to version 5 of the Intel specification. + +\b Fix the handling of accesses to context-local macros from higher + levels in the context stack. + +\b Treat \c{WAIT} as a prefix rather than as an instruction, thereby + allowing constructs like \c{O16 FSAVE} to work correctly. + +\b Support for structures with a non-zero base offset. See \k{struc}. + +\b Correctly handle preprocessor token concatenation (see \k{concat}) + involving floating-point numbers. + +\b The \c{PINSR} series of instructions have been corrected and + rationalized. + +\b Removed AMD SSE5, replaced with the new XOP/FMA4/CVT16 (rev 3.03) + spec. + +\b The ELF backends no longer automatically generate a \c{.comment} section. + +\b Add additional "well-known" ELF sections with default attributes. See + \k{elfsect}. + + +\S{cl-2.05.01} Version 2.05.01 + +\b Fix the \c{-w}/\c{-W} option parsing, which was broken in NASM 2.05. + + +\S{cl-2.05} Version 2.05 + +\b Fix redundant REX.W prefix on \c{JMP reg64}. + +\b Make the behaviour of \c{-O0} match NASM 0.98 legacy behavior. + See \k{opt-O}. + +\b \c{-w-user} can be used to suppress the output of \c{%warning} directives. + See \k{opt-w}. + +\b Fix bug where \c{ALIGN} would issue a full alignment datum instead of + zero bytes. + +\b Fix offsets in list files. + +\b Fix \c{%include} inside multi-line macros or loops. + +\b Fix error where NASM would generate a spurious warning on valid + optimizations of immediate values. + +\b Fix arguments to a number of the \c{CVT} SSE instructions. + +\b Fix RIP-relative offsets when the instruction carries an immediate. + +\b Massive overhaul of the ELF64 backend for spec compliance. + +\b Fix the Geode \c{PFRCPV} and \c{PFRSQRTV} instruction. + +\b Fix the SSE 4.2 \c{CRC32} instruction. + + \S{cl-2.04} Version 2.04 \b Sanitize macro handing in the \c{%error} directive. \b New \c{%warning} directive to issue user-controlled warnings. +\b \c{%error} directives are now deferred to the final assembly phase. + +\b New \c{%fatal} directive to immediately terminate assembly. + +\b New \c{%strcat} directive to join quoted strings together. + +\b New \c{%use} macro directive to support standard macro directives. See + \k{use}. + +\b Excess default parameters to \c{%macro} now issues a warning by default. + See \k{mlmacro}. + +\b Fix \c{%ifn} and \c{%elifn}. + +\b Fix nested \c{%else} clauses. + +\b Correct the handling of nested \c{%rep}s. + +\b New \c{%unmacro} directive to undeclare a multi-line macro. + See \k{unmacro}. + +\b Builtin macro \c{__PASS__} which expands to the current assembly pass. + See \k{pass_macro}. + \b \c{__utf16__} and \c{__utf32__} operators to generate UTF-16 and UTF-32 - strings. + strings. See \k{unicode}. \b Fix bug in case-insensitive matching when compiled on platforms that don't use the \c{configure} script. Of the official release binaries, - that only affects the OS/2 binary. + that only affected the OS/2 binary. -\b Correct the handling of nested \c{%rep}s. +\b Support for x87 packed BCD constants. See \k{bcdconst}. -\b Support for x87 packed BCD constants. +\b Correct the \c{LTR} and \c{SLDT} instructions in 64-bit mode. -\b New \c{%strcat} directive to join quoted strings together. +\b Fix unnecessary REX.W prefix on indirect jumps in 64-bit mode. -\b Correct the \c{LTR} instruction in 64-bit mode. +\b Add AVX versions of the AES instructions (\c{VAES}...). -\b Fix unnecessary REX.W prefix on indirect jumps in 64-bit mode. +\b Fix the 256-bit FMA instructions. -\b New \c{%use} macro directive to support standard macro directives. See - \k{use}. +\b Add 256-bit AVX stores per the latest AVX spec. -\b Excess default parameters to \c{%macro} now issues a warning by default. - See \k{mlmacro}. +\b VIA XCRYPT instructions can now be written either with or without + \c{REP}, apparently different versions of the VIA spec wrote them + differently. + +\b Add missing 64-bit \c{MOVNTI} instruction. + +\b Fix the operand size of \c{VMREAD} and \c{VMWRITE}. \b Numerous bug fixes, especially to the AES, AVX and VTX instructions. +\b The optimizer now always runs until it converges. It also runs even + when disabled, but doesn't optimize. This allows most forward references + to be resolved properly. + +\b \c{%push} no longer needs a context identifier; omitting the context + identifier results in an anonymous context. + \S{cl-2.03.01} Version 2.03.01 @@ -95,8 +240,8 @@ creation. \b Fix forward references used in \c{EQU} statements. -\S{cl-2.02} Version 2.02 +\S{cl-2.02} Version 2.02 \b Additional fixes for MMX operands with explicit \c{qword}, as well as (hopefully) SSE operands with \c{oword}. @@ -133,8 +278,8 @@ creation. \b Autogenerated instruction list added to the documentation. -\S{cl-2.01} Version 2.01 +\S{cl-2.01} Version 2.01 \b Fix the handling of MMX registers with explicit \c{qword} tags on memory (broken in 2.00 due to 64-bit changes.) @@ -207,6 +352,14 @@ creation. \b Significant performance improvements. +\b \c{-w+warning} and \c{-w-warning} can now be written as -Wwarning and + -Wno-warning, respectively. See \k{opt-w}. + +\b Add \c{-w+error} to treat warnings as errors. See \k{opt-w}. + +\b Add \c{-w+all} and \c{-w-all} to enable or disable all suppressible + warnings. See \k{opt-w}. + \H{cl-0.98.xx} NASM 0.98 Series diff --git a/doc/genps.pl b/doc/genps.pl index 5517d844..c7c23cf4 100755 --- a/doc/genps.pl +++ b/doc/genps.pl @@ -1,4 +1,37 @@ #!/usr/bin/perl +## -------------------------------------------------------------------------- +## +## Copyright 1996-2009 The NASM Authors - All Rights Reserved +## See the file AUTHORS included with the NASM distribution for +## the specific copyright holders. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following +## conditions are met: +## +## * Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above +## copyright notice, this list of conditions and the following +## disclaimer in the documentation and/or other materials provided +## with the distribution. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## -------------------------------------------------------------------------- + # # Format the documentation as PostScript # @@ -217,7 +250,8 @@ sub string2array($) my($s) = @_; my(@a) = (); - $s =~ s/ \- / $charcode{'endash'} /g; # Replace " - " with en dash + $s =~ s/\B\-\-\B/$charcode{'emdash'}/g; + $s =~ s/\B\-\B/ $charcode{'endash'} /g; while ( $s =~ /^(\s+|\S+)(.*)$/ ) { push(@a, [0,$1]); @@ -594,11 +628,16 @@ unshift(@ptypes, @tocptypes); undef @tocptypes; # # Add copyright notice to the beginning # -unshift(@paras, - [[0, $charcode{'copyright'}], [0, ' '], [0,$metadata{'year'}], - [0, ' '], string2array($metadata{'author'})], - [string2array($metadata{'license'})]); -unshift(@ptypes, 'norm', 'norm'); +@copyright_page = +([[0, $charcode{'copyright'}], + [0, ' '], [0, $metadata{'year'}], + [0, ' '], string2array($metadata{'author'}), + [0, ' '], string2array($metadata{'copyright_tail'})], + [string2array($metadata{'license'})], + [string2array($metadata{'auxinfo'})]); + +unshift(@paras, @copyright_page); +unshift(@ptypes, ('norm') x scalar(@copyright_page)); $npara = scalar(@paras); diff --git a/doc/genpsdriver.pl b/doc/genpsdriver.pl index dd9b7a7f..58e1f9a9 100644 --- a/doc/genpsdriver.pl +++ b/doc/genpsdriver.pl @@ -1,4 +1,37 @@ #!/usr/bin/perl +## -------------------------------------------------------------------------- +## +## Copyright 1996-2009 The NASM Authors - All Rights Reserved +## See the file AUTHORS included with the NASM distribution for +## the specific copyright holders. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following +## conditions are met: +## +## * Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above +## copyright notice, this list of conditions and the following +## disclaimer in the documentation and/or other materials provided +## with the distribution. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## -------------------------------------------------------------------------- + # # Runs the equivalent of the following command line: # diff --git a/doc/inslist.pl b/doc/inslist.pl index 7b560387..509de000 100644 --- a/doc/inslist.pl +++ b/doc/inslist.pl @@ -1,11 +1,40 @@ #!/usr/bin/perl +## -------------------------------------------------------------------------- +## +## Copyright 1996-2009 The NASM Authors - All Rights Reserved +## See the file AUTHORS included with the NASM distribution for +## the specific copyright holders. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following +## conditions are met: +## +## * Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above +## copyright notice, this list of conditions and the following +## disclaimer in the documentation and/or other materials provided +## with the distribution. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## -------------------------------------------------------------------------- + # # inslist.pl produce inslist.src # -# The Netwide Assembler is copyright (C) 1996 Simon Tatham and -# Julian Hall. All rights reserved. The software is -# redistributable under the licence given in the file "Licence" -# distributed in the NASM archive. # Opcode prefixes which need their own opcode tables # LONGER PREFIXES FIRST! diff --git a/doc/insref.src b/doc/insref.src deleted file mode 100644 index 1406f871..00000000 --- a/doc/insref.src +++ /dev/null @@ -1,6732 +0,0 @@ -\A{iref} x86 Instruction Reference - -This appendix provides a complete list of the machine instructions -which NASM will assemble, and a short description of the function of -each one. - -It is not intended to be an exhaustive documentation on the fine -details of the instructions' function, such as which exceptions they -can trigger: for such documentation, you should go to Intel's Web -site, \W{http://developer.intel.com/design/Pentium4/manuals/}\c{http://developer.intel.com/design/Pentium4/manuals/}. - -Instead, this appendix is intended primarily to provide -documentation on the way the instructions may be used within NASM. -For example, looking up \c{LOOP} will tell you that NASM allows -\c{CX} or \c{ECX} to be specified as an optional second argument to -the \c{LOOP} instruction, to enforce which of the two possible -counter registers should be used if the default is not the one -desired. - -The instructions are not quite listed in alphabetical order, since -groups of instructions with similar functions are lumped together in -the same entry. Most of them don't move very far from their -alphabetic position because of this. - - -\H{iref-opr} Key to Operand Specifications - -The instruction descriptions in this appendix specify their operands -using the following notation: - -\b Registers: \c{reg8} denotes an 8-bit \i{general purpose -register}, \c{reg16} denotes a 16-bit general purpose register, -\c{reg32} a 32-bit one and \c{reg64} a 64-bit one. \c{fpureg} denotes -one of the eight FPU stack registers, \c{mmxreg} denotes one of the -eight 64-bit MMX registers, and \c{segreg} denotes a segment register. -\c{xmmreg} denotes one of the 8, or 16 in x64 long mode, SSE XMM registers. -In addition, some registers (such as \c{AL}, \c{DX}, \c{ECX} or \c{RAX}) -may be specified explicitly. - -\b Immediate operands: \c{imm} denotes a generic \i{immediate operand}. -\c{imm8}, \c{imm16} and \c{imm32} are used when the operand is -intended to be a specific size. For some of these instructions, NASM -needs an explicit specifier: for example, \c{ADD ESP,16} could be -interpreted as either \c{ADD r/m32,imm32} or \c{ADD r/m32,imm8}. -NASM chooses the former by default, and so you must specify \c{ADD -ESP,BYTE 16} for the latter. There is a special case of the allowance -of an \c{imm64} for particular x64 versions of the MOV instruction. - -\b Memory references: \c{mem} denotes a generic \i{memory reference}; -\c{mem8}, \c{mem16}, \c{mem32}, \c{mem64} and \c{mem80} are used -when the operand needs to be a specific size. Again, a specifier is -needed in some cases: \c{DEC [address]} is ambiguous and will be -rejected by NASM. You must specify \c{DEC BYTE [address]}, \c{DEC -WORD [address]} or \c{DEC DWORD [address]} instead. - -\b \i{Restricted memory references}: one form of the \c{MOV} -instruction allows a memory address to be specified \e{without} -allowing the normal range of register combinations and effective -address processing. This is denoted by \c{memoffs8}, \c{memoffs16}, -\c{memoffs32} or \c{memoffs64}. - -\b Register or memory choices: many instructions can accept either a -register \e{or} a memory reference as an operand. \c{r/m8} is -shorthand for \c{reg8/mem8}; similarly \c{r/m16} and \c{r/m32}. -On legacy x86 modes, \c{r/m64} is MMX-related, and is shorthand for -\c{mmxreg/mem64}. When utilizing the x86-64 architecture extension, -\c{r/m64} denotes use of a 64-bit GPR as well, and is shorthand for -\c{reg64/mem64}. - - -\H{iref-opc} Key to Opcode Descriptions - -This appendix also provides the opcodes which NASM will generate for -each form of each instruction. The opcodes are listed in the -following way: - -\b A hex number, such as \c{3F}, indicates a fixed byte containing -that number. - -\b A hex number followed by \c{+r}, such as \c{C8+r}, indicates that -one of the operands to the instruction is a register, and the -`register value' of that register should be added to the hex number -to produce the generated byte. For example, EDX has register value -2, so the code \c{C8+r}, when the register operand is EDX, generates -the hex byte \c{CA}. Register values for specific registers are -given in \k{iref-rv}. - -\b A hex number followed by \c{+cc}, such as \c{40+cc}, indicates -that the instruction name has a condition code suffix, and the -numeric representation of the condition code should be added to the -hex number to produce the generated byte. For example, the code -\c{40+cc}, when the instruction contains the \c{NE} condition, -generates the hex byte \c{45}. Condition codes and their numeric -representations are given in \k{iref-cc}. - -\b A slash followed by a digit, such as \c{/2}, indicates that one -of the operands to the instruction is a memory address or register -(denoted \c{mem} or \c{r/m}, with an optional size). This is to be -encoded as an effective address, with a \i{ModR/M byte}, an optional -\i{SIB byte}, and an optional displacement, and the spare (register) -field of the ModR/M byte should be the digit given (which will be -from 0 to 7, so it fits in three bits). The encoding of effective -addresses is given in \k{iref-ea}. - -\b The code \c{/r} combines the above two: it indicates that one of -the operands is a memory address or \c{r/m}, and another is a -register, and that an effective address should be generated with the -spare (register) field in the ModR/M byte being equal to the -`register value' of the register operand. The encoding of effective -addresses is given in \k{iref-ea}; register values are given in -\k{iref-rv}. - -\b The codes \c{ib}, \c{iw} and \c{id} indicate that one of the -operands to the instruction is an immediate value, and that this is -to be encoded as a byte, little-endian word or little-endian -doubleword respectively. - -\b The codes \c{rb}, \c{rw} and \c{rd} indicate that one of the -operands to the instruction is an immediate value, and that the -\e{difference} between this value and the address of the end of the -instruction is to be encoded as a byte, word or doubleword -respectively. Where the form \c{rw/rd} appears, it indicates that -either \c{rw} or \c{rd} should be used according to whether assembly -is being performed in \c{BITS 16} or \c{BITS 32} state respectively. - -\b The codes \c{ow} and \c{od} indicate that one of the operands to -the instruction is a reference to the contents of a memory address -specified as an immediate value: this encoding is used in some forms -of the \c{MOV} instruction in place of the standard -effective-address mechanism. The displacement is encoded as a word -or doubleword. Again, \c{ow/od} denotes that \c{ow} or \c{od} should -be chosen according to the \c{BITS} setting. - -\b The codes \c{o16} and \c{o32} indicate that the given form of the -instruction should be assembled with operand size 16 or 32 bits. In -other words, \c{o16} indicates a \c{66} prefix in \c{BITS 32} state, -but generates no code in \c{BITS 16} state; and \c{o32} indicates a -\c{66} prefix in \c{BITS 16} state but generates nothing in \c{BITS -32}. - -\b The codes \c{a16} and \c{a32}, similarly to \c{o16} and \c{o32}, -indicate the address size of the given form of the instruction. -Where this does not match the \c{BITS} setting, a \c{67} prefix is -required. Please note that \c{a16} is useless in long mode as -16-bit addressing is depreciated on the x86-64 architecture extension. - - -\S{iref-rv} Register Values - -Where an instruction requires a register value, it is already -implicit in the encoding of the rest of the instruction what type of -register is intended: an 8-bit general-purpose register, a segment -register, a debug register, an MMX register, or whatever. Therefore -there is no problem with registers of different types sharing an -encoding value. - -Please note that for the register classes listed below, the register -extensions (REX) classes require the use of the REX prefix, in which -is only available when in long mode on the x86-64 processor. This -pretty much goes for any register that has a number higher than 7. - -The encodings for the various classes of register are: - -\b 8-bit general registers: \c{AL} is 0, \c{CL} is 1, \c{DL} is 2, -\c{BL} is 3, \c{AH} is 4, \c{CH} is 5, \c{DH} is 6 and \c{BH} is -7. Please note that \c{AH}, \c{BH}, \c{CH} and \c{DH} are not -addressable when using the REX prefix in long mode. - -\b 8-bit general register extensions (REX): \c{SPL} is 4, \c{BPL} is 5, -\c{SIL} is 6, \c{DIL} is 7, \c{R8B} is 8, \c{R9B} is 9, \c{R10B} is 10, -\c{R11B} is 11, \c{R12B} is 12, \c{R13B} is 13, \c{R14B} is 14 and -\c{R15B} is 15. - -\b 16-bit general registers: \c{AX} is 0, \c{CX} is 1, \c{DX} is 2, -\c{BX} is 3, \c{SP} is 4, \c{BP} is 5, \c{SI} is 6, and \c{DI} is 7. - -\b 16-bit general register extensions (REX): \c{R8W} is 8, \c{R9W} is 9, -\c{R10w} is 10, \c{R11W} is 11, \c{R12W} is 12, \c{R13W} is 13, \c{R14W} -is 14 and \c{R15W} is 15. - -\b 32-bit general registers: \c{EAX} is 0, \c{ECX} is 1, \c{EDX} is -2, \c{EBX} is 3, \c{ESP} is 4, \c{EBP} is 5, \c{ESI} is 6, and -\c{EDI} is 7. - -\b 32-bit general register extensions (REX): \c{R8D} is 8, \c{R9D} is 9, -\c{R10D} is 10, \c{R11D} is 11, \c{R12D} is 12, \c{R13D} is 13, \c{R14D} -is 14 and \c{R15D} is 15. - -\b 64-bit general register extensions (REX): \c{RAX} is 0, \c{RCX} is 1, -\c{RDX} is 2, \c{RBX} is 3, \c{RSP} is 4, \c{RBP} is 5, \c{RSI} is 6, -\c{RDI} is 7, \c{R8} is 8, \c{R9} is 9, \c{R10} is 10, \c{R11} is 11, -\c{R12} is 12, \c{R13} is 13, \c{R14} is 14 and \c{R15} is 15. - -\b \i{Segment registers}: \c{ES} is 0, \c{CS} is 1, \c{SS} is 2, \c{DS} -is 3, \c{FS} is 4, and \c{GS} is 5. - -\b \I{floating-point, registers}Floating-point registers: \c{ST0} -is 0, \c{ST1} is 1, \c{ST2} is 2, \c{ST3} is 3, \c{ST4} is 4, -\c{ST5} is 5, \c{ST6} is 6, and \c{ST7} is 7. - -\b 64-bit \i{MMX registers}: \c{MM0} is 0, \c{MM1} is 1, \c{MM2} is 2, -\c{MM3} is 3, \c{MM4} is 4, \c{MM5} is 5, \c{MM6} is 6, and \c{MM7} -is 7. - -\b 128-bit \i{XMM (SSE) registers}: \c{XMM0} is 0, \c{XMM1} is 1, -\c{XMM2} is 2, \c{XMM3} is 3, \c{XMM4} is 4, \c{XMM5} is 5, \c{XMM6} is -6 and \c{XMM7} is 7. - -\b 128-bit \i{XMM (SSE) register} extensions (REX): \c{XMM8} is 8, -\c{XMM9} is 9, \c{XMM10} is 10, \c{XMM11} is 11, \c{XMM12} is 12, -\c{XMM13} is 13, \c{XMM14} is 14 and \c{XMM15} is 15. - -\b \i{Control registers}: \c{CR0} is 0, \c{CR2} is 2, \c{CR3} is 3, -and \c{CR4} is 4. - -\b \i{Control register} extensions: \c{CR8} is 8. - -\b \i{Debug registers}: \c{DR0} is 0, \c{DR1} is 1, \c{DR2} is 2, -\c{DR3} is 3, \c{DR6} is 6, and \c{DR7} is 7. - -\b \i{Test registers}: \c{TR3} is 3, \c{TR4} is 4, \c{TR5} is 5, -\c{TR6} is 6, and \c{TR7} is 7. - -(Note that wherever a register name contains a number, that number -is also the register value for that register.) - - -\S{iref-cc} \i{Condition Codes} - -The available condition codes are given here, along with their -numeric representations as part of opcodes. Many of these condition -codes have synonyms, so several will be listed at a time. - -In the following descriptions, the word `either', when applied to two -possible trigger conditions, is used to mean `either or both'. If -`either but not both' is meant, the phrase `exactly one of' is used. - -\b \c{O} is 0 (trigger if the overflow flag is set); \c{NO} is 1. - -\b \c{B}, \c{C} and \c{NAE} are 2 (trigger if the carry flag is -set); \c{AE}, \c{NB} and \c{NC} are 3. - -\b \c{E} and \c{Z} are 4 (trigger if the zero flag is set); \c{NE} -and \c{NZ} are 5. - -\b \c{BE} and \c{NA} are 6 (trigger if either of the carry or zero -flags is set); \c{A} and \c{NBE} are 7. - -\b \c{S} is 8 (trigger if the sign flag is set); \c{NS} is 9. - -\b \c{P} and \c{PE} are 10 (trigger if the parity flag is set); -\c{NP} and \c{PO} are 11. - -\b \c{L} and \c{NGE} are 12 (trigger if exactly one of the sign and -overflow flags is set); \c{GE} and \c{NL} are 13. - -\b \c{LE} and \c{NG} are 14 (trigger if either the zero flag is set, -or exactly one of the sign and overflow flags is set); \c{G} and -\c{NLE} are 15. - -Note that in all cases, the sense of a condition code may be -reversed by changing the low bit of the numeric representation. - -For details of when an instruction sets each of the status flags, -see the individual instruction, plus the Status Flags reference -in \k{iref-Flags} - - -\S{iref-SSE-cc} \i{SSE Condition Predicates} - -The condition predicates for SSE comparison instructions are the -codes used as part of the opcode, to determine what form of -comparison is being carried out. In each case, the imm8 value is -the final byte of the opcode encoding, and the predicate is the -code used as part of the mnemonic for the instruction (equivalent -to the "cc" in an integer instruction that used a condition code). -The instructions that use this will give details of what the various -mnemonics are, this table is used to help you work out details of what -is happening. - -\c Predi- imm8 Description Relation where: Emula- Result QNaN -\c cate Encod- A Is 1st Operand tion if NaN Signal -\c ing B Is 2nd Operand Operand Invalid -\c -\c EQ 000B equal A = B False No -\c -\c LT 001B less-than A < B False Yes -\c -\c LE 010B less-than- A <= B False Yes -\c or-equal -\c -\c --- ---- greater A > B Swap False Yes -\c than Operands, -\c Use LT -\c -\c --- ---- greater- A >= B Swap False Yes -\c than-or-equal Operands, -\c Use LE -\c -\c UNORD 011B unordered A, B = Unordered True No -\c -\c NEQ 100B not-equal A != B True No -\c -\c NLT 101B not-less- NOT(A < B) True Yes -\c than -\c -\c NLE 110B not-less- NOT(A <= B) True Yes -\c than-or- -\c equal -\c -\c --- ---- not-greater NOT(A > B) Swap True Yes -\c than Operands, -\c Use NLT -\c -\c --- ---- not-greater NOT(A >= B) Swap True Yes -\c than- Operands, -\c or-equal Use NLE -\c -\c ORD 111B ordered A , B = Ordered False No - -The unordered relationship is true when at least one of the two -values being compared is a NaN or in an unsupported format. - -Note that the comparisons which are listed as not having a predicate -or encoding can only be achieved through software emulation, as -described in the "emulation" column. Note in particular that an -instruction such as \c{greater-than} is not the same as \c{NLE}, as, -unlike with the \c{CMP} instruction, it has to take into account the -possibility of one operand containing a NaN or an unsupported numeric -format. - - -\S{iref-Flags} \i{Status Flags} - -The status flags provide some information about the result of the -arithmetic instructions. This information can be used by conditional -instructions (such a \c{Jcc} and \c{CMOVcc}) as well as by some of -the other instructions (such as \c{ADC} and \c{INTO}). - -There are 6 status flags: - -\c CF - Carry flag. - -Set if an arithmetic operation generates a -carry or a borrow out of the most-significant bit of the result; -cleared otherwise. This flag indicates an overflow condition for -unsigned-integer arithmetic. It is also used in multiple-precision -arithmetic. - -\c PF - Parity flag. - -Set if the least-significant byte of the result contains an even -number of 1 bits; cleared otherwise. - -\c AF - Adjust flag. - -Set if an arithmetic operation generates a carry or a borrow -out of bit 3 of the result; cleared otherwise. This flag is used -in binary-coded decimal (BCD) arithmetic. - -\c ZF - Zero flag. - -Set if the result is zero; cleared otherwise. - -\c SF - Sign flag. - -Set equal to the most-significant bit of the result, which is the -sign bit of a signed integer. (0 indicates a positive value and 1 -indicates a negative value.) - -\c OF - Overflow flag. - -Set if the integer result is too large a positive number or too -small a negative number (excluding the sign-bit) to fit in the -destination operand; cleared otherwise. This flag indicates an -overflow condition for signed-integer (two's complement) arithmetic. - - -\S{iref-ea} Effective Address Encoding: \i{ModR/M} and \i{SIB} - -An \i{effective address} is encoded in up to three parts: a ModR/M -byte, an optional SIB byte, and an optional byte, word or doubleword -displacement field. - -The ModR/M byte consists of three fields: the \c{mod} field, ranging -from 0 to 3, in the upper two bits of the byte, the \c{r/m} field, -ranging from 0 to 7, in the lower three bits, and the spare -(register) field in the middle (bit 3 to bit 5). The spare field is -not relevant to the effective address being encoded, and either -contains an extension to the instruction opcode or the register -value of another operand. - -The ModR/M system can be used to encode a direct register reference -rather than a memory access. This is always done by setting the -\c{mod} field to 3 and the \c{r/m} field to the register value of -the register in question (it must be a general-purpose register, and -the size of the register must already be implicit in the encoding of -the rest of the instruction). In this case, the SIB byte and -displacement field are both absent. - -In 16-bit addressing mode (either \c{BITS 16} with no \c{67} prefix, -or \c{BITS 32} with a \c{67} prefix), the SIB byte is never used. -The general rules for \c{mod} and \c{r/m} (there is an exception, -given below) are: - -\b The \c{mod} field gives the length of the displacement field: 0 -means no displacement, 1 means one byte, and 2 means two bytes. - -\b The \c{r/m} field encodes the combination of registers to be -added to the displacement to give the accessed address: 0 means -\c{BX+SI}, 1 means \c{BX+DI}, 2 means \c{BP+SI}, 3 means \c{BP+DI}, -4 means \c{SI} only, 5 means \c{DI} only, 6 means \c{BP} only, and 7 -means \c{BX} only. - -However, there is a special case: - -\b If \c{mod} is 0 and \c{r/m} is 6, the effective address encoded -is not \c{[BP]} as the above rules would suggest, but instead -\c{[disp16]}: the displacement field is present and is two bytes -long, and no registers are added to the displacement. - -Therefore the effective address \c{[BP]} cannot be encoded as -efficiently as \c{[BX]}; so if you code \c{[BP]} in a program, NASM -adds a notional 8-bit zero displacement, and sets \c{mod} to 1, -\c{r/m} to 6, and the one-byte displacement field to 0. - -In 32-bit addressing mode (either \c{BITS 16} with a \c{67} prefix, -or \c{BITS 32} with no \c{67} prefix) the general rules (again, -there are exceptions) for \c{mod} and \c{r/m} are: - -\b The \c{mod} field gives the length of the displacement field: 0 -means no displacement, 1 means one byte, and 2 means four bytes. - -\b If only one register is to be added to the displacement, and it -is not \c{ESP}, the \c{r/m} field gives its register value, and the -SIB byte is absent. If the \c{r/m} field is 4 (which would encode -\c{ESP}), the SIB byte is present and gives the combination and -scaling of registers to be added to the displacement. - -If the SIB byte is present, it describes the combination of -registers (an optional base register, and an optional index register -scaled by multiplication by 1, 2, 4 or 8) to be added to the -displacement. The SIB byte is divided into the \c{scale} field, in -the top two bits, the \c{index} field in the next three, and the -\c{base} field in the bottom three. The general rules are: - -\b The \c{base} field encodes the register value of the base -register. - -\b The \c{index} field encodes the register value of the index -register, unless it is 4, in which case no index register is used -(so \c{ESP} cannot be used as an index register). - -\b The \c{scale} field encodes the multiplier by which the index -register is scaled before adding it to the base and displacement: 0 -encodes a multiplier of 1, 1 encodes 2, 2 encodes 4 and 3 encodes 8. - -The exceptions to the 32-bit encoding rules are: - -\b If \c{mod} is 0 and \c{r/m} is 5, the effective address encoded -is not \c{[EBP]} as the above rules would suggest, but instead -\c{[disp32]}: the displacement field is present and is four bytes -long, and no registers are added to the displacement. - -\b If \c{mod} is 0, \c{r/m} is 4 (meaning the SIB byte is present) -and \c{base} is 5, the effective address encoded is not -\c{[EBP+index]} as the above rules would suggest, but instead -\c{[disp32+index]}: the displacement field is present and is four -bytes long, and there is no base register (but the index register is -still processed in the normal way). - - -\S{iref-rex} Register Extensions: The \i{REX} Prefix - -The Register Extensions, or \i{REX} for short, prefix is the means -of accessing extended registers on the x86-64 architecture. \i{REX} -is considered an instruction prefix, but is required to be after -all other prefixes and thus immediately before the first instruction -opcode itself. So overall, \i{REX} can be thought of as an "Opcode -Prefix" instead. The \i{REX} prefix itself is indicated by a value -of 0x4X, where X is one of 16 different combinations of the actual -\i{REX} flags. - -The \i{REX} prefix flags consist of four 1-bit extensions fields. -These flags are found in the lower nibble of the actual \i{REX} -prefix opcode. Below is the list of \i{REX} prefix flags, from -high bit to low bit. - -\c{REX.W}: When set, this flag indicates the use of a 64-bit operand, -as opposed to the default of using 32-bit operands as found in 32-bit -Protected Mode. - -\c{REX.R}: When set, this flag extends the \c{reg (spare)} field of -the \c{ModRM} byte. Overall, this raises the amount of addressable -registers in this field from 8 to 16. - -\c{REX.X}: When set, this flag extends the \c{index} field of the -\c{SIB} byte. Overall, this raises the amount of addressable -registers in this field from 8 to 16. - -\c{REX.B}: When set, this flag extends the \c{r/m} field of the -\c{ModRM} byte. This flag can also represent an extension to the -opcode register \c{(/r)} field. The determination of which is used -varies depending on which instruction is used. Overall, this raises -the amount of addressable registers in these fields from 8 to 16. - -Interal use of the \i{REX} prefix by the processor is consistent, -yet non-trivial. Most instructions use the \i{REX} prefix as -indicated by the above flags. Some instructions require the \i{REX} -prefix to be present even if the flags are empty. Some instructions -default to a 64-bit operand and require the \i{REX} prefix only for -actual register extensions, and thus ignores the \c{REX.W} field -completely. - -At any rate, NASM is designed to handle, and fully supports, the -\i{REX} prefix internally. Please read the appropriate processor -documentation for further information on the \i{REX} prefix. - -You may have noticed that opcodes 0x40 through 0x4F are actually -opcodes for the INC/DEC instructions for each General Purpose -Register. This is, of course, correct... for legacy x86. While -in long mode, opcodes 0x40 through 0x4F are reserved for use as -the REX prefix. The other opcode forms of the INC/DEC instructions -are used instead. - - -\H{iref-flg} Key to Instruction Flags - -Given along with each instruction in this appendix is a set of -flags, denoting the type of the instruction. The types are as follows: - -\b \c{8086}, \c{186}, \c{286}, \c{386}, \c{486}, \c{PENT} and \c{P6} -denote the lowest processor type that supports the instruction. Most -instructions run on all processors above the given type; those that -do not are documented. The Pentium II contains no additional -instructions beyond the P6 (Pentium Pro); from the point of view of -its instruction set, it can be thought of as a P6 with MMX -capability. - -\b \c{3DNOW} indicates that the instruction is a 3DNow! one, and will -run on the AMD K6-2 and later processors. ATHLON extensions to the -3DNow! instruction set are documented as such. - -\b \c{CYRIX} indicates that the instruction is specific to Cyrix -processors, for example the extra MMX instructions in the Cyrix -extended MMX instruction set. - -\b \c{FPU} indicates that the instruction is a floating-point one, -and will only run on machines with a coprocessor (automatically -including 486DX, Pentium and above). - -\b \c{KATMAI} indicates that the instruction was introduced as part -of the Katmai New Instruction set. These instructions are available -on the Pentium III and later processors. Those which are not -specifically SSE instructions are also available on the AMD Athlon. - -\b \c{MMX} indicates that the instruction is an MMX one, and will -run on MMX-capable Pentium processors and the Pentium II. - -\b \c{PRIV} indicates that the instruction is a protected-mode -management instruction. Many of these may only be used in protected -mode, or only at privilege level zero. - -\b \c{SSE} and \c{SSE2} indicate that the instruction is a Streaming -SIMD Extension instruction. These instructions operate on multiple -values in a single operation. SSE was introduced with the Pentium III -and SSE2 was introduced with the Pentium 4. - -\b \c{UNDOC} indicates that the instruction is an undocumented one, -and not part of the official Intel Architecture; it may or may not -be supported on any given machine. - -\b \c{WILLAMETTE} indicates that the instruction was introduced as -part of the new instruction set in the Pentium 4 and Intel Xeon -processors. These instructions are also known as SSE2 instructions. - -\b \c{X64} indicates that the instruction was introduced as part of -the new instruction set in the x86-64 architecture extension, -commonly referred to as x64, AMD64 or EM64T. - - -\H{iref-inst} x86 Instruction Set - - -\S{insAAA} \i\c{AAA}, \i\c{AAS}, \i\c{AAM}, \i\c{AAD}: ASCII -Adjustments - -\c AAA ; 37 [8086] - -\c AAS ; 3F [8086] - -\c AAD ; D5 0A [8086] -\c AAD imm ; D5 ib [8086] - -\c AAM ; D4 0A [8086] -\c AAM imm ; D4 ib [8086] - -These instructions are used in conjunction with the add, subtract, -multiply and divide instructions to perform binary-coded decimal -arithmetic in \e{unpacked} (one BCD digit per byte - easy to -translate to and from \c{ASCII}, hence the instruction names) form. -There are also packed BCD instructions \c{DAA} and \c{DAS}: see -\k{insDAA}. - -\b \c{AAA} (ASCII Adjust After Addition) should be used after a -one-byte \c{ADD} instruction whose destination was the \c{AL} -register: by means of examining the value in the low nibble of -\c{AL} and also the auxiliary carry flag \c{AF}, it determines -whether the addition has overflowed, and adjusts it (and sets -the carry flag) if so. You can add long BCD strings together -by doing \c{ADD}/\c{AAA} on the low digits, then doing -\c{ADC}/\c{AAA} on each subsequent digit. - -\b \c{AAS} (ASCII Adjust AL After Subtraction) works similarly to -\c{AAA}, but is for use after \c{SUB} instructions rather than -\c{ADD}. - -\b \c{AAM} (ASCII Adjust AX After Multiply) is for use after you -have multiplied two decimal digits together and left the result -in \c{AL}: it divides \c{AL} by ten and stores the quotient in -\c{AH}, leaving the remainder in \c{AL}. The divisor 10 can be -changed by specifying an operand to the instruction: a particularly -handy use of this is \c{AAM 16}, causing the two nibbles in \c{AL} -to be separated into \c{AH} and \c{AL}. - -\b \c{AAD} (ASCII Adjust AX Before Division) performs the inverse -operation to \c{AAM}: it multiplies \c{AH} by ten, adds it to -\c{AL}, and sets \c{AH} to zero. Again, the multiplier 10 can -be changed. - - -\S{insADC} \i\c{ADC}: Add with Carry - -\c ADC r/m8,reg8 ; 10 /r [8086] -\c ADC r/m16,reg16 ; o16 11 /r [8086] -\c ADC r/m32,reg32 ; o32 11 /r [386] - -\c ADC reg8,r/m8 ; 12 /r [8086] -\c ADC reg16,r/m16 ; o16 13 /r [8086] -\c ADC reg32,r/m32 ; o32 13 /r [386] - -\c ADC r/m8,imm8 ; 80 /2 ib [8086] -\c ADC r/m16,imm16 ; o16 81 /2 iw [8086] -\c ADC r/m32,imm32 ; o32 81 /2 id [386] - -\c ADC r/m16,imm8 ; o16 83 /2 ib [8086] -\c ADC r/m32,imm8 ; o32 83 /2 ib [386] - -\c ADC AL,imm8 ; 14 ib [8086] -\c ADC AX,imm16 ; o16 15 iw [8086] -\c ADC EAX,imm32 ; o32 15 id [386] - -\c{ADC} performs integer addition: it adds its two operands -together, plus the value of the carry flag, and leaves the result in -its destination (first) operand. The destination operand can be a -register or a memory location. The source operand can be a register, -a memory location or an immediate value. - -The flags are set according to the result of the operation: in -particular, the carry flag is affected and can be used by a -subsequent \c{ADC} instruction. - -In the forms with an 8-bit immediate second operand and a longer -first operand, the second operand is considered to be signed, and is -sign-extended to the length of the first operand. In these cases, -the \c{BYTE} qualifier is necessary to force NASM to generate this -form of the instruction. - -To add two numbers without also adding the contents of the carry -flag, use \c{ADD} (\k{insADD}). - - -\S{insADD} \i\c{ADD}: Add Integers - -\c ADD r/m8,reg8 ; 00 /r [8086] -\c ADD r/m16,reg16 ; o16 01 /r [8086] -\c ADD r/m32,reg32 ; o32 01 /r [386] - -\c ADD reg8,r/m8 ; 02 /r [8086] -\c ADD reg16,r/m16 ; o16 03 /r [8086] -\c ADD reg32,r/m32 ; o32 03 /r [386] - -\c ADD r/m8,imm8 ; 80 /7 ib [8086] -\c ADD r/m16,imm16 ; o16 81 /7 iw [8086] -\c ADD r/m32,imm32 ; o32 81 /7 id [386] - -\c ADD r/m16,imm8 ; o16 83 /7 ib [8086] -\c ADD r/m32,imm8 ; o32 83 /7 ib [386] - -\c ADD AL,imm8 ; 04 ib [8086] -\c ADD AX,imm16 ; o16 05 iw [8086] -\c ADD EAX,imm32 ; o32 05 id [386] - -\c{ADD} performs integer addition: it adds its two operands -together, and leaves the result in its destination (first) operand. -The destination operand can be a register or a memory location. -The source operand can be a register, a memory location or an -immediate value. - -The flags are set according to the result of the operation: in -particular, the carry flag is affected and can be used by a -subsequent \c{ADC} instruction. - -In the forms with an 8-bit immediate second operand and a longer -first operand, the second operand is considered to be signed, and is -sign-extended to the length of the first operand. In these cases, -the \c{BYTE} qualifier is necessary to force NASM to generate this -form of the instruction. - - -\S{insADDPD} \i\c{ADDPD}: ADD Packed Double-Precision FP Values - -\c ADDPD xmm1,xmm2/mem128 ; 66 0F 58 /r [WILLAMETTE,SSE2] - -\c{ADDPD} performs addition on each of two packed double-precision -FP value pairs. - -\c dst[0-63] := dst[0-63] + src[0-63], -\c dst[64-127] := dst[64-127] + src[64-127]. - -The destination is an \c{XMM} register. The source operand can be -either an \c{XMM} register or a 128-bit memory location. - - -\S{insADDPS} \i\c{ADDPS}: ADD Packed Single-Precision FP Values - -\c ADDPS xmm1,xmm2/mem128 ; 0F 58 /r [KATMAI,SSE] - -\c{ADDPS} performs addition on each of four packed single-precision -FP value pairs - -\c dst[0-31] := dst[0-31] + src[0-31], -\c dst[32-63] := dst[32-63] + src[32-63], -\c dst[64-95] := dst[64-95] + src[64-95], -\c dst[96-127] := dst[96-127] + src[96-127]. - -The destination is an \c{XMM} register. The source operand can be -either an \c{XMM} register or a 128-bit memory location. - - -\S{insADDSD} \i\c{ADDSD}: ADD Scalar Double-Precision FP Values - -\c ADDSD xmm1,xmm2/mem64 ; F2 0F 58 /r [KATMAI,SSE] - -\c{ADDSD} adds the low double-precision FP values from the source -and destination operands and stores the double-precision FP result -in the destination operand. - -\c dst[0-63] := dst[0-63] + src[0-63], -\c dst[64-127) remains unchanged. - -The destination is an \c{XMM} register. The source operand can be -either an \c{XMM} register or a 64-bit memory location. - - -\S{insADDSS} \i\c{ADDSS}: ADD Scalar Single-Precision FP Values - -\c ADDSS xmm1,xmm2/mem32 ; F3 0F 58 /r [WILLAMETTE,SSE2] - -\c{ADDSS} adds the low single-precision FP values from the source -and destination operands and stores the single-precision FP result -in the destination operand. - -\c dst[0-31] := dst[0-31] + src[0-31], -\c dst[32-127] remains unchanged. - -The destination is an \c{XMM} register. The source operand can be -either an \c{XMM} register or a 32-bit memory location. - - -\S{insAND} \i\c{AND}: Bitwise AND - -\c AND r/m8,reg8 ; 20 /r [8086] -\c AND r/m16,reg16 ; o16 21 /r [8086] -\c AND r/m32,reg32 ; o32 21 /r [386] - -\c AND reg8,r/m8 ; 22 /r [8086] -\c AND reg16,r/m16 ; o16 23 /r [8086] -\c AND reg32,r/m32 ; o32 23 /r [386] - -\c AND r/m8,imm8 ; 80 /4 ib [8086] -\c AND r/m16,imm16 ; o16 81 /4 iw [8086] -\c AND r/m32,imm32 ; o32 81 /4 id [386] - -\c AND r/m16,imm8 ; o16 83 /4 ib [8086] -\c AND r/m32,imm8 ; o32 83 /4 ib [386] - -\c AND AL,imm8 ; 24 ib [8086] -\c AND AX,imm16 ; o16 25 iw [8086] -\c AND EAX,imm32 ; o32 25 id [386] - -\c{AND} performs a bitwise AND operation between its two operands -(i.e. each bit of the result is 1 if and only if the corresponding -bits of the two inputs were both 1), and stores the result in the -destination (first) operand. The destination operand can be a -register or a memory location. The source operand can be a register, -a memory location or an immediate value. - -In the forms with an 8-bit immediate second operand and a longer -first operand, the second operand is considered to be signed, and is -sign-extended to the length of the first operand. In these cases, -the \c{BYTE} qualifier is necessary to force NASM to generate this -form of the instruction. - -The \c{MMX} instruction \c{PAND} (see \k{insPAND}) performs the same -operation on the 64-bit \c{MMX} registers. - - -\S{insANDNPD} \i\c{ANDNPD}: Bitwise Logical AND NOT of -Packed Double-Precision FP Values - -\c ANDNPD xmm1,xmm2/mem128 ; 66 0F 55 /r [WILLAMETTE,SSE2] - -\c{ANDNPD} inverts the bits of the two double-precision -floating-point values in the destination register, and then -performs a logical AND between the two double-precision -floating-point values in the source operand and the temporary -inverted result, storing the result in the destination register. - -\c dst[0-63] := src[0-63] AND NOT dst[0-63], -\c dst[64-127] := src[64-127] AND NOT dst[64-127]. - -The destination is an \c{XMM} register. The source operand can be -either an \c{XMM} register or a 128-bit memory location. - - -\S{insANDNPS} \i\c{ANDNPS}: Bitwise Logical AND NOT of -Packed Single-Precision FP Values - -\c ANDNPS xmm1,xmm2/mem128 ; 0F 55 /r [KATMAI,SSE] - -\c{ANDNPS} inverts the bits of the four single-precision -floating-point values in the destination register, and then -performs a logical AND between the four single-precision -floating-point values in the source operand and the temporary -inverted result, storing the result in the destination register. - -\c dst[0-31] := src[0-31] AND NOT dst[0-31], -\c dst[32-63] := src[32-63] AND NOT dst[32-63], -\c dst[64-95] := src[64-95] AND NOT dst[64-95], -\c dst[96-127] := src[96-127] AND NOT dst[96-127]. - -The destination is an \c{XMM} register. The source operand can be -either an \c{XMM} register or a 128-bit memory location. - - -\S{insANDPD} \i\c{ANDPD}: Bitwise Logical AND For Single FP - -\c ANDPD xmm1,xmm2/mem128 ; 66 0F 54 /r [WILLAMETTE,SSE2] - -\c{ANDPD} performs a bitwise logical AND of the two double-precision -floating point values in the source and destination operand, and -stores the result in the destination register. - -\c dst[0-63] := src[0-63] AND dst[0-63], -\c dst[64-127] := src[64-127] AND dst[64-127]. - -The destination is an \c{XMM} register. The source operand can be -either an \c{XMM} register or a 128-bit memory location. - - -\S{insANDPS} \i\c{ANDPS}: Bitwise Logical AND For Single FP - -\c ANDPS xmm1,xmm2/mem128 ; 0F 54 /r [KATMAI,SSE] - -\c{ANDPS} performs a bitwise logical AND of the four single-precision -floating point values in the source and destination operand, and -stores the result in the destination register. - -\c dst[0-31] := src[0-31] AND dst[0-31], -\c dst[32-63] := src[32-63] AND dst[32-63], -\c dst[64-95] := src[64-95] AND dst[64-95], -\c dst[96-127] := src[96-127] AND dst[96-127]. - -The destination is an \c{XMM} register. The source operand can be -either an \c{XMM} register or a 128-bit memory location. - - -\S{insARPL} \i\c{ARPL}: Adjust RPL Field of Selector - -\c ARPL r/m16,reg16 ; 63 /r [286,PRIV] - -\c{ARPL} expects its two word operands to be segment selectors. It -adjusts the \i\c{RPL} (requested privilege level - stored in the bottom -two bits of the selector) field of the destination (first) operand -to ensure that it is no less (i.e. no more privileged than) the \c{RPL} -field of the source operand. The zero flag is set if and only if a -change had to be made. - - -\S{insBOUND} \i\c{BOUND}: Check Array Index against Bounds - -\c BOUND reg16,mem ; o16 62 /r [186] -\c BOUND reg32,mem ; o32 62 /r [386] - -\c{BOUND} expects its second operand to point to an area of memory -containing two signed values of the same size as its first operand -(i.e. two words for the 16-bit form; two doublewords for the 32-bit -form). It performs two signed comparisons: if the value in the -register passed as its first operand is less than the first of the -in-memory values, or is greater than or equal to the second, it -throws a \c{BR} exception. Otherwise, it does nothing. - - -\S{insBSF} \i\c{BSF}, \i\c{BSR}: Bit Scan - -\c BSF reg16,r/m16 ; o16 0F BC /r [386] -\c BSF reg32,r/m32 ; o32 0F BC /r [386] - -\c BSR reg16,r/m16 ; o16 0F BD /r [386] -\c BSR reg32,r/m32 ; o32 0F BD /r [386] - -\b \c{BSF} searches for the least significant set bit in its source -(second) operand, and if it finds one, stores the index in -its destination (first) operand. If no set bit is found, the -contents of the destination operand are undefined. If the source -operand is zero, the zero flag is set. - -\b \c{BSR} performs the same function, but searches from the top -instead, so it finds the most significant set bit. - -Bit indices are from 0 (least significant) to 15 or 31 (most -significant). The destination operand can only be a register. -The source operand can be a register or a memory location. - - -\S{insBSWAP} \i\c{BSWAP}: Byte Swap - -\c BSWAP reg32 ; o32 0F C8+r [486] - -\c{BSWAP} swaps the order of the four bytes of a 32-bit register: -bits 0-7 exchange places with bits 24-31, and bits 8-15 swap with -bits 16-23. There is no explicit 16-bit equivalent: to byte-swap -\c{AX}, \c{BX}, \c{CX} or \c{DX}, \c{XCHG} can be used. When \c{BSWAP} -is used with a 16-bit register, the result is undefined. - - -\S{insBT} \i\c{BT}, \i\c{BTC}, \i\c{BTR}, \i\c{BTS}: Bit Test - -\c BT r/m16,reg16 ; o16 0F A3 /r [386] -\c BT r/m32,reg32 ; o32 0F A3 /r [386] -\c BT r/m16,imm8 ; o16 0F BA /4 ib [386] -\c BT r/m32,imm8 ; o32 0F BA /4 ib [386] - -\c BTC r/m16,reg16 ; o16 0F BB /r [386] -\c BTC r/m32,reg32 ; o32 0F BB /r [386] -\c BTC r/m16,imm8 ; o16 0F BA /7 ib [386] -\c BTC r/m32,imm8 ; o32 0F BA /7 ib [386] - -\c BTR r/m16,reg16 ; o16 0F B3 /r [386] -\c BTR r/m32,reg32 ; o32 0F B3 /r [386] -\c BTR r/m16,imm8 ; o16 0F BA /6 ib [386] -\c BTR r/m32,imm8 ; o32 0F BA /6 ib [386] - -\c BTS r/m16,reg16 ; o16 0F AB /r [386] -\c BTS r/m32,reg32 ; o32 0F AB /r [386] -\c BTS r/m16,imm ; o16 0F BA /5 ib [386] -\c BTS r/m32,imm ; o32 0F BA /5 ib [386] - -These instructions all test one bit of their first operand, whose -index is given by the second operand, and store the value of that -bit into the carry flag. Bit indices are from 0 (least significant) -to 15 or 31 (most significant). - -In addition to storing the original value of the bit into the carry -flag, \c{BTR} also resets (clears) the bit in the operand itself. -\c{BTS} sets the bit, and \c{BTC} complements the bit. \c{BT} does -not modify its operands. - -The destination can be a register or a memory location. The source can -be a register or an immediate value. - -If the destination operand is a register, the bit offset should be -in the range 0-15 (for 16-bit operands) or 0-31 (for 32-bit operands). -An immediate value outside these ranges will be taken modulo 16/32 -by the processor. - -If the destination operand is a memory location, then an immediate -bit offset follows the same rules as for a register. If the bit offset -is in a register, then it can be anything within the signed range of -the register used (ie, for a 32-bit operand, it can be (-2^31) to (2^31 - 1) - - -\S{insCALL} \i\c{CALL}: Call Subroutine - -\c CALL imm ; E8 rw/rd [8086] -\c CALL imm:imm16 ; o16 9A iw iw [8086] -\c CALL imm:imm32 ; o32 9A id iw [386] -\c CALL FAR mem16 ; o16 FF /3 [8086] -\c CALL FAR mem32 ; o32 FF /3 [386] -\c CALL r/m16 ; o16 FF /2 [8086] -\c CALL r/m32 ; o32 FF /2 [386] - -\c{CALL} calls a subroutine, by means of pushing the current -instruction pointer (\c{IP}) and optionally \c{CS} as well on the -stack, and then jumping to a given address. - -\c{CS} is pushed as well as \c{IP} if and only if the call is a far -call, i.e. a destination segment address is specified in the -instruction. The forms involving two colon-separated arguments are -far calls; so are the \c{CALL FAR mem} forms. - -The immediate \i{near call} takes one of two forms (\c{call imm16/imm32}, -determined by the current segment size limit. For 16-bit operands, -you would use \c{CALL 0x1234}, and for 32-bit operands you would use -\c{CALL 0x12345678}. The value passed as an operand is a relative offset. - -You can choose between the two immediate \i{far call} forms -(\c{CALL imm:imm}) by the use of the \c{WORD} and \c{DWORD} keywords: -\c{CALL WORD 0x1234:0x5678}) or \c{CALL DWORD 0x1234:0x56789abc}. - -The \c{CALL FAR mem} forms execute a far call by loading the -destination address out of memory. The address loaded consists of 16 -or 32 bits of offset (depending on the operand size), and 16 bits of -segment. The operand size may be overridden using \c{CALL WORD FAR -mem} or \c{CALL DWORD FAR mem}. - -The \c{CALL r/m} forms execute a \i{near call} (within the same -segment), loading the destination address out of memory or out of a -register. The keyword \c{NEAR} may be specified, for clarity, in -these forms, but is not necessary. Again, operand size can be -overridden using \c{CALL WORD mem} or \c{CALL DWORD mem}. - -As a convenience, NASM does not require you to call a far procedure -symbol by coding the cumbersome \c{CALL SEG routine:routine}, but -instead allows the easier synonym \c{CALL FAR routine}. - -The \c{CALL r/m} forms given above are near calls; NASM will accept -the \c{NEAR} keyword (e.g. \c{CALL NEAR [address]}), even though it -is not strictly necessary. - - -\S{insCBW} \i\c{CBW}, \i\c{CWD}, \i\c{CDQ}, \i\c{CWDE}: Sign Extensions - -\c CBW ; o16 98 [8086] -\c CWDE ; o32 98 [386] - -\c CWD ; o16 99 [8086] -\c CDQ ; o32 99 [386] - -All these instructions sign-extend a short value into a longer one, -by replicating the top bit of the original value to fill the -extended one. - -\c{CBW} extends \c{AL} into \c{AX} by repeating the top bit of -\c{AL} in every bit of \c{AH}. \c{CWDE} extends \c{AX} into -\c{EAX}. \c{CWD} extends \c{AX} into \c{DX:AX} by repeating -the top bit of \c{AX} throughout \c{DX}, and \c{CDQ} extends -\c{EAX} into \c{EDX:EAX}. - - -\S{insCLC} \i\c{CLC}, \i\c{CLD}, \i\c{CLI}, \i\c{CLTS}: Clear Flags - -\c CLC ; F8 [8086] -\c CLD ; FC [8086] -\c CLI ; FA [8086] -\c CLTS ; 0F 06 [286,PRIV] - -These instructions clear various flags. \c{CLC} clears the carry -flag; \c{CLD} clears the direction flag; \c{CLI} clears the -interrupt flag (thus disabling interrupts); and \c{CLTS} clears the -task-switched (\c{TS}) flag in \c{CR0}. - -To set the carry, direction, or interrupt flags, use the \c{STC}, -\c{STD} and \c{STI} instructions (\k{insSTC}). To invert the carry -flag, use \c{CMC} (\k{insCMC}). - - -\S{insCLFLUSH} \i\c{CLFLUSH}: Flush Cache Line - -\c CLFLUSH mem ; 0F AE /7 [WILLAMETTE,SSE2] - -\c{CLFLUSH} invalidates the cache line that contains the linear address -specified by the source operand from all levels of the processor cache -hierarchy (data and instruction). If, at any level of the cache -hierarchy, the line is inconsistent with memory (dirty) it is written -to memory before invalidation. The source operand points to a -byte-sized memory location. - -Although \c{CLFLUSH} is flagged \c{SSE2} and above, it may not be -present on all processors which have \c{SSE2} support, and it may be -supported on other processors; the \c{CPUID} instruction (\k{insCPUID}) -will return a bit which indicates support for the \c{CLFLUSH} instruction. - - -\S{insCMC} \i\c{CMC}: Complement Carry Flag - -\c CMC ; F5 [8086] - -\c{CMC} changes the value of the carry flag: if it was 0, it sets it -to 1, and vice versa. - - -\S{insCMOVcc} \i\c{CMOVcc}: Conditional Move - -\c CMOVcc reg16,r/m16 ; o16 0F 40+cc /r [P6] -\c CMOVcc reg32,r/m32 ; o32 0F 40+cc /r [P6] - -\c{CMOV} moves its source (second) operand into its destination -(first) operand if the given condition code is satisfied; otherwise -it does nothing. - -For a list of condition codes, see \k{iref-cc}. - -Although the \c{CMOV} instructions are flagged \c{P6} and above, they -may not be supported by all Pentium Pro processors; the \c{CPUID} -instruction (\k{insCPUID}) will return a bit which indicates whether -conditional moves are supported. - - -\S{insCMP} \i\c{CMP}: Compare Integers - -\c CMP r/m8,reg8 ; 38 /r [8086] -\c CMP r/m16,reg16 ; o16 39 /r [8086] -\c CMP r/m32,reg32 ; o32 39 /r [386] - -\c CMP reg8,r/m8 ; 3A /r [8086] -\c CMP reg16,r/m16 ; o16 3B /r [8086] -\c CMP reg32,r/m32 ; o32 3B /r [386] - -\c CMP r/m8,imm8 ; 80 /7 ib [8086] -\c CMP r/m16,imm16 ; o16 81 /7 iw [8086] -\c CMP r/m32,imm32 ; o32 81 /7 id [386] - -\c CMP r/m16,imm8 ; o16 83 /7 ib [8086] -\c CMP r/m32,imm8 ; o32 83 /7 ib [386] - -\c CMP AL,imm8 ; 3C ib [8086] -\c CMP AX,imm16 ; o16 3D iw [8086] -\c CMP EAX,imm32 ; o32 3D id [386] - -\c{CMP} performs a `mental' subtraction of its second operand from -its first operand, and affects the flags as if the subtraction had -taken place, but does not store the result of the subtraction -anywhere. - -In the forms with an 8-bit immediate second operand and a longer -first operand, the second operand is considered to be signed, and is -sign-extended to the length of the first operand. In these cases, -the \c{BYTE} qualifier is necessary to force NASM to generate this -form of the instruction. - -The destination operand can be a register or a memory location. The -source can be a register, memory location or an immediate value of -the same size as the destination. - - -\S{insCMPccPD} \i\c{CMPccPD}: Packed Double-Precision FP Compare -\I\c{CMPEQPD} \I\c{CMPLTPD} \I\c{CMPLEPD} \I\c{CMPUNORDPD} -\I\c{CMPNEQPD} \I\c{CMPNLTPD} \I\c{CMPNLEPD} \I\c{CMPORDPD} - -\c CMPPD xmm1,xmm2/mem128,imm8 ; 66 0F C2 /r ib [WILLAMETTE,SSE2] - -\c CMPEQPD xmm1,xmm2/mem128 ; 66 0F C2 /r 00 [WILLAMETTE,SSE2] -\c CMPLTPD xmm1,xmm2/mem128 ; 66 0F C2 /r 01 [WILLAMETTE,SSE2] -\c CMPLEPD xmm1,xmm2/mem128 ; 66 0F C2 /r 02 [WILLAMETTE,SSE2] -\c CMPUNORDPD xmm1,xmm2/mem128 ; 66 0F C2 /r 03 [WILLAMETTE,SSE2] -\c CMPNEQPD xmm1,xmm2/mem128 ; 66 0F C2 /r 04 [WILLAMETTE,SSE2] -\c CMPNLTPD xmm1,xmm2/mem128 ; 66 0F C2 /r 05 [WILLAMETTE,SSE2] -\c CMPNLEPD xmm1,xmm2/mem128 ; 66 0F C2 /r 06 [WILLAMETTE,SSE2] -\c CMPORDPD xmm1,xmm2/mem128 ; 66 0F C2 /r 07 [WILLAMETTE,SSE2] - -The \c{CMPccPD} instructions compare the two packed double-precision -FP values in the source and destination operands, and returns the -result of the comparison in the destination register. The result of -each comparison is a quadword mask of all 1s (comparison true) or -all 0s (comparison false). - -The destination is an \c{XMM} register. The source can be either an -\c{XMM} register or a 128-bit memory location. - -The third operand is an 8-bit immediate value, of which the low 3 -bits define the type of comparison. For ease of programming, the -8 two-operand pseudo-instructions are provided, with the third -operand already filled in. The \I{Condition Predicates} -\c{Condition Predicates} are: - -\c EQ 0 Equal -\c LT 1 Less-than -\c LE 2 Less-than-or-equal -\c UNORD 3 Unordered -\c NE 4 Not-equal -\c NLT 5 Not-less-than -\c NLE 6 Not-less-than-or-equal -\c ORD 7 Ordered - -For more details of the comparison predicates, and details of how -to emulate the "greater-than" equivalents, see \k{iref-SSE-cc} - - -\S{insCMPccPS} \i\c{CMPccPS}: Packed Single-Precision FP Compare -\I\c{CMPEQPS} \I\c{CMPLTPS} \I\c{CMPLEPS} \I\c{CMPUNORDPS} -\I\c{CMPNEQPS} \I\c{CMPNLTPS} \I\c{CMPNLEPS} \I\c{CMPORDPS} - -\c CMPPS xmm1,xmm2/mem128,imm8 ; 0F C2 /r ib [KATMAI,SSE] - -\c CMPEQPS xmm1,xmm2/mem128 ; 0F C2 /r 00 [KATMAI,SSE] -\c CMPLTPS xmm1,xmm2/mem128 ; 0F C2 /r 01 [KATMAI,SSE] -\c CMPLEPS xmm1,xmm2/mem128 ; 0F C2 /r 02 [KATMAI,SSE] -\c CMPUNORDPS xmm1,xmm2/mem128 ; 0F C2 /r 03 [KATMAI,SSE] -\c CMPNEQPS xmm1,xmm2/mem128 ; 0F C2 /r 04 [KATMAI,SSE] -\c CMPNLTPS xmm1,xmm2/mem128 ; 0F C2 /r 05 [KATMAI,SSE] -\c CMPNLEPS xmm1,xmm2/mem128 ; 0F C2 /r 06 [KATMAI,SSE] -\c CMPORDPS xmm1,xmm2/mem128 ; 0F C2 /r 07 [KATMAI,SSE] - -The \c{CMPccPS} instructions compare the two packed single-precision -FP values in the source and destination operands, and returns the -result of the comparison in the destination register. The result of -each comparison is a doubleword mask of all 1s (comparison true) or -all 0s (comparison false). - -The destination is an \c{XMM} register. The source can be either an -\c{XMM} register or a 128-bit memory location. - -The third operand is an 8-bit immediate value, of which the low 3 -bits define the type of comparison. For ease of programming, the -8 two-operand pseudo-instructions are provided, with the third -operand already filled in. The \I{Condition Predicates} -\c{Condition Predicates} are: - -\c EQ 0 Equal -\c LT 1 Less-than -\c LE 2 Less-than-or-equal -\c UNORD 3 Unordered -\c NE 4 Not-equal -\c NLT 5 Not-less-than -\c NLE 6 Not-less-than-or-equal -\c ORD 7 Ordered - -For more details of the comparison predicates, and details of how -to emulate the "greater-than" equivalents, see \k{iref-SSE-cc} - - -\S{insCMPSB} \i\c{CMPSB}, \i\c{CMPSW}, \i\c{CMPSD}: Compare Strings - -\c CMPSB ; A6 [8086] -\c CMPSW ; o16 A7 [8086] -\c CMPSD ; o32 A7 [386] - -\c{CMPSB} compares the byte at \c{[DS:SI]} or \c{[DS:ESI]} with the -byte at \c{[ES:DI]} or \c{[ES:EDI]}, and sets the flags accordingly. -It then increments or decrements (depending on the direction flag: -increments if the flag is clear, decrements if it is set) \c{SI} and -\c{DI} (or \c{ESI} and \c{EDI}). - -The registers used are \c{SI} and \c{DI} if the address size is 16 -bits, and \c{ESI} and \c{EDI} if it is 32 bits. If you need to use -an address size not equal to the current \c{BITS} setting, you can -use an explicit \i\c{a16} or \i\c{a32} prefix. - -The segment register used to load from \c{[SI]} or \c{[ESI]} can be -overridden by using a segment register name as a prefix (for -example, \c{ES CMPSB}). The use of \c{ES} for the load from \c{[DI]} -or \c{[EDI]} cannot be overridden. - -\c{CMPSW} and \c{CMPSD} work in the same way, but they compare a -word or a doubleword instead of a byte, and increment or decrement -the addressing registers by 2 or 4 instead of 1. - -The \c{REPE} and \c{REPNE} prefixes (equivalently, \c{REPZ} and -\c{REPNZ}) may be used to repeat the instruction up to \c{CX} (or -\c{ECX} - again, the address size chooses which) times until the -first unequal or equal byte is found. - - -\S{insCMPccSD} \i\c{CMPccSD}: Scalar Double-Precision FP Compare -\I\c{CMPEQSD} \I\c{CMPLTSD} \I\c{CMPLESD} \I\c{CMPUNORDSD} -\I\c{CMPNEQSD} \I\c{CMPNLTSD} \I\c{CMPNLESD} \I\c{CMPORDSD} - -\c CMPSD xmm1,xmm2/mem64,imm8 ; F2 0F C2 /r ib [WILLAMETTE,SSE2] - -\c CMPEQSD xmm1,xmm2/mem64 ; F2 0F C2 /r 00 [WILLAMETTE,SSE2] -\c CMPLTSD xmm1,xmm2/mem64 ; F2 0F C2 /r 01 [WILLAMETTE,SSE2] -\c CMPLESD xmm1,xmm2/mem64 ; F2 0F C2 /r 02 [WILLAMETTE,SSE2] -\c CMPUNORDSD xmm1,xmm2/mem64 ; F2 0F C2 /r 03 [WILLAMETTE,SSE2] -\c CMPNEQSD xmm1,xmm2/mem64 ; F2 0F C2 /r 04 [WILLAMETTE,SSE2] -\c CMPNLTSD xmm1,xmm2/mem64 ; F2 0F C2 /r 05 [WILLAMETTE,SSE2] -\c CMPNLESD xmm1,xmm2/mem64 ; F2 0F C2 /r 06 [WILLAMETTE,SSE2] -\c CMPORDSD xmm1,xmm2/mem64 ; F2 0F C2 /r 07 [WILLAMETTE,SSE2] - -The \c{CMPccSD} instructions compare the low-order double-precision -FP values in the source and destination operands, and returns the -result of the comparison in the destination register. The result of -each comparison is a quadword mask of all 1s (comparison true) or -all 0s (comparison false). - -The destination is an \c{XMM} register. The source can be either an -\c{XMM} register or a 128-bit memory location. - -The third operand is an 8-bit immediate value, of which the low 3 -bits define the type of comparison. For ease of programming, the -8 two-operand pseudo-instructions are provided, with the third -operand already filled in. The \I{Condition Predicates} -\c{Condition Predicates} are: - -\c EQ 0 Equal -\c LT 1 Less-than -\c LE 2 Less-than-or-equal -\c UNORD 3 Unordered -\c NE 4 Not-equal -\c NLT 5 Not-less-than -\c NLE 6 Not-less-than-or-equal -\c ORD 7 Ordered - -For more details of the comparison predicates, and details of how -to emulate the "greater-than" equivalents, see \k{iref-SSE-cc} - - -\S{insCMPccSS} \i\c{CMPccSS}: Scalar Single-Precision FP Compare -\I\c{CMPEQSS} \I\c{CMPLTSS} \I\c{CMPLESS} \I\c{CMPUNORDSS} -\I\c{CMPNEQSS} \I\c{CMPNLTSS} \I\c{CMPNLESS} \I\c{CMPORDSS} - -\c CMPSS xmm1,xmm2/mem32,imm8 ; F3 0F C2 /r ib [KATMAI,SSE] - -\c CMPEQSS xmm1,xmm2/mem32 ; F3 0F C2 /r 00 [KATMAI,SSE] -\c CMPLTSS xmm1,xmm2/mem32 ; F3 0F C2 /r 01 [KATMAI,SSE] -\c CMPLESS xmm1,xmm2/mem32 ; F3 0F C2 /r 02 [KATMAI,SSE] -\c CMPUNORDSS xmm1,xmm2/mem32 ; F3 0F C2 /r 03 [KATMAI,SSE] -\c CMPNEQSS xmm1,xmm2/mem32 ; F3 0F C2 /r 04 [KATMAI,SSE] -\c CMPNLTSS xmm1,xmm2/mem32 ; F3 0F C2 /r 05 [KATMAI,SSE] -\c CMPNLESS xmm1,xmm2/mem32 ; F3 0F C2 /r 06 [KATMAI,SSE] -\c CMPORDSS xmm1,xmm2/mem32 ; F3 0F C2 /r 07 [KATMAI,SSE] - -The \c{CMPccSS} instructions compare the low-order single-precision -FP values in the source and destination operands, and returns the -result of the comparison in the destination register. The result of -each comparison is a doubleword mask of all 1s (comparison true) or -all 0s (comparison false). - -The destination is an \c{XMM} register. The source can be either an -\c{XMM} register or a 128-bit memory location. - -The third operand is an 8-bit immediate value, of which the low 3 -bits define the type of comparison. For ease of programming, the -8 two-operand pseudo-instructions are provided, with the third -operand already filled in. The \I{Condition Predicates} -\c{Condition Predicates} are: - -\c EQ 0 Equal -\c LT 1 Less-than -\c LE 2 Less-than-or-equal -\c UNORD 3 Unordered -\c NE 4 Not-equal -\c NLT 5 Not-less-than -\c NLE 6 Not-less-than-or-equal -\c ORD 7 Ordered - -For more details of the comparison predicates, and details of how -to emulate the "greater-than" equivalents, see \k{iref-SSE-cc} - - -\S{insCMPXCHG} \i\c{CMPXCHG}, \i\c{CMPXCHG486}: Compare and Exchange - -\c CMPXCHG r/m8,reg8 ; 0F B0 /r [PENT] -\c CMPXCHG r/m16,reg16 ; o16 0F B1 /r [PENT] -\c CMPXCHG r/m32,reg32 ; o32 0F B1 /r [PENT] - -\c CMPXCHG486 r/m8,reg8 ; 0F A6 /r [486,UNDOC] -\c CMPXCHG486 r/m16,reg16 ; o16 0F A7 /r [486,UNDOC] -\c CMPXCHG486 r/m32,reg32 ; o32 0F A7 /r [486,UNDOC] - -These two instructions perform exactly the same operation; however, -apparently some (not all) 486 processors support it under a -non-standard opcode, so NASM provides the undocumented -\c{CMPXCHG486} form to generate the non-standard opcode. - -\c{CMPXCHG} compares its destination (first) operand to the value in -\c{AL}, \c{AX} or \c{EAX} (depending on the operand size of the -instruction). If they are equal, it copies its source (second) -operand into the destination and sets the zero flag. Otherwise, it -clears the zero flag and copies the destination register to AL, AX or EAX. - -The destination can be either a register or a memory location. The -source is a register. - -\c{CMPXCHG} is intended to be used for atomic operations in -multitasking or multiprocessor environments. To safely update a -value in shared memory, for example, you might load the value into -\c{EAX}, load the updated value into \c{EBX}, and then execute the -instruction \c{LOCK CMPXCHG [value],EBX}. If \c{value} has not -changed since being loaded, it is updated with your desired new -value, and the zero flag is set to let you know it has worked. (The -\c{LOCK} prefix prevents another processor doing anything in the -middle of this operation: it guarantees atomicity.) However, if -another processor has modified the value in between your load and -your attempted store, the store does not happen, and you are -notified of the failure by a cleared zero flag, so you can go round -and try again. - - -\S{insCMPXCHG8B} \i\c{CMPXCHG8B}: Compare and Exchange Eight Bytes - -\c CMPXCHG8B mem ; 0F C7 /1 [PENT] - -This is a larger and more unwieldy version of \c{CMPXCHG}: it -compares the 64-bit (eight-byte) value stored at \c{[mem]} with the -value in \c{EDX:EAX}. If they are equal, it sets the zero flag and -stores \c{ECX:EBX} into the memory area. If they are unequal, it -clears the zero flag and stores the memory contents into \c{EDX:EAX}. - -\c{CMPXCHG8B} can be used with the \c{LOCK} prefix, to allow atomic -execution. This is useful in multi-processor and multi-tasking -environments. - - -\S{insCOMISD} \i\c{COMISD}: Scalar Ordered Double-Precision FP Compare and Set EFLAGS - -\c COMISD xmm1,xmm2/mem64 ; 66 0F 2F /r [WILLAMETTE,SSE2] - -\c{COMISD} compares the low-order double-precision FP value in the -two source operands. ZF, PF and CF are set according to the result. -OF, AF and AF are cleared. The unordered result is returned if either -source is a NaN (QNaN or SNaN). - -The destination operand is an \c{XMM} register. The source can be either -an \c{XMM} register or a memory location. - -The flags are set according to the following rules: - -\c Result Flags Values - -\c UNORDERED: ZF,PF,CF <-- 111; -\c GREATER_THAN: ZF,PF,CF <-- 000; -\c LESS_THAN: ZF,PF,CF <-- 001; -\c EQUAL: ZF,PF,CF <-- 100; - - -\S{insCOMISS} \i\c{COMISS}: Scalar Ordered Single-Precision FP Compare and Set EFLAGS - -\c COMISS xmm1,xmm2/mem32 ; 66 0F 2F /r [KATMAI,SSE] - -\c{COMISS} compares the low-order single-precision FP value in the -two source operands. ZF, PF and CF are set according to the result. -OF, AF and AF are cleared. The unordered result is returned if either -source is a NaN (QNaN or SNaN). - -The destination operand is an \c{XMM} register. The source can be either -an \c{XMM} register or a memory location. - -The flags are set according to the following rules: - -\c Result Flags Values - -\c UNORDERED: ZF,PF,CF <-- 111; -\c GREATER_THAN: ZF,PF,CF <-- 000; -\c LESS_THAN: ZF,PF,CF <-- 001; -\c EQUAL: ZF,PF,CF <-- 100; - - -\S{insCPUID} \i\c{CPUID}: Get CPU Identification Code - -\c CPUID ; 0F A2 [PENT] - -\c{CPUID} returns various information about the processor it is -being executed on. It fills the four registers \c{EAX}, \c{EBX}, -\c{ECX} and \c{EDX} with information, which varies depending on the -input contents of \c{EAX}. - -\c{CPUID} also acts as a barrier to serialize instruction execution: -executing the \c{CPUID} instruction guarantees that all the effects -(memory modification, flag modification, register modification) of -previous instructions have been completed before the next -instruction gets fetched. - -The information returned is as follows: - -\b If \c{EAX} is zero on input, \c{EAX} on output holds the maximum -acceptable input value of \c{EAX}, and \c{EBX:EDX:ECX} contain the -string \c{"GenuineIntel"} (or not, if you have a clone processor). -That is to say, \c{EBX} contains \c{"Genu"} (in NASM's own sense of -character constants, described in \k{chrconst}), \c{EDX} contains -\c{"ineI"} and \c{ECX} contains \c{"ntel"}. - -\b If \c{EAX} is one on input, \c{EAX} on output contains version -information about the processor, and \c{EDX} contains a set of -feature flags, showing the presence and absence of various features. -For example, bit 8 is set if the \c{CMPXCHG8B} instruction -(\k{insCMPXCHG8B}) is supported, bit 15 is set if the conditional -move instructions (\k{insCMOVcc} and \k{insFCMOVB}) are supported, -and bit 23 is set if \c{MMX} instructions are supported. - -\b If \c{EAX} is two on input, \c{EAX}, \c{EBX}, \c{ECX} and \c{EDX} -all contain information about caches and TLBs (Translation Lookahead -Buffers). - -For more information on the data returned from \c{CPUID}, see the -documentation from Intel and other processor manufacturers. - - -\S{insCVTDQ2PD} \i\c{CVTDQ2PD}: -Packed Signed INT32 to Packed Double-Precision FP Conversion - -\c CVTDQ2PD xmm1,xmm2/mem64 ; F3 0F E6 /r [WILLAMETTE,SSE2] - -\c{CVTDQ2PD} converts two packed signed doublewords from the source -operand to two packed double-precision FP values in the destination -operand. - -The destination operand is an \c{XMM} register. The source can be -either an \c{XMM} register or a 64-bit memory location. If the -source is a register, the packed integers are in the low quadword. - - -\S{insCVTDQ2PS} \i\c{CVTDQ2PS}: -Packed Signed INT32 to Packed Single-Precision FP Conversion - -\c CVTDQ2PS xmm1,xmm2/mem128 ; 0F 5B /r [WILLAMETTE,SSE2] - -\c{CVTDQ2PS} converts four packed signed doublewords from the source -operand to four packed single-precision FP values in the destination -operand. - -The destination operand is an \c{XMM} register. The source can be -either an \c{XMM} register or a 128-bit memory location. - -For more details of this instruction, see the Intel Processor manuals. - - -\S{insCVTPD2DQ} \i\c{CVTPD2DQ}: -Packed Double-Precision FP to Packed Signed INT32 Conversion - -\c CVTPD2DQ xmm1,xmm2/mem128 ; F2 0F E6 /r [WILLAMETTE,SSE2] - -\c{CVTPD2DQ} converts two packed double-precision FP values from the -source operand to two packed signed doublewords in the low quadword -of the destination operand. The high quadword of the destination is -set to all 0s. - -The destination operand is an \c{XMM} register. The source can be -either an \c{XMM} register or a 128-bit memory location. - -For more details of this instruction, see the Intel Processor manuals. - - -\S{insCVTPD2PI} \i\c{CVTPD2PI}: -Packed Double-Precision FP to Packed Signed INT32 Conversion - -\c CVTPD2PI mm,xmm/mem128 ; 66 0F 2D /r [WILLAMETTE,SSE2] - -\c{CVTPD2PI} converts two packed double-precision FP values from the -source operand to two packed signed doublewords in the destination -operand. - -The destination operand is an \c{MMX} register. The source can be -either an \c{XMM} register or a 128-bit memory location. - -For more details of this instruction, see the Intel Processor manuals. - - -\S{insCVTPD2PS} \i\c{CVTPD2PS}: -Packed Double-Precision FP to Packed Single-Precision FP Conversion - -\c CVTPD2PS xmm1,xmm2/mem128 ; 66 0F 5A /r [WILLAMETTE,SSE2] - -\c{CVTPD2PS} converts two packed double-precision FP values from the -source operand to two packed single-precision FP values in the low -quadword of the destination operand. The high quadword of the -destination is set to all 0s. - -The destination operand is an \c{XMM} register. The source can be -either an \c{XMM} register or a 128-bit memory location. - -For more details of this instruction, see the Intel Processor manuals. - - -\S{insCVTPI2PD} \i\c{CVTPI2PD}: -Packed Signed INT32 to Packed Double-Precision FP Conversion - -\c CVTPI2PD xmm,mm/mem64 ; 66 0F 2A /r [WILLAMETTE,SSE2] - -\c{CVTPI2PD} converts two packed signed doublewords from the source -operand to two packed double-precision FP values in the destination -operand. - -The destination operand is an \c{XMM} register. The source can be -either an \c{MMX} register or a 64-bit memory location. - -For more details of this instruction, see the Intel Processor manuals. - - -\S{insCVTPI2PS} \i\c{CVTPI2PS}: -Packed Signed INT32 to Packed Single-FP Conversion - -\c CVTPI2PS xmm,mm/mem64 ; 0F 2A /r [KATMAI,SSE] - -\c{CVTPI2PS} converts two packed signed doublewords from the source -operand to two packed single-precision FP values in the low quadword -of the destination operand. The high quadword of the destination -remains unchanged. - -The destination operand is an \c{XMM} register. The source can be -either an \c{MMX} register or a 64-bit memory location. - -For more details of this instruction, see the Intel Processor manuals. - - -\S{insCVTPS2DQ} \i\c{CVTPS2DQ}: -Packed Single-Precision FP to Packed Signed INT32 Conversion - -\c CVTPS2DQ xmm1,xmm2/mem128 ; 66 0F 5B /r [WILLAMETTE,SSE2] - -\c{CVTPS2DQ} converts four packed single-precision FP values from the -source operand to four packed signed doublewords in the destination operand. - -The destination operand is an \c{XMM} register. The source can be -either an \c{XMM} register or a 128-bit memory location. - -For more details of this instruction, see the Intel Processor manuals. - - -\S{insCVTPS2PD} \i\c{CVTPS2PD}: -Packed Single-Precision FP to Packed Double-Precision FP Conversion - -\c CVTPS2PD xmm1,xmm2/mem64 ; 0F 5A /r [WILLAMETTE,SSE2] - -\c{CVTPS2PD} converts two packed single-precision FP values from the -source operand to two packed double-precision FP values in the destination -operand. - -The destination operand is an \c{XMM} register. The source can be -either an \c{XMM} register or a 64-bit memory location. If the source -is a register, the input values are in the low quadword. - -For more details of this instruction, see the Intel Processor manuals. - - -\S{insCVTPS2PI} \i\c{CVTPS2PI}: -Packed Single-Precision FP to Packed Signed INT32 Conversion - -\c CVTPS2PI mm,xmm/mem64 ; 0F 2D /r [KATMAI,SSE] - -\c{CVTPS2PI} converts two packed single-precision FP values from -the source operand to two packed signed doublewords in the destination -operand. - -The destination operand is an \c{MMX} register. The source can be -either an \c{XMM} register or a 64-bit memory location. If the -source is a register, the input values are in the low quadword. - -For more details of this instruction, see the Intel Processor manuals. - - -\S{insCVTSD2SI} \i\c{CVTSD2SI}: -Scalar Double-Precision FP to Signed INT32 Conversion - -\c CVTSD2SI reg32,xmm/mem64 ; F2 0F 2D /r [WILLAMETTE,SSE2] - -\c{CVTSD2SI} converts a double-precision FP value from the source -operand to a signed doubleword in the destination operand. - -The destination operand is a general purpose register. The source can be -either an \c{XMM} register or a 64-bit memory location. If the -source is a register, the input value is in the low quadword. - -For more details of this instruction, see the Intel Processor manuals. - - -\S{insCVTSD2SS} \i\c{CVTSD2SS}: -Scalar Double-Precision FP to Scalar Single-Precision FP Conversion - -\c CVTSD2SS xmm1,xmm2/mem64 ; F2 0F 5A /r [KATMAI,SSE] - -\c{CVTSD2SS} converts a double-precision FP value from the source -operand to a single-precision FP value in the low doubleword of the -destination operand. The upper 3 doublewords are left unchanged. - -The destination operand is an \c{XMM} register. The source can be -either an \c{XMM} register or a 64-bit memory location. If the -source is a register, the input value is in the low quadword. - -For more details of this instruction, see the Intel Processor manuals. - - -\S{insCVTSI2SD} \i\c{CVTSI2SD}: -Signed INT32 to Scalar Double-Precision FP Conversion - -\c CVTSI2SD xmm,r/m32 ; F2 0F 2A /r [WILLAMETTE,SSE2] - -\c{CVTSI2SD} converts a signed doubleword from the source operand to -a double-precision FP value in the low quadword of the destination -operand. The high quadword is left unchanged. - -The destination operand is an \c{XMM} register. The source can be either -a general purpose register or a 32-bit memory location. - -For more details of this instruction, see the Intel Processor manuals. - - -\S{insCVTSI2SS} \i\c{CVTSI2SS}: -Signed INT32 to Scalar Single-Precision FP Conversion - -\c CVTSI2SS xmm,r/m32 ; F3 0F 2A /r [KATMAI,SSE] - -\c{CVTSI2SS} converts a signed doubleword from the source operand to a -single-precision FP value in the low doubleword of the destination operand. -The upper 3 doublewords are left unchanged. - -The destination operand is an \c{XMM} register. The source can be either -a general purpose register or a 32-bit memory location. - -For more details of this instruction, see the Intel Processor manuals. - - -\S{insCVTSS2SD} \i\c{CVTSS2SD}: -Scalar Single-Precision FP to Scalar Double-Precision FP Conversion - -\c CVTSS2SD xmm1,xmm2/mem32 ; F3 0F 5A /r [WILLAMETTE,SSE2] - -\c{CVTSS2SD} converts a single-precision FP value from the source operand -to a double-precision FP value in the low quadword of the destination -operand. The upper quadword is left unchanged. - -The destination operand is an \c{XMM} register. The source can be either -an \c{XMM} register or a 32-bit memory location. If the source is a -register, the input value is contained in the low doubleword. - -For more details of this instruction, see the Intel Processor manuals. - - -\S{insCVTSS2SI} \i\c{CVTSS2SI}: -Scalar Single-Precision FP to Signed INT32 Conversion - -\c CVTSS2SI reg32,xmm/mem32 ; F3 0F 2D /r [KATMAI,SSE] - -\c{CVTSS2SI} converts a single-precision FP value from the source -operand to a signed doubleword in the destination operand. - -The destination operand is a general purpose register. The source can be -either an \c{XMM} register or a 32-bit memory location. If the -source is a register, the input value is in the low doubleword. - -For more details of this instruction, see the Intel Processor manuals. - - -\S{insCVTTPD2DQ} \i\c{CVTTPD2DQ}: -Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation - -\c CVTTPD2DQ xmm1,xmm2/mem128 ; 66 0F E6 /r [WILLAMETTE,SSE2] - -\c{CVTTPD2DQ} converts two packed double-precision FP values in the source -operand to two packed single-precision FP values in the destination operand. -If the result is inexact, it is truncated (rounded toward zero). The high -quadword is set to all 0s. - -The destination operand is an \c{XMM} register. The source can be -either an \c{XMM} register or a 128-bit memory location. - -For more details of this instruction, see the Intel Processor manuals. - - -\S{insCVTTPD2PI} \i\c{CVTTPD2PI}: -Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation - -\c CVTTPD2PI mm,xmm/mem128 ; 66 0F 2C /r [WILLAMETTE,SSE2] - -\c{CVTTPD2PI} converts two packed double-precision FP values in the source -operand to two packed single-precision FP values in the destination operand. -If the result is inexact, it is truncated (rounded toward zero). - -The destination operand is an \c{MMX} register. The source can be -either an \c{XMM} register or a 128-bit memory location. - -For more details of this instruction, see the Intel Processor manuals. - - -\S{insCVTTPS2DQ} \i\c{CVTTPS2DQ}: -Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation - -\c CVTTPS2DQ xmm1,xmm2/mem128 ; F3 0F 5B /r [WILLAMETTE,SSE2] - -\c{CVTTPS2DQ} converts four packed single-precision FP values in the source -operand to four packed signed doublewords in the destination operand. -If the result is inexact, it is truncated (rounded toward zero). - -The destination operand is an \c{XMM} register. The source can be -either an \c{XMM} register or a 128-bit memory location. - -For more details of this instruction, see the Intel Processor manuals. - - -\S{insCVTTPS2PI} \i\c{CVTTPS2PI}: -Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation - -\c CVTTPS2PI mm,xmm/mem64 ; 0F 2C /r [KATMAI,SSE] - -\c{CVTTPS2PI} converts two packed single-precision FP values in the source -operand to two packed signed doublewords in the destination operand. -If the result is inexact, it is truncated (rounded toward zero). If -the source is a register, the input values are in the low quadword. - -The destination operand is an \c{MMX} register. The source can be -either an \c{XMM} register or a 64-bit memory location. If the source -is a register, the input value is in the low quadword. - -For more details of this instruction, see the Intel Processor manuals. - - -\S{insCVTTSD2SI} \i\c{CVTTSD2SI}: -Scalar Double-Precision FP to Signed INT32 Conversion with Truncation - -\c CVTTSD2SI reg32,xmm/mem64 ; F2 0F 2C /r [WILLAMETTE,SSE2] - -\c{CVTTSD2SI} converts a double-precision FP value in the source operand -to a signed doubleword in the destination operand. If the result is -inexact, it is truncated (rounded toward zero). - -The destination operand is a general purpose register. The source can be -either an \c{XMM} register or a 64-bit memory location. If the source is a -register, the input value is in the low quadword. - -For more details of this instruction, see the Intel Processor manuals. - - -\S{insCVTTSS2SI} \i\c{CVTTSS2SI}: -Scalar Single-Precision FP to Signed INT32 Conversion with Truncation - -\c CVTTSD2SI reg32,xmm/mem32 ; F3 0F 2C /r [KATMAI,SSE] - -\c{CVTTSS2SI} converts a single-precision FP value in the source operand -to a signed doubleword in the destination operand. If the result is -inexact, it is truncated (rounded toward zero). - -The destination operand is a general purpose register. The source can be -either an \c{XMM} register or a 32-bit memory location. If the source is a -register, the input value is in the low doubleword. - -For more details of this instruction, see the Intel Processor manuals. - - -\S{insDAA} \i\c{DAA}, \i\c{DAS}: Decimal Adjustments - -\c DAA ; 27 [8086] -\c DAS ; 2F [8086] - -These instructions are used in conjunction with the add and subtract -instructions to perform binary-coded decimal arithmetic in -\e{packed} (one BCD digit per nibble) form. For the unpacked -equivalents, see \k{insAAA}. - -\c{DAA} should be used after a one-byte \c{ADD} instruction whose -destination was the \c{AL} register: by means of examining the value -in the \c{AL} and also the auxiliary carry flag \c{AF}, it -determines whether either digit of the addition has overflowed, and -adjusts it (and sets the carry and auxiliary-carry flags) if so. You -can add long BCD strings together by doing \c{ADD}/\c{DAA} on the -low two digits, then doing \c{ADC}/\c{DAA} on each subsequent pair -of digits. - -\c{DAS} works similarly to \c{DAA}, but is for use after \c{SUB} -instructions rather than \c{ADD}. - - -\S{insDEC} \i\c{DEC}: Decrement Integer - -\c DEC reg16 ; o16 48+r [8086] -\c DEC reg32 ; o32 48+r [386] -\c DEC r/m8 ; FE /1 [8086] -\c DEC r/m16 ; o16 FF /1 [8086] -\c DEC r/m32 ; o32 FF /1 [386] - -\c{DEC} subtracts 1 from its operand. It does \e{not} affect the -carry flag: to affect the carry flag, use \c{SUB something,1} (see -\k{insSUB}). \c{DEC} affects all the other flags according to the result. - -This instruction can be used with a \c{LOCK} prefix to allow atomic -execution. - -See also \c{INC} (\k{insINC}). - - -\S{insDIV} \i\c{DIV}: Unsigned Integer Divide - -\c DIV r/m8 ; F6 /6 [8086] -\c DIV r/m16 ; o16 F7 /6 [8086] -\c DIV r/m32 ; o32 F7 /6 [386] - -\c{DIV} performs unsigned integer division. The explicit operand -provided is the divisor; the dividend and destination operands are -implicit, in the following way: - -\b For \c{DIV r/m8}, \c{AX} is divided by the given operand; the -quotient is stored in \c{AL} and the remainder in \c{AH}. - -\b For \c{DIV r/m16}, \c{DX:AX} is divided by the given operand; the -quotient is stored in \c{AX} and the remainder in \c{DX}. - -\b For \c{DIV r/m32}, \c{EDX:EAX} is divided by the given operand; -the quotient is stored in \c{EAX} and the remainder in \c{EDX}. - -Signed integer division is performed by the \c{IDIV} instruction: -see \k{insIDIV}. - - -\S{insDIVPD} \i\c{DIVPD}: Packed Double-Precision FP Divide - -\c DIVPD xmm1,xmm2/mem128 ; 66 0F 5E /r [WILLAMETTE,SSE2] - -\c{DIVPD} divides the two packed double-precision FP values in -the destination operand by the two packed double-precision FP -values in the source operand, and stores the packed double-precision -results in the destination register. - -The destination is an \c{XMM} register. The source operand can be -either an \c{XMM} register or a 128-bit memory location. - -\c dst[0-63] := dst[0-63] / src[0-63], -\c dst[64-127] := dst[64-127] / src[64-127]. - - -\S{insDIVPS} \i\c{DIVPS}: Packed Single-Precision FP Divide - -\c DIVPS xmm1,xmm2/mem128 ; 0F 5E /r [KATMAI,SSE] - -\c{DIVPS} divides the four packed single-precision FP values in -the destination operand by the four packed single-precision FP -values in the source operand, and stores the packed single-precision -results in the destination register. - -The destination is an \c{XMM} register. The source operand can be -either an \c{XMM} register or a 128-bit memory location. - -\c dst[0-31] := dst[0-31] / src[0-31], -\c dst[32-63] := dst[32-63] / src[32-63], -\c dst[64-95] := dst[64-95] / src[64-95], -\c dst[96-127] := dst[96-127] / src[96-127]. - - -\S{insDIVSD} \i\c{DIVSD}: Scalar Double-Precision FP Divide - -\c DIVSD xmm1,xmm2/mem64 ; F2 0F 5E /r [WILLAMETTE,SSE2] - -\c{DIVSD} divides the low-order double-precision FP value in the -destination operand by the low-order double-precision FP value in -the source operand, and stores the double-precision result in the -destination register. - -The destination is an \c{XMM} register. The source operand can be -either an \c{XMM} register or a 64-bit memory location. - -\c dst[0-63] := dst[0-63] / src[0-63], -\c dst[64-127] remains unchanged. - - -\S{insDIVSS} \i\c{DIVSS}: Scalar Single-Precision FP Divide - -\c DIVSS xmm1,xmm2/mem32 ; F3 0F 5E /r [KATMAI,SSE] - -\c{DIVSS} divides the low-order single-precision FP value in the -destination operand by the low-order single-precision FP value in -the source operand, and stores the single-precision result in the -destination register. - -The destination is an \c{XMM} register. The source operand can be -either an \c{XMM} register or a 32-bit memory location. - -\c dst[0-31] := dst[0-31] / src[0-31], -\c dst[32-127] remains unchanged. - - -\S{insEMMS} \i\c{EMMS}: Empty MMX State - -\c EMMS ; 0F 77 [PENT,MMX] - -\c{EMMS} sets the FPU tag word (marking which floating-point registers -are available) to all ones, meaning all registers are available for -the FPU to use. It should be used after executing \c{MMX} instructions -and before executing any subsequent floating-point operations. - - -\S{insENTER} \i\c{ENTER}: Create Stack Frame - -\c ENTER imm,imm ; C8 iw ib [186] - -\c{ENTER} constructs a \i\c{stack frame} for a high-level language -procedure call. The first operand (the \c{iw} in the opcode -definition above refers to the first operand) gives the amount of -stack space to allocate for local variables; the second (the \c{ib} -above) gives the nesting level of the procedure (for languages like -Pascal, with nested procedures). - -The function of \c{ENTER}, with a nesting level of zero, is -equivalent to - -\c PUSH EBP ; or PUSH BP in 16 bits -\c MOV EBP,ESP ; or MOV BP,SP in 16 bits -\c SUB ESP,operand1 ; or SUB SP,operand1 in 16 bits - -This creates a stack frame with the procedure parameters accessible -upwards from \c{EBP}, and local variables accessible downwards from -\c{EBP}. - -With a nesting level of one, the stack frame created is 4 (or 2) -bytes bigger, and the value of the final frame pointer \c{EBP} is -accessible in memory at \c{[EBP-4]}. - -This allows \c{ENTER}, when called with a nesting level of two, to -look at the stack frame described by the \e{previous} value of -\c{EBP}, find the frame pointer at offset -4 from that, and push it -along with its new frame pointer, so that when a level-two procedure -is called from within a level-one procedure, \c{[EBP-4]} holds the -frame pointer of the most recent level-one procedure call and -\c{[EBP-8]} holds that of the most recent level-two call. And so on, -for nesting levels up to 31. - -Stack frames created by \c{ENTER} can be destroyed by the \c{LEAVE} -instruction: see \k{insLEAVE}. - - -\S{insF2XM1} \i\c{F2XM1}: Calculate 2**X-1 - -\c F2XM1 ; D9 F0 [8086,FPU] - -\c{F2XM1} raises 2 to the power of \c{ST0}, subtracts one, and -stores the result back into \c{ST0}. The initial contents of \c{ST0} -must be a number in the range -1.0 to +1.0. - - -\S{insFABS} \i\c{FABS}: Floating-Point Absolute Value - -\c FABS ; D9 E1 [8086,FPU] - -\c{FABS} computes the absolute value of \c{ST0},by clearing the sign -bit, and stores the result back in \c{ST0}. - - -\S{insFADD} \i\c{FADD}, \i\c{FADDP}: Floating-Point Addition - -\c FADD mem32 ; D8 /0 [8086,FPU] -\c FADD mem64 ; DC /0 [8086,FPU] - -\c FADD fpureg ; D8 C0+r [8086,FPU] -\c FADD ST0,fpureg ; D8 C0+r [8086,FPU] - -\c FADD TO fpureg ; DC C0+r [8086,FPU] -\c FADD fpureg,ST0 ; DC C0+r [8086,FPU] - -\c FADDP fpureg ; DE C0+r [8086,FPU] -\c FADDP fpureg,ST0 ; DE C0+r [8086,FPU] - -\b \c{FADD}, given one operand, adds the operand to \c{ST0} and stores -the result back in \c{ST0}. If the operand has the \c{TO} modifier, -the result is stored in the register given rather than in \c{ST0}. - -\b \c{FADDP} performs the same function as \c{FADD TO}, but pops the -register stack after storing the result. - -The given two-operand forms are synonyms for the one-operand forms. - -To add an integer value to \c{ST0}, use the c{FIADD} instruction -(\k{insFIADD}) - - -\S{insFBLD} \i\c{FBLD}, \i\c{FBSTP}: BCD Floating-Point Load and Store - -\c FBLD mem80 ; DF /4 [8086,FPU] -\c FBSTP mem80 ; DF /6 [8086,FPU] - -\c{FBLD} loads an 80-bit (ten-byte) packed binary-coded decimal -number from the given memory address, converts it to a real, and -pushes it on the register stack. \c{FBSTP} stores the value of -\c{ST0}, in packed BCD, at the given address and then pops the -register stack. - - -\S{insFCHS} \i\c{FCHS}: Floating-Point Change Sign - -\c FCHS ; D9 E0 [8086,FPU] - -\c{FCHS} negates the number in \c{ST0}, by inverting the sign bit: -negative numbers become positive, and vice versa. - - -\S{insFCLEX} \i\c{FCLEX}, \c{FNCLEX}: Clear Floating-Point Exceptions - -\c FCLEX ; 9B DB E2 [8086,FPU] -\c FNCLEX ; DB E2 [8086,FPU] - -\c{FCLEX} clears any floating-point exceptions which may be pending. -\c{FNCLEX} does the same thing but doesn't wait for previous -floating-point operations (including the \e{handling} of pending -exceptions) to finish first. - - -\S{insFCMOVB} \i\c{FCMOVcc}: Floating-Point Conditional Move - -\c FCMOVB fpureg ; DA C0+r [P6,FPU] -\c FCMOVB ST0,fpureg ; DA C0+r [P6,FPU] - -\c FCMOVE fpureg ; DA C8+r [P6,FPU] -\c FCMOVE ST0,fpureg ; DA C8+r [P6,FPU] - -\c FCMOVBE fpureg ; DA D0+r [P6,FPU] -\c FCMOVBE ST0,fpureg ; DA D0+r [P6,FPU] - -\c FCMOVU fpureg ; DA D8+r [P6,FPU] -\c FCMOVU ST0,fpureg ; DA D8+r [P6,FPU] - -\c FCMOVNB fpureg ; DB C0+r [P6,FPU] -\c FCMOVNB ST0,fpureg ; DB C0+r [P6,FPU] - -\c FCMOVNE fpureg ; DB C8+r [P6,FPU] -\c FCMOVNE ST0,fpureg ; DB C8+r [P6,FPU] - -\c FCMOVNBE fpureg ; DB D0+r [P6,FPU] -\c FCMOVNBE ST0,fpureg ; DB D0+r [P6,FPU] - -\c FCMOVNU fpureg ; DB D8+r [P6,FPU] -\c FCMOVNU ST0,fpureg ; DB D8+r [P6,FPU] - -The \c{FCMOV} instructions perform conditional move operations: each -of them moves the contents of the given register into \c{ST0} if its -condition is satisfied, and does nothing if not. - -The conditions are not the same as the standard condition codes used -with conditional jump instructions. The conditions \c{B}, \c{BE}, -\c{NB}, \c{NBE}, \c{E} and \c{NE} are exactly as normal, but none of -the other standard ones are supported. Instead, the condition \c{U} -and its counterpart \c{NU} are provided; the \c{U} condition is -satisfied if the last two floating-point numbers compared were -\e{unordered}, i.e. they were not equal but neither one could be -said to be greater than the other, for example if they were NaNs. -(The flag state which signals this is the setting of the parity -flag: so the \c{U} condition is notionally equivalent to \c{PE}, and -\c{NU} is equivalent to \c{PO}.) - -The \c{FCMOV} conditions test the main processor's status flags, not -the FPU status flags, so using \c{FCMOV} directly after \c{FCOM} -will not work. Instead, you should either use \c{FCOMI} which writes -directly to the main CPU flags word, or use \c{FSTSW} to extract the -FPU flags. - -Although the \c{FCMOV} instructions are flagged \c{P6} above, they -may not be supported by all Pentium Pro processors; the \c{CPUID} -instruction (\k{insCPUID}) will return a bit which indicates whether -conditional moves are supported. - - -\S{insFCOM} \i\c{FCOM}, \i\c{FCOMP}, \i\c{FCOMPP}, \i\c{FCOMI}, -\i\c{FCOMIP}: Floating-Point Compare - -\c FCOM mem32 ; D8 /2 [8086,FPU] -\c FCOM mem64 ; DC /2 [8086,FPU] -\c FCOM fpureg ; D8 D0+r [8086,FPU] -\c FCOM ST0,fpureg ; D8 D0+r [8086,FPU] - -\c FCOMP mem32 ; D8 /3 [8086,FPU] -\c FCOMP mem64 ; DC /3 [8086,FPU] -\c FCOMP fpureg ; D8 D8+r [8086,FPU] -\c FCOMP ST0,fpureg ; D8 D8+r [8086,FPU] - -\c FCOMPP ; DE D9 [8086,FPU] - -\c FCOMI fpureg ; DB F0+r [P6,FPU] -\c FCOMI ST0,fpureg ; DB F0+r [P6,FPU] - -\c FCOMIP fpureg ; DF F0+r [P6,FPU] -\c FCOMIP ST0,fpureg ; DF F0+r [P6,FPU] - -\c{FCOM} compares \c{ST0} with the given operand, and sets the FPU -flags accordingly. \c{ST0} is treated as the left-hand side of the -comparison, so that the carry flag is set (for a `less-than' result) -if \c{ST0} is less than the given operand. - -\c{FCOMP} does the same as \c{FCOM}, but pops the register stack -afterwards. \c{FCOMPP} compares \c{ST0} with \c{ST1} and then pops -the register stack twice. - -\c{FCOMI} and \c{FCOMIP} work like the corresponding forms of -\c{FCOM} and \c{FCOMP}, but write their results directly to the CPU -flags register rather than the FPU status word, so they can be -immediately followed by conditional jump or conditional move -instructions. - -The \c{FCOM} instructions differ from the \c{FUCOM} instructions -(\k{insFUCOM}) only in the way they handle quiet NaNs: \c{FUCOM} -will handle them silently and set the condition code flags to an -`unordered' result, whereas \c{FCOM} will generate an exception. - - -\S{insFCOS} \i\c{FCOS}: Cosine - -\c FCOS ; D9 FF [386,FPU] - -\c{FCOS} computes the cosine of \c{ST0} (in radians), and stores the -result in \c{ST0}. The absolute value of \c{ST0} must be less than 2**63. - -See also \c{FSINCOS} (\k{insFSIN}). - - -\S{insFDECSTP} \i\c{FDECSTP}: Decrement Floating-Point Stack Pointer - -\c FDECSTP ; D9 F6 [8086,FPU] - -\c{FDECSTP} decrements the `top' field in the floating-point status -word. This has the effect of rotating the FPU register stack by one, -as if the contents of \c{ST7} had been pushed on the stack. See also -\c{FINCSTP} (\k{insFINCSTP}). - - -\S{insFDISI} \i\c{FxDISI}, \i\c{FxENI}: Disable and Enable Floating-Point Interrupts - -\c FDISI ; 9B DB E1 [8086,FPU] -\c FNDISI ; DB E1 [8086,FPU] - -\c FENI ; 9B DB E0 [8086,FPU] -\c FNENI ; DB E0 [8086,FPU] - -\c{FDISI} and \c{FENI} disable and enable floating-point interrupts. -These instructions are only meaningful on original 8087 processors: -the 287 and above treat them as no-operation instructions. - -\c{FNDISI} and \c{FNENI} do the same thing as \c{FDISI} and \c{FENI} -respectively, but without waiting for the floating-point processor -to finish what it was doing first. - - -\S{insFDIV} \i\c{FDIV}, \i\c{FDIVP}, \i\c{FDIVR}, \i\c{FDIVRP}: Floating-Point Division - -\c FDIV mem32 ; D8 /6 [8086,FPU] -\c FDIV mem64 ; DC /6 [8086,FPU] - -\c FDIV fpureg ; D8 F0+r [8086,FPU] -\c FDIV ST0,fpureg ; D8 F0+r [8086,FPU] - -\c FDIV TO fpureg ; DC F8+r [8086,FPU] -\c FDIV fpureg,ST0 ; DC F8+r [8086,FPU] - -\c FDIVR mem32 ; D8 /7 [8086,FPU] -\c FDIVR mem64 ; DC /7 [8086,FPU] - -\c FDIVR fpureg ; D8 F8+r [8086,FPU] -\c FDIVR ST0,fpureg ; D8 F8+r [8086,FPU] - -\c FDIVR TO fpureg ; DC F0+r [8086,FPU] -\c FDIVR fpureg,ST0 ; DC F0+r [8086,FPU] - -\c FDIVP fpureg ; DE F8+r [8086,FPU] -\c FDIVP fpureg,ST0 ; DE F8+r [8086,FPU] - -\c FDIVRP fpureg ; DE F0+r [8086,FPU] -\c FDIVRP fpureg,ST0 ; DE F0+r [8086,FPU] - -\b \c{FDIV} divides \c{ST0} by the given operand and stores the result -back in \c{ST0}, unless the \c{TO} qualifier is given, in which case -it divides the given operand by \c{ST0} and stores the result in the -operand. - -\b \c{FDIVR} does the same thing, but does the division the other way -up: so if \c{TO} is not given, it divides the given operand by -\c{ST0} and stores the result in \c{ST0}, whereas if \c{TO} is given -it divides \c{ST0} by its operand and stores the result in the -operand. - -\b \c{FDIVP} operates like \c{FDIV TO}, but pops the register stack -once it has finished. - -\b \c{FDIVRP} operates like \c{FDIVR TO}, but pops the register stack -once it has finished. - -For FP/Integer divisions, see \c{FIDIV} (\k{insFIDIV}). - - -\S{insFEMMS} \i\c{FEMMS}: Faster Enter/Exit of the MMX or floating-point state - -\c FEMMS ; 0F 0E [PENT,3DNOW] - -\c{FEMMS} can be used in place of the \c{EMMS} instruction on -processors which support the 3DNow! instruction set. Following -execution of \c{FEMMS}, the state of the \c{MMX/FP} registers -is undefined, and this allows a faster context switch between -\c{FP} and \c{MMX} instructions. The \c{FEMMS} instruction can -also be used \e{before} executing \c{MMX} instructions - - -\S{insFFREE} \i\c{FFREE}: Flag Floating-Point Register as Unused - -\c FFREE fpureg ; DD C0+r [8086,FPU] -\c FFREEP fpureg ; DF C0+r [286,FPU,UNDOC] - -\c{FFREE} marks the given register as being empty. - -\c{FFREEP} marks the given register as being empty, and then -pops the register stack. - - -\S{insFIADD} \i\c{FIADD}: Floating-Point/Integer Addition - -\c FIADD mem16 ; DE /0 [8086,FPU] -\c FIADD mem32 ; DA /0 [8086,FPU] - -\c{FIADD} adds the 16-bit or 32-bit integer stored in the given -memory location to \c{ST0}, storing the result in \c{ST0}. - - -\S{insFICOM} \i\c{FICOM}, \i\c{FICOMP}: Floating-Point/Integer Compare - -\c FICOM mem16 ; DE /2 [8086,FPU] -\c FICOM mem32 ; DA /2 [8086,FPU] - -\c FICOMP mem16 ; DE /3 [8086,FPU] -\c FICOMP mem32 ; DA /3 [8086,FPU] - -\c{FICOM} compares \c{ST0} with the 16-bit or 32-bit integer stored -in the given memory location, and sets the FPU flags accordingly. -\c{FICOMP} does the same, but pops the register stack afterwards. - - -\S{insFIDIV} \i\c{FIDIV}, \i\c{FIDIVR}: Floating-Point/Integer Division - -\c FIDIV mem16 ; DE /6 [8086,FPU] -\c FIDIV mem32 ; DA /6 [8086,FPU] - -\c FIDIVR mem16 ; DE /7 [8086,FPU] -\c FIDIVR mem32 ; DA /7 [8086,FPU] - -\c{FIDIV} divides \c{ST0} by the 16-bit or 32-bit integer stored in -the given memory location, and stores the result in \c{ST0}. -\c{FIDIVR} does the division the other way up: it divides the -integer by \c{ST0}, but still stores the result in \c{ST0}. - - -\S{insFILD} \i\c{FILD}, \i\c{FIST}, \i\c{FISTP}: Floating-Point/Integer Conversion - -\c FILD mem16 ; DF /0 [8086,FPU] -\c FILD mem32 ; DB /0 [8086,FPU] -\c FILD mem64 ; DF /5 [8086,FPU] - -\c FIST mem16 ; DF /2 [8086,FPU] -\c FIST mem32 ; DB /2 [8086,FPU] - -\c FISTP mem16 ; DF /3 [8086,FPU] -\c FISTP mem32 ; DB /3 [8086,FPU] -\c FISTP mem64 ; DF /7 [8086,FPU] - -\c{FILD} loads an integer out of a memory location, converts it to a -real, and pushes it on the FPU register stack. \c{FIST} converts -\c{ST0} to an integer and stores that in memory; \c{FISTP} does the -same as \c{FIST}, but pops the register stack afterwards. - - -\S{insFIMUL} \i\c{FIMUL}: Floating-Point/Integer Multiplication - -\c FIMUL mem16 ; DE /1 [8086,FPU] -\c FIMUL mem32 ; DA /1 [8086,FPU] - -\c{FIMUL} multiplies \c{ST0} by the 16-bit or 32-bit integer stored -in the given memory location, and stores the result in \c{ST0}. - - -\S{insFINCSTP} \i\c{FINCSTP}: Increment Floating-Point Stack Pointer - -\c FINCSTP ; D9 F7 [8086,FPU] - -\c{FINCSTP} increments the `top' field in the floating-point status -word. This has the effect of rotating the FPU register stack by one, -as if the register stack had been popped; however, unlike the -popping of the stack performed by many FPU instructions, it does not -flag the new \c{ST7} (previously \c{ST0}) as empty. See also -\c{FDECSTP} (\k{insFDECSTP}). - - -\S{insFINIT} \i\c{FINIT}, \i\c{FNINIT}: initialize Floating-Point Unit - -\c FINIT ; 9B DB E3 [8086,FPU] -\c FNINIT ; DB E3 [8086,FPU] - -\c{FINIT} initializes the FPU to its default state. It flags all -registers as empty, without actually change their values, clears -the top of stack pointer. \c{FNINIT} does the same, without first -waiting for pending exceptions to clear. - - -\S{insFISUB} \i\c{FISUB}: Floating-Point/Integer Subtraction - -\c FISUB mem16 ; DE /4 [8086,FPU] -\c FISUB mem32 ; DA /4 [8086,FPU] - -\c FISUBR mem16 ; DE /5 [8086,FPU] -\c FISUBR mem32 ; DA /5 [8086,FPU] - -\c{FISUB} subtracts the 16-bit or 32-bit integer stored in the given -memory location from \c{ST0}, and stores the result in \c{ST0}. -\c{FISUBR} does the subtraction the other way round, i.e. it -subtracts \c{ST0} from the given integer, but still stores the -result in \c{ST0}. - - -\S{insFLD} \i\c{FLD}: Floating-Point Load - -\c FLD mem32 ; D9 /0 [8086,FPU] -\c FLD mem64 ; DD /0 [8086,FPU] -\c FLD mem80 ; DB /5 [8086,FPU] -\c FLD fpureg ; D9 C0+r [8086,FPU] - -\c{FLD} loads a floating-point value out of the given register or -memory location, and pushes it on the FPU register stack. - - -\S{insFLD1} \i\c{FLDxx}: Floating-Point Load Constants - -\c FLD1 ; D9 E8 [8086,FPU] -\c FLDL2E ; D9 EA [8086,FPU] -\c FLDL2T ; D9 E9 [8086,FPU] -\c FLDLG2 ; D9 EC [8086,FPU] -\c FLDLN2 ; D9 ED [8086,FPU] -\c FLDPI ; D9 EB [8086,FPU] -\c FLDZ ; D9 EE [8086,FPU] - -These instructions push specific standard constants on the FPU -register stack. - -\c Instruction Constant pushed - -\c FLD1 1 -\c FLDL2E base-2 logarithm of e -\c FLDL2T base-2 log of 10 -\c FLDLG2 base-10 log of 2 -\c FLDLN2 base-e log of 2 -\c FLDPI pi -\c FLDZ zero - - -\S{insFLDCW} \i\c{FLDCW}: Load Floating-Point Control Word - -\c FLDCW mem16 ; D9 /5 [8086,FPU] - -\c{FLDCW} loads a 16-bit value out of memory and stores it into the -FPU control word (governing things like the rounding mode, the -precision, and the exception masks). See also \c{FSTCW} -(\k{insFSTCW}). If exceptions are enabled and you don't want to -generate one, use \c{FCLEX} or \c{FNCLEX} (\k{insFCLEX}) before -loading the new control word. - - -\S{insFLDENV} \i\c{FLDENV}: Load Floating-Point Environment - -\c FLDENV mem ; D9 /4 [8086,FPU] - -\c{FLDENV} loads the FPU operating environment (control word, status -word, tag word, instruction pointer, data pointer and last opcode) -from memory. The memory area is 14 or 28 bytes long, depending on -the CPU mode at the time. See also \c{FSTENV} (\k{insFSTENV}). - - -\S{insFMUL} \i\c{FMUL}, \i\c{FMULP}: Floating-Point Multiply - -\c FMUL mem32 ; D8 /1 [8086,FPU] -\c FMUL mem64 ; DC /1 [8086,FPU] - -\c FMUL fpureg ; D8 C8+r [8086,FPU] -\c FMUL ST0,fpureg ; D8 C8+r [8086,FPU] - -\c FMUL TO fpureg ; DC C8+r [8086,FPU] -\c FMUL fpureg,ST0 ; DC C8+r [8086,FPU] - -\c FMULP fpureg ; DE C8+r [8086,FPU] -\c FMULP fpureg,ST0 ; DE C8+r [8086,FPU] - -\c{FMUL} multiplies \c{ST0} by the given operand, and stores the -result in \c{ST0}, unless the \c{TO} qualifier is used in which case -it stores the result in the operand. \c{FMULP} performs the same -operation as \c{FMUL TO}, and then pops the register stack. - - -\S{insFNOP} \i\c{FNOP}: Floating-Point No Operation - -\c FNOP ; D9 D0 [8086,FPU] - -\c{FNOP} does nothing. - - -\S{insFPATAN} \i\c{FPATAN}, \i\c{FPTAN}: Arctangent and Tangent - -\c FPATAN ; D9 F3 [8086,FPU] -\c FPTAN ; D9 F2 [8086,FPU] - -\c{FPATAN} computes the arctangent, in radians, of the result of -dividing \c{ST1} by \c{ST0}, stores the result in \c{ST1}, and pops -the register stack. It works like the C \c{atan2} function, in that -changing the sign of both \c{ST0} and \c{ST1} changes the output -value by pi (so it performs true rectangular-to-polar coordinate -conversion, with \c{ST1} being the Y coordinate and \c{ST0} being -the X coordinate, not merely an arctangent). - -\c{FPTAN} computes the tangent of the value in \c{ST0} (in radians), -and stores the result back into \c{ST0}. - -The absolute value of \c{ST0} must be less than 2**63. - - -\S{insFPREM} \i\c{FPREM}, \i\c{FPREM1}: Floating-Point Partial Remainder - -\c FPREM ; D9 F8 [8086,FPU] -\c FPREM1 ; D9 F5 [386,FPU] - -These instructions both produce the remainder obtained by dividing -\c{ST0} by \c{ST1}. This is calculated, notionally, by dividing -\c{ST0} by \c{ST1}, rounding the result to an integer, multiplying -by \c{ST1} again, and computing the value which would need to be -added back on to the result to get back to the original value in -\c{ST0}. - -The two instructions differ in the way the notional round-to-integer -operation is performed. \c{FPREM} does it by rounding towards zero, -so that the remainder it returns always has the same sign as the -original value in \c{ST0}; \c{FPREM1} does it by rounding to the -nearest integer, so that the remainder always has at most half the -magnitude of \c{ST1}. - -Both instructions calculate \e{partial} remainders, meaning that -they may not manage to provide the final result, but might leave -intermediate results in \c{ST0} instead. If this happens, they will -set the C2 flag in the FPU status word; therefore, to calculate a -remainder, you should repeatedly execute \c{FPREM} or \c{FPREM1} -until C2 becomes clear. - - -\S{insFRNDINT} \i\c{FRNDINT}: Floating-Point Round to Integer - -\c FRNDINT ; D9 FC [8086,FPU] - -\c{FRNDINT} rounds the contents of \c{ST0} to an integer, according -to the current rounding mode set in the FPU control word, and stores -the result back in \c{ST0}. - - -\S{insFRSTOR} \i\c{FSAVE}, \i\c{FRSTOR}: Save/Restore Floating-Point State - -\c FSAVE mem ; 9B DD /6 [8086,FPU] -\c FNSAVE mem ; DD /6 [8086,FPU] - -\c FRSTOR mem ; DD /4 [8086,FPU] - -\c{FSAVE} saves the entire floating-point unit state, including all -the information saved by \c{FSTENV} (\k{insFSTENV}) plus the -contents of all the registers, to a 94 or 108 byte area of memory -(depending on the CPU mode). \c{FRSTOR} restores the floating-point -state from the same area of memory. - -\c{FNSAVE} does the same as \c{FSAVE}, without first waiting for -pending floating-point exceptions to clear. - - -\S{insFSCALE} \i\c{FSCALE}: Scale Floating-Point Value by Power of Two - -\c FSCALE ; D9 FD [8086,FPU] - -\c{FSCALE} scales a number by a power of two: it rounds \c{ST1} -towards zero to obtain an integer, then multiplies \c{ST0} by two to -the power of that integer, and stores the result in \c{ST0}. - - -\S{insFSETPM} \i\c{FSETPM}: Set Protected Mode - -\c FSETPM ; DB E4 [286,FPU] - -This instruction initializes protected mode on the 287 floating-point -coprocessor. It is only meaningful on that processor: the 387 and -above treat the instruction as a no-operation. - - -\S{insFSIN} \i\c{FSIN}, \i\c{FSINCOS}: Sine and Cosine - -\c FSIN ; D9 FE [386,FPU] -\c FSINCOS ; D9 FB [386,FPU] - -\c{FSIN} calculates the sine of \c{ST0} (in radians) and stores the -result in \c{ST0}. \c{FSINCOS} does the same, but then pushes the -cosine of the same value on the register stack, so that the sine -ends up in \c{ST1} and the cosine in \c{ST0}. \c{FSINCOS} is faster -than executing \c{FSIN} and \c{FCOS} (see \k{insFCOS}) in succession. - -The absolute value of \c{ST0} must be less than 2**63. - - -\S{insFSQRT} \i\c{FSQRT}: Floating-Point Square Root - -\c FSQRT ; D9 FA [8086,FPU] - -\c{FSQRT} calculates the square root of \c{ST0} and stores the -result in \c{ST0}. - - -\S{insFST} \i\c{FST}, \i\c{FSTP}: Floating-Point Store - -\c FST mem32 ; D9 /2 [8086,FPU] -\c FST mem64 ; DD /2 [8086,FPU] -\c FST fpureg ; DD D0+r [8086,FPU] - -\c FSTP mem32 ; D9 /3 [8086,FPU] -\c FSTP mem64 ; DD /3 [8086,FPU] -\c FSTP mem80 ; DB /7 [8086,FPU] -\c FSTP fpureg ; DD D8+r [8086,FPU] - -\c{FST} stores the value in \c{ST0} into the given memory location -or other FPU register. \c{FSTP} does the same, but then pops the -register stack. - - -\S{insFSTCW} \i\c{FSTCW}: Store Floating-Point Control Word - -\c FSTCW mem16 ; 9B D9 /7 [8086,FPU] -\c FNSTCW mem16 ; D9 /7 [8086,FPU] - -\c{FSTCW} stores the \c{FPU} control word (governing things like the -rounding mode, the precision, and the exception masks) into a 2-byte -memory area. See also \c{FLDCW} (\k{insFLDCW}). - -\c{FNSTCW} does the same thing as \c{FSTCW}, without first waiting -for pending floating-point exceptions to clear. - - -\S{insFSTENV} \i\c{FSTENV}: Store Floating-Point Environment - -\c FSTENV mem ; 9B D9 /6 [8086,FPU] -\c FNSTENV mem ; D9 /6 [8086,FPU] - -\c{FSTENV} stores the \c{FPU} operating environment (control word, -status word, tag word, instruction pointer, data pointer and last -opcode) into memory. The memory area is 14 or 28 bytes long, -depending on the CPU mode at the time. See also \c{FLDENV} -(\k{insFLDENV}). - -\c{FNSTENV} does the same thing as \c{FSTENV}, without first waiting -for pending floating-point exceptions to clear. - - -\S{insFSTSW} \i\c{FSTSW}: Store Floating-Point Status Word - -\c FSTSW mem16 ; 9B DD /7 [8086,FPU] -\c FSTSW AX ; 9B DF E0 [286,FPU] - -\c FNSTSW mem16 ; DD /7 [8086,FPU] -\c FNSTSW AX ; DF E0 [286,FPU] - -\c{FSTSW} stores the \c{FPU} status word into \c{AX} or into a 2-byte -memory area. - -\c{FNSTSW} does the same thing as \c{FSTSW}, without first waiting -for pending floating-point exceptions to clear. - - -\S{insFSUB} \i\c{FSUB}, \i\c{FSUBP}, \i\c{FSUBR}, \i\c{FSUBRP}: Floating-Point Subtract - -\c FSUB mem32 ; D8 /4 [8086,FPU] -\c FSUB mem64 ; DC /4 [8086,FPU] - -\c FSUB fpureg ; D8 E0+r [8086,FPU] -\c FSUB ST0,fpureg ; D8 E0+r [8086,FPU] - -\c FSUB TO fpureg ; DC E8+r [8086,FPU] -\c FSUB fpureg,ST0 ; DC E8+r [8086,FPU] - -\c FSUBR mem32 ; D8 /5 [8086,FPU] -\c FSUBR mem64 ; DC /5 [8086,FPU] - -\c FSUBR fpureg ; D8 E8+r [8086,FPU] -\c FSUBR ST0,fpureg ; D8 E8+r [8086,FPU] - -\c FSUBR TO fpureg ; DC E0+r [8086,FPU] -\c FSUBR fpureg,ST0 ; DC E0+r [8086,FPU] - -\c FSUBP fpureg ; DE E8+r [8086,FPU] -\c FSUBP fpureg,ST0 ; DE E8+r [8086,FPU] - -\c FSUBRP fpureg ; DE E0+r [8086,FPU] -\c FSUBRP fpureg,ST0 ; DE E0+r [8086,FPU] - -\b \c{FSUB} subtracts the given operand from \c{ST0} and stores the -result back in \c{ST0}, unless the \c{TO} qualifier is given, in -which case it subtracts \c{ST0} from the given operand and stores -the result in the operand. - -\b \c{FSUBR} does the same thing, but does the subtraction the other -way up: so if \c{TO} is not given, it subtracts \c{ST0} from the given -operand and stores the result in \c{ST0}, whereas if \c{TO} is given -it subtracts its operand from \c{ST0} and stores the result in the -operand. - -\b \c{FSUBP} operates like \c{FSUB TO}, but pops the register stack -once it has finished. - -\b \c{FSUBRP} operates like \c{FSUBR TO}, but pops the register stack -once it has finished. - - -\S{insFTST} \i\c{FTST}: Test \c{ST0} Against Zero - -\c FTST ; D9 E4 [8086,FPU] - -\c{FTST} compares \c{ST0} with zero and sets the FPU flags -accordingly. \c{ST0} is treated as the left-hand side of the -comparison, so that a `less-than' result is generated if \c{ST0} is -negative. - - -\S{insFUCOM} \i\c{FUCOMxx}: Floating-Point Unordered Compare - -\c FUCOM fpureg ; DD E0+r [386,FPU] -\c FUCOM ST0,fpureg ; DD E0+r [386,FPU] - -\c FUCOMP fpureg ; DD E8+r [386,FPU] -\c FUCOMP ST0,fpureg ; DD E8+r [386,FPU] - -\c FUCOMPP ; DA E9 [386,FPU] - -\c FUCOMI fpureg ; DB E8+r [P6,FPU] -\c FUCOMI ST0,fpureg ; DB E8+r [P6,FPU] - -\c FUCOMIP fpureg ; DF E8+r [P6,FPU] -\c FUCOMIP ST0,fpureg ; DF E8+r [P6,FPU] - -\b \c{FUCOM} compares \c{ST0} with the given operand, and sets the -FPU flags accordingly. \c{ST0} is treated as the left-hand side of -the comparison, so that the carry flag is set (for a `less-than' -result) if \c{ST0} is less than the given operand. - -\b \c{FUCOMP} does the same as \c{FUCOM}, but pops the register stack -afterwards. \c{FUCOMPP} compares \c{ST0} with \c{ST1} and then pops -the register stack twice. - -\b \c{FUCOMI} and \c{FUCOMIP} work like the corresponding forms of -\c{FUCOM} and \c{FUCOMP}, but write their results directly to the CPU -flags register rather than the FPU status word, so they can be -immediately followed by conditional jump or conditional move -instructions. - -The \c{FUCOM} instructions differ from the \c{FCOM} instructions -(\k{insFCOM}) only in the way they handle quiet NaNs: \c{FUCOM} will -handle them silently and set the condition code flags to an -`unordered' result, whereas \c{FCOM} will generate an exception. - - -\S{insFXAM} \i\c{FXAM}: Examine Class of Value in \c{ST0} - -\c FXAM ; D9 E5 [8086,FPU] - -\c{FXAM} sets the FPU flags \c{C3}, \c{C2} and \c{C0} depending on -the type of value stored in \c{ST0}: - -\c Register contents Flags - -\c Unsupported format 000 -\c NaN 001 -\c Finite number 010 -\c Infinity 011 -\c Zero 100 -\c Empty register 101 -\c Denormal 110 - -Additionally, the \c{C1} flag is set to the sign of the number. - - -\S{insFXCH} \i\c{FXCH}: Floating-Point Exchange - -\c FXCH ; D9 C9 [8086,FPU] -\c FXCH fpureg ; D9 C8+r [8086,FPU] -\c FXCH fpureg,ST0 ; D9 C8+r [8086,FPU] -\c FXCH ST0,fpureg ; D9 C8+r [8086,FPU] - -\c{FXCH} exchanges \c{ST0} with a given FPU register. The no-operand -form exchanges \c{ST0} with \c{ST1}. - - -\S{insFXRSTOR} \i\c{FXRSTOR}: Restore \c{FP}, \c{MMX} and \c{SSE} State - -\c FXRSTOR memory ; 0F AE /1 [P6,SSE,FPU] - -The \c{FXRSTOR} instruction reloads the \c{FPU}, \c{MMX} and \c{SSE} -state (environment and registers), from the 512 byte memory area defined -by the source operand. This data should have been written by a previous -\c{FXSAVE}. - - -\S{insFXSAVE} \i\c{FXSAVE}: Store \c{FP}, \c{MMX} and \c{SSE} State - -\c FXSAVE memory ; 0F AE /0 [P6,SSE,FPU] - -\c{FXSAVE}The FXSAVE instruction writes the current \c{FPU}, \c{MMX} -and \c{SSE} technology states (environment and registers), to the -512 byte memory area defined by the destination operand. It does this -without checking for pending unmasked floating-point exceptions -(similar to the operation of \c{FNSAVE}). - -Unlike the \c{FSAVE/FNSAVE} instructions, the processor retains the -contents of the \c{FPU}, \c{MMX} and \c{SSE} state in the processor -after the state has been saved. This instruction has been optimized -to maximize floating-point save performance. - - -\S{insFXTRACT} \i\c{FXTRACT}: Extract Exponent and Significand - -\c FXTRACT ; D9 F4 [8086,FPU] - -\c{FXTRACT} separates the number in \c{ST0} into its exponent and -significand (mantissa), stores the exponent back into \c{ST0}, and -then pushes the significand on the register stack (so that the -significand ends up in \c{ST0}, and the exponent in \c{ST1}). - - -\S{insFYL2X} \i\c{FYL2X}, \i\c{FYL2XP1}: Compute Y times Log2(X) or Log2(X+1) - -\c FYL2X ; D9 F1 [8086,FPU] -\c FYL2XP1 ; D9 F9 [8086,FPU] - -\c{FYL2X} multiplies \c{ST1} by the base-2 logarithm of \c{ST0}, -stores the result in \c{ST1}, and pops the register stack (so that -the result ends up in \c{ST0}). \c{ST0} must be non-zero and -positive. - -\c{FYL2XP1} works the same way, but replacing the base-2 log of -\c{ST0} with that of \c{ST0} plus one. This time, \c{ST0} must have -magnitude no greater than 1 minus half the square root of two. - - -\S{insHLT} \i\c{HLT}: Halt Processor - -\c HLT ; F4 [8086,PRIV] - -\c{HLT} puts the processor into a halted state, where it will -perform no more operations until restarted by an interrupt or a -reset. - -On the 286 and later processors, this is a privileged instruction. - - -\S{insIBTS} \i\c{IBTS}: Insert Bit String - -\c IBTS r/m16,reg16 ; o16 0F A7 /r [386,UNDOC] -\c IBTS r/m32,reg32 ; o32 0F A7 /r [386,UNDOC] - -The implied operation of this instruction is: - -\c IBTS r/m16,AX,CL,reg16 -\c IBTS r/m32,EAX,CL,reg32 - -Writes a bit string from the source operand to the destination. -\c{CL} indicates the number of bits to be copied, from the low bits -of the source. \c{(E)AX} indicates the low order bit offset in the -destination that is written to. For example, if \c{CL} is set to 4 -and \c{AX} (for 16-bit code) is set to 5, bits 0-3 of \c{src} will -be copied to bits 5-8 of \c{dst}. This instruction is very poorly -documented, and I have been unable to find any official source of -documentation on it. - -\c{IBTS} is supported only on the early Intel 386s, and conflicts -with the opcodes for \c{CMPXCHG486} (on early Intel 486s). NASM -supports it only for completeness. Its counterpart is \c{XBTS} -(see \k{insXBTS}). - - -\S{insIDIV} \i\c{IDIV}: Signed Integer Divide - -\c IDIV r/m8 ; F6 /7 [8086] -\c IDIV r/m16 ; o16 F7 /7 [8086] -\c IDIV r/m32 ; o32 F7 /7 [386] - -\c{IDIV} performs signed integer division. The explicit operand -provided is the divisor; the dividend and destination operands -are implicit, in the following way: - -\b For \c{IDIV r/m8}, \c{AX} is divided by the given operand; -the quotient is stored in \c{AL} and the remainder in \c{AH}. - -\b For \c{IDIV r/m16}, \c{DX:AX} is divided by the given operand; -the quotient is stored in \c{AX} and the remainder in \c{DX}. - -\b For \c{IDIV r/m32}, \c{EDX:EAX} is divided by the given operand; -the quotient is stored in \c{EAX} and the remainder in \c{EDX}. - -Unsigned integer division is performed by the \c{DIV} instruction: -see \k{insDIV}. - - -\S{insIMUL} \i\c{IMUL}: Signed Integer Multiply - -\c IMUL r/m8 ; F6 /5 [8086] -\c IMUL r/m16 ; o16 F7 /5 [8086] -\c IMUL r/m32 ; o32 F7 /5 [386] - -\c IMUL reg16,r/m16 ; o16 0F AF /r [386] -\c IMUL reg32,r/m32 ; o32 0F AF /r [386] - -\c IMUL reg16,imm8 ; o16 6B /r ib [186] -\c IMUL reg16,imm16 ; o16 69 /r iw [186] -\c IMUL reg32,imm8 ; o32 6B /r ib [386] -\c IMUL reg32,imm32 ; o32 69 /r id [386] - -\c IMUL reg16,r/m16,imm8 ; o16 6B /r ib [186] -\c IMUL reg16,r/m16,imm16 ; o16 69 /r iw [186] -\c IMUL reg32,r/m32,imm8 ; o32 6B /r ib [386] -\c IMUL reg32,r/m32,imm32 ; o32 69 /r id [386] - -\c{IMUL} performs signed integer multiplication. For the -single-operand form, the other operand and destination are -implicit, in the following way: - -\b For \c{IMUL r/m8}, \c{AL} is multiplied by the given operand; -the product is stored in \c{AX}. - -\b For \c{IMUL r/m16}, \c{AX} is multiplied by the given operand; -the product is stored in \c{DX:AX}. - -\b For \c{IMUL r/m32}, \c{EAX} is multiplied by the given operand; -the product is stored in \c{EDX:EAX}. - -The two-operand form multiplies its two operands and stores the -result in the destination (first) operand. The three-operand -form multiplies its last two operands and stores the result in -the first operand. - -The two-operand form with an immediate second operand is in -fact a shorthand for the three-operand form, as can be seen by -examining the opcode descriptions: in the two-operand form, the -code \c{/r} takes both its register and \c{r/m} parts from the -same operand (the first one). - -In the forms with an 8-bit immediate operand and another longer -source operand, the immediate operand is considered to be signed, -and is sign-extended to the length of the other source operand. -In these cases, the \c{BYTE} qualifier is necessary to force -NASM to generate this form of the instruction. - -Unsigned integer multiplication is performed by the \c{MUL} -instruction: see \k{insMUL}. - - -\S{insIN} \i\c{IN}: Input from I/O Port - -\c IN AL,imm8 ; E4 ib [8086] -\c IN AX,imm8 ; o16 E5 ib [8086] -\c IN EAX,imm8 ; o32 E5 ib [386] -\c IN AL,DX ; EC [8086] -\c IN AX,DX ; o16 ED [8086] -\c IN EAX,DX ; o32 ED [386] - -\c{IN} reads a byte, word or doubleword from the specified I/O port, -and stores it in the given destination register. The port number may -be specified as an immediate value if it is between 0 and 255, and -otherwise must be stored in \c{DX}. See also \c{OUT} (\k{insOUT}). - - -\S{insINC} \i\c{INC}: Increment Integer - -\c INC reg16 ; o16 40+r [8086] -\c INC reg32 ; o32 40+r [386] -\c INC r/m8 ; FE /0 [8086] -\c INC r/m16 ; o16 FF /0 [8086] -\c INC r/m32 ; o32 FF /0 [386] - -\c{INC} adds 1 to its operand. It does \e{not} affect the carry -flag: to affect the carry flag, use \c{ADD something,1} (see -\k{insADD}). \c{INC} affects all the other flags according to the result. - -This instruction can be used with a \c{LOCK} prefix to allow atomic execution. - -See also \c{DEC} (\k{insDEC}). - - -\S{insINSB} \i\c{INSB}, \i\c{INSW}, \i\c{INSD}: Input String from I/O Port - -\c INSB ; 6C [186] -\c INSW ; o16 6D [186] -\c INSD ; o32 6D [386] - -\c{INSB} inputs a byte from the I/O port specified in \c{DX} and -stores it at \c{[ES:DI]} or \c{[ES:EDI]}. It then increments or -decrements (depending on the direction flag: increments if the flag -is clear, decrements if it is set) \c{DI} or \c{EDI}. - -The register used is \c{DI} if the address size is 16 bits, and -\c{EDI} if it is 32 bits. If you need to use an address size not -equal to the current \c{BITS} setting, you can use an explicit -\i\c{a16} or \i\c{a32} prefix. - -Segment override prefixes have no effect for this instruction: the -use of \c{ES} for the load from \c{[DI]} or \c{[EDI]} cannot be -overridden. - -\c{INSW} and \c{INSD} work in the same way, but they input a word or -a doubleword instead of a byte, and increment or decrement the -addressing register by 2 or 4 instead of 1. - -The \c{REP} prefix may be used to repeat the instruction \c{CX} (or -\c{ECX} - again, the address size chooses which) times. - -See also \c{OUTSB}, \c{OUTSW} and \c{OUTSD} (\k{insOUTSB}). - - -\S{insINT} \i\c{INT}: Software Interrupt - -\c INT imm8 ; CD ib [8086] - -\c{INT} causes a software interrupt through a specified vector -number from 0 to 255. - -The code generated by the \c{INT} instruction is always two bytes -long: although there are short forms for some \c{INT} instructions, -NASM does not generate them when it sees the \c{INT} mnemonic. In -order to generate single-byte breakpoint instructions, use the -\c{INT3} or \c{INT1} instructions (see \k{insINT1}) instead. - - -\S{insINT1} \i\c{INT3}, \i\c{INT1}, \i\c{ICEBP}, \i\c{INT01}: Breakpoints - -\c INT1 ; F1 [P6] -\c ICEBP ; F1 [P6] -\c INT01 ; F1 [P6] - -\c INT3 ; CC [8086] -\c INT03 ; CC [8086] - -\c{INT1} and \c{INT3} are short one-byte forms of the instructions -\c{INT 1} and \c{INT 3} (see \k{insINT}). They perform a similar -function to their longer counterparts, but take up less code space. -They are used as breakpoints by debuggers. - -\b \c{INT1}, and its alternative synonyms \c{INT01} and \c{ICEBP}, is -an instruction used by in-circuit emulators (ICEs). It is present, -though not documented, on some processors down to the 286, but is -only documented for the Pentium Pro. \c{INT3} is the instruction -normally used as a breakpoint by debuggers. - -\b \c{INT3}, and its synonym \c{INT03}, is not precisely equivalent to -\c{INT 3}: the short form, since it is designed to be used as a -breakpoint, bypasses the normal \c{IOPL} checks in virtual-8086 mode, -and also does not go through interrupt redirection. - - -\S{insINTO} \i\c{INTO}: Interrupt if Overflow - -\c INTO ; CE [8086] - -\c{INTO} performs an \c{INT 4} software interrupt (see \k{insINT}) -if and only if the overflow flag is set. - - -\S{insINVD} \i\c{INVD}: Invalidate Internal Caches - -\c INVD ; 0F 08 [486] - -\c{INVD} invalidates and empties the processor's internal caches, -and causes the processor to instruct external caches to do the same. -It does not write the contents of the caches back to memory first: -any modified data held in the caches will be lost. To write the data -back first, use \c{WBINVD} (\k{insWBINVD}). - - -\S{insINVLPG} \i\c{INVLPG}: Invalidate TLB Entry - -\c INVLPG mem ; 0F 01 /7 [486] - -\c{INVLPG} invalidates the translation lookahead buffer (TLB) entry -associated with the supplied memory address. - - -\S{insIRET} \i\c{IRET}, \i\c{IRETW}, \i\c{IRETD}: Return from Interrupt - -\c IRET ; CF [8086] -\c IRETW ; o16 CF [8086] -\c IRETD ; o32 CF [386] - -\c{IRET} returns from an interrupt (hardware or software) by means -of popping \c{IP} (or \c{EIP}), \c{CS} and the flags off the stack -and then continuing execution from the new \c{CS:IP}. - -\c{IRETW} pops \c{IP}, \c{CS} and the flags as 2 bytes each, taking -6 bytes off the stack in total. \c{IRETD} pops \c{EIP} as 4 bytes, -pops a further 4 bytes of which the top two are discarded and the -bottom two go into \c{CS}, and pops the flags as 4 bytes as well, -taking 12 bytes off the stack. - -\c{IRET} is a shorthand for either \c{IRETW} or \c{IRETD}, depending -on the default \c{BITS} setting at the time. - - -\S{insJcc} \i\c{Jcc}: Conditional Branch - -\c Jcc imm ; 70+cc rb [8086] -\c Jcc NEAR imm ; 0F 80+cc rw/rd [386] - -The \i{conditional jump} instructions execute a near (same segment) -jump if and only if their conditions are satisfied. For example, -\c{JNZ} jumps only if the zero flag is not set. - -The ordinary form of the instructions has only a 128-byte range; the -\c{NEAR} form is a 386 extension to the instruction set, and can -span the full size of a segment. NASM will not override your choice -of jump instruction: if you want \c{Jcc NEAR}, you have to use the -\c{NEAR} keyword. - -The \c{SHORT} keyword is allowed on the first form of the -instruction, for clarity, but is not necessary. - -For details of the condition codes, see \k{iref-cc}. - - -\S{insJCXZ} \i\c{JCXZ}, \i\c{JECXZ}: Jump if CX/ECX Zero - -\c JCXZ imm ; a16 E3 rb [8086] -\c JECXZ imm ; a32 E3 rb [386] - -\c{JCXZ} performs a short jump (with maximum range 128 bytes) if and -only if the contents of the \c{CX} register is 0. \c{JECXZ} does the -same thing, but with \c{ECX}. - - -\S{insJMP} \i\c{JMP}: Jump - -\c JMP imm ; E9 rw/rd [8086] -\c JMP SHORT imm ; EB rb [8086] -\c JMP imm:imm16 ; o16 EA iw iw [8086] -\c JMP imm:imm32 ; o32 EA id iw [386] -\c JMP FAR mem ; o16 FF /5 [8086] -\c JMP FAR mem32 ; o32 FF /5 [386] -\c JMP r/m16 ; o16 FF /4 [8086] -\c JMP r/m32 ; o32 FF /4 [386] - -\c{JMP} jumps to a given address. The address may be specified as an -absolute segment and offset, or as a relative jump within the -current segment. - -\c{JMP SHORT imm} has a maximum range of 128 bytes, since the -displacement is specified as only 8 bits, but takes up less code -space. NASM does not choose when to generate \c{JMP SHORT} for you: -you must explicitly code \c{SHORT} every time you want a short jump. - -You can choose between the two immediate \i{far jump} forms (\c{JMP -imm:imm}) by the use of the \c{WORD} and \c{DWORD} keywords: \c{JMP -WORD 0x1234:0x5678}) or \c{JMP DWORD 0x1234:0x56789abc}. - -The \c{JMP FAR mem} forms execute a far jump by loading the -destination address out of memory. The address loaded consists of 16 -or 32 bits of offset (depending on the operand size), and 16 bits of -segment. The operand size may be overridden using \c{JMP WORD FAR -mem} or \c{JMP DWORD FAR mem}. - -The \c{JMP r/m} forms execute a \i{near jump} (within the same -segment), loading the destination address out of memory or out of a -register. The keyword \c{NEAR} may be specified, for clarity, in -these forms, but is not necessary. Again, operand size can be -overridden using \c{JMP WORD mem} or \c{JMP DWORD mem}. - -As a convenience, NASM does not require you to jump to a far symbol -by coding the cumbersome \c{JMP SEG routine:routine}, but instead -allows the easier synonym \c{JMP FAR routine}. - -The \c{JMP r/m} forms given above are near calls; NASM will accept -the \c{NEAR} keyword (e.g. \c{JMP NEAR [address]}), even though it -is not strictly necessary. - - -\S{insLAHF} \i\c{LAHF}: Load AH from Flags - -\c LAHF ; 9F [8086] - -\c{LAHF} sets the \c{AH} register according to the contents of the -low byte of the flags word. - -The operation of \c{LAHF} is: - -\c AH <-- SF:ZF:0:AF:0:PF:1:CF - -See also \c{SAHF} (\k{insSAHF}). - - -\S{insLAR} \i\c{LAR}: Load Access Rights - -\c LAR reg16,r/m16 ; o16 0F 02 /r [286,PRIV] -\c LAR reg32,r/m32 ; o32 0F 02 /r [286,PRIV] - -\c{LAR} takes the segment selector specified by its source (second) -operand, finds the corresponding segment descriptor in the GDT or -LDT, and loads the access-rights byte of the descriptor into its -destination (first) operand. - - -\S{insLDMXCSR} \i\c{LDMXCSR}: Load Streaming SIMD Extension - Control/Status - -\c LDMXCSR mem32 ; 0F AE /2 [KATMAI,SSE] - -\c{LDMXCSR} loads 32-bits of data from the specified memory location -into the \c{MXCSR} control/status register. \c{MXCSR} is used to -enable masked/unmasked exception handling, to set rounding modes, -to set flush-to-zero mode, and to view exception status flags. - -For details of the \c{MXCSR} register, see the Intel processor docs. - -See also \c{STMXCSR} (\k{insSTMXCSR} - - -\S{insLDS} \i\c{LDS}, \i\c{LES}, \i\c{LFS}, \i\c{LGS}, \i\c{LSS}: Load Far Pointer - -\c LDS reg16,mem ; o16 C5 /r [8086] -\c LDS reg32,mem ; o32 C5 /r [386] - -\c LES reg16,mem ; o16 C4 /r [8086] -\c LES reg32,mem ; o32 C4 /r [386] - -\c LFS reg16,mem ; o16 0F B4 /r [386] -\c LFS reg32,mem ; o32 0F B4 /r [386] - -\c LGS reg16,mem ; o16 0F B5 /r [386] -\c LGS reg32,mem ; o32 0F B5 /r [386] - -\c LSS reg16,mem ; o16 0F B2 /r [386] -\c LSS reg32,mem ; o32 0F B2 /r [386] - -These instructions load an entire far pointer (16 or 32 bits of -offset, plus 16 bits of segment) out of memory in one go. \c{LDS}, -for example, loads 16 or 32 bits from the given memory address into -the given register (depending on the size of the register), then -loads the \e{next} 16 bits from memory into \c{DS}. \c{LES}, -\c{LFS}, \c{LGS} and \c{LSS} work in the same way but use the other -segment registers. - - -\S{insLEA} \i\c{LEA}: Load Effective Address - -\c LEA reg16,mem ; o16 8D /r [8086] -\c LEA reg32,mem ; o32 8D /r [386] - -\c{LEA}, despite its syntax, does not access memory. It calculates -the effective address specified by its second operand as if it were -going to load or store data from it, but instead it stores the -calculated address into the register specified by its first operand. -This can be used to perform quite complex calculations (e.g. \c{LEA -EAX,[EBX+ECX*4+100]}) in one instruction. - -\c{LEA}, despite being a purely arithmetic instruction which -accesses no memory, still requires square brackets around its second -operand, as if it were a memory reference. - -The size of the calculation is the current \e{address} size, and the -size that the result is stored as is the current \e{operand} size. -If the address and operand size are not the same, then if the -addressing mode was 32-bits, the low 16-bits are stored, and if the -address was 16-bits, it is zero-extended to 32-bits before storing. - - -\S{insLEAVE} \i\c{LEAVE}: Destroy Stack Frame - -\c LEAVE ; C9 [186] - -\c{LEAVE} destroys a stack frame of the form created by the -\c{ENTER} instruction (see \k{insENTER}). It is functionally -equivalent to \c{MOV ESP,EBP} followed by \c{POP EBP} (or \c{MOV -SP,BP} followed by \c{POP BP} in 16-bit mode). - - -\S{insLFENCE} \i\c{LFENCE}: Load Fence - -\c LFENCE ; 0F AE /5 [WILLAMETTE,SSE2] - -\c{LFENCE} performs a serialising operation on all loads from memory -that were issued before the \c{LFENCE} instruction. This guarantees that -all memory reads before the \c{LFENCE} instruction are visible before any -reads after the \c{LFENCE} instruction. - -\c{LFENCE} is ordered respective to other \c{LFENCE} instruction, \c{MFENCE}, -any memory read and any other serialising instruction (such as \c{CPUID}). - -Weakly ordered memory types can be used to achieve higher processor -performance through such techniques as out-of-order issue and -speculative reads. The degree to which a consumer of data recognizes -or knows that the data is weakly ordered varies among applications -and may be unknown to the producer of this data. The \c{LFENCE} -instruction provides a performance-efficient way of ensuring load -ordering between routines that produce weakly-ordered results and -routines that consume that data. - -\c{LFENCE} uses the following ModRM encoding: - -\c Mod (7:6) = 11B -\c Reg/Opcode (5:3) = 101B -\c R/M (2:0) = 000B - -All other ModRM encodings are defined to be reserved, and use -of these encodings risks incompatibility with future processors. - -See also \c{SFENCE} (\k{insSFENCE}) and \c{MFENCE} (\k{insMFENCE}). - - -\S{insLGDT} \i\c{LGDT}, \i\c{LIDT}, \i\c{LLDT}: Load Descriptor Tables - -\c LGDT mem ; 0F 01 /2 [286,PRIV] -\c LIDT mem ; 0F 01 /3 [286,PRIV] -\c LLDT r/m16 ; 0F 00 /2 [286,PRIV] - -\c{LGDT} and \c{LIDT} both take a 6-byte memory area as an operand: -they load a 16-bit size limit and a 32-bit linear address from that -area (in the opposite order) into the \c{GDTR} (global descriptor table -register) or \c{IDTR} (interrupt descriptor table register). These are -the only instructions which directly use \e{linear} addresses, rather -than segment/offset pairs. - -\c{LLDT} takes a segment selector as an operand. The processor looks -up that selector in the GDT and stores the limit and base address -given there into the \c{LDTR} (local descriptor table register). - -See also \c{SGDT}, \c{SIDT} and \c{SLDT} (\k{insSGDT}). - - -\S{insLMSW} \i\c{LMSW}: Load/Store Machine Status Word - -\c LMSW r/m16 ; 0F 01 /6 [286,PRIV] - -\c{LMSW} loads the bottom four bits of the source operand into the -bottom four bits of the \c{CR0} control register (or the Machine -Status Word, on 286 processors). See also \c{SMSW} (\k{insSMSW}). - - -\S{insLOADALL} \i\c{LOADALL}, \i\c{LOADALL286}: Load Processor State - -\c LOADALL ; 0F 07 [386,UNDOC] -\c LOADALL286 ; 0F 05 [286,UNDOC] - -This instruction, in its two different-opcode forms, is apparently -supported on most 286 processors, some 386 and possibly some 486. -The opcode differs between the 286 and the 386. - -The function of the instruction is to load all information relating -to the state of the processor out of a block of memory: on the 286, -this block is located implicitly at absolute address \c{0x800}, and -on the 386 and 486 it is at \c{[ES:EDI]}. - - -\S{insLODSB} \i\c{LODSB}, \i\c{LODSW}, \i\c{LODSD}: Load from String - -\c LODSB ; AC [8086] -\c LODSW ; o16 AD [8086] -\c LODSD ; o32 AD [386] - -\c{LODSB} loads a byte from \c{[DS:SI]} or \c{[DS:ESI]} into \c{AL}. -It then increments or decrements (depending on the direction flag: -increments if the flag is clear, decrements if it is set) \c{SI} or -\c{ESI}. - -The register used is \c{SI} if the address size is 16 bits, and -\c{ESI} if it is 32 bits. If you need to use an address size not -equal to the current \c{BITS} setting, you can use an explicit -\i\c{a16} or \i\c{a32} prefix. - -The segment register used to load from \c{[SI]} or \c{[ESI]} can be -overridden by using a segment register name as a prefix (for -example, \c{ES LODSB}). - -\c{LODSW} and \c{LODSD} work in the same way, but they load a -word or a doubleword instead of a byte, and increment or decrement -the addressing registers by 2 or 4 instead of 1. - - -\S{insLOOP} \i\c{LOOP}, \i\c{LOOPE}, \i\c{LOOPZ}, \i\c{LOOPNE}, \i\c{LOOPNZ}: Loop with Counter - -\c LOOP imm ; E2 rb [8086] -\c LOOP imm,CX ; a16 E2 rb [8086] -\c LOOP imm,ECX ; a32 E2 rb [386] - -\c LOOPE imm ; E1 rb [8086] -\c LOOPE imm,CX ; a16 E1 rb [8086] -\c LOOPE imm,ECX ; a32 E1 rb [386] -\c LOOPZ imm ; E1 rb [8086] -\c LOOPZ imm,CX ; a16 E1 rb [8086] -\c LOOPZ imm,ECX ; a32 E1 rb [386] - -\c LOOPNE imm ; E0 rb [8086] -\c LOOPNE imm,CX ; a16 E0 rb [8086] -\c LOOPNE imm,ECX ; a32 E0 rb [386] -\c LOOPNZ imm ; E0 rb [8086] -\c LOOPNZ imm,CX ; a16 E0 rb [8086] -\c LOOPNZ imm,ECX ; a32 E0 rb [386] - -\c{LOOP} decrements its counter register (either \c{CX} or \c{ECX} - -if one is not specified explicitly, the \c{BITS} setting dictates -which is used) by one, and if the counter does not become zero as a -result of this operation, it jumps to the given label. The jump has -a range of 128 bytes. - -\c{LOOPE} (or its synonym \c{LOOPZ}) adds the additional condition -that it only jumps if the counter is nonzero \e{and} the zero flag -is set. Similarly, \c{LOOPNE} (and \c{LOOPNZ}) jumps only if the -counter is nonzero and the zero flag is clear. - - -\S{insLSL} \i\c{LSL}: Load Segment Limit - -\c LSL reg16,r/m16 ; o16 0F 03 /r [286,PRIV] -\c LSL reg32,r/m32 ; o32 0F 03 /r [286,PRIV] - -\c{LSL} is given a segment selector in its source (second) operand; -it computes the segment limit value by loading the segment limit -field from the associated segment descriptor in the \c{GDT} or \c{LDT}. -(This involves shifting left by 12 bits if the segment limit is -page-granular, and not if it is byte-granular; so you end up with a -byte limit in either case.) The segment limit obtained is then -loaded into the destination (first) operand. - - -\S{insLTR} \i\c{LTR}: Load Task Register - -\c LTR r/m16 ; 0F 00 /3 [286,PRIV] - -\c{LTR} looks up the segment base and limit in the GDT or LDT -descriptor specified by the segment selector given as its operand, -and loads them into the Task Register. - - -\S{insMASKMOVDQU} \i\c{MASKMOVDQU}: Byte Mask Write - -\c MASKMOVDQU xmm1,xmm2 ; 66 0F F7 /r [WILLAMETTE,SSE2] - -\c{MASKMOVDQU} stores data from xmm1 to the location specified by -\c{ES:(E)DI}. The size of the store depends on the address-size -attribute. The most significant bit in each byte of the mask -register xmm2 is used to selectively write the data (0 = no write, -1 = write) on a per-byte basis. - - -\S{insMASKMOVQ} \i\c{MASKMOVQ}: Byte Mask Write - -\c MASKMOVQ mm1,mm2 ; 0F F7 /r [KATMAI,MMX] - -\c{MASKMOVQ} stores data from mm1 to the location specified by -\c{ES:(E)DI}. The size of the store depends on the address-size -attribute. The most significant bit in each byte of the mask -register mm2 is used to selectively write the data (0 = no write, -1 = write) on a per-byte basis. - - -\S{insMAXPD} \i\c{MAXPD}: Return Packed Double-Precision FP Maximum - -\c MAXPD xmm1,xmm2/m128 ; 66 0F 5F /r [WILLAMETTE,SSE2] - -\c{MAXPD} performs a SIMD compare of the packed double-precision -FP numbers from xmm1 and xmm2/mem, and stores the maximum values -of each pair of values in xmm1. If the values being compared are -both zeroes, source2 (xmm2/m128) would be returned. If source2 -(xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the -destination (i.e., a QNaN version of the SNaN is not returned). - - -\S{insMAXPS} \i\c{MAXPS}: Return Packed Single-Precision FP Maximum - -\c MAXPS xmm1,xmm2/m128 ; 0F 5F /r [KATMAI,SSE] - -\c{MAXPS} performs a SIMD compare of the packed single-precision -FP numbers from xmm1 and xmm2/mem, and stores the maximum values -of each pair of values in xmm1. If the values being compared are -both zeroes, source2 (xmm2/m128) would be returned. If source2 -(xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the -destination (i.e., a QNaN version of the SNaN is not returned). - - -\S{insMAXSD} \i\c{MAXSD}: Return Scalar Double-Precision FP Maximum - -\c MAXSD xmm1,xmm2/m64 ; F2 0F 5F /r [WILLAMETTE,SSE2] - -\c{MAXSD} compares the low-order double-precision FP numbers from -xmm1 and xmm2/mem, and stores the maximum value in xmm1. If the -values being compared are both zeroes, source2 (xmm2/m64) would -be returned. If source2 (xmm2/m64) is an SNaN, this SNaN is -forwarded unchanged to the destination (i.e., a QNaN version of -the SNaN is not returned). The high quadword of the destination -is left unchanged. - - -\S{insMAXSS} \i\c{MAXSS}: Return Scalar Single-Precision FP Maximum - -\c MAXSS xmm1,xmm2/m32 ; F3 0F 5F /r [KATMAI,SSE] - -\c{MAXSS} compares the low-order single-precision FP numbers from -xmm1 and xmm2/mem, and stores the maximum value in xmm1. If the -values being compared are both zeroes, source2 (xmm2/m32) would -be returned. If source2 (xmm2/m32) is an SNaN, this SNaN is -forwarded unchanged to the destination (i.e., a QNaN version of -the SNaN is not returned). The high three doublewords of the -destination are left unchanged. - - -\S{insMFENCE} \i\c{MFENCE}: Memory Fence - -\c MFENCE ; 0F AE /6 [WILLAMETTE,SSE2] - -\c{MFENCE} performs a serialising operation on all loads from memory -and writes to memory that were issued before the \c{MFENCE} instruction. -This guarantees that all memory reads and writes before the \c{MFENCE} -instruction are completed before any reads and writes after the -\c{MFENCE} instruction. - -\c{MFENCE} is ordered respective to other \c{MFENCE} instructions, -\c{LFENCE}, \c{SFENCE}, any memory read and any other serialising -instruction (such as \c{CPUID}). - -Weakly ordered memory types can be used to achieve higher processor -performance through such techniques as out-of-order issue, speculative -reads, write-combining, and write-collapsing. The degree to which a -consumer of data recognizes or knows that the data is weakly ordered -varies among applications and may be unknown to the producer of this -data. The \c{MFENCE} instruction provides a performance-efficient way -of ensuring load and store ordering between routines that produce -weakly-ordered results and routines that consume that data. - -\c{MFENCE} uses the following ModRM encoding: - -\c Mod (7:6) = 11B -\c Reg/Opcode (5:3) = 110B -\c R/M (2:0) = 000B - -All other ModRM encodings are defined to be reserved, and use -of these encodings risks incompatibility with future processors. - -See also \c{LFENCE} (\k{insLFENCE}) and \c{SFENCE} (\k{insSFENCE}). - - -\S{insMINPD} \i\c{MINPD}: Return Packed Double-Precision FP Minimum - -\c MINPD xmm1,xmm2/m128 ; 66 0F 5D /r [WILLAMETTE,SSE2] - -\c{MINPD} performs a SIMD compare of the packed double-precision -FP numbers from xmm1 and xmm2/mem, and stores the minimum values -of each pair of values in xmm1. If the values being compared are -both zeroes, source2 (xmm2/m128) would be returned. If source2 -(xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the -destination (i.e., a QNaN version of the SNaN is not returned). - - -\S{insMINPS} \i\c{MINPS}: Return Packed Single-Precision FP Minimum - -\c MINPS xmm1,xmm2/m128 ; 0F 5D /r [KATMAI,SSE] - -\c{MINPS} performs a SIMD compare of the packed single-precision -FP numbers from xmm1 and xmm2/mem, and stores the minimum values -of each pair of values in xmm1. If the values being compared are -both zeroes, source2 (xmm2/m128) would be returned. If source2 -(xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the -destination (i.e., a QNaN version of the SNaN is not returned). - - -\S{insMINSD} \i\c{MINSD}: Return Scalar Double-Precision FP Minimum - -\c MINSD xmm1,xmm2/m64 ; F2 0F 5D /r [WILLAMETTE,SSE2] - -\c{MINSD} compares the low-order double-precision FP numbers from -xmm1 and xmm2/mem, and stores the minimum value in xmm1. If the -values being compared are both zeroes, source2 (xmm2/m64) would -be returned. If source2 (xmm2/m64) is an SNaN, this SNaN is -forwarded unchanged to the destination (i.e., a QNaN version of -the SNaN is not returned). The high quadword of the destination -is left unchanged. - - -\S{insMINSS} \i\c{MINSS}: Return Scalar Single-Precision FP Minimum - -\c MINSS xmm1,xmm2/m32 ; F3 0F 5D /r [KATMAI,SSE] - -\c{MINSS} compares the low-order single-precision FP numbers from -xmm1 and xmm2/mem, and stores the minimum value in xmm1. If the -values being compared are both zeroes, source2 (xmm2/m32) would -be returned. If source2 (xmm2/m32) is an SNaN, this SNaN is -forwarded unchanged to the destination (i.e., a QNaN version of -the SNaN is not returned). The high three doublewords of the -destination are left unchanged. - - -\S{insMOV} \i\c{MOV}: Move Data - -\c MOV r/m8,reg8 ; 88 /r [8086] -\c MOV r/m16,reg16 ; o16 89 /r [8086] -\c MOV r/m32,reg32 ; o32 89 /r [386] -\c MOV reg8,r/m8 ; 8A /r [8086] -\c MOV reg16,r/m16 ; o16 8B /r [8086] -\c MOV reg32,r/m32 ; o32 8B /r [386] - -\c MOV reg8,imm8 ; B0+r ib [8086] -\c MOV reg16,imm16 ; o16 B8+r iw [8086] -\c MOV reg32,imm32 ; o32 B8+r id [386] -\c MOV r/m8,imm8 ; C6 /0 ib [8086] -\c MOV r/m16,imm16 ; o16 C7 /0 iw [8086] -\c MOV r/m32,imm32 ; o32 C7 /0 id [386] - -\c MOV AL,memoffs8 ; A0 ow/od [8086] -\c MOV AX,memoffs16 ; o16 A1 ow/od [8086] -\c MOV EAX,memoffs32 ; o32 A1 ow/od [386] -\c MOV memoffs8,AL ; A2 ow/od [8086] -\c MOV memoffs16,AX ; o16 A3 ow/od [8086] -\c MOV memoffs32,EAX ; o32 A3 ow/od [386] - -\c MOV r/m16,segreg ; o16 8C /r [8086] -\c MOV r/m32,segreg ; o32 8C /r [386] -\c MOV segreg,r/m16 ; o16 8E /r [8086] -\c MOV segreg,r/m32 ; o32 8E /r [386] - -\c MOV reg32,CR0/2/3/4 ; 0F 20 /r [386] -\c MOV reg32,DR0/1/2/3/6/7 ; 0F 21 /r [386] -\c MOV reg32,TR3/4/5/6/7 ; 0F 24 /r [386] -\c MOV CR0/2/3/4,reg32 ; 0F 22 /r [386] -\c MOV DR0/1/2/3/6/7,reg32 ; 0F 23 /r [386] -\c MOV TR3/4/5/6/7,reg32 ; 0F 26 /r [386] - -\c{MOV} copies the contents of its source (second) operand into its -destination (first) operand. - -In all forms of the \c{MOV} instruction, the two operands are the -same size, except for moving between a segment register and an -\c{r/m32} operand. These instructions are treated exactly like the -corresponding 16-bit equivalent (so that, for example, \c{MOV -DS,EAX} functions identically to \c{MOV DS,AX} but saves a prefix -when in 32-bit mode), except that when a segment register is moved -into a 32-bit destination, the top two bytes of the result are -undefined. - -\c{MOV} may not use \c{CS} as a destination. - -\c{CR4} is only a supported register on the Pentium and above. - -Test registers are supported on 386/486 processors and on some -non-Intel Pentium class processors. - - -\S{insMOVAPD} \i\c{MOVAPD}: Move Aligned Packed Double-Precision FP Values - -\c MOVAPD xmm1,xmm2/mem128 ; 66 0F 28 /r [WILLAMETTE,SSE2] -\c MOVAPD xmm1/mem128,xmm2 ; 66 0F 29 /r [WILLAMETTE,SSE2] - -\c{MOVAPD} moves a double quadword containing 2 packed double-precision -FP values from the source operand to the destination. When the source -or destination operand is a memory location, it must be aligned on a -16-byte boundary. - -To move data in and out of memory locations that are not known to be on -16-byte boundaries, use the \c{MOVUPD} instruction (\k{insMOVUPD}). - - -\S{insMOVAPS} \i\c{MOVAPS}: Move Aligned Packed Single-Precision FP Values - -\c MOVAPS xmm1,xmm2/mem128 ; 0F 28 /r [KATMAI,SSE] -\c MOVAPS xmm1/mem128,xmm2 ; 0F 29 /r [KATMAI,SSE] - -\c{MOVAPS} moves a double quadword containing 4 packed single-precision -FP values from the source operand to the destination. When the source -or destination operand is a memory location, it must be aligned on a -16-byte boundary. - -To move data in and out of memory locations that are not known to be on -16-byte boundaries, use the \c{MOVUPS} instruction (\k{insMOVUPS}). - - -\S{insMOVD} \i\c{MOVD}: Move Doubleword to/from MMX Register - -\c MOVD mm,r/m32 ; 0F 6E /r [PENT,MMX] -\c MOVD r/m32,mm ; 0F 7E /r [PENT,MMX] -\c MOVD xmm,r/m32 ; 66 0F 6E /r [WILLAMETTE,SSE2] -\c MOVD r/m32,xmm ; 66 0F 7E /r [WILLAMETTE,SSE2] - -\c{MOVD} copies 32 bits from its source (second) operand into its -destination (first) operand. When the destination is a 64-bit \c{MMX} -register or a 128-bit \c{XMM} register, the input value is zero-extended -to fill the destination register. - - -\S{insMOVDQ2Q} \i\c{MOVDQ2Q}: Move Quadword from XMM to MMX register. - -\c MOVDQ2Q mm,xmm ; F2 OF D6 /r [WILLAMETTE,SSE2] - -\c{MOVDQ2Q} moves the low quadword from the source operand to the -destination operand. - - -\S{insMOVDQA} \i\c{MOVDQA}: Move Aligned Double Quadword - -\c MOVDQA xmm1,xmm2/m128 ; 66 OF 6F /r [WILLAMETTE,SSE2] -\c MOVDQA xmm1/m128,xmm2 ; 66 OF 7F /r [WILLAMETTE,SSE2] - -\c{MOVDQA} moves a double quadword from the source operand to the -destination operand. When the source or destination operand is a -memory location, it must be aligned to a 16-byte boundary. - -To move a double quadword to or from unaligned memory locations, -use the \c{MOVDQU} instruction (\k{insMOVDQU}). - - -\S{insMOVDQU} \i\c{MOVDQU}: Move Unaligned Double Quadword - -\c MOVDQU xmm1,xmm2/m128 ; F3 OF 6F /r [WILLAMETTE,SSE2] -\c MOVDQU xmm1/m128,xmm2 ; F3 OF 7F /r [WILLAMETTE,SSE2] - -\c{MOVDQU} moves a double quadword from the source operand to the -destination operand. When the source or destination operand is a -memory location, the memory may be unaligned. - -To move a double quadword to or from known aligned memory locations, -use the \c{MOVDQA} instruction (\k{insMOVDQA}). - - -\S{insMOVHLPS} \i\c{MOVHLPS}: Move Packed Single-Precision FP High to Low - -\c MOVHLPS xmm1,xmm2 ; OF 12 /r [KATMAI,SSE] - -\c{MOVHLPS} moves the two packed single-precision FP values from the -high quadword of the source register xmm2 to the low quadword of the -destination register, xmm2. The upper quadword of xmm1 is left unchanged. - -The operation of this instruction is: - -\c dst[0-63] := src[64-127], -\c dst[64-127] remains unchanged. - - -\S{insMOVHPD} \i\c{MOVHPD}: Move High Packed Double-Precision FP - -\c MOVHPD xmm,m64 ; 66 OF 16 /r [WILLAMETTE,SSE2] -\c MOVHPD m64,xmm ; 66 OF 17 /r [WILLAMETTE,SSE2] - -\c{MOVHPD} moves a double-precision FP value between the source and -destination operands. One of the operands is a 64-bit memory location, -the other is the high quadword of an \c{XMM} register. - -The operation of this instruction is: - -\c mem[0-63] := xmm[64-127]; - -or - -\c xmm[0-63] remains unchanged; -\c xmm[64-127] := mem[0-63]. - - -\S{insMOVHPS} \i\c{MOVHPS}: Move High Packed Single-Precision FP - -\c MOVHPS xmm,m64 ; 0F 16 /r [KATMAI,SSE] -\c MOVHPS m64,xmm ; 0F 17 /r [KATMAI,SSE] - -\c{MOVHPS} moves two packed single-precision FP values between the source -and destination operands. One of the operands is a 64-bit memory location, -the other is the high quadword of an \c{XMM} register. - -The operation of this instruction is: - -\c mem[0-63] := xmm[64-127]; - -or - -\c xmm[0-63] remains unchanged; -\c xmm[64-127] := mem[0-63]. - - -\S{insMOVLHPS} \i\c{MOVLHPS}: Move Packed Single-Precision FP Low to High - -\c MOVLHPS xmm1,xmm2 ; OF 16 /r [KATMAI,SSE] - -\c{MOVLHPS} moves the two packed single-precision FP values from the -low quadword of the source register xmm2 to the high quadword of the -destination register, xmm2. The low quadword of xmm1 is left unchanged. - -The operation of this instruction is: - -\c dst[0-63] remains unchanged; -\c dst[64-127] := src[0-63]. - -\S{insMOVLPD} \i\c{MOVLPD}: Move Low Packed Double-Precision FP - -\c MOVLPD xmm,m64 ; 66 OF 12 /r [WILLAMETTE,SSE2] -\c MOVLPD m64,xmm ; 66 OF 13 /r [WILLAMETTE,SSE2] - -\c{MOVLPD} moves a double-precision FP value between the source and -destination operands. One of the operands is a 64-bit memory location, -the other is the low quadword of an \c{XMM} register. - -The operation of this instruction is: - -\c mem(0-63) := xmm(0-63); - -or - -\c xmm(0-63) := mem(0-63); -\c xmm(64-127) remains unchanged. - -\S{insMOVLPS} \i\c{MOVLPS}: Move Low Packed Single-Precision FP - -\c MOVLPS xmm,m64 ; OF 12 /r [KATMAI,SSE] -\c MOVLPS m64,xmm ; OF 13 /r [KATMAI,SSE] - -\c{MOVLPS} moves two packed single-precision FP values between the source -and destination operands. One of the operands is a 64-bit memory location, -the other is the low quadword of an \c{XMM} register. - -The operation of this instruction is: - -\c mem(0-63) := xmm(0-63); - -or - -\c xmm(0-63) := mem(0-63); -\c xmm(64-127) remains unchanged. - - -\S{insMOVMSKPD} \i\c{MOVMSKPD}: Extract Packed Double-Precision FP Sign Mask - -\c MOVMSKPD reg32,xmm ; 66 0F 50 /r [WILLAMETTE,SSE2] - -\c{MOVMSKPD} inserts a 2-bit mask in r32, formed of the most significant -bits of each double-precision FP number of the source operand. - - -\S{insMOVMSKPS} \i\c{MOVMSKPS}: Extract Packed Single-Precision FP Sign Mask - -\c MOVMSKPS reg32,xmm ; 0F 50 /r [KATMAI,SSE] - -\c{MOVMSKPS} inserts a 4-bit mask in r32, formed of the most significant -bits of each single-precision FP number of the source operand. - - -\S{insMOVNTDQ} \i\c{MOVNTDQ}: Move Double Quadword Non Temporal - -\c MOVNTDQ m128,xmm ; 66 0F E7 /r [WILLAMETTE,SSE2] - -\c{MOVNTDQ} moves the double quadword from the \c{XMM} source -register to the destination memory location, using a non-temporal -hint. This store instruction minimizes cache pollution. - - -\S{insMOVNTI} \i\c{MOVNTI}: Move Doubleword Non Temporal - -\c MOVNTI m32,reg32 ; 0F C3 /r [WILLAMETTE,SSE2] - -\c{MOVNTI} moves the doubleword in the source register -to the destination memory location, using a non-temporal -hint. This store instruction minimizes cache pollution. - - -\S{insMOVNTPD} \i\c{MOVNTPD}: Move Aligned Four Packed Single-Precision -FP Values Non Temporal - -\c MOVNTPD m128,xmm ; 66 0F 2B /r [WILLAMETTE,SSE2] - -\c{MOVNTPD} moves the double quadword from the \c{XMM} source -register to the destination memory location, using a non-temporal -hint. This store instruction minimizes cache pollution. The memory -location must be aligned to a 16-byte boundary. - - -\S{insMOVNTPS} \i\c{MOVNTPS}: Move Aligned Four Packed Single-Precision -FP Values Non Temporal - -\c MOVNTPS m128,xmm ; 0F 2B /r [KATMAI,SSE] - -\c{MOVNTPS} moves the double quadword from the \c{XMM} source -register to the destination memory location, using a non-temporal -hint. This store instruction minimizes cache pollution. The memory -location must be aligned to a 16-byte boundary. - - -\S{insMOVNTQ} \i\c{MOVNTQ}: Move Quadword Non Temporal - -\c MOVNTQ m64,mm ; 0F E7 /r [KATMAI,MMX] - -\c{MOVNTQ} moves the quadword in the \c{MMX} source register -to the destination memory location, using a non-temporal -hint. This store instruction minimizes cache pollution. - - -\S{insMOVQ} \i\c{MOVQ}: Move Quadword to/from MMX Register - -\c MOVQ mm1,mm2/m64 ; 0F 6F /r [PENT,MMX] -\c MOVQ mm1/m64,mm2 ; 0F 7F /r [PENT,MMX] - -\c MOVQ xmm1,xmm2/m64 ; F3 0F 7E /r [WILLAMETTE,SSE2] -\c MOVQ xmm1/m64,xmm2 ; 66 0F D6 /r [WILLAMETTE,SSE2] - -\c{MOVQ} copies 64 bits from its source (second) operand into its -destination (first) operand. When the source is an \c{XMM} register, -the low quadword is moved. When the destination is an \c{XMM} register, -the destination is the low quadword, and the high quadword is cleared. - - -\S{insMOVQ2DQ} \i\c{MOVQ2DQ}: Move Quadword from MMX to XMM register. - -\c MOVQ2DQ xmm,mm ; F3 OF D6 /r [WILLAMETTE,SSE2] - -\c{MOVQ2DQ} moves the quadword from the source operand to the low -quadword of the destination operand, and clears the high quadword. - - -\S{insMOVSB} \i\c{MOVSB}, \i\c{MOVSW}, \i\c{MOVSD}: Move String - -\c MOVSB ; A4 [8086] -\c MOVSW ; o16 A5 [8086] -\c MOVSD ; o32 A5 [386] - -\c{MOVSB} copies the byte at \c{[DS:SI]} or \c{[DS:ESI]} to -\c{[ES:DI]} or \c{[ES:EDI]}. It then increments or decrements -(depending on the direction flag: increments if the flag is clear, -decrements if it is set) \c{SI} and \c{DI} (or \c{ESI} and \c{EDI}). - -The registers used are \c{SI} and \c{DI} if the address size is 16 -bits, and \c{ESI} and \c{EDI} if it is 32 bits. If you need to use -an address size not equal to the current \c{BITS} setting, you can -use an explicit \i\c{a16} or \i\c{a32} prefix. - -The segment register used to load from \c{[SI]} or \c{[ESI]} can be -overridden by using a segment register name as a prefix (for -example, \c{es movsb}). The use of \c{ES} for the store to \c{[DI]} -or \c{[EDI]} cannot be overridden. - -\c{MOVSW} and \c{MOVSD} work in the same way, but they copy a word -or a doubleword instead of a byte, and increment or decrement the -addressing registers by 2 or 4 instead of 1. - -The \c{REP} prefix may be used to repeat the instruction \c{CX} (or -\c{ECX} - again, the address size chooses which) times. - - -\S{insMOVSD} \i\c{MOVSD}: Move Scalar Double-Precision FP Value - -\c MOVSD xmm1,xmm2/m64 ; F2 0F 10 /r [WILLAMETTE,SSE2] -\c MOVSD xmm1/m64,xmm2 ; F2 0F 11 /r [WILLAMETTE,SSE2] - -\c{MOVSD} moves a double-precision FP value from the source operand -to the destination operand. When the source or destination is a -register, the low-order FP value is read or written. - - -\S{insMOVSS} \i\c{MOVSS}: Move Scalar Single-Precision FP Value - -\c MOVSS xmm1,xmm2/m32 ; F3 0F 10 /r [KATMAI,SSE] -\c MOVSS xmm1/m32,xmm2 ; F3 0F 11 /r [KATMAI,SSE] - -\c{MOVSS} moves a single-precision FP value from the source operand -to the destination operand. When the source or destination is a -register, the low-order FP value is read or written. - - -\S{insMOVSX} \i\c{MOVSX}, \i\c{MOVZX}: Move Data with Sign or Zero Extend - -\c MOVSX reg16,r/m8 ; o16 0F BE /r [386] -\c MOVSX reg32,r/m8 ; o32 0F BE /r [386] -\c MOVSX reg32,r/m16 ; o32 0F BF /r [386] - -\c MOVZX reg16,r/m8 ; o16 0F B6 /r [386] -\c MOVZX reg32,r/m8 ; o32 0F B6 /r [386] -\c MOVZX reg32,r/m16 ; o32 0F B7 /r [386] - -\c{MOVSX} sign-extends its source (second) operand to the length of -its destination (first) operand, and copies the result into the -destination operand. \c{MOVZX} does the same, but zero-extends -rather than sign-extending. - - -\S{insMOVUPD} \i\c{MOVUPD}: Move Unaligned Packed Double-Precision FP Values - -\c MOVUPD xmm1,xmm2/mem128 ; 66 0F 10 /r [WILLAMETTE,SSE2] -\c MOVUPD xmm1/mem128,xmm2 ; 66 0F 11 /r [WILLAMETTE,SSE2] - -\c{MOVUPD} moves a double quadword containing 2 packed double-precision -FP values from the source operand to the destination. This instruction -makes no assumptions about alignment of memory operands. - -To move data in and out of memory locations that are known to be on 16-byte -boundaries, use the \c{MOVAPD} instruction (\k{insMOVAPD}). - - -\S{insMOVUPS} \i\c{MOVUPS}: Move Unaligned Packed Single-Precision FP Values - -\c MOVUPS xmm1,xmm2/mem128 ; 0F 10 /r [KATMAI,SSE] -\c MOVUPS xmm1/mem128,xmm2 ; 0F 11 /r [KATMAI,SSE] - -\c{MOVUPS} moves a double quadword containing 4 packed single-precision -FP values from the source operand to the destination. This instruction -makes no assumptions about alignment of memory operands. - -To move data in and out of memory locations that are known to be on 16-byte -boundaries, use the \c{MOVAPS} instruction (\k{insMOVAPS}). - - -\S{insMUL} \i\c{MUL}: Unsigned Integer Multiply - -\c MUL r/m8 ; F6 /4 [8086] -\c MUL r/m16 ; o16 F7 /4 [8086] -\c MUL r/m32 ; o32 F7 /4 [386] - -\c{MUL} performs unsigned integer multiplication. The other operand -to the multiplication, and the destination operand, are implicit, in -the following way: - -\b For \c{MUL r/m8}, \c{AL} is multiplied by the given operand; the -product is stored in \c{AX}. - -\b For \c{MUL r/m16}, \c{AX} is multiplied by the given operand; -the product is stored in \c{DX:AX}. - -\b For \c{MUL r/m32}, \c{EAX} is multiplied by the given operand; -the product is stored in \c{EDX:EAX}. - -Signed integer multiplication is performed by the \c{IMUL} -instruction: see \k{insIMUL}. - - -\S{insMULPD} \i\c{MULPD}: Packed Single-FP Multiply - -\c MULPD xmm1,xmm2/mem128 ; 66 0F 59 /r [WILLAMETTE,SSE2] - -\c{MULPD} performs a SIMD multiply of the packed double-precision FP -values in both operands, and stores the results in the destination register. - - -\S{insMULPS} \i\c{MULPS}: Packed Single-FP Multiply - -\c MULPS xmm1,xmm2/mem128 ; 0F 59 /r [KATMAI,SSE] - -\c{MULPS} performs a SIMD multiply of the packed single-precision FP -values in both operands, and stores the results in the destination register. - - -\S{insMULSD} \i\c{MULSD}: Scalar Single-FP Multiply - -\c MULSD xmm1,xmm2/mem32 ; F2 0F 59 /r [WILLAMETTE,SSE2] - -\c{MULSD} multiplies the lowest double-precision FP values of both -operands, and stores the result in the low quadword of xmm1. - - -\S{insMULSS} \i\c{MULSS}: Scalar Single-FP Multiply - -\c MULSS xmm1,xmm2/mem32 ; F3 0F 59 /r [KATMAI,SSE] - -\c{MULSS} multiplies the lowest single-precision FP values of both -operands, and stores the result in the low doubleword of xmm1. - - -\S{insNEG} \i\c{NEG}, \i\c{NOT}: Two's and One's Complement - -\c NEG r/m8 ; F6 /3 [8086] -\c NEG r/m16 ; o16 F7 /3 [8086] -\c NEG r/m32 ; o32 F7 /3 [386] - -\c NOT r/m8 ; F6 /2 [8086] -\c NOT r/m16 ; o16 F7 /2 [8086] -\c NOT r/m32 ; o32 F7 /2 [386] - -\c{NEG} replaces the contents of its operand by the two's complement -negation (invert all the bits and then add one) of the original -value. \c{NOT}, similarly, performs one's complement (inverts all -the bits). - - -\S{insNOP} \i\c{NOP}: No Operation - -\c NOP ; 90 [8086] - -\c{NOP} performs no operation. Its opcode is the same as that -generated by \c{XCHG AX,AX} or \c{XCHG EAX,EAX} (depending on the -processor mode; see \k{insXCHG}). - - -\S{insOR} \i\c{OR}: Bitwise OR - -\c OR r/m8,reg8 ; 08 /r [8086] -\c OR r/m16,reg16 ; o16 09 /r [8086] -\c OR r/m32,reg32 ; o32 09 /r [386] - -\c OR reg8,r/m8 ; 0A /r [8086] -\c OR reg16,r/m16 ; o16 0B /r [8086] -\c OR reg32,r/m32 ; o32 0B /r [386] - -\c OR r/m8,imm8 ; 80 /1 ib [8086] -\c OR r/m16,imm16 ; o16 81 /1 iw [8086] -\c OR r/m32,imm32 ; o32 81 /1 id [386] - -\c OR r/m16,imm8 ; o16 83 /1 ib [8086] -\c OR r/m32,imm8 ; o32 83 /1 ib [386] - -\c OR AL,imm8 ; 0C ib [8086] -\c OR AX,imm16 ; o16 0D iw [8086] -\c OR EAX,imm32 ; o32 0D id [386] - -\c{OR} performs a bitwise OR operation between its two operands -(i.e. each bit of the result is 1 if and only if at least one of the -corresponding bits of the two inputs was 1), and stores the result -in the destination (first) operand. - -In the forms with an 8-bit immediate second operand and a longer -first operand, the second operand is considered to be signed, and is -sign-extended to the length of the first operand. In these cases, -the \c{BYTE} qualifier is necessary to force NASM to generate this -form of the instruction. - -The MMX instruction \c{POR} (see \k{insPOR}) performs the same -operation on the 64-bit MMX registers. - - -\S{insORPD} \i\c{ORPD}: Bit-wise Logical OR of Double-Precision FP Data - -\c ORPD xmm1,xmm2/m128 ; 66 0F 56 /r [WILLAMETTE,SSE2] - -\c{ORPD} return a bit-wise logical OR between xmm1 and xmm2/mem, -and stores the result in xmm1. If the source operand is a memory -location, it must be aligned to a 16-byte boundary. - - -\S{insORPS} \i\c{ORPS}: Bit-wise Logical OR of Single-Precision FP Data - -\c ORPS xmm1,xmm2/m128 ; 0F 56 /r [KATMAI,SSE] - -\c{ORPS} return a bit-wise logical OR between xmm1 and xmm2/mem, -and stores the result in xmm1. If the source operand is a memory -location, it must be aligned to a 16-byte boundary. - - -\S{insOUT} \i\c{OUT}: Output Data to I/O Port - -\c OUT imm8,AL ; E6 ib [8086] -\c OUT imm8,AX ; o16 E7 ib [8086] -\c OUT imm8,EAX ; o32 E7 ib [386] -\c OUT DX,AL ; EE [8086] -\c OUT DX,AX ; o16 EF [8086] -\c OUT DX,EAX ; o32 EF [386] - -\c{OUT} writes the contents of the given source register to the -specified I/O port. The port number may be specified as an immediate -value if it is between 0 and 255, and otherwise must be stored in -\c{DX}. See also \c{IN} (\k{insIN}). - - -\S{insOUTSB} \i\c{OUTSB}, \i\c{OUTSW}, \i\c{OUTSD}: Output String to I/O Port - -\c OUTSB ; 6E [186] -\c OUTSW ; o16 6F [186] -\c OUTSD ; o32 6F [386] - -\c{OUTSB} loads a byte from \c{[DS:SI]} or \c{[DS:ESI]} and writes -it to the I/O port specified in \c{DX}. It then increments or -decrements (depending on the direction flag: increments if the flag -is clear, decrements if it is set) \c{SI} or \c{ESI}. - -The register used is \c{SI} if the address size is 16 bits, and -\c{ESI} if it is 32 bits. If you need to use an address size not -equal to the current \c{BITS} setting, you can use an explicit -\i\c{a16} or \i\c{a32} prefix. - -The segment register used to load from \c{[SI]} or \c{[ESI]} can be -overridden by using a segment register name as a prefix (for -example, \c{es outsb}). - -\c{OUTSW} and \c{OUTSD} work in the same way, but they output a -word or a doubleword instead of a byte, and increment or decrement -the addressing registers by 2 or 4 instead of 1. - -The \c{REP} prefix may be used to repeat the instruction \c{CX} (or -\c{ECX} - again, the address size chooses which) times. - - -\S{insPACKSSDW} \i\c{PACKSSDW}, \i\c{PACKSSWB}, \i\c{PACKUSWB}: Pack Data - -\c PACKSSDW mm1,mm2/m64 ; 0F 6B /r [PENT,MMX] -\c PACKSSWB mm1,mm2/m64 ; 0F 63 /r [PENT,MMX] -\c PACKUSWB mm1,mm2/m64 ; 0F 67 /r [PENT,MMX] - -\c PACKSSDW xmm1,xmm2/m128 ; 66 0F 6B /r [WILLAMETTE,SSE2] -\c PACKSSWB xmm1,xmm2/m128 ; 66 0F 63 /r [WILLAMETTE,SSE2] -\c PACKUSWB xmm1,xmm2/m128 ; 66 0F 67 /r [WILLAMETTE,SSE2] - -All these instructions start by combining the source and destination -operands, and then splitting the result in smaller sections which it -then packs into the destination register. The \c{MMX} versions pack -two 64-bit operands into one 64-bit register, while the \c{SSE} -versions pack two 128-bit operands into one 128-bit register. - -\b \c{PACKSSWB} splits the combined value into words, and then reduces -the words to bytes, using signed saturation. It then packs the bytes -into the destination register in the same order the words were in. - -\b \c{PACKSSDW} performs the same operation as \c{PACKSSWB}, except that -it reduces doublewords to words, then packs them into the destination -register. - -\b \c{PACKUSWB} performs the same operation as \c{PACKSSWB}, except that -it uses unsigned saturation when reducing the size of the elements. - -To perform signed saturation on a number, it is replaced by the largest -signed number (\c{7FFFh} or \c{7Fh}) that \e{will} fit, and if it is too -small it is replaced by the smallest signed number (\c{8000h} or -\c{80h}) that will fit. To perform unsigned saturation, the input is -treated as unsigned, and the input is replaced by the largest unsigned -number that will fit. - - -\S{insPADDB} \i\c{PADDB}, \i\c{PADDW}, \i\c{PADDD}: Add Packed Integers - -\c PADDB mm1,mm2/m64 ; 0F FC /r [PENT,MMX] -\c PADDW mm1,mm2/m64 ; 0F FD /r [PENT,MMX] -\c PADDD mm1,mm2/m64 ; 0F FE /r [PENT,MMX] - -\c PADDB xmm1,xmm2/m128 ; 66 0F FC /r [WILLAMETTE,SSE2] -\c PADDW xmm1,xmm2/m128 ; 66 0F FD /r [WILLAMETTE,SSE2] -\c PADDD xmm1,xmm2/m128 ; 66 0F FE /r [WILLAMETTE,SSE2] - -\c{PADDx} performs packed addition of the two operands, storing the -result in the destination (first) operand. - -\b \c{PADDB} treats the operands as packed bytes, and adds each byte -individually; - -\b \c{PADDW} treats the operands as packed words; - -\b \c{PADDD} treats its operands as packed doublewords. - -When an individual result is too large to fit in its destination, it -is wrapped around and the low bits are stored, with the carry bit -discarded. - - -\S{insPADDQ} \i\c{PADDQ}: Add Packed Quadword Integers - -\c PADDQ mm1,mm2/m64 ; 0F D4 /r [PENT,MMX] - -\c PADDQ xmm1,xmm2/m128 ; 66 0F D4 /r [WILLAMETTE,SSE2] - -\c{PADDQ} adds the quadwords in the source and destination operands, and -stores the result in the destination register. - -When an individual result is too large to fit in its destination, it -is wrapped around and the low bits are stored, with the carry bit -discarded. - - -\S{insPADDSB} \i\c{PADDSB}, \i\c{PADDSW}: Add Packed Signed Integers With Saturation - -\c PADDSB mm1,mm2/m64 ; 0F EC /r [PENT,MMX] -\c PADDSW mm1,mm2/m64 ; 0F ED /r [PENT,MMX] - -\c PADDSB xmm1,xmm2/m128 ; 66 0F EC /r [WILLAMETTE,SSE2] -\c PADDSW xmm1,xmm2/m128 ; 66 0F ED /r [WILLAMETTE,SSE2] - -\c{PADDSx} performs packed addition of the two operands, storing the -result in the destination (first) operand. -\c{PADDSB} treats the operands as packed bytes, and adds each byte -individually; and \c{PADDSW} treats the operands as packed words. - -When an individual result is too large to fit in its destination, a -saturated value is stored. The resulting value is the value with the -largest magnitude of the same sign as the result which will fit in -the available space. - - -\S{insPADDSIW} \i\c{PADDSIW}: MMX Packed Addition to Implicit Destination - -\c PADDSIW mmxreg,r/m64 ; 0F 51 /r [CYRIX,MMX] - -\c{PADDSIW}, specific to the Cyrix extensions to the MMX instruction -set, performs the same function as \c{PADDSW}, except that the result -is placed in an implied register. - -To work out the implied register, invert the lowest bit in the register -number. So \c{PADDSIW MM0,MM2} would put the result in \c{MM1}, but -\c{PADDSIW MM1,MM2} would put the result in \c{MM0}. - - -\S{insPADDUSB} \i\c{PADDUSB}, \i\c{PADDUSW}: Add Packed Unsigned Integers With Saturation - -\c PADDUSB mm1,mm2/m64 ; 0F DC /r [PENT,MMX] -\c PADDUSW mm1,mm2/m64 ; 0F DD /r [PENT,MMX] - -\c PADDUSB xmm1,xmm2/m128 ; 66 0F DC /r [WILLAMETTE,SSE2] -\c PADDUSW xmm1,xmm2/m128 ; 66 0F DD /r [WILLAMETTE,SSE2] - -\c{PADDUSx} performs packed addition of the two operands, storing the -result in the destination (first) operand. -\c{PADDUSB} treats the operands as packed bytes, and adds each byte -individually; and \c{PADDUSW} treats the operands as packed words. - -When an individual result is too large to fit in its destination, a -saturated value is stored. The resulting value is the maximum value -that will fit in the available space. - - -\S{insPAND} \i\c{PAND}, \i\c{PANDN}: MMX Bitwise AND and AND-NOT - -\c PAND mm1,mm2/m64 ; 0F DB /r [PENT,MMX] -\c PANDN mm1,mm2/m64 ; 0F DF /r [PENT,MMX] - -\c PAND xmm1,xmm2/m128 ; 66 0F DB /r [WILLAMETTE,SSE2] -\c PANDN xmm1,xmm2/m128 ; 66 0F DF /r [WILLAMETTE,SSE2] - - -\c{PAND} performs a bitwise AND operation between its two operands -(i.e. each bit of the result is 1 if and only if the corresponding -bits of the two inputs were both 1), and stores the result in the -destination (first) operand. - -\c{PANDN} performs the same operation, but performs a one's -complement operation on the destination (first) operand first. - - -\S{insPAUSE} \i\c{PAUSE}: Spin Loop Hint - -\c PAUSE ; F3 90 [WILLAMETTE,SSE2] - -\c{PAUSE} provides a hint to the processor that the following code -is a spin loop. This improves processor performance by bypassing -possible memory order violations. On older processors, this instruction -operates as a \c{NOP}. - - -\S{insPAVEB} \i\c{PAVEB}: MMX Packed Average - -\c PAVEB mmxreg,r/m64 ; 0F 50 /r [CYRIX,MMX] - -\c{PAVEB}, specific to the Cyrix MMX extensions, treats its two -operands as vectors of eight unsigned bytes, and calculates the -average of the corresponding bytes in the operands. The resulting -vector of eight averages is stored in the first operand. - -This opcode maps to \c{MOVMSKPS r32, xmm} on processors that support -the SSE instruction set. - - -\S{insPAVGB} \i\c{PAVGB} \i\c{PAVGW}: Average Packed Integers - -\c PAVGB mm1,mm2/m64 ; 0F E0 /r [KATMAI,MMX] -\c PAVGW mm1,mm2/m64 ; 0F E3 /r [KATMAI,MMX,SM] - -\c PAVGB xmm1,xmm2/m128 ; 66 0F E0 /r [WILLAMETTE,SSE2] -\c PAVGW xmm1,xmm2/m128 ; 66 0F E3 /r [WILLAMETTE,SSE2] - -\c{PAVGB} and \c{PAVGW} add the unsigned data elements of the source -operand to the unsigned data elements of the destination register, -then adds 1 to the temporary results. The results of the add are then -each independently right-shifted by one bit position. The high order -bits of each element are filled with the carry bits of the corresponding -sum. - -\b \c{PAVGB} operates on packed unsigned bytes, and - -\b \c{PAVGW} operates on packed unsigned words. - - -\S{insPAVGUSB} \i\c{PAVGUSB}: Average of unsigned packed 8-bit values - -\c PAVGUSB mm1,mm2/m64 ; 0F 0F /r BF [PENT,3DNOW] - -\c{PAVGUSB} adds the unsigned data elements of the source operand to -the unsigned data elements of the destination register, then adds 1 -to the temporary results. The results of the add are then each -independently right-shifted by one bit position. The high order bits -of each element are filled with the carry bits of the corresponding -sum. - -This instruction performs exactly the same operations as the \c{PAVGB} -\c{MMX} instruction (\k{insPAVGB}). - - -\S{insPCMPEQB} \i\c{PCMPxx}: Compare Packed Integers. - -\c PCMPEQB mm1,mm2/m64 ; 0F 74 /r [PENT,MMX] -\c PCMPEQW mm1,mm2/m64 ; 0F 75 /r [PENT,MMX] -\c PCMPEQD mm1,mm2/m64 ; 0F 76 /r [PENT,MMX] - -\c PCMPGTB mm1,mm2/m64 ; 0F 64 /r [PENT,MMX] -\c PCMPGTW mm1,mm2/m64 ; 0F 65 /r [PENT,MMX] -\c PCMPGTD mm1,mm2/m64 ; 0F 66 /r [PENT,MMX] - -\c PCMPEQB xmm1,xmm2/m128 ; 66 0F 74 /r [WILLAMETTE,SSE2] -\c PCMPEQW xmm1,xmm2/m128 ; 66 0F 75 /r [WILLAMETTE,SSE2] -\c PCMPEQD xmm1,xmm2/m128 ; 66 0F 76 /r [WILLAMETTE,SSE2] - -\c PCMPGTB xmm1,xmm2/m128 ; 66 0F 64 /r [WILLAMETTE,SSE2] -\c PCMPGTW xmm1,xmm2/m128 ; 66 0F 65 /r [WILLAMETTE,SSE2] -\c PCMPGTD xmm1,xmm2/m128 ; 66 0F 66 /r [WILLAMETTE,SSE2] - -The \c{PCMPxx} instructions all treat their operands as vectors of -bytes, words, or doublewords; corresponding elements of the source -and destination are compared, and the corresponding element of the -destination (first) operand is set to all zeros or all ones -depending on the result of the comparison. - -\b \c{PCMPxxB} treats the operands as vectors of bytes; - -\b \c{PCMPxxW} treats the operands as vectors of words; - -\b \c{PCMPxxD} treats the operands as vectors of doublewords; - -\b \c{PCMPEQx} sets the corresponding element of the destination -operand to all ones if the two elements compared are equal; - -\b \c{PCMPGTx} sets the destination element to all ones if the element -of the first (destination) operand is greater (treated as a signed -integer) than that of the second (source) operand. - - -\S{insPDISTIB} \i\c{PDISTIB}: MMX Packed Distance and Accumulate -with Implied Register - -\c PDISTIB mm,m64 ; 0F 54 /r [CYRIX,MMX] - -\c{PDISTIB}, specific to the Cyrix MMX extensions, treats its two -input operands as vectors of eight unsigned bytes. For each byte -position, it finds the absolute difference between the bytes in that -position in the two input operands, and adds that value to the byte -in the same position in the implied output register. The addition is -saturated to an unsigned byte in the same way as \c{PADDUSB}. - -To work out the implied register, invert the lowest bit in the register -number. So \c{PDISTIB MM0,M64} would put the result in \c{MM1}, but -\c{PDISTIB MM1,M64} would put the result in \c{MM0}. - -Note that \c{PDISTIB} cannot take a register as its second source -operand. - -Operation: - -\c dstI[0-7] := dstI[0-7] + ABS(src0[0-7] - src1[0-7]), -\c dstI[8-15] := dstI[8-15] + ABS(src0[8-15] - src1[8-15]), -\c ....... -\c ....... -\c dstI[56-63] := dstI[56-63] + ABS(src0[56-63] - src1[56-63]). - - -\S{insPEXTRW} \i\c{PEXTRW}: Extract Word - -\c PEXTRW reg32,mm,imm8 ; 0F C5 /r ib [KATMAI,MMX] -\c PEXTRW reg32,xmm,imm8 ; 66 0F C5 /r ib [WILLAMETTE,SSE2] - -\c{PEXTRW} moves the word in the source register (second operand) -that is pointed to by the count operand (third operand), into the -lower half of a 32-bit general purpose register. The upper half of -the register is cleared to all 0s. - -When the source operand is an \c{MMX} register, the two least -significant bits of the count specify the source word. When it is -an \c{SSE} register, the three least significant bits specify the -word location. - - -\S{insPF2ID} \i\c{PF2ID}: Packed Single-Precision FP to Integer Convert - -\c PF2ID mm1,mm2/m64 ; 0F 0F /r 1D [PENT,3DNOW] - -\c{PF2ID} converts two single-precision FP values in the source operand -to signed 32-bit integers, using truncation, and stores them in the -destination operand. Source values that are outside the range supported -by the destination are saturated to the largest absolute value of the -same sign. - - -\S{insPF2IW} \i\c{PF2IW}: Packed Single-Precision FP to Integer Word Convert - -\c PF2IW mm1,mm2/m64 ; 0F 0F /r 1C [PENT,3DNOW] - -\c{PF2IW} converts two single-precision FP values in the source operand -to signed 16-bit integers, using truncation, and stores them in the -destination operand. Source values that are outside the range supported -by the destination are saturated to the largest absolute value of the -same sign. - -\b In the K6-2 and K6-III, the 16-bit value is zero-extended to 32-bits -before storing. - -\b In the K6-2+, K6-III+ and Athlon processors, the value is sign-extended -to 32-bits before storing. - - -\S{insPFACC} \i\c{PFACC}: Packed Single-Precision FP Accumulate - -\c PFACC mm1,mm2/m64 ; 0F 0F /r AE [PENT,3DNOW] - -\c{PFACC} adds the two single-precision FP values from the destination -operand together, then adds the two single-precision FP values from the -source operand, and places the results in the low and high doublewords -of the destination operand. - -The operation is: - -\c dst[0-31] := dst[0-31] + dst[32-63], -\c dst[32-63] := src[0-31] + src[32-63]. - - -\S{insPFADD} \i\c{PFADD}: Packed Single-Precision FP Addition - -\c PFADD mm1,mm2/m64 ; 0F 0F /r 9E [PENT,3DNOW] - -\c{PFADD} performs addition on each of two packed single-precision -FP value pairs. - -\c dst[0-31] := dst[0-31] + src[0-31], -\c dst[32-63] := dst[32-63] + src[32-63]. - - -\S{insPFCMP} \i\c{PFCMPxx}: Packed Single-Precision FP Compare -\I\c{PFCMPEQ} \I\c{PFCMPGE} \I\c{PFCMPGT} - -\c PFCMPEQ mm1,mm2/m64 ; 0F 0F /r B0 [PENT,3DNOW] -\c PFCMPGE mm1,mm2/m64 ; 0F 0F /r 90 [PENT,3DNOW] -\c PFCMPGT mm1,mm2/m64 ; 0F 0F /r A0 [PENT,3DNOW] - -The \c{PFCMPxx} instructions compare the packed single-point FP values -in the source and destination operands, and set the destination -according to the result. If the condition is true, the destination is -set to all 1s, otherwise it's set to all 0s. - -\b \c{PFCMPEQ} tests whether dst == src; - -\b \c{PFCMPGE} tests whether dst >= src; - -\b \c{PFCMPGT} tests whether dst > src. - - -\S{insPFMAX} \i\c{PFMAX}: Packed Single-Precision FP Maximum - -\c PFMAX mm1,mm2/m64 ; 0F 0F /r A4 [PENT,3DNOW] - -\c{PFMAX} returns the higher of each pair of single-precision FP values. -If the higher value is zero, it is returned as positive zero. - - -\S{insPFMIN} \i\c{PFMIN}: Packed Single-Precision FP Minimum - -\c PFMIN mm1,mm2/m64 ; 0F 0F /r 94 [PENT,3DNOW] - -\c{PFMIN} returns the lower of each pair of single-precision FP values. -If the lower value is zero, it is returned as positive zero. - - -\S{insPFMUL} \i\c{PFMUL}: Packed Single-Precision FP Multiply - -\c PFMUL mm1,mm2/m64 ; 0F 0F /r B4 [PENT,3DNOW] - -\c{PFMUL} returns the product of each pair of single-precision FP values. - -\c dst[0-31] := dst[0-31] * src[0-31], -\c dst[32-63] := dst[32-63] * src[32-63]. - - -\S{insPFNACC} \i\c{PFNACC}: Packed Single-Precision FP Negative Accumulate - -\c PFNACC mm1,mm2/m64 ; 0F 0F /r 8A [PENT,3DNOW] - -\c{PFNACC} performs a negative accumulate of the two single-precision -FP values in the source and destination registers. The result of the -accumulate from the destination register is stored in the low doubleword -of the destination, and the result of the source accumulate is stored in -the high doubleword of the destination register. - -The operation is: - -\c dst[0-31] := dst[0-31] - dst[32-63], -\c dst[32-63] := src[0-31] - src[32-63]. - - -\S{insPFPNACC} \i\c{PFPNACC}: Packed Single-Precision FP Mixed Accumulate - -\c PFPNACC mm1,mm2/m64 ; 0F 0F /r 8E [PENT,3DNOW] - -\c{PFPNACC} performs a positive accumulate of the two single-precision -FP values in the source register and a negative accumulate of the -destination register. The result of the accumulate from the destination -register is stored in the low doubleword of the destination, and the -result of the source accumulate is stored in the high doubleword of the -destination register. - -The operation is: - -\c dst[0-31] := dst[0-31] - dst[32-63], -\c dst[32-63] := src[0-31] + src[32-63]. - - -\S{insPFRCP} \i\c{PFRCP}: Packed Single-Precision FP Reciprocal Approximation - -\c PFRCP mm1,mm2/m64 ; 0F 0F /r 96 [PENT,3DNOW] - -\c{PFRCP} performs a low precision estimate of the reciprocal of the -low-order single-precision FP value in the source operand, storing the -result in both halves of the destination register. The result is accurate -to 14 bits. - -For higher precision reciprocals, this instruction should be followed by -two more instructions: \c{PFRCPIT1} (\k{insPFRCPIT1}) and \c{PFRCPIT2} -(\k{insPFRCPIT1}). This will result in a 24-bit accuracy. For more details, -see the AMD 3DNow! technology manual. - - -\S{insPFRCPIT1} \i\c{PFRCPIT1}: Packed Single-Precision FP Reciprocal, -First Iteration Step - -\c PFRCPIT1 mm1,mm2/m64 ; 0F 0F /r A6 [PENT,3DNOW] - -\c{PFRCPIT1} performs the first intermediate step in the calculation of -the reciprocal of a single-precision FP value. The first source value -(\c{mm1} is the original value, and the second source value (\c{mm2/m64} -is the result of a \c{PFRCP} instruction. - -For the final step in a reciprocal, returning the full 24-bit accuracy -of a single-precision FP value, see \c{PFRCPIT2} (\k{insPFRCPIT2}). For -more details, see the AMD 3DNow! technology manual. - - -\S{insPFRCPIT2} \i\c{PFRCPIT2}: Packed Single-Precision FP -Reciprocal/ Reciprocal Square Root, Second Iteration Step - -\c PFRCPIT2 mm1,mm2/m64 ; 0F 0F /r B6 [PENT,3DNOW] - -\c{PFRCPIT2} performs the second and final intermediate step in the -calculation of a reciprocal or reciprocal square root, refining the -values returned by the \c{PFRCP} and \c{PFRSQRT} instructions, -respectively. - -The first source value (\c{mm1}) is the output of either a \c{PFRCPIT1} -or a \c{PFRSQIT1} instruction, and the second source is the output of -either the \c{PFRCP} or the \c{PFRSQRT} instruction. For more details, -see the AMD 3DNow! technology manual. - - -\S{insPFRSQIT1} \i\c{PFRSQIT1}: Packed Single-Precision FP Reciprocal -Square Root, First Iteration Step - -\c PFRSQIT1 mm1,mm2/m64 ; 0F 0F /r A7 [PENT,3DNOW] - -\c{PFRSQIT1} performs the first intermediate step in the calculation of -the reciprocal square root of a single-precision FP value. The first -source value (\c{mm1} is the square of the result of a \c{PFRSQRT} -instruction, and the second source value (\c{mm2/m64} is the original -value. - -For the final step in a calculation, returning the full 24-bit accuracy -of a single-precision FP value, see \c{PFRCPIT2} (\k{insPFRCPIT2}). For -more details, see the AMD 3DNow! technology manual. - - -\S{insPFRSQRT} \i\c{PFRSQRT}: Packed Single-Precision FP Reciprocal -Square Root Approximation - -\c PFRSQRT mm1,mm2/m64 ; 0F 0F /r 97 [PENT,3DNOW] - -\c{PFRSQRT} performs a low precision estimate of the reciprocal square -root of the low-order single-precision FP value in the source operand, -storing the result in both halves of the destination register. The result -is accurate to 15 bits. - -For higher precision reciprocals, this instruction should be followed by -two more instructions: \c{PFRSQIT1} (\k{insPFRSQIT1}) and \c{PFRCPIT2} -(\k{insPFRCPIT1}). This will result in a 24-bit accuracy. For more details, -see the AMD 3DNow! technology manual. - - -\S{insPFSUB} \i\c{PFSUB}: Packed Single-Precision FP Subtract - -\c PFSUB mm1,mm2/m64 ; 0F 0F /r 9A [PENT,3DNOW] - -\c{PFSUB} subtracts the single-precision FP values in the source from -those in the destination, and stores the result in the destination -operand. - -\c dst[0-31] := dst[0-31] - src[0-31], -\c dst[32-63] := dst[32-63] - src[32-63]. - - -\S{insPFSUBR} \i\c{PFSUBR}: Packed Single-Precision FP Reverse Subtract - -\c PFSUBR mm1,mm2/m64 ; 0F 0F /r AA [PENT,3DNOW] - -\c{PFSUBR} subtracts the single-precision FP values in the destination -from those in the source, and stores the result in the destination -operand. - -\c dst[0-31] := src[0-31] - dst[0-31], -\c dst[32-63] := src[32-63] - dst[32-63]. - - -\S{insPI2FD} \i\c{PI2FD}: Packed Doubleword Integer to Single-Precision FP Convert - -\c PI2FD mm1,mm2/m64 ; 0F 0F /r 0D [PENT,3DNOW] - -\c{PF2ID} converts two signed 32-bit integers in the source operand -to single-precision FP values, using truncation of significant digits, -and stores them in the destination operand. - - -\S{insPF2IW} \i\c{PF2IW}: Packed Word Integer to Single-Precision FP Convert - -\c PI2FW mm1,mm2/m64 ; 0F 0F /r 0C [PENT,3DNOW] - -\c{PF2IW} converts two signed 16-bit integers in the source operand -to single-precision FP values, and stores them in the destination -operand. The input values are in the low word of each doubleword. - - -\S{insPINSRW} \i\c{PINSRW}: Insert Word - -\c PINSRW mm,r16/r32/m16,imm8 ;0F C4 /r ib [KATMAI,MMX] -\c PINSRW xmm,r16/r32/m16,imm8 ;66 0F C4 /r ib [WILLAMETTE,SSE2] - -\c{PINSRW} loads a word from a 16-bit register (or the low half of a -32-bit register), or from memory, and loads it to the word position -in the destination register, pointed at by the count operand (third -operand). If the destination is an \c{MMX} register, the low two bits -of the count byte are used, if it is an \c{XMM} register the low 3 -bits are used. The insertion is done in such a way that the other -words from the destination register are left untouched. - - -\S{insPMACHRIW} \i\c{PMACHRIW}: Packed Multiply and Accumulate with Rounding - -\c PMACHRIW mm,m64 ; 0F 5E /r [CYRIX,MMX] - -\c{PMACHRIW} takes two packed 16-bit integer inputs, multiplies the -values in the inputs, rounds on bit 15 of each result, then adds bits -15-30 of each result to the corresponding position of the \e{implied} -destination register. - -The operation of this instruction is: - -\c dstI[0-15] := dstI[0-15] + (mm[0-15] *m64[0-15] -\c + 0x00004000)[15-30], -\c dstI[16-31] := dstI[16-31] + (mm[16-31]*m64[16-31] -\c + 0x00004000)[15-30], -\c dstI[32-47] := dstI[32-47] + (mm[32-47]*m64[32-47] -\c + 0x00004000)[15-30], -\c dstI[48-63] := dstI[48-63] + (mm[48-63]*m64[48-63] -\c + 0x00004000)[15-30]. - -Note that \c{PMACHRIW} cannot take a register as its second source -operand. - - -\S{insPMADDWD} \i\c{PMADDWD}: MMX Packed Multiply and Add - -\c PMADDWD mm1,mm2/m64 ; 0F F5 /r [PENT,MMX] -\c PMADDWD xmm1,xmm2/m128 ; 66 0F F5 /r [WILLAMETTE,SSE2] - -\c{PMADDWD} treats its two inputs as vectors of signed words. It -multiplies corresponding elements of the two operands, giving doubleword -results. These are then added together in pairs and stored in the -destination operand. - -The operation of this instruction is: - -\c dst[0-31] := (dst[0-15] * src[0-15]) -\c + (dst[16-31] * src[16-31]); -\c dst[32-63] := (dst[32-47] * src[32-47]) -\c + (dst[48-63] * src[48-63]); - -The following apply to the \c{SSE} version of the instruction: - -\c dst[64-95] := (dst[64-79] * src[64-79]) -\c + (dst[80-95] * src[80-95]); -\c dst[96-127] := (dst[96-111] * src[96-111]) -\c + (dst[112-127] * src[112-127]). - - -\S{insPMAGW} \i\c{PMAGW}: MMX Packed Magnitude - -\c PMAGW mm1,mm2/m64 ; 0F 52 /r [CYRIX,MMX] - -\c{PMAGW}, specific to the Cyrix MMX extensions, treats both its -operands as vectors of four signed words. It compares the absolute -values of the words in corresponding positions, and sets each word -of the destination (first) operand to whichever of the two words in -that position had the larger absolute value. - - -\S{insPMAXSW} \i\c{PMAXSW}: Packed Signed Integer Word Maximum - -\c PMAXSW mm1,mm2/m64 ; 0F EE /r [KATMAI,MMX] -\c PMAXSW xmm1,xmm2/m128 ; 66 0F EE /r [WILLAMETTE,SSE2] - -\c{PMAXSW} compares each pair of words in the two source operands, and -for each pair it stores the maximum value in the destination register. - - -\S{insPMAXUB} \i\c{PMAXUB}: Packed Unsigned Integer Byte Maximum - -\c PMAXUB mm1,mm2/m64 ; 0F DE /r [KATMAI,MMX] -\c PMAXUB xmm1,xmm2/m128 ; 66 0F DE /r [WILLAMETTE,SSE2] - -\c{PMAXUB} compares each pair of bytes in the two source operands, and -for each pair it stores the maximum value in the destination register. - - -\S{insPMINSW} \i\c{PMINSW}: Packed Signed Integer Word Minimum - -\c PMINSW mm1,mm2/m64 ; 0F EA /r [KATMAI,MMX] -\c PMINSW xmm1,xmm2/m128 ; 66 0F EA /r [WILLAMETTE,SSE2] - -\c{PMINSW} compares each pair of words in the two source operands, and -for each pair it stores the minimum value in the destination register. - - -\S{insPMINUB} \i\c{PMINUB}: Packed Unsigned Integer Byte Minimum - -\c PMINUB mm1,mm2/m64 ; 0F DA /r [KATMAI,MMX] -\c PMINUB xmm1,xmm2/m128 ; 66 0F DA /r [WILLAMETTE,SSE2] - -\c{PMINUB} compares each pair of bytes in the two source operands, and -for each pair it stores the minimum value in the destination register. - - -\S{insPMOVMSKB} \i\c{PMOVMSKB}: Move Byte Mask To Integer - -\c PMOVMSKB reg32,mm ; 0F D7 /r [KATMAI,MMX] -\c PMOVMSKB reg32,xmm ; 66 0F D7 /r [WILLAMETTE,SSE2] - -\c{PMOVMSKB} returns an 8-bit or 16-bit mask formed of the most -significant bits of each byte of source operand (8-bits for an -\c{MMX} register, 16-bits for an \c{XMM} register). - - -\S{insPMULHRW} \i\c{PMULHRWC}, \i\c{PMULHRIW}: Multiply Packed 16-bit Integers -With Rounding, and Store High Word - -\c PMULHRWC mm1,mm2/m64 ; 0F 59 /r [CYRIX,MMX] -\c PMULHRIW mm1,mm2/m64 ; 0F 5D /r [CYRIX,MMX] - -These instructions take two packed 16-bit integer inputs, multiply the -values in the inputs, round on bit 15 of each result, then store bits -15-30 of each result to the corresponding position of the destination -register. - -\b For \c{PMULHRWC}, the destination is the first source operand. - -\b For \c{PMULHRIW}, the destination is an implied register (worked out -as described for \c{PADDSIW} (\k{insPADDSIW})). - -The operation of this instruction is: - -\c dst[0-15] := (src1[0-15] *src2[0-15] + 0x00004000)[15-30] -\c dst[16-31] := (src1[16-31]*src2[16-31] + 0x00004000)[15-30] -\c dst[32-47] := (src1[32-47]*src2[32-47] + 0x00004000)[15-30] -\c dst[48-63] := (src1[48-63]*src2[48-63] + 0x00004000)[15-30] - -See also \c{PMULHRWA} (\k{insPMULHRWA}) for a 3DNow! version of this -instruction. - - -\S{insPMULHRWA} \i\c{PMULHRWA}: Multiply Packed 16-bit Integers -With Rounding, and Store High Word - -\c PMULHRWA mm1,mm2/m64 ; 0F 0F /r B7 [PENT,3DNOW] - -\c{PMULHRWA} takes two packed 16-bit integer inputs, multiplies -the values in the inputs, rounds on bit 16 of each result, then -stores bits 16-31 of each result to the corresponding position -of the destination register. - -The operation of this instruction is: - -\c dst[0-15] := (src1[0-15] *src2[0-15] + 0x00008000)[16-31]; -\c dst[16-31] := (src1[16-31]*src2[16-31] + 0x00008000)[16-31]; -\c dst[32-47] := (src1[32-47]*src2[32-47] + 0x00008000)[16-31]; -\c dst[48-63] := (src1[48-63]*src2[48-63] + 0x00008000)[16-31]. - -See also \c{PMULHRWC} (\k{insPMULHRW}) for a Cyrix version of this -instruction. - - -\S{insPMULHUW} \i\c{PMULHUW}: Multiply Packed 16-bit Integers, -and Store High Word - -\c PMULHUW mm1,mm2/m64 ; 0F E4 /r [KATMAI,MMX] -\c PMULHUW xmm1,xmm2/m128 ; 66 0F E4 /r [WILLAMETTE,SSE2] - -\c{PMULHUW} takes two packed unsigned 16-bit integer inputs, multiplies -the values in the inputs, then stores bits 16-31 of each result to the -corresponding position of the destination register. - - -\S{insPMULHW} \i\c{PMULHW}, \i\c{PMULLW}: Multiply Packed 16-bit Integers, -and Store - -\c PMULHW mm1,mm2/m64 ; 0F E5 /r [PENT,MMX] -\c PMULLW mm1,mm2/m64 ; 0F D5 /r [PENT,MMX] - -\c PMULHW xmm1,xmm2/m128 ; 66 0F E5 /r [WILLAMETTE,SSE2] -\c PMULLW xmm1,xmm2/m128 ; 66 0F D5 /r [WILLAMETTE,SSE2] - -\c{PMULxW} takes two packed unsigned 16-bit integer inputs, and -multiplies the values in the inputs, forming doubleword results. - -\b \c{PMULHW} then stores the top 16 bits of each doubleword in the -destination (first) operand; - -\b \c{PMULLW} stores the bottom 16 bits of each doubleword in the -destination operand. - - -\S{insPMULUDQ} \i\c{PMULUDQ}: Multiply Packed Unsigned -32-bit Integers, and Store. - -\c PMULUDQ mm1,mm2/m64 ; 0F F4 /r [WILLAMETTE,SSE2] -\c PMULUDQ xmm1,xmm2/m128 ; 66 0F F4 /r [WILLAMETTE,SSE2] - -\c{PMULUDQ} takes two packed unsigned 32-bit integer inputs, and -multiplies the values in the inputs, forming quadword results. The -source is either an unsigned doubleword in the low doubleword of a -64-bit operand, or it's two unsigned doublewords in the first and -third doublewords of a 128-bit operand. This produces either one or -two 64-bit results, which are stored in the respective quadword -locations of the destination register. - -The operation is: - -\c dst[0-63] := dst[0-31] * src[0-31]; -\c dst[64-127] := dst[64-95] * src[64-95]. - - -\S{insPMVccZB} \i\c{PMVccZB}: MMX Packed Conditional Move - -\c PMVZB mmxreg,mem64 ; 0F 58 /r [CYRIX,MMX] -\c PMVNZB mmxreg,mem64 ; 0F 5A /r [CYRIX,MMX] -\c PMVLZB mmxreg,mem64 ; 0F 5B /r [CYRIX,MMX] -\c PMVGEZB mmxreg,mem64 ; 0F 5C /r [CYRIX,MMX] - -These instructions, specific to the Cyrix MMX extensions, perform -parallel conditional moves. The two input operands are treated as -vectors of eight bytes. Each byte of the destination (first) operand -is either written from the corresponding byte of the source (second) -operand, or left alone, depending on the value of the byte in the -\e{implied} operand (specified in the same way as \c{PADDSIW}, in -\k{insPADDSIW}). - -\b \c{PMVZB} performs each move if the corresponding byte in the -implied operand is zero; - -\b \c{PMVNZB} moves if the byte is non-zero; - -\b \c{PMVLZB} moves if the byte is less than zero; - -\b \c{PMVGEZB} moves if the byte is greater than or equal to zero. - -Note that these instructions cannot take a register as their second -source operand. - - -\S{insPOP} \i\c{POP}: Pop Data from Stack - -\c POP reg16 ; o16 58+r [8086] -\c POP reg32 ; o32 58+r [386] - -\c POP r/m16 ; o16 8F /0 [8086] -\c POP r/m32 ; o32 8F /0 [386] - -\c POP CS ; 0F [8086,UNDOC] -\c POP DS ; 1F [8086] -\c POP ES ; 07 [8086] -\c POP SS ; 17 [8086] -\c POP FS ; 0F A1 [386] -\c POP GS ; 0F A9 [386] - -\c{POP} loads a value from the stack (from \c{[SS:SP]} or -\c{[SS:ESP]}) and then increments the stack pointer. - -The address-size attribute of the instruction determines whether -\c{SP} or \c{ESP} is used as the stack pointer: to deliberately -override the default given by the \c{BITS} setting, you can use an -\i\c{a16} or \i\c{a32} prefix. - -The operand-size attribute of the instruction determines whether the -stack pointer is incremented by 2 or 4: this means that segment -register pops in \c{BITS 32} mode will pop 4 bytes off the stack and -discard the upper two of them. If you need to override that, you can -use an \i\c{o16} or \i\c{o32} prefix. - -The above opcode listings give two forms for general-purpose -register pop instructions: for example, \c{POP BX} has the two forms -\c{5B} and \c{8F C3}. NASM will always generate the shorter form -when given \c{POP BX}. NDISASM will disassemble both. - -\c{POP CS} is not a documented instruction, and is not supported on -any processor above the 8086 (since they use \c{0Fh} as an opcode -prefix for instruction set extensions). However, at least some 8086 -processors do support it, and so NASM generates it for completeness. - - -\S{insPOPA} \i\c{POPAx}: Pop All General-Purpose Registers - -\c POPA ; 61 [186] -\c POPAW ; o16 61 [186] -\c POPAD ; o32 61 [386] - -\b \c{POPAW} pops a word from the stack into each of, successively, -\c{DI}, \c{SI}, \c{BP}, nothing (it discards a word from the stack -which was a placeholder for \c{SP}), \c{BX}, \c{DX}, \c{CX} and -\c{AX}. It is intended to reverse the operation of \c{PUSHAW} (see -\k{insPUSHA}), but it ignores the value for \c{SP} that was pushed -on the stack by \c{PUSHAW}. - -\b \c{POPAD} pops twice as much data, and places the results in -\c{EDI}, \c{ESI}, \c{EBP}, nothing (placeholder for \c{ESP}), -\c{EBX}, \c{EDX}, \c{ECX} and \c{EAX}. It reverses the operation of -\c{PUSHAD}. - -\c{POPA} is an alias mnemonic for either \c{POPAW} or \c{POPAD}, -depending on the current \c{BITS} setting. - -Note that the registers are popped in reverse order of their numeric -values in opcodes (see \k{iref-rv}). - - -\S{insPOPF} \i\c{POPFx}: Pop Flags Register - -\c POPF ; 9D [8086] -\c POPFW ; o16 9D [8086] -\c POPFD ; o32 9D [386] - -\b \c{POPFW} pops a word from the stack and stores it in the bottom 16 -bits of the flags register (or the whole flags register, on -processors below a 386). - -\b \c{POPFD} pops a doubleword and stores it in the entire flags register. - -\c{POPF} is an alias mnemonic for either \c{POPFW} or \c{POPFD}, -depending on the current \c{BITS} setting. - -See also \c{PUSHF} (\k{insPUSHF}). - - -\S{insPOR} \i\c{POR}: MMX Bitwise OR - -\c POR mm1,mm2/m64 ; 0F EB /r [PENT,MMX] -\c POR xmm1,xmm2/m128 ; 66 0F EB /r [WILLAMETTE,SSE2] - -\c{POR} performs a bitwise OR operation between its two operands -(i.e. each bit of the result is 1 if and only if at least one of the -corresponding bits of the two inputs was 1), and stores the result -in the destination (first) operand. - - -\S{insPREFETCH} \i\c{PREFETCH}: Prefetch Data Into Caches - -\c PREFETCH mem8 ; 0F 0D /0 [PENT,3DNOW] -\c PREFETCHW mem8 ; 0F 0D /1 [PENT,3DNOW] - -\c{PREFETCH} and \c{PREFETCHW} fetch the line of data from memory that -contains the specified byte. \c{PREFETCHW} performs differently on the -Athlon to earlier processors. - -For more details, see the 3DNow! Technology Manual. - - -\S{insPREFETCHh} \i\c{PREFETCHh}: Prefetch Data Into Caches -\I\c{PREFETCHNTA} \I\c{PREFETCHT0} \I\c{PREFETCHT1} \I\c{PREFETCHT2} - -\c PREFETCHNTA m8 ; 0F 18 /0 [KATMAI] -\c PREFETCHT0 m8 ; 0F 18 /1 [KATMAI] -\c PREFETCHT1 m8 ; 0F 18 /2 [KATMAI] -\c PREFETCHT2 m8 ; 0F 18 /3 [KATMAI] - -The \c{PREFETCHh} instructions fetch the line of data from memory -that contains the specified byte. It is placed in the cache -according to rules specified by locality hints \c{h}: - -The hints are: - -\b \c{T0} (temporal data) - prefetch data into all levels of the -cache hierarchy. - -\b \c{T1} (temporal data with respect to first level cache) - -prefetch data into level 2 cache and higher. - -\b \c{T2} (temporal data with respect to second level cache) - -prefetch data into level 2 cache and higher. - -\b \c{NTA} (non-temporal data with respect to all cache levels) - -prefetch data into non-temporal cache structure and into a -location close to the processor, minimizing cache pollution. - -Note that this group of instructions doesn't provide a guarantee -that the data will be in the cache when it is needed. For more -details, see the Intel IA32 Software Developer Manual, Volume 2. - - -\S{insPSADBW} \i\c{PSADBW}: Packed Sum of Absolute Differences - -\c PSADBW mm1,mm2/m64 ; 0F F6 /r [KATMAI,MMX] -\c PSADBW xmm1,xmm2/m128 ; 66 0F F6 /r [WILLAMETTE,SSE2] - -\c{PSADBW} The PSADBW instruction computes the absolute value of the -difference of the packed unsigned bytes in the two source operands. -These differences are then summed to produce a word result in the lower -16-bit field of the destination register; the rest of the register is -cleared. The destination operand is an \c{MMX} or an \c{XMM} register. -The source operand can either be a register or a memory operand. - - -\S{insPSHUFD} \i\c{PSHUFD}: Shuffle Packed Doublewords - -\c PSHUFD xmm1,xmm2/m128,imm8 ; 66 0F 70 /r ib [WILLAMETTE,SSE2] - -\c{PSHUFD} shuffles the doublewords in the source (second) operand -according to the encoding specified by imm8, and stores the result -in the destination (first) operand. - -Bits 0 and 1 of imm8 encode the source position of the doubleword to -be copied to position 0 in the destination operand. Bits 2 and 3 -encode for position 1, bits 4 and 5 encode for position 2, and bits -6 and 7 encode for position 3. For example, an encoding of 10 in -bits 0 and 1 of imm8 indicates that the doubleword at bits 64-95 of -the source operand will be copied to bits 0-31 of the destination. - - -\S{insPSHUFHW} \i\c{PSHUFHW}: Shuffle Packed High Words - -\c PSHUFHW xmm1,xmm2/m128,imm8 ; F3 0F 70 /r ib [WILLAMETTE,SSE2] - -\c{PSHUFW} shuffles the words in the high quadword of the source -(second) operand according to the encoding specified by imm8, and -stores the result in the high quadword of the destination (first) -operand. - -The operation of this instruction is similar to the \c{PSHUFW} -instruction, except that the source and destination are the top -quadword of a 128-bit operand, instead of being 64-bit operands. -The low quadword is copied from the source to the destination -without any changes. - - -\S{insPSHUFLW} \i\c{PSHUFLW}: Shuffle Packed Low Words - -\c PSHUFLW xmm1,xmm2/m128,imm8 ; F2 0F 70 /r ib [WILLAMETTE,SSE2] - -\c{PSHUFLW} shuffles the words in the low quadword of the source -(second) operand according to the encoding specified by imm8, and -stores the result in the low quadword of the destination (first) -operand. - -The operation of this instruction is similar to the \c{PSHUFW} -instruction, except that the source and destination are the low -quadword of a 128-bit operand, instead of being 64-bit operands. -The high quadword is copied from the source to the destination -without any changes. - - -\S{insPSHUFW} \i\c{PSHUFW}: Shuffle Packed Words - -\c PSHUFW mm1,mm2/m64,imm8 ; 0F 70 /r ib [KATMAI,MMX] - -\c{PSHUFW} shuffles the words in the source (second) operand -according to the encoding specified by imm8, and stores the result -in the destination (first) operand. - -Bits 0 and 1 of imm8 encode the source position of the word to be -copied to position 0 in the destination operand. Bits 2 and 3 encode -for position 1, bits 4 and 5 encode for position 2, and bits 6 and 7 -encode for position 3. For example, an encoding of 10 in bits 0 and 1 -of imm8 indicates that the word at bits 32-47 of the source operand -will be copied to bits 0-15 of the destination. - - -\S{insPSLLD} \i\c{PSLLx}: Packed Data Bit Shift Left Logical - -\c PSLLW mm1,mm2/m64 ; 0F F1 /r [PENT,MMX] -\c PSLLW mm,imm8 ; 0F 71 /6 ib [PENT,MMX] - -\c PSLLW xmm1,xmm2/m128 ; 66 0F F1 /r [WILLAMETTE,SSE2] -\c PSLLW xmm,imm8 ; 66 0F 71 /6 ib [WILLAMETTE,SSE2] - -\c PSLLD mm1,mm2/m64 ; 0F F2 /r [PENT,MMX] -\c PSLLD mm,imm8 ; 0F 72 /6 ib [PENT,MMX] - -\c PSLLD xmm1,xmm2/m128 ; 66 0F F2 /r [WILLAMETTE,SSE2] -\c PSLLD xmm,imm8 ; 66 0F 72 /6 ib [WILLAMETTE,SSE2] - -\c PSLLQ mm1,mm2/m64 ; 0F F3 /r [PENT,MMX] -\c PSLLQ mm,imm8 ; 0F 73 /6 ib [PENT,MMX] - -\c PSLLQ xmm1,xmm2/m128 ; 66 0F F3 /r [WILLAMETTE,SSE2] -\c PSLLQ xmm,imm8 ; 66 0F 73 /6 ib [WILLAMETTE,SSE2] - -\c PSLLDQ xmm1,imm8 ; 66 0F 73 /7 ib [WILLAMETTE,SSE2] - -\c{PSLLx} performs logical left shifts of the data elements in the -destination (first) operand, moving each bit in the separate elements -left by the number of bits specified in the source (second) operand, -clearing the low-order bits as they are vacated. \c{PSLLDQ} -shifts bytes, not bits. - -\b \c{PSLLW} shifts word sized elements. - -\b \c{PSLLD} shifts doubleword sized elements. - -\b \c{PSLLQ} shifts quadword sized elements. - -\b \c{PSLLDQ} shifts double quadword sized elements. - - -\S{insPSRAD} \i\c{PSRAx}: Packed Data Bit Shift Right Arithmetic - -\c PSRAW mm1,mm2/m64 ; 0F E1 /r [PENT,MMX] -\c PSRAW mm,imm8 ; 0F 71 /4 ib [PENT,MMX] - -\c PSRAW xmm1,xmm2/m128 ; 66 0F E1 /r [WILLAMETTE,SSE2] -\c PSRAW xmm,imm8 ; 66 0F 71 /4 ib [WILLAMETTE,SSE2] - -\c PSRAD mm1,mm2/m64 ; 0F E2 /r [PENT,MMX] -\c PSRAD mm,imm8 ; 0F 72 /4 ib [PENT,MMX] - -\c PSRAD xmm1,xmm2/m128 ; 66 0F E2 /r [WILLAMETTE,SSE2] -\c PSRAD xmm,imm8 ; 66 0F 72 /4 ib [WILLAMETTE,SSE2] - -\c{PSRAx} performs arithmetic right shifts of the data elements in the -destination (first) operand, moving each bit in the separate elements -right by the number of bits specified in the source (second) operand, -setting the high-order bits to the value of the original sign bit. - -\b \c{PSRAW} shifts word sized elements. - -\b \c{PSRAD} shifts doubleword sized elements. - - -\S{insPSRLD} \i\c{PSRLx}: Packed Data Bit Shift Right Logical - -\c PSRLW mm1,mm2/m64 ; 0F D1 /r [PENT,MMX] -\c PSRLW mm,imm8 ; 0F 71 /2 ib [PENT,MMX] - -\c PSRLW xmm1,xmm2/m128 ; 66 0F D1 /r [WILLAMETTE,SSE2] -\c PSRLW xmm,imm8 ; 66 0F 71 /2 ib [WILLAMETTE,SSE2] - -\c PSRLD mm1,mm2/m64 ; 0F D2 /r [PENT,MMX] -\c PSRLD mm,imm8 ; 0F 72 /2 ib [PENT,MMX] - -\c PSRLD xmm1,xmm2/m128 ; 66 0F D2 /r [WILLAMETTE,SSE2] -\c PSRLD xmm,imm8 ; 66 0F 72 /2 ib [WILLAMETTE,SSE2] - -\c PSRLQ mm1,mm2/m64 ; 0F D3 /r [PENT,MMX] -\c PSRLQ mm,imm8 ; 0F 73 /2 ib [PENT,MMX] - -\c PSRLQ xmm1,xmm2/m128 ; 66 0F D3 /r [WILLAMETTE,SSE2] -\c PSRLQ xmm,imm8 ; 66 0F 73 /2 ib [WILLAMETTE,SSE2] - -\c PSRLDQ xmm1,imm8 ; 66 0F 73 /3 ib [WILLAMETTE,SSE2] - -\c{PSRLx} performs logical right shifts of the data elements in the -destination (first) operand, moving each bit in the separate elements -right by the number of bits specified in the source (second) operand, -clearing the high-order bits as they are vacated. \c{PSRLDQ} -shifts bytes, not bits. - -\b \c{PSRLW} shifts word sized elements. - -\b \c{PSRLD} shifts doubleword sized elements. - -\b \c{PSRLQ} shifts quadword sized elements. - -\b \c{PSRLDQ} shifts double quadword sized elements. - - -\S{insPSUBB} \i\c{PSUBx}: Subtract Packed Integers - -\c PSUBB mm1,mm2/m64 ; 0F F8 /r [PENT,MMX] -\c PSUBW mm1,mm2/m64 ; 0F F9 /r [PENT,MMX] -\c PSUBD mm1,mm2/m64 ; 0F FA /r [PENT,MMX] -\c PSUBQ mm1,mm2/m64 ; 0F FB /r [WILLAMETTE,SSE2] - -\c PSUBB xmm1,xmm2/m128 ; 66 0F F8 /r [WILLAMETTE,SSE2] -\c PSUBW xmm1,xmm2/m128 ; 66 0F F9 /r [WILLAMETTE,SSE2] -\c PSUBD xmm1,xmm2/m128 ; 66 0F FA /r [WILLAMETTE,SSE2] -\c PSUBQ xmm1,xmm2/m128 ; 66 0F FB /r [WILLAMETTE,SSE2] - -\c{PSUBx} subtracts packed integers in the source operand from those -in the destination operand. It doesn't differentiate between signed -and unsigned integers, and doesn't set any of the flags. - -\b \c{PSUBB} operates on byte sized elements. - -\b \c{PSUBW} operates on word sized elements. - -\b \c{PSUBD} operates on doubleword sized elements. - -\b \c{PSUBQ} operates on quadword sized elements. - - -\S{insPSUBSB} \i\c{PSUBSxx}, \i\c{PSUBUSx}: Subtract Packed Integers With Saturation - -\c PSUBSB mm1,mm2/m64 ; 0F E8 /r [PENT,MMX] -\c PSUBSW mm1,mm2/m64 ; 0F E9 /r [PENT,MMX] - -\c PSUBSB xmm1,xmm2/m128 ; 66 0F E8 /r [WILLAMETTE,SSE2] -\c PSUBSW xmm1,xmm2/m128 ; 66 0F E9 /r [WILLAMETTE,SSE2] - -\c PSUBUSB mm1,mm2/m64 ; 0F D8 /r [PENT,MMX] -\c PSUBUSW mm1,mm2/m64 ; 0F D9 /r [PENT,MMX] - -\c PSUBUSB xmm1,xmm2/m128 ; 66 0F D8 /r [WILLAMETTE,SSE2] -\c PSUBUSW xmm1,xmm2/m128 ; 66 0F D9 /r [WILLAMETTE,SSE2] - -\c{PSUBSx} and \c{PSUBUSx} subtracts packed integers in the source -operand from those in the destination operand, and use saturation for -results that are outside the range supported by the destination operand. - -\b \c{PSUBSB} operates on signed bytes, and uses signed saturation on the -results. - -\b \c{PSUBSW} operates on signed words, and uses signed saturation on the -results. - -\b \c{PSUBUSB} operates on unsigned bytes, and uses signed saturation on -the results. - -\b \c{PSUBUSW} operates on unsigned words, and uses signed saturation on -the results. - - -\S{insPSUBSIW} \i\c{PSUBSIW}: MMX Packed Subtract with Saturation to -Implied Destination - -\c PSUBSIW mm1,mm2/m64 ; 0F 55 /r [CYRIX,MMX] - -\c{PSUBSIW}, specific to the Cyrix extensions to the MMX instruction -set, performs the same function as \c{PSUBSW}, except that the -result is not placed in the register specified by the first operand, -but instead in the implied destination register, specified as for -\c{PADDSIW} (\k{insPADDSIW}). - - -\S{insPSWAPD} \i\c{PSWAPD}: Swap Packed Data -\I\c{PSWAPW} - -\c PSWAPD mm1,mm2/m64 ; 0F 0F /r BB [PENT,3DNOW] - -\c{PSWAPD} swaps the packed doublewords in the source operand, and -stores the result in the destination operand. - -In the \c{K6-2} and \c{K6-III} processors, this opcode uses the -mnemonic \c{PSWAPW}, and it swaps the order of words when copying -from the source to the destination. - -The operation in the \c{K6-2} and \c{K6-III} processors is - -\c dst[0-15] = src[48-63]; -\c dst[16-31] = src[32-47]; -\c dst[32-47] = src[16-31]; -\c dst[48-63] = src[0-15]. - -The operation in the \c{K6-x+}, \c{ATHLON} and later processors is: - -\c dst[0-31] = src[32-63]; -\c dst[32-63] = src[0-31]. - - -\S{insPUNPCKHBW} \i\c{PUNPCKxxx}: Unpack and Interleave Data - -\c PUNPCKHBW mm1,mm2/m64 ; 0F 68 /r [PENT,MMX] -\c PUNPCKHWD mm1,mm2/m64 ; 0F 69 /r [PENT,MMX] -\c PUNPCKHDQ mm1,mm2/m64 ; 0F 6A /r [PENT,MMX] - -\c PUNPCKHBW xmm1,xmm2/m128 ; 66 0F 68 /r [WILLAMETTE,SSE2] -\c PUNPCKHWD xmm1,xmm2/m128 ; 66 0F 69 /r [WILLAMETTE,SSE2] -\c PUNPCKHDQ xmm1,xmm2/m128 ; 66 0F 6A /r [WILLAMETTE,SSE2] -\c PUNPCKHQDQ xmm1,xmm2/m128 ; 66 0F 6D /r [WILLAMETTE,SSE2] - -\c PUNPCKLBW mm1,mm2/m32 ; 0F 60 /r [PENT,MMX] -\c PUNPCKLWD mm1,mm2/m32 ; 0F 61 /r [PENT,MMX] -\c PUNPCKLDQ mm1,mm2/m32 ; 0F 62 /r [PENT,MMX] - -\c PUNPCKLBW xmm1,xmm2/m128 ; 66 0F 60 /r [WILLAMETTE,SSE2] -\c PUNPCKLWD xmm1,xmm2/m128 ; 66 0F 61 /r [WILLAMETTE,SSE2] -\c PUNPCKLDQ xmm1,xmm2/m128 ; 66 0F 62 /r [WILLAMETTE,SSE2] -\c PUNPCKLQDQ xmm1,xmm2/m128 ; 66 0F 6C /r [WILLAMETTE,SSE2] - -\c{PUNPCKxx} all treat their operands as vectors, and produce a new -vector generated by interleaving elements from the two inputs. The -\c{PUNPCKHxx} instructions start by throwing away the bottom half of -each input operand, and the \c{PUNPCKLxx} instructions throw away -the top half. - -The remaining elements, are then interleaved into the destination, -alternating elements from the second (source) operand and the first -(destination) operand: so the leftmost part of each element in the -result always comes from the second operand, and the rightmost from -the destination. - -\b \c{PUNPCKxBW} works a byte at a time, producing word sized output -elements. - -\b \c{PUNPCKxWD} works a word at a time, producing doubleword sized -output elements. - -\b \c{PUNPCKxDQ} works a doubleword at a time, producing quadword sized -output elements. - -\b \c{PUNPCKxQDQ} works a quadword at a time, producing double quadword -sized output elements. - -So, for example, for \c{MMX} operands, if the first operand held -\c{0x7A6A5A4A3A2A1A0A} and the second held \c{0x7B6B5B4B3B2B1B0B}, -then: - -\b \c{PUNPCKHBW} would return \c{0x7B7A6B6A5B5A4B4A}. - -\b \c{PUNPCKHWD} would return \c{0x7B6B7A6A5B4B5A4A}. - -\b \c{PUNPCKHDQ} would return \c{0x7B6B5B4B7A6A5A4A}. - -\b \c{PUNPCKLBW} would return \c{0x3B3A2B2A1B1A0B0A}. - -\b \c{PUNPCKLWD} would return \c{0x3B2B3A2A1B0B1A0A}. - -\b \c{PUNPCKLDQ} would return \c{0x3B2B1B0B3A2A1A0A}. - - -\S{insPUSH} \i\c{PUSH}: Push Data on Stack - -\c PUSH reg16 ; o16 50+r [8086] -\c PUSH reg32 ; o32 50+r [386] - -\c PUSH r/m16 ; o16 FF /6 [8086] -\c PUSH r/m32 ; o32 FF /6 [386] - -\c PUSH CS ; 0E [8086] -\c PUSH DS ; 1E [8086] -\c PUSH ES ; 06 [8086] -\c PUSH SS ; 16 [8086] -\c PUSH FS ; 0F A0 [386] -\c PUSH GS ; 0F A8 [386] - -\c PUSH imm8 ; 6A ib [186] -\c PUSH imm16 ; o16 68 iw [186] -\c PUSH imm32 ; o32 68 id [386] - -\c{PUSH} decrements the stack pointer (\c{SP} or \c{ESP}) by 2 or 4, -and then stores the given value at \c{[SS:SP]} or \c{[SS:ESP]}. - -The address-size attribute of the instruction determines whether -\c{SP} or \c{ESP} is used as the stack pointer: to deliberately -override the default given by the \c{BITS} setting, you can use an -\i\c{a16} or \i\c{a32} prefix. - -The operand-size attribute of the instruction determines whether the -stack pointer is decremented by 2 or 4: this means that segment -register pushes in \c{BITS 32} mode will push 4 bytes on the stack, -of which the upper two are undefined. If you need to override that, -you can use an \i\c{o16} or \i\c{o32} prefix. - -The above opcode listings give two forms for general-purpose -\i{register push} instructions: for example, \c{PUSH BX} has the two -forms \c{53} and \c{FF F3}. NASM will always generate the shorter -form when given \c{PUSH BX}. NDISASM will disassemble both. - -Unlike the undocumented and barely supported \c{POP CS}, \c{PUSH CS} -is a perfectly valid and sensible instruction, supported on all -processors. - -The instruction \c{PUSH SP} may be used to distinguish an 8086 from -later processors: on an 8086, the value of \c{SP} stored is the -value it has \e{after} the push instruction, whereas on later -processors it is the value \e{before} the push instruction. - - -\S{insPUSHA} \i\c{PUSHAx}: Push All General-Purpose Registers - -\c PUSHA ; 60 [186] -\c PUSHAD ; o32 60 [386] -\c PUSHAW ; o16 60 [186] - -\c{PUSHAW} pushes, in succession, \c{AX}, \c{CX}, \c{DX}, \c{BX}, -\c{SP}, \c{BP}, \c{SI} and \c{DI} on the stack, decrementing the -stack pointer by a total of 16. - -\c{PUSHAD} pushes, in succession, \c{EAX}, \c{ECX}, \c{EDX}, -\c{EBX}, \c{ESP}, \c{EBP}, \c{ESI} and \c{EDI} on the stack, -decrementing the stack pointer by a total of 32. - -In both cases, the value of \c{SP} or \c{ESP} pushed is its -\e{original} value, as it had before the instruction was executed. - -\c{PUSHA} is an alias mnemonic for either \c{PUSHAW} or \c{PUSHAD}, -depending on the current \c{BITS} setting. - -Note that the registers are pushed in order of their numeric values -in opcodes (see \k{iref-rv}). - -See also \c{POPA} (\k{insPOPA}). - - -\S{insPUSHF} \i\c{PUSHFx}: Push Flags Register - -\c PUSHF ; 9C [8086] -\c PUSHFD ; o32 9C [386] -\c PUSHFW ; o16 9C [8086] - -\b \c{PUSHFW} pushes the bottom 16 bits of the flags register -(or the whole flags register, on processors below a 386) onto -the stack. - -\b \c{PUSHFD} pushes the entire flags register onto the stack. - -\c{PUSHF} is an alias mnemonic for either \c{PUSHFW} or \c{PUSHFD}, -depending on the current \c{BITS} setting. - -See also \c{POPF} (\k{insPOPF}). - - -\S{insPXOR} \i\c{PXOR}: MMX Bitwise XOR - -\c PXOR mm1,mm2/m64 ; 0F EF /r [PENT,MMX] -\c PXOR xmm1,xmm2/m128 ; 66 0F EF /r [WILLAMETTE,SSE2] - -\c{PXOR} performs a bitwise XOR operation between its two operands -(i.e. each bit of the result is 1 if and only if exactly one of the -corresponding bits of the two inputs was 1), and stores the result -in the destination (first) operand. - - -\S{insRCL} \i\c{RCL}, \i\c{RCR}: Bitwise Rotate through Carry Bit - -\c RCL r/m8,1 ; D0 /2 [8086] -\c RCL r/m8,CL ; D2 /2 [8086] -\c RCL r/m8,imm8 ; C0 /2 ib [186] -\c RCL r/m16,1 ; o16 D1 /2 [8086] -\c RCL r/m16,CL ; o16 D3 /2 [8086] -\c RCL r/m16,imm8 ; o16 C1 /2 ib [186] -\c RCL r/m32,1 ; o32 D1 /2 [386] -\c RCL r/m32,CL ; o32 D3 /2 [386] -\c RCL r/m32,imm8 ; o32 C1 /2 ib [386] - -\c RCR r/m8,1 ; D0 /3 [8086] -\c RCR r/m8,CL ; D2 /3 [8086] -\c RCR r/m8,imm8 ; C0 /3 ib [186] -\c RCR r/m16,1 ; o16 D1 /3 [8086] -\c RCR r/m16,CL ; o16 D3 /3 [8086] -\c RCR r/m16,imm8 ; o16 C1 /3 ib [186] -\c RCR r/m32,1 ; o32 D1 /3 [386] -\c RCR r/m32,CL ; o32 D3 /3 [386] -\c RCR r/m32,imm8 ; o32 C1 /3 ib [386] - -\c{RCL} and \c{RCR} perform a 9-bit, 17-bit or 33-bit bitwise -rotation operation, involving the given source/destination (first) -operand and the carry bit. Thus, for example, in the operation -\c{RCL AL,1}, a 9-bit rotation is performed in which \c{AL} is -shifted left by 1, the top bit of \c{AL} moves into the carry flag, -and the original value of the carry flag is placed in the low bit of -\c{AL}. - -The number of bits to rotate by is given by the second operand. Only -the bottom five bits of the rotation count are considered by -processors above the 8086. - -You can force the longer (286 and upwards, beginning with a \c{C1} -byte) form of \c{RCL foo,1} by using a \c{BYTE} prefix: \c{RCL -foo,BYTE 1}. Similarly with \c{RCR}. - - -\S{insRCPPS} \i\c{RCPPS}: Packed Single-Precision FP Reciprocal - -\c RCPPS xmm1,xmm2/m128 ; 0F 53 /r [KATMAI,SSE] - -\c{RCPPS} returns an approximation of the reciprocal of the packed -single-precision FP values from xmm2/m128. The maximum error for this -approximation is: |Error| <= 1.5 x 2^-12 - - -\S{insRCPSS} \i\c{RCPSS}: Scalar Single-Precision FP Reciprocal - -\c RCPSS xmm1,xmm2/m128 ; F3 0F 53 /r [KATMAI,SSE] - -\c{RCPSS} returns an approximation of the reciprocal of the lower -single-precision FP value from xmm2/m32; the upper three fields are -passed through from xmm1. The maximum error for this approximation is: -|Error| <= 1.5 x 2^-12 - - -\S{insRDMSR} \i\c{RDMSR}: Read Model-Specific Registers - -\c RDMSR ; 0F 32 [PENT,PRIV] - -\c{RDMSR} reads the processor Model-Specific Register (MSR) whose -index is stored in \c{ECX}, and stores the result in \c{EDX:EAX}. -See also \c{WRMSR} (\k{insWRMSR}). - - -\S{insRDPMC} \i\c{RDPMC}: Read Performance-Monitoring Counters - -\c RDPMC ; 0F 33 [P6] - -\c{RDPMC} reads the processor performance-monitoring counter whose -index is stored in \c{ECX}, and stores the result in \c{EDX:EAX}. - -This instruction is available on P6 and later processors and on MMX -class processors. - - -\S{insRDSHR} \i\c{RDSHR}: Read SMM Header Pointer Register - -\c RDSHR r/m32 ; 0F 36 /0 [386,CYRIX,SMM] - -\c{RDSHR} reads the contents of the SMM header pointer register and -saves it to the destination operand, which can be either a 32 bit -memory location or a 32 bit register. - -See also \c{WRSHR} (\k{insWRSHR}). - - -\S{insRDTSC} \i\c{RDTSC}: Read Time-Stamp Counter - -\c RDTSC ; 0F 31 [PENT] - -\c{RDTSC} reads the processor's time-stamp counter into \c{EDX:EAX}. - - -\S{insRET} \i\c{RET}, \i\c{RETF}, \i\c{RETN}: Return from Procedure Call - -\c RET ; C3 [8086] -\c RET imm16 ; C2 iw [8086] - -\c RETF ; CB [8086] -\c RETF imm16 ; CA iw [8086] - -\c RETN ; C3 [8086] -\c RETN imm16 ; C2 iw [8086] - -\b \c{RET}, and its exact synonym \c{RETN}, pop \c{IP} or \c{EIP} from -the stack and transfer control to the new address. Optionally, if a -numeric second operand is provided, they increment the stack pointer -by a further \c{imm16} bytes after popping the return address. - -\b \c{RETF} executes a far return: after popping \c{IP}/\c{EIP}, it -then pops \c{CS}, and \e{then} increments the stack pointer by the -optional argument if present. - - -\S{insROL} \i\c{ROL}, \i\c{ROR}: Bitwise Rotate - -\c ROL r/m8,1 ; D0 /0 [8086] -\c ROL r/m8,CL ; D2 /0 [8086] -\c ROL r/m8,imm8 ; C0 /0 ib [186] -\c ROL r/m16,1 ; o16 D1 /0 [8086] -\c ROL r/m16,CL ; o16 D3 /0 [8086] -\c ROL r/m16,imm8 ; o16 C1 /0 ib [186] -\c ROL r/m32,1 ; o32 D1 /0 [386] -\c ROL r/m32,CL ; o32 D3 /0 [386] -\c ROL r/m32,imm8 ; o32 C1 /0 ib [386] - -\c ROR r/m8,1 ; D0 /1 [8086] -\c ROR r/m8,CL ; D2 /1 [8086] -\c ROR r/m8,imm8 ; C0 /1 ib [186] -\c ROR r/m16,1 ; o16 D1 /1 [8086] -\c ROR r/m16,CL ; o16 D3 /1 [8086] -\c ROR r/m16,imm8 ; o16 C1 /1 ib [186] -\c ROR r/m32,1 ; o32 D1 /1 [386] -\c ROR r/m32,CL ; o32 D3 /1 [386] -\c ROR r/m32,imm8 ; o32 C1 /1 ib [386] - -\c{ROL} and \c{ROR} perform a bitwise rotation operation on the given -source/destination (first) operand. Thus, for example, in the -operation \c{ROL AL,1}, an 8-bit rotation is performed in which -\c{AL} is shifted left by 1 and the original top bit of \c{AL} moves -round into the low bit. - -The number of bits to rotate by is given by the second operand. Only -the bottom five bits of the rotation count are considered by processors -above the 8086. - -You can force the longer (286 and upwards, beginning with a \c{C1} -byte) form of \c{ROL foo,1} by using a \c{BYTE} prefix: \c{ROL -foo,BYTE 1}. Similarly with \c{ROR}. - - -\S{insRSDC} \i\c{RSDC}: Restore Segment Register and Descriptor - -\c RSDC segreg,m80 ; 0F 79 /r [486,CYRIX,SMM] - -\c{RSDC} restores a segment register (DS, ES, FS, GS, or SS) from mem80, -and sets up its descriptor. - - -\S{insRSLDT} \i\c{RSLDT}: Restore Segment Register and Descriptor - -\c RSLDT m80 ; 0F 7B /0 [486,CYRIX,SMM] - -\c{RSLDT} restores the Local Descriptor Table (LDTR) from mem80. - - -\S{insRSM} \i\c{RSM}: Resume from System-Management Mode - -\c RSM ; 0F AA [PENT] - -\c{RSM} returns the processor to its normal operating mode when it -was in System-Management Mode. - - -\S{insRSQRTPS} \i\c{RSQRTPS}: Packed Single-Precision FP Square Root Reciprocal - -\c RSQRTPS xmm1,xmm2/m128 ; 0F 52 /r [KATMAI,SSE] - -\c{RSQRTPS} computes the approximate reciprocals of the square -roots of the packed single-precision floating-point values in the -source and stores the results in xmm1. The maximum error for this -approximation is: |Error| <= 1.5 x 2^-12 - - -\S{insRSQRTSS} \i\c{RSQRTSS}: Scalar Single-Precision FP Square Root Reciprocal - -\c RSQRTSS xmm1,xmm2/m128 ; F3 0F 52 /r [KATMAI,SSE] - -\c{RSQRTSS} returns an approximation of the reciprocal of the -square root of the lowest order single-precision FP value from -the source, and stores it in the low doubleword of the destination -register. The upper three fields of xmm1 are preserved. The maximum -error for this approximation is: |Error| <= 1.5 x 2^-12 - - -\S{insRSTS} \i\c{RSTS}: Restore TSR and Descriptor - -\c RSTS m80 ; 0F 7D /0 [486,CYRIX,SMM] - -\c{RSTS} restores Task State Register (TSR) from mem80. - - -\S{insSAHF} \i\c{SAHF}: Store AH to Flags - -\c SAHF ; 9E [8086] - -\c{SAHF} sets the low byte of the flags word according to the -contents of the \c{AH} register. - -The operation of \c{SAHF} is: - -\c AH --> SF:ZF:0:AF:0:PF:1:CF - -See also \c{LAHF} (\k{insLAHF}). - - -\S{insSAL} \i\c{SAL}, \i\c{SAR}: Bitwise Arithmetic Shifts - -\c SAL r/m8,1 ; D0 /4 [8086] -\c SAL r/m8,CL ; D2 /4 [8086] -\c SAL r/m8,imm8 ; C0 /4 ib [186] -\c SAL r/m16,1 ; o16 D1 /4 [8086] -\c SAL r/m16,CL ; o16 D3 /4 [8086] -\c SAL r/m16,imm8 ; o16 C1 /4 ib [186] -\c SAL r/m32,1 ; o32 D1 /4 [386] -\c SAL r/m32,CL ; o32 D3 /4 [386] -\c SAL r/m32,imm8 ; o32 C1 /4 ib [386] - -\c SAR r/m8,1 ; D0 /7 [8086] -\c SAR r/m8,CL ; D2 /7 [8086] -\c SAR r/m8,imm8 ; C0 /7 ib [186] -\c SAR r/m16,1 ; o16 D1 /7 [8086] -\c SAR r/m16,CL ; o16 D3 /7 [8086] -\c SAR r/m16,imm8 ; o16 C1 /7 ib [186] -\c SAR r/m32,1 ; o32 D1 /7 [386] -\c SAR r/m32,CL ; o32 D3 /7 [386] -\c SAR r/m32,imm8 ; o32 C1 /7 ib [386] - -\c{SAL} and \c{SAR} perform an arithmetic shift operation on the given -source/destination (first) operand. The vacated bits are filled with -zero for \c{SAL}, and with copies of the original high bit of the -source operand for \c{SAR}. - -\c{SAL} is a synonym for \c{SHL} (see \k{insSHL}). NASM will -assemble either one to the same code, but NDISASM will always -disassemble that code as \c{SHL}. - -The number of bits to shift by is given by the second operand. Only -the bottom five bits of the shift count are considered by processors -above the 8086. - -You can force the longer (286 and upwards, beginning with a \c{C1} -byte) form of \c{SAL foo,1} by using a \c{BYTE} prefix: \c{SAL -foo,BYTE 1}. Similarly with \c{SAR}. - - -\S{insSALC} \i\c{SALC}: Set AL from Carry Flag - -\c SALC ; D6 [8086,UNDOC] - -\c{SALC} is an early undocumented instruction similar in concept to -\c{SETcc} (\k{insSETcc}). Its function is to set \c{AL} to zero if -the carry flag is clear, or to \c{0xFF} if it is set. - - -\S{insSBB} \i\c{SBB}: Subtract with Borrow - -\c SBB r/m8,reg8 ; 18 /r [8086] -\c SBB r/m16,reg16 ; o16 19 /r [8086] -\c SBB r/m32,reg32 ; o32 19 /r [386] - -\c SBB reg8,r/m8 ; 1A /r [8086] -\c SBB reg16,r/m16 ; o16 1B /r [8086] -\c SBB reg32,r/m32 ; o32 1B /r [386] - -\c SBB r/m8,imm8 ; 80 /3 ib [8086] -\c SBB r/m16,imm16 ; o16 81 /3 iw [8086] -\c SBB r/m32,imm32 ; o32 81 /3 id [386] - -\c SBB r/m16,imm8 ; o16 83 /3 ib [8086] -\c SBB r/m32,imm8 ; o32 83 /3 ib [386] - -\c SBB AL,imm8 ; 1C ib [8086] -\c SBB AX,imm16 ; o16 1D iw [8086] -\c SBB EAX,imm32 ; o32 1D id [386] - -\c{SBB} performs integer subtraction: it subtracts its second -operand, plus the value of the carry flag, from its first, and -leaves the result in its destination (first) operand. The flags are -set according to the result of the operation: in particular, the -carry flag is affected and can be used by a subsequent \c{SBB} -instruction. - -In the forms with an 8-bit immediate second operand and a longer -first operand, the second operand is considered to be signed, and is -sign-extended to the length of the first operand. In these cases, -the \c{BYTE} qualifier is necessary to force NASM to generate this -form of the instruction. - -To subtract one number from another without also subtracting the -contents of the carry flag, use \c{SUB} (\k{insSUB}). - - -\S{insSCASB} \i\c{SCASB}, \i\c{SCASW}, \i\c{SCASD}: Scan String - -\c SCASB ; AE [8086] -\c SCASW ; o16 AF [8086] -\c SCASD ; o32 AF [386] - -\c{SCASB} compares the byte in \c{AL} with the byte at \c{[ES:DI]} -or \c{[ES:EDI]}, and sets the flags accordingly. It then increments -or decrements (depending on the direction flag: increments if the -flag is clear, decrements if it is set) \c{DI} (or \c{EDI}). - -The register used is \c{DI} if the address size is 16 bits, and -\c{EDI} if it is 32 bits. If you need to use an address size not -equal to the current \c{BITS} setting, you can use an explicit -\i\c{a16} or \i\c{a32} prefix. - -Segment override prefixes have no effect for this instruction: the -use of \c{ES} for the load from \c{[DI]} or \c{[EDI]} cannot be -overridden. - -\c{SCASW} and \c{SCASD} work in the same way, but they compare a -word to \c{AX} or a doubleword to \c{EAX} instead of a byte to -\c{AL}, and increment or decrement the addressing registers by 2 or -4 instead of 1. - -The \c{REPE} and \c{REPNE} prefixes (equivalently, \c{REPZ} and -\c{REPNZ}) may be used to repeat the instruction up to \c{CX} (or -\c{ECX} - again, the address size chooses which) times until the -first unequal or equal byte is found. - - -\S{insSETcc} \i\c{SETcc}: Set Register from Condition - -\c SETcc r/m8 ; 0F 90+cc /2 [386] - -\c{SETcc} sets the given 8-bit operand to zero if its condition is -not satisfied, and to 1 if it is. - - -\S{insSFENCE} \i\c{SFENCE}: Store Fence - -\c SFENCE ; 0F AE /7 [KATMAI] - -\c{SFENCE} performs a serialising operation on all writes to memory -that were issued before the \c{SFENCE} instruction. This guarantees that -all memory writes before the \c{SFENCE} instruction are visible before any -writes after the \c{SFENCE} instruction. - -\c{SFENCE} is ordered respective to other \c{SFENCE} instruction, \c{MFENCE}, -any memory write and any other serialising instruction (such as \c{CPUID}). - -Weakly ordered memory types can be used to achieve higher processor -performance through such techniques as out-of-order issue, -write-combining, and write-collapsing. The degree to which a consumer -of data recognizes or knows that the data is weakly ordered varies -among applications and may be unknown to the producer of this data. -The \c{SFENCE} instruction provides a performance-efficient way of -insuring store ordering between routines that produce weakly-ordered -results and routines that consume this data. - -\c{SFENCE} uses the following ModRM encoding: - -\c Mod (7:6) = 11B -\c Reg/Opcode (5:3) = 111B -\c R/M (2:0) = 000B - -All other ModRM encodings are defined to be reserved, and use -of these encodings risks incompatibility with future processors. - -See also \c{LFENCE} (\k{insLFENCE}) and \c{MFENCE} (\k{insMFENCE}). - - -\S{insSGDT} \i\c{SGDT}, \i\c{SIDT}, \i\c{SLDT}: Store Descriptor Table Pointers - -\c SGDT mem ; 0F 01 /0 [286,PRIV] -\c SIDT mem ; 0F 01 /1 [286,PRIV] -\c SLDT r/m16 ; 0F 00 /0 [286,PRIV] - -\c{SGDT} and \c{SIDT} both take a 6-byte memory area as an operand: -they store the contents of the GDTR (global descriptor table -register) or IDTR (interrupt descriptor table register) into that -area as a 32-bit linear address and a 16-bit size limit from that -area (in that order). These are the only instructions which directly -use \e{linear} addresses, rather than segment/offset pairs. - -\c{SLDT} stores the segment selector corresponding to the LDT (local -descriptor table) into the given operand. - -See also \c{LGDT}, \c{LIDT} and \c{LLDT} (\k{insLGDT}). - - -\S{insSHL} \i\c{SHL}, \i\c{SHR}: Bitwise Logical Shifts - -\c SHL r/m8,1 ; D0 /4 [8086] -\c SHL r/m8,CL ; D2 /4 [8086] -\c SHL r/m8,imm8 ; C0 /4 ib [186] -\c SHL r/m16,1 ; o16 D1 /4 [8086] -\c SHL r/m16,CL ; o16 D3 /4 [8086] -\c SHL r/m16,imm8 ; o16 C1 /4 ib [186] -\c SHL r/m32,1 ; o32 D1 /4 [386] -\c SHL r/m32,CL ; o32 D3 /4 [386] -\c SHL r/m32,imm8 ; o32 C1 /4 ib [386] - -\c SHR r/m8,1 ; D0 /5 [8086] -\c SHR r/m8,CL ; D2 /5 [8086] -\c SHR r/m8,imm8 ; C0 /5 ib [186] -\c SHR r/m16,1 ; o16 D1 /5 [8086] -\c SHR r/m16,CL ; o16 D3 /5 [8086] -\c SHR r/m16,imm8 ; o16 C1 /5 ib [186] -\c SHR r/m32,1 ; o32 D1 /5 [386] -\c SHR r/m32,CL ; o32 D3 /5 [386] -\c SHR r/m32,imm8 ; o32 C1 /5 ib [386] - -\c{SHL} and \c{SHR} perform a logical shift operation on the given -source/destination (first) operand. The vacated bits are filled with -zero. - -A synonym for \c{SHL} is \c{SAL} (see \k{insSAL}). NASM will -assemble either one to the same code, but NDISASM will always -disassemble that code as \c{SHL}. - -The number of bits to shift by is given by the second operand. Only -the bottom five bits of the shift count are considered by processors -above the 8086. - -You can force the longer (286 and upwards, beginning with a \c{C1} -byte) form of \c{SHL foo,1} by using a \c{BYTE} prefix: \c{SHL -foo,BYTE 1}. Similarly with \c{SHR}. - - -\S{insSHLD} \i\c{SHLD}, \i\c{SHRD}: Bitwise Double-Precision Shifts - -\c SHLD r/m16,reg16,imm8 ; o16 0F A4 /r ib [386] -\c SHLD r/m16,reg32,imm8 ; o32 0F A4 /r ib [386] -\c SHLD r/m16,reg16,CL ; o16 0F A5 /r [386] -\c SHLD r/m16,reg32,CL ; o32 0F A5 /r [386] - -\c SHRD r/m16,reg16,imm8 ; o16 0F AC /r ib [386] -\c SHRD r/m32,reg32,imm8 ; o32 0F AC /r ib [386] -\c SHRD r/m16,reg16,CL ; o16 0F AD /r [386] -\c SHRD r/m32,reg32,CL ; o32 0F AD /r [386] - -\b \c{SHLD} performs a double-precision left shift. It notionally -places its second operand to the right of its first, then shifts -the entire bit string thus generated to the left by a number of -bits specified in the third operand. It then updates only the -\e{first} operand according to the result of this. The second -operand is not modified. - -\b \c{SHRD} performs the corresponding right shift: it notionally -places the second operand to the \e{left} of the first, shifts the -whole bit string right, and updates only the first operand. - -For example, if \c{EAX} holds \c{0x01234567} and \c{EBX} holds -\c{0x89ABCDEF}, then the instruction \c{SHLD EAX,EBX,4} would update -\c{EAX} to hold \c{0x12345678}. Under the same conditions, \c{SHRD -EAX,EBX,4} would update \c{EAX} to hold \c{0xF0123456}. - -The number of bits to shift by is given by the third operand. Only -the bottom five bits of the shift count are considered. - - -\S{insSHUFPD} \i\c{SHUFPD}: Shuffle Packed Double-Precision FP Values - -\c SHUFPD xmm1,xmm2/m128,imm8 ; 66 0F C6 /r ib [WILLAMETTE,SSE2] - -\c{SHUFPD} moves one of the packed double-precision FP values from -the destination operand into the low quadword of the destination -operand; the upper quadword is generated by moving one of the -double-precision FP values from the source operand into the -destination. The select (third) operand selects which of the values -are moved to the destination register. - -The select operand is an 8-bit immediate: bit 0 selects which value -is moved from the destination operand to the result (where 0 selects -the low quadword and 1 selects the high quadword) and bit 1 selects -which value is moved from the source operand to the result. -Bits 2 through 7 of the shuffle operand are reserved. - - -\S{insSHUFPS} \i\c{SHUFPS}: Shuffle Packed Single-Precision FP Values - -\c SHUFPS xmm1,xmm2/m128,imm8 ; 0F C6 /r ib [KATMAI,SSE] - -\c{SHUFPS} moves two of the packed single-precision FP values from -the destination operand into the low quadword of the destination -operand; the upper quadword is generated by moving two of the -single-precision FP values from the source operand into the -destination. The select (third) operand selects which of the -values are moved to the destination register. - -The select operand is an 8-bit immediate: bits 0 and 1 select the -value to be moved from the destination operand the low doubleword of -the result, bits 2 and 3 select the value to be moved from the -destination operand the second doubleword of the result, bits 4 and -5 select the value to be moved from the source operand the third -doubleword of the result, and bits 6 and 7 select the value to be -moved from the source operand to the high doubleword of the result. - - -\S{insSMI} \i\c{SMI}: System Management Interrupt - -\c SMI ; F1 [386,UNDOC] - -\c{SMI} puts some AMD processors into SMM mode. It is available on some -386 and 486 processors, and is only available when DR7 bit 12 is set, -otherwise it generates an Int 1. - - -\S{insSMINT} \i\c{SMINT}, \i\c{SMINTOLD}: Software SMM Entry (CYRIX) - -\c SMINT ; 0F 38 [PENT,CYRIX] -\c SMINTOLD ; 0F 7E [486,CYRIX] - -\c{SMINT} puts the processor into SMM mode. The CPU state information is -saved in the SMM memory header, and then execution begins at the SMM base -address. - -\c{SMINTOLD} is the same as \c{SMINT}, but was the opcode used on the 486. - -This pair of opcodes are specific to the Cyrix and compatible range of -processors (Cyrix, IBM, Via). - - -\S{insSMSW} \i\c{SMSW}: Store Machine Status Word - -\c SMSW r/m16 ; 0F 01 /4 [286,PRIV] - -\c{SMSW} stores the bottom half of the \c{CR0} control register (or -the Machine Status Word, on 286 processors) into the destination -operand. See also \c{LMSW} (\k{insLMSW}). - -For 32-bit code, this would store all of \c{CR0} in the specified -register (or the bottom 16 bits if the destination is a memory location), - without needing an operand size override byte. - - -\S{insSQRTPD} \i\c{SQRTPD}: Packed Double-Precision FP Square Root - -\c SQRTPD xmm1,xmm2/m128 ; 66 0F 51 /r [WILLAMETTE,SSE2] - -\c{SQRTPD} calculates the square root of the packed double-precision -FP value from the source operand, and stores the double-precision -results in the destination register. - - -\S{insSQRTPS} \i\c{SQRTPS}: Packed Single-Precision FP Square Root - -\c SQRTPS xmm1,xmm2/m128 ; 0F 51 /r [KATMAI,SSE] - -\c{SQRTPS} calculates the square root of the packed single-precision -FP value from the source operand, and stores the single-precision -results in the destination register. - - -\S{insSQRTSD} \i\c{SQRTSD}: Scalar Double-Precision FP Square Root - -\c SQRTSD xmm1,xmm2/m128 ; F2 0F 51 /r [WILLAMETTE,SSE2] - -\c{SQRTSD} calculates the square root of the low-order double-precision -FP value from the source operand, and stores the double-precision -result in the destination register. The high-quadword remains unchanged. - - -\S{insSQRTSS} \i\c{SQRTSS}: Scalar Single-Precision FP Square Root - -\c SQRTSS xmm1,xmm2/m128 ; F3 0F 51 /r [KATMAI,SSE] - -\c{SQRTSS} calculates the square root of the low-order single-precision -FP value from the source operand, and stores the single-precision -result in the destination register. The three high doublewords remain -unchanged. - - -\S{insSTC} \i\c{STC}, \i\c{STD}, \i\c{STI}: Set Flags - -\c STC ; F9 [8086] -\c STD ; FD [8086] -\c STI ; FB [8086] - -These instructions set various flags. \c{STC} sets the carry flag; -\c{STD} sets the direction flag; and \c{STI} sets the interrupt flag -(thus enabling interrupts). - -To clear the carry, direction, or interrupt flags, use the \c{CLC}, -\c{CLD} and \c{CLI} instructions (\k{insCLC}). To invert the carry -flag, use \c{CMC} (\k{insCMC}). - - -\S{insSTMXCSR} \i\c{STMXCSR}: Store Streaming SIMD Extension - Control/Status - -\c STMXCSR m32 ; 0F AE /3 [KATMAI,SSE] - -\c{STMXCSR} stores the contents of the \c{MXCSR} control/status -register to the specified memory location. \c{MXCSR} is used to -enable masked/unmasked exception handling, to set rounding modes, -to set flush-to-zero mode, and to view exception status flags. -The reserved bits in the \c{MXCSR} register are stored as 0s. - -For details of the \c{MXCSR} register, see the Intel processor docs. - -See also \c{LDMXCSR} (\k{insLDMXCSR}). - - -\S{insSTOSB} \i\c{STOSB}, \i\c{STOSW}, \i\c{STOSD}: Store Byte to String - -\c STOSB ; AA [8086] -\c STOSW ; o16 AB [8086] -\c STOSD ; o32 AB [386] - -\c{STOSB} stores the byte in \c{AL} at \c{[ES:DI]} or \c{[ES:EDI]}, -and sets the flags accordingly. It then increments or decrements -(depending on the direction flag: increments if the flag is clear, -decrements if it is set) \c{DI} (or \c{EDI}). - -The register used is \c{DI} if the address size is 16 bits, and -\c{EDI} if it is 32 bits. If you need to use an address size not -equal to the current \c{BITS} setting, you can use an explicit -\i\c{a16} or \i\c{a32} prefix. - -Segment override prefixes have no effect for this instruction: the -use of \c{ES} for the store to \c{[DI]} or \c{[EDI]} cannot be -overridden. - -\c{STOSW} and \c{STOSD} work in the same way, but they store the -word in \c{AX} or the doubleword in \c{EAX} instead of the byte in -\c{AL}, and increment or decrement the addressing registers by 2 or -4 instead of 1. - -The \c{REP} prefix may be used to repeat the instruction \c{CX} (or -\c{ECX} - again, the address size chooses which) times. - - -\S{insSTR} \i\c{STR}: Store Task Register - -\c STR r/m16 ; 0F 00 /1 [286,PRIV] - -\c{STR} stores the segment selector corresponding to the contents of -the Task Register into its operand. When the operand size is 32 bit and -the destination is a register, the upper 16-bits are cleared to 0s. -When the destination operand is a memory location, 16 bits are -written regardless of the operand size. - - -\S{insSUB} \i\c{SUB}: Subtract Integers - -\c SUB r/m8,reg8 ; 28 /r [8086] -\c SUB r/m16,reg16 ; o16 29 /r [8086] -\c SUB r/m32,reg32 ; o32 29 /r [386] - -\c SUB reg8,r/m8 ; 2A /r [8086] -\c SUB reg16,r/m16 ; o16 2B /r [8086] -\c SUB reg32,r/m32 ; o32 2B /r [386] - -\c SUB r/m8,imm8 ; 80 /5 ib [8086] -\c SUB r/m16,imm16 ; o16 81 /5 iw [8086] -\c SUB r/m32,imm32 ; o32 81 /5 id [386] - -\c SUB r/m16,imm8 ; o16 83 /5 ib [8086] -\c SUB r/m32,imm8 ; o32 83 /5 ib [386] - -\c SUB AL,imm8 ; 2C ib [8086] -\c SUB AX,imm16 ; o16 2D iw [8086] -\c SUB EAX,imm32 ; o32 2D id [386] - -\c{SUB} performs integer subtraction: it subtracts its second -operand from its first, and leaves the result in its destination -(first) operand. The flags are set according to the result of the -operation: in particular, the carry flag is affected and can be used -by a subsequent \c{SBB} instruction (\k{insSBB}). - -In the forms with an 8-bit immediate second operand and a longer -first operand, the second operand is considered to be signed, and is -sign-extended to the length of the first operand. In these cases, -the \c{BYTE} qualifier is necessary to force NASM to generate this -form of the instruction. - - -\S{insSUBPD} \i\c{SUBPD}: Packed Double-Precision FP Subtract - -\c SUBPD xmm1,xmm2/m128 ; 66 0F 5C /r [WILLAMETTE,SSE2] - -\c{SUBPD} subtracts the packed double-precision FP values of -the source operand from those of the destination operand, and -stores the result in the destination operation. - - -\S{insSUBPS} \i\c{SUBPS}: Packed Single-Precision FP Subtract - -\c SUBPS xmm1,xmm2/m128 ; 0F 5C /r [KATMAI,SSE] - -\c{SUBPS} subtracts the packed single-precision FP values of -the source operand from those of the destination operand, and -stores the result in the destination operation. - - -\S{insSUBSD} \i\c{SUBSD}: Scalar Single-FP Subtract - -\c SUBSD xmm1,xmm2/m128 ; F2 0F 5C /r [WILLAMETTE,SSE2] - -\c{SUBSD} subtracts the low-order double-precision FP value of -the source operand from that of the destination operand, and -stores the result in the destination operation. The high -quadword is unchanged. - - -\S{insSUBSS} \i\c{SUBSS}: Scalar Single-FP Subtract - -\c SUBSS xmm1,xmm2/m128 ; F3 0F 5C /r [KATMAI,SSE] - -\c{SUBSS} subtracts the low-order single-precision FP value of -the source operand from that of the destination operand, and -stores the result in the destination operation. The three high -doublewords are unchanged. - - -\S{insSVDC} \i\c{SVDC}: Save Segment Register and Descriptor - -\c SVDC m80,segreg ; 0F 78 /r [486,CYRIX,SMM] - -\c{SVDC} saves a segment register (DS, ES, FS, GS, or SS) and its -descriptor to mem80. - - -\S{insSVLDT} \i\c{SVLDT}: Save LDTR and Descriptor - -\c SVLDT m80 ; 0F 7A /0 [486,CYRIX,SMM] - -\c{SVLDT} saves the Local Descriptor Table (LDTR) to mem80. - - -\S{insSVTS} \i\c{SVTS}: Save TSR and Descriptor - -\c SVTS m80 ; 0F 7C /0 [486,CYRIX,SMM] - -\c{SVTS} saves the Task State Register (TSR) to mem80. - - -\S{insSYSCALL} \i\c{SYSCALL}: Call Operating System - -\c SYSCALL ; 0F 05 [P6,AMD] - -\c{SYSCALL} provides a fast method of transferring control to a fixed -entry point in an operating system. - -\b The \c{EIP} register is copied into the \c{ECX} register. - -\b Bits [31-0] of the 64-bit SYSCALL/SYSRET Target Address Register -(\c{STAR}) are copied into the \c{EIP} register. - -\b Bits [47-32] of the \c{STAR} register specify the selector that is -copied into the \c{CS} register. - -\b Bits [47-32]+1000b of the \c{STAR} register specify the selector that -is copied into the SS register. - -The \c{CS} and \c{SS} registers should not be modified by the operating -system between the execution of the \c{SYSCALL} instruction and its -corresponding \c{SYSRET} instruction. - -For more information, see the \c{SYSCALL and SYSRET Instruction Specification} -(AMD document number 21086.pdf). - - -\S{insSYSENTER} \i\c{SYSENTER}: Fast System Call - -\c SYSENTER ; 0F 34 [P6] - -\c{SYSENTER} executes a fast call to a level 0 system procedure or -routine. Before using this instruction, various MSRs need to be set -up: - -\b \c{SYSENTER_CS_MSR} contains the 32-bit segment selector for the -privilege level 0 code segment. (This value is also used to compute -the segment selector of the privilege level 0 stack segment.) - -\b \c{SYSENTER_EIP_MSR} contains the 32-bit offset into the privilege -level 0 code segment to the first instruction of the selected operating -procedure or routine. - -\b \c{SYSENTER_ESP_MSR} contains the 32-bit stack pointer for the -privilege level 0 stack. - -\c{SYSENTER} performs the following sequence of operations: - -\b Loads the segment selector from the \c{SYSENTER_CS_MSR} into the -\c{CS} register. - -\b Loads the instruction pointer from the \c{SYSENTER_EIP_MSR} into -the \c{EIP} register. - -\b Adds 8 to the value in \c{SYSENTER_CS_MSR} and loads it into the -\c{SS} register. - -\b Loads the stack pointer from the \c{SYSENTER_ESP_MSR} into the -\c{ESP} register. - -\b Switches to privilege level 0. - -\b Clears the \c{VM} flag in the \c{EFLAGS} register, if the flag -is set. - -\b Begins executing the selected system procedure. - -In particular, note that this instruction des not save the values of -\c{CS} or \c{(E)IP}. If you need to return to the calling code, you -need to write your code to cater for this. - -For more information, see the Intel Architecture Software Developer's -Manual, Volume 2. - - -\S{insSYSEXIT} \i\c{SYSEXIT}: Fast Return From System Call - -\c SYSEXIT ; 0F 35 [P6,PRIV] - -\c{SYSEXIT} executes a fast return to privilege level 3 user code. -This instruction is a companion instruction to the \c{SYSENTER} -instruction, and can only be executed by privilege level 0 code. -Various registers need to be set up before calling this instruction: - -\b \c{SYSENTER_CS_MSR} contains the 32-bit segment selector for the -privilege level 0 code segment in which the processor is currently -executing. (This value is used to compute the segment selectors for -the privilege level 3 code and stack segments.) - -\b \c{EDX} contains the 32-bit offset into the privilege level 3 code -segment to the first instruction to be executed in the user code. - -\b \c{ECX} contains the 32-bit stack pointer for the privilege level 3 -stack. - -\c{SYSEXIT} performs the following sequence of operations: - -\b Adds 16 to the value in \c{SYSENTER_CS_MSR} and loads the sum into -the \c{CS} selector register. - -\b Loads the instruction pointer from the \c{EDX} register into the -\c{EIP} register. - -\b Adds 24 to the value in \c{SYSENTER_CS_MSR} and loads the sum -into the \c{SS} selector register. - -\b Loads the stack pointer from the \c{ECX} register into the \c{ESP} -register. - -\b Switches to privilege level 3. - -\b Begins executing the user code at the \c{EIP} address. - -For more information on the use of the \c{SYSENTER} and \c{SYSEXIT} -instructions, see the Intel Architecture Software Developer's -Manual, Volume 2. - - -\S{insSYSRET} \i\c{SYSRET}: Return From Operating System - -\c SYSRET ; 0F 07 [P6,AMD,PRIV] - -\c{SYSRET} is the return instruction used in conjunction with the -\c{SYSCALL} instruction to provide fast entry/exit to an operating system. - -\b The \c{ECX} register, which points to the next sequential instruction -after the corresponding \c{SYSCALL} instruction, is copied into the \c{EIP} -register. - -\b Bits [63-48] of the \c{STAR} register specify the selector that is copied -into the \c{CS} register. - -\b Bits [63-48]+1000b of the \c{STAR} register specify the selector that is -copied into the \c{SS} register. - -\b Bits [1-0] of the \c{SS} register are set to 11b (RPL of 3) regardless of -the value of bits [49-48] of the \c{STAR} register. - -The \c{CS} and \c{SS} registers should not be modified by the operating -system between the execution of the \c{SYSCALL} instruction and its -corresponding \c{SYSRET} instruction. - -For more information, see the \c{SYSCALL and SYSRET Instruction Specification} -(AMD document number 21086.pdf). - - -\S{insTEST} \i\c{TEST}: Test Bits (notional bitwise AND) - -\c TEST r/m8,reg8 ; 84 /r [8086] -\c TEST r/m16,reg16 ; o16 85 /r [8086] -\c TEST r/m32,reg32 ; o32 85 /r [386] - -\c TEST r/m8,imm8 ; F6 /0 ib [8086] -\c TEST r/m16,imm16 ; o16 F7 /0 iw [8086] -\c TEST r/m32,imm32 ; o32 F7 /0 id [386] - -\c TEST AL,imm8 ; A8 ib [8086] -\c TEST AX,imm16 ; o16 A9 iw [8086] -\c TEST EAX,imm32 ; o32 A9 id [386] - -\c{TEST} performs a `mental' bitwise AND of its two operands, and -affects the flags as if the operation had taken place, but does not -store the result of the operation anywhere. - - -\S{insUCOMISD} \i\c{UCOMISD}: Unordered Scalar Double-Precision FP -compare and set EFLAGS - -\c UCOMISD xmm1,xmm2/m128 ; 66 0F 2E /r [WILLAMETTE,SSE2] - -\c{UCOMISD} compares the low-order double-precision FP numbers in the -two operands, and sets the \c{ZF}, \c{PF} and \c{CF} bits in the -\c{EFLAGS} register. In addition, the \c{OF}, \c{SF} and \c{AF} bits -in the \c{EFLAGS} register are zeroed out. The unordered predicate -(\c{ZF}, \c{PF} and \c{CF} all set) is returned if either source -operand is a \c{NaN} (\c{qNaN} or \c{sNaN}). - - -\S{insUCOMISS} \i\c{UCOMISS}: Unordered Scalar Single-Precision FP -compare and set EFLAGS - -\c UCOMISS xmm1,xmm2/m128 ; 0F 2E /r [KATMAI,SSE] - -\c{UCOMISS} compares the low-order single-precision FP numbers in the -two operands, and sets the \c{ZF}, \c{PF} and \c{CF} bits in the -\c{EFLAGS} register. In addition, the \c{OF}, \c{SF} and \c{AF} bits -in the \c{EFLAGS} register are zeroed out. The unordered predicate -(\c{ZF}, \c{PF} and \c{CF} all set) is returned if either source -operand is a \c{NaN} (\c{qNaN} or \c{sNaN}). - - -\S{insUD2} \i\c{UD0}, \i\c{UD1}, \i\c{UD2}: Undefined Instruction - -\c UD0 ; 0F FF [186,UNDOC] -\c UD1 ; 0F B9 [186,UNDOC] -\c UD2 ; 0F 0B [186] - -\c{UDx} can be used to generate an invalid opcode exception, for testing -purposes. - -\c{UD0} is specifically documented by AMD as being reserved for this -purpose. - -\c{UD1} is documented by Intel as being available for this purpose. - -\c{UD2} is specifically documented by Intel as being reserved for this -purpose. Intel document this as the preferred method of generating an -invalid opcode exception. - -All these opcodes can be used to generate invalid opcode exceptions on -all currently available processors. - - -\S{insUMOV} \i\c{UMOV}: User Move Data - -\c UMOV r/m8,reg8 ; 0F 10 /r [386,UNDOC] -\c UMOV r/m16,reg16 ; o16 0F 11 /r [386,UNDOC] -\c UMOV r/m32,reg32 ; o32 0F 11 /r [386,UNDOC] - -\c UMOV reg8,r/m8 ; 0F 12 /r [386,UNDOC] -\c UMOV reg16,r/m16 ; o16 0F 13 /r [386,UNDOC] -\c UMOV reg32,r/m32 ; o32 0F 13 /r [386,UNDOC] - -This undocumented instruction is used by in-circuit emulators to -access user memory (as opposed to host memory). It is used just like -an ordinary memory/register or register/register \c{MOV} -instruction, but accesses user space. - -This instruction is only available on some AMD and IBM 386 and 486 -processors. - - -\S{insUNPCKHPD} \i\c{UNPCKHPD}: Unpack and Interleave High Packed -Double-Precision FP Values - -\c UNPCKHPD xmm1,xmm2/m128 ; 66 0F 15 /r [WILLAMETTE,SSE2] - -\c{UNPCKHPD} performs an interleaved unpack of the high-order data -elements of the source and destination operands, saving the result -in \c{xmm1}. It ignores the lower half of the sources. - -The operation of this instruction is: - -\c dst[63-0] := dst[127-64]; -\c dst[127-64] := src[127-64]. - - -\S{insUNPCKHPS} \i\c{UNPCKHPS}: Unpack and Interleave High Packed -Single-Precision FP Values - -\c UNPCKHPS xmm1,xmm2/m128 ; 0F 15 /r [KATMAI,SSE] - -\c{UNPCKHPS} performs an interleaved unpack of the high-order data -elements of the source and destination operands, saving the result -in \c{xmm1}. It ignores the lower half of the sources. - -The operation of this instruction is: - -\c dst[31-0] := dst[95-64]; -\c dst[63-32] := src[95-64]; -\c dst[95-64] := dst[127-96]; -\c dst[127-96] := src[127-96]. - - -\S{insUNPCKLPD} \i\c{UNPCKLPD}: Unpack and Interleave Low Packed -Double-Precision FP Data - -\c UNPCKLPD xmm1,xmm2/m128 ; 66 0F 14 /r [WILLAMETTE,SSE2] - -\c{UNPCKLPD} performs an interleaved unpack of the low-order data -elements of the source and destination operands, saving the result -in \c{xmm1}. It ignores the lower half of the sources. - -The operation of this instruction is: - -\c dst[63-0] := dst[63-0]; -\c dst[127-64] := src[63-0]. - - -\S{insUNPCKLPS} \i\c{UNPCKLPS}: Unpack and Interleave Low Packed -Single-Precision FP Data - -\c UNPCKLPS xmm1,xmm2/m128 ; 0F 14 /r [KATMAI,SSE] - -\c{UNPCKLPS} performs an interleaved unpack of the low-order data -elements of the source and destination operands, saving the result -in \c{xmm1}. It ignores the lower half of the sources. - -The operation of this instruction is: - -\c dst[31-0] := dst[31-0]; -\c dst[63-32] := src[31-0]; -\c dst[95-64] := dst[63-32]; -\c dst[127-96] := src[63-32]. - - -\S{insVERR} \i\c{VERR}, \i\c{VERW}: Verify Segment Readability/Writability - -\c VERR r/m16 ; 0F 00 /4 [286,PRIV] - -\c VERW r/m16 ; 0F 00 /5 [286,PRIV] - -\b \c{VERR} sets the zero flag if the segment specified by the selector -in its operand can be read from at the current privilege level. -Otherwise it is cleared. - -\b \c{VERW} sets the zero flag if the segment can be written. - - -\S{insWAIT} \i\c{WAIT}: Wait for Floating-Point Processor - -\c WAIT ; 9B [8086] -\c FWAIT ; 9B [8086] - -\c{WAIT}, on 8086 systems with a separate 8087 FPU, waits for the -FPU to have finished any operation it is engaged in before -continuing main processor operations, so that (for example) an FPU -store to main memory can be guaranteed to have completed before the -CPU tries to read the result back out. - -On higher processors, \c{WAIT} is unnecessary for this purpose, and -it has the alternative purpose of ensuring that any pending unmasked -FPU exceptions have happened before execution continues. - - -\S{insWBINVD} \i\c{WBINVD}: Write Back and Invalidate Cache - -\c WBINVD ; 0F 09 [486] - -\c{WBINVD} invalidates and empties the processor's internal caches, -and causes the processor to instruct external caches to do the same. -It writes the contents of the caches back to memory first, so no -data is lost. To flush the caches quickly without bothering to write -the data back first, use \c{INVD} (\k{insINVD}). - - -\S{insWRMSR} \i\c{WRMSR}: Write Model-Specific Registers - -\c WRMSR ; 0F 30 [PENT] - -\c{WRMSR} writes the value in \c{EDX:EAX} to the processor -Model-Specific Register (MSR) whose index is stored in \c{ECX}. -See also \c{RDMSR} (\k{insRDMSR}). - - -\S{insWRSHR} \i\c{WRSHR}: Write SMM Header Pointer Register - -\c WRSHR r/m32 ; 0F 37 /0 [386,CYRIX,SMM] - -\c{WRSHR} loads the contents of either a 32-bit memory location or a -32-bit register into the SMM header pointer register. - -See also \c{RDSHR} (\k{insRDSHR}). - - -\S{insXADD} \i\c{XADD}: Exchange and Add - -\c XADD r/m8,reg8 ; 0F C0 /r [486] -\c XADD r/m16,reg16 ; o16 0F C1 /r [486] -\c XADD r/m32,reg32 ; o32 0F C1 /r [486] - -\c{XADD} exchanges the values in its two operands, and then adds -them together and writes the result into the destination (first) -operand. This instruction can be used with a \c{LOCK} prefix for -multi-processor synchronisation purposes. - - -\S{insXBTS} \i\c{XBTS}: Extract Bit String - -\c XBTS reg16,r/m16 ; o16 0F A6 /r [386,UNDOC] -\c XBTS reg32,r/m32 ; o32 0F A6 /r [386,UNDOC] - -The implied operation of this instruction is: - -\c XBTS r/m16,reg16,AX,CL -\c XBTS r/m32,reg32,EAX,CL - -Writes a bit string from the source operand to the destination. \c{CL} -indicates the number of bits to be copied, and \c{(E)AX} indicates the -low order bit offset in the source. The bits are written to the low -order bits of the destination register. For example, if \c{CL} is set -to 4 and \c{AX} (for 16-bit code) is set to 5, bits 5-8 of \c{src} will -be copied to bits 0-3 of \c{dst}. This instruction is very poorly -documented, and I have been unable to find any official source of -documentation on it. - -\c{XBTS} is supported only on the early Intel 386s, and conflicts with -the opcodes for \c{CMPXCHG486} (on early Intel 486s). NASM supports it -only for completeness. Its counterpart is \c{IBTS} (see \k{insIBTS}). - - -\S{insXCHG} \i\c{XCHG}: Exchange - -\c XCHG reg8,r/m8 ; 86 /r [8086] -\c XCHG reg16,r/m8 ; o16 87 /r [8086] -\c XCHG reg32,r/m32 ; o32 87 /r [386] - -\c XCHG r/m8,reg8 ; 86 /r [8086] -\c XCHG r/m16,reg16 ; o16 87 /r [8086] -\c XCHG r/m32,reg32 ; o32 87 /r [386] - -\c XCHG AX,reg16 ; o16 90+r [8086] -\c XCHG EAX,reg32 ; o32 90+r [386] -\c XCHG reg16,AX ; o16 90+r [8086] -\c XCHG reg32,EAX ; o32 90+r [386] - -\c{XCHG} exchanges the values in its two operands. It can be used -with a \c{LOCK} prefix for purposes of multi-processor -synchronisation. - -\c{XCHG AX,AX} or \c{XCHG EAX,EAX} (depending on the \c{BITS} -setting) generates the opcode \c{90h}, and so is a synonym for -\c{NOP} (\k{insNOP}). - - -\S{insXLATB} \i\c{XLATB}: Translate Byte in Lookup Table - -\c XLAT ; D7 [8086] -\c XLATB ; D7 [8086] - -\c{XLATB} adds the value in \c{AL}, treated as an unsigned byte, to -\c{BX} or \c{EBX}, and loads the byte from the resulting address (in -the segment specified by \c{DS}) back into \c{AL}. - -The base register used is \c{BX} if the address size is 16 bits, and -\c{EBX} if it is 32 bits. If you need to use an address size not -equal to the current \c{BITS} setting, you can use an explicit -\i\c{a16} or \i\c{a32} prefix. - -The segment register used to load from \c{[BX+AL]} or \c{[EBX+AL]} -can be overridden by using a segment register name as a prefix (for -example, \c{es xlatb}). - - -\S{insXOR} \i\c{XOR}: Bitwise Exclusive OR - -\c XOR r/m8,reg8 ; 30 /r [8086] -\c XOR r/m16,reg16 ; o16 31 /r [8086] -\c XOR r/m32,reg32 ; o32 31 /r [386] - -\c XOR reg8,r/m8 ; 32 /r [8086] -\c XOR reg16,r/m16 ; o16 33 /r [8086] -\c XOR reg32,r/m32 ; o32 33 /r [386] - -\c XOR r/m8,imm8 ; 80 /6 ib [8086] -\c XOR r/m16,imm16 ; o16 81 /6 iw [8086] -\c XOR r/m32,imm32 ; o32 81 /6 id [386] - -\c XOR r/m16,imm8 ; o16 83 /6 ib [8086] -\c XOR r/m32,imm8 ; o32 83 /6 ib [386] - -\c XOR AL,imm8 ; 34 ib [8086] -\c XOR AX,imm16 ; o16 35 iw [8086] -\c XOR EAX,imm32 ; o32 35 id [386] - -\c{XOR} performs a bitwise XOR operation between its two operands -(i.e. each bit of the result is 1 if and only if exactly one of the -corresponding bits of the two inputs was 1), and stores the result -in the destination (first) operand. - -In the forms with an 8-bit immediate second operand and a longer -first operand, the second operand is considered to be signed, and is -sign-extended to the length of the first operand. In these cases, -the \c{BYTE} qualifier is necessary to force NASM to generate this -form of the instruction. - -The \c{MMX} instruction \c{PXOR} (see \k{insPXOR}) performs the same -operation on the 64-bit \c{MMX} registers. - - -\S{insXORPD} \i\c{XORPD}: Bitwise Logical XOR of Double-Precision FP Values - -\c XORPD xmm1,xmm2/m128 ; 66 0F 57 /r [WILLAMETTE,SSE2] - -\c{XORPD} returns a bit-wise logical XOR between the source and -destination operands, storing the result in the destination operand. - - -\S{insXORPS} \i\c{XORPS}: Bitwise Logical XOR of Single-Precision FP Values - -\c XORPS xmm1,xmm2/m128 ; 0F 57 /r [KATMAI,SSE] - -\c{XORPS} returns a bit-wise logical XOR between the source and -destination operands, storing the result in the destination operand. - - diff --git a/doc/nasmdoc.src b/doc/nasmdoc.src index 66856064..bda3b6f8 100644 --- a/doc/nasmdoc.src +++ b/doc/nasmdoc.src @@ -1,11 +1,45 @@ +\# -------------------------------------------------------------------------- +\# +\# Copyright 1996-2009 The NASM Authors - All Rights Reserved +\# See the file AUTHORS included with the NASM distribution for +\# the specific copyright holders. +\# +\# Redistribution and use in source and binary forms, with or without +\# modification, are permitted provided that the following +\# conditions are met: +\# +\# * Redistributions of source code must retain the above copyright +\# notice, this list of conditions and the following disclaimer. +\# * Redistributions in binary form must reproduce the above +\# copyright notice, this list of conditions and the following +\# disclaimer in the documentation and/or other materials provided +\# with the distribution. +\# +\# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +\# CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +\# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +\# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +\# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +\# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +\# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +\# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +\# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +\# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +\# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +\# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +\# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +\# +\# -------------------------------------------------------------------------- \# \# Source code to NASM documentation \# \M{category}{Programming} \M{title}{NASM - The Netwide Assembler} -\M{year}{2008} +\M{year}{1996-2009} \M{author}{The NASM Development Team} -\M{license}{All rights reserved. This document is redistributable under the license given in the file "COPYING" distributed in the NASM archive.} +\M{copyright_tail}{-- All Rights Reserved} +\M{license}{This document is redistributable under the license given in the file "COPYING" distributed in the NASM archive.} +\M{auxinfo}{This release is dedicated to the memory of Charles A. Crayne. We miss you, Chuck.} \M{summary}{This file documents NASM, the Netwide Assembler: an assembler targetting the Intel x86 series of processors, with portable source.} \M{infoname}{NASM} \M{infofile}{nasm} @@ -22,7 +56,7 @@ \IR{-MP} \c{-MP} option \IR{-MQ} \c{-MQ} option \IR{-MT} \c{-MT} option -\IR{-On} \c{-On} option +\IR{-O} \c{-O} option \IR{-P} \c{-P} option \IR{-U} \c{-U} option \IR{-X} \c{-X} option @@ -38,6 +72,7 @@ \IR{-s} \c{-s} option \IR{-u} \c{-u} option \IR{-v} \c{-v} option +\IR{-W} \c{-W} option \IR{-w} \c{-w} option \IR{-y} \c{-y} option \IR{-Z} \c{-Z} option @@ -285,12 +320,39 @@ know who you are), and we'll improve it out of all recognition. Again. -\S{legal} License Conditions +\S{legal} \i{License} Conditions + +Please see the file \c{LICENSE}, supplied as part of any NASM +distribution archive, for the license conditions under which you may +use NASM. NASM is now under the so-called 2-clause BSD license, also +known as the simplified BSD license. + +Copyright 1996-2009 the NASM Authors - All rights reserved. -Please see the file \c{COPYING}, supplied as part of any NASM -distribution archive, for the \i{license} conditions under which you -may use NASM. NASM is now under the so-called GNU Lesser General -Public License, LGPL. +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: + +\b Redistributions of source code must retain the above copyright +notice, this list of conditions and the following disclaimer. + +\b Redistributions in binary form must reproduce the above copyright +notice, this list of conditions and the following disclaimer in the +documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \H{contact} Contact Information @@ -300,32 +362,20 @@ team of developers, accessible through the \c{nasm-devel} mailing list (see below for the link). If you want to report a bug, please read \k{bugs} first. -NASM has a \i{WWW page} at -\W{http://nasm.sourceforge.net}\c{http://nasm.sourceforge.net}. If it's -not there, google for us! - - -The original authors are \i{e\-mail}able as -\W{mailto:jules@dsf.org.uk}\c{jules@dsf.org.uk} and -\W{mailto:anakin@pobox.com}\c{anakin@pobox.com}. -The latter is no longer involved in the development team. +NASM has a \i{website} at +\W{http://www.nasm.us/}\c{http://www.nasm.us/}. If it's not there, +google for us! -\i{New releases} of NASM are uploaded to the official sites -\W{http://nasm.sourceforge.net}\c{http://nasm.sourceforge.net} -and to -\W{ftp://ftp.kernel.org/pub/software/devel/nasm/}\i\c{ftp.kernel.org} -and -\W{ftp://ibiblio.org/pub/Linux/devel/lang/assemblers/}\i\c{ibiblio.org}. +\i{New releases} of NASM are available from the official web site. Announcements are posted to \W{news:comp.lang.asm.x86}\i\c{comp.lang.asm.x86}, -\W{news:alt.lang.asm}\i\c{alt.lang.asm} and -\W{news:comp.os.linux.announce}\i\c{comp.os.linux.announce} +and to the web site +\W{http://www.freshmeat.net/}\c{http://www.freshmeat.net/}. If you want information about NASM beta releases, and the current -development status, please subscribe to the \i\c{nasm-devel} email list -by registering at -\W{http://sourceforge.net/projects/nasm}\c{http://sourceforge.net/projects/nasm}. +development status, please subscribe to the \i\c{nasm-devel} email +list; see link from the website. \H{install} Installation @@ -480,7 +530,7 @@ an intervening space. For example: \c nasm -f bin driver.asm -odriver.sys Note that this is a small o, and is different from a capital O , which -is used to specify the number of optimisation passes required. See \k{opt-On}. +is used to specify the number of optimisation passes required. See \k{opt-O}. \S{opt-f} The \i\c{-f} Option: Specifying the \i{Output File Format} @@ -510,10 +560,10 @@ right. For example: \c nasm -f elf myfile.asm -l myfile.lst -If a list file is selected, you may turn off listing for a +If a list file is selected, you may turn off listing for a section of your source with \c{[list -]}, and turn it back on -with \c{[list +]}, (the default, obviously). There is no "user -form" (without the brackets). This can be used to list only +with \c{[list +]}, (the default, obviously). There is no "user +form" (without the brackets). This can be used to list only sections of interest, avoiding excessively long listings. @@ -588,7 +638,7 @@ A complete list of the available debug file formats for an output format can be seen by issuing the command \c{nasm -f <format> -y}. Not all output formats currently support debugging output. See \k{opt-y}. -This should not be confused with the \c{-f dbg} output format option which +This should not be confused with the \c{-f dbg} output format option which is not built into NASM by default. For information on how to enable it when building from the sources, see \k{dbgfmt}. @@ -596,25 +646,25 @@ to enable it when building from the sources, see \k{dbgfmt}. \S{opt-g} The \i\c{-g} Option: Enabling \i{Debug Information}. This option can be used to generate debugging information in the specified -format. See \k{opt-F}. Using \c{-g} without \c{-F} results in emitting +format. See \k{opt-F}. Using \c{-g} without \c{-F} results in emitting debug info in the default format, if any, for the selected output format. -If no debug information is currently implemented in the selected output +If no debug information is currently implemented in the selected output format, \c{-g} is \e{silently ignored}. \S{opt-X} The \i\c{-X} Option: Selecting an \i{Error Reporting Format} -This option can be used to select an error reporting format for any +This option can be used to select an error reporting format for any error messages that might be produced by NASM. Currently, two error reporting formats may be selected. They are -the \c{-Xvc} option and the \c{-Xgnu} option. The GNU format is +the \c{-Xvc} option and the \c{-Xgnu} option. The GNU format is the default and looks like this: -\c filename.asm:65: error: specific error message +\c filename.asm:65: error: specific error message where \c{filename.asm} is the name of the source file in which the -error was detected, \c{65} is the source file line number on which +error was detected, \c{65} is the source file line number on which the error was detected, \c{error} is the severity of the error (this could be \c{warning}), and \c{specific error message} is a more detailed text message which should help pinpoint the exact problem. @@ -625,7 +675,7 @@ Visual C++ and some other programs. It looks like this: \c filename.asm(65) : error: specific error message where the only difference is that the line number is in parentheses -instead of being delimited by colons. +instead of being delimited by colons. See also the \c{Visual C++} output format, \k{win32fmt}. @@ -781,41 +831,38 @@ argument, instructs NASM to replace its powerful \i{preprocessor} with a \i{stub preprocessor} which does nothing. -\S{opt-On} The \i\c{-On} Option: Specifying \i{Multipass Optimization}. +\S{opt-O} The \i\c{-O} Option: Specifying \i{Multipass Optimization} -NASM defaults to being a two pass assembler. This means that if you -have a complex source file which needs more than 2 passes to assemble -optimally, you have to enable extra passes. +NASM defaults to not optimizing operands which can fit into a signed byte. +This means that if you want the shortest possible object code, +you have to enable optimization. -Using the \c{-O} option, you can tell NASM to carry out multiple passes. -The syntax is: +Using the \c{-O} option, you can tell NASM to carry out different +levels of optimization. The syntax is: -\b \c{-O0} strict two-pass assembly, JMP and Jcc are handled more - like v0.98, except that backward JMPs are short, if possible. - Immediate operands take their long forms if a short form is - not specified. +\b \c{-O0}: No optimization. All operands take their long forms, + if a short form is not specified, except conditional jumps. + This is intended to match NASM 0.98 behavior. -\b \c{-O1} strict two-pass assembly, but forward branches are assembled - with code guaranteed to reach; may produce larger code than - -O0, but will produce successful assembly more often if - branch offset sizes are not specified. - Additionally, immediate operands which will fit in a signed byte - are optimized, unless the long form is specified. +\b \c{-O1}: Minimal optimization. As above, but immediate operands + which will fit in a signed byte are optimized, + unless the long form is specified. Conditional jumps default + to the long form unless otherwise specified. -\b \c{-On} multi-pass optimization, minimize branch offsets; also will - minimize signed immediate bytes, overriding size specification - unless the \c{strict} keyword has been used (see \k{strict}). - The number specifies the maximum number of passes. The more - passes, the better the code, but the slower is the assembly. +\b \c{-Ox} (where \c{x} is the actual letter \c{x}): Multipass optimization. + Minimize branch offsets and signed immediate bytes, + overriding size specification unless the \c{strict} keyword + has been used (see \k{strict}). For compatability with earlier + releases, the letter \c{x} may also be any number greater than + one. This number has no effect on the actual number of passes. -\b \c{-Ox} where \c{x} is the actual letter \c{x}, indicates to NASM - to do unlimited passes. +The \c{-Ox} mode is recommended for most uses. Note that this is a capital \c{O}, and is different from a small \c{o}, which is used to specify the output file name. See \k{opt-o}. -\S{opt-t} The \i\c{-t} option: Enable TASM Compatibility Mode +\S{opt-t} The \i\c{-t} Option: Enable TASM Compatibility Mode NASM includes a limited form of compatibility with Borland's \i\c{TASM}. When NASM's \c{-t} option is used, the following changes are made: @@ -833,7 +880,7 @@ the instruction. \c{else}, \c{endif}, \c{if}, \c{ifdef}, \c{ifdifi}, \c{ifndef}, \c{include}, \c{local}) -\S{opt-w} The \i\c{-w} Option: Enable or Disable Assembly \i{Warnings} +\S{opt-w} The \i\c{-w} and \i\c{-W} Options: Enable or Disable Assembly \i{Warnings} NASM can observe many conditions during the course of assembly which are worth mentioning to the user, but not a sufficiently severe @@ -853,15 +900,12 @@ disable it by \c{-w-orphan-labels}. The \i{suppressible warning} classes are: -\b \i\c{error} decides if warnings should be treated as errors. -It is disabled by default. - \b \i\c{macro-params} covers warnings about \i{multi-line macros} being invoked with the wrong number of parameters. This warning class is enabled by default; see \k{mlmacover} for an example of why you might want to disable it. -\b \i\c{macro-selfref} warns if a macro references itself. This +\b \i\c{macro-selfref} warns if a macro references itself. This warning class is disabled by default. \b\i\c{macro-defaults} warns when a macro has more default @@ -876,8 +920,8 @@ see \k{syntax} for more information. \b \i\c{number-overflow} covers warnings about numeric constants which don't fit in 64 bits. This warning class is enabled by default. -\b \i\c{gnu-elf-extensions} warns if 8-bit or 16-bit relocations -are used in \c{-f elf} format. The GNU extensions allow this. +\b \i\c{gnu-elf-extensions} warns if 8-bit or 16-bit relocations +are used in \c{-f elf} format. The GNU extensions allow this. This warning class is disabled by default. \b \i\c{float-overflow} warns about floating point overflow. @@ -892,12 +936,25 @@ Disabled by default. \b \i\c{float-toolong} warns about too many digits in floating-point numbers. Enabled by default. +\b \i\c{user} controls \c{%warning} directives (see \k{pperror}). +Enabled by default. + +\b \i\c{error} causes warnings to be treated as errors. Disabled by +default. + +\b \i\c{all} is an alias for \e{all} suppressible warning classes (not +including \c{error}). Thus, \c{-w+all} enables all available warnings. + In addition, you can set warning classes across sections. Warning classes may be enabled with \i\c{[warning +warning-name]}, disabled with \i\c{[warning -warning-name]} or reset to their original value with \i\c{[warning *warning-name]}. No "user form" (without the brackets) exists. +Since version 2.00, NASM has also supported the gcc-like syntax +\c{-Wwarning} and \c{-Wno-warning} instead of \c{-w+warning} and +\c{-w-warning}, respectively. + \S{opt-v} The \i\c{-v} Option: Display \i{Version} Info @@ -908,8 +965,8 @@ You will need the version number if you report a bug. \S{opt-y} The \i\c{-y} Option: Display Available Debug Info Formats -Typing \c{nasm -f <option> -y} will display a list of the available -debug info formats for the given output format. The default format +Typing \c{nasm -f <option> -y} will display a list of the available +debug info formats for the given output format. The default format is indicated by an asterisk. For example: \c nasm -f elf -y @@ -922,10 +979,10 @@ is indicated by an asterisk. For example: \S{opt-pfix} The \i\c{--prefix} and \i\c{--postfix} Options. -The \c{--prefix} and \c{--postfix} options prepend or append +The \c{--prefix} and \c{--postfix} options prepend or append (respectively) the given argument to all \c{global} or -\c{extern} variables. E.g. \c{--prefix_} will prepend the -underscore to all global and external variables, as C sometimes +\c{extern} variables. E.g. \c{--prefix _} will prepend the +underscore to all global and external variables, as C sometimes (but not always) likes it. @@ -1133,7 +1190,7 @@ An identifier may also be prefixed with a \I{$, prefix}\c{$} to indicate that it is intended to be read as an identifier and not a reserved word; thus, if some other module you are linking with defines a symbol called \c{eax}, you can refer to \c{$eax} in NASM -code to distinguish the symbol from the register. Maximum length of +code to distinguish the symbol from the register. Maximum length of an identifier is 4095 characters. The instruction field may contain any machine instruction: Pentium @@ -1141,8 +1198,8 @@ and P6 instructions, FPU instructions, MMX instructions and even undocumented instructions are all supported. The instruction may be prefixed by \c{LOCK}, \c{REP}, \c{REPE}/\c{REPZ} or \c{REPNE}/\c{REPNZ}, in the usual way. Explicit \I{address-size -prefixes}address-size and \i{operand-size prefixes} \c{A16}, -\c{A32}, \c{O16} and \c{O32} are provided - one example of their use +prefixes}address-size and \i{operand-size prefixes} \i\c{A16}, +\i\c{A32}, \i\c{A64}, \i\c{O16} and \i\c{O32}, \i\c{O64} are provided - one example of their use is given in \k{mixsize}. You can also use the name of a \I{segment override}segment register as an instruction prefix: coding \c{es mov [bx],ax} is equivalent to coding \c{mov [es:bx],ax}. We @@ -1275,9 +1332,7 @@ redefined later. This is not a \i{preprocessor} definition either: the value of \c{msglen} is evaluated \e{once}, using the value of \c{$} (see \k{expr} for an explanation of \c{$}) at the point of definition, rather than being evaluated wherever it is referenced -and using the value of \c{$} at the point of reference. Note that -the operand to an \c{EQU} is also a \i{critical expression} -(\k{crit}). +and using the value of \c{$} at the point of reference. \S{times} \i\c{TIMES}: \i{Repeating} Instructions or Data @@ -1306,8 +1361,7 @@ Note that there is no effective difference between \c{times 100 resb 1} and \c{resb 100}, except that the latter will be assembled about 100 times faster due to the internal structure of the assembler. -The operand to \c{TIMES}, like that of \c{EQU} and those of \c{RESB} -and friends, is a critical expression (\k{crit}). +The operand to \c{TIMES} is a critical expression (\k{crit}). Note also that \c{TIMES} can't be applied to \i{macros}: the reason for this is that \c{TIMES} is processed after the macro phase, which @@ -1400,27 +1454,37 @@ character, string and floating-point. A numeric constant is simply a number. NASM allows you to specify numbers in a variety of number bases, in a variety of ways: you can -suffix \c{H}, \c{Q} or \c{O}, and \c{B} for \i{hex}, \i{octal} and \i{binary}, -or you can prefix \c{0x} for hex in the style of C, or you can -prefix \c{$} for hex in the style of Borland Pascal. Note, though, -that the \I{$, prefix}\c{$} prefix does double duty as a prefix on -identifiers (see \k{syntax}), so a hex number prefixed with a \c{$} -sign must have a digit after the \c{$} rather than a letter. +suffix \c{H} or \c{X}, \c{Q} or \c{O}, and \c{B} for \i{hexadecimal}, +\i{octal} and \i{binary} respectively, or you can prefix \c{0x} for +hexadecimal in the style of C, or you can prefix \c{$} for hexadecimal +in the style of Borland Pascal. Note, though, that the \I{$, +prefix}\c{$} prefix does double duty as a prefix on identifiers (see +\k{syntax}), so a hex number prefixed with a \c{$} sign must have a +digit after the \c{$} rather than a letter. In addition, current +versions of NASM accept the prefix \c{0h} for hexadecimal, \c{0o} or +\c{0q} for octal, and \c{0b} for binary. Please note that unlike C, a +\c{0} prefix by itself does \e{not} imply an octal constant! Numeric constants can have underscores (\c{_}) interspersed to break up long strings. -Some examples: - -\c mov ax,100 ; decimal -\c mov ax,0a2h ; hex -\c mov ax,$0a2 ; hex again: the 0 is required -\c mov ax,0xa2 ; hex yet again -\c mov ax,777q ; octal -\c mov ax,777o ; octal again -\c mov ax,10010011b ; binary -\c mov ax,1001_0011b ; same binary constant - +Some examples (all producing exactly the same code): + +\c mov ax,200 ; decimal +\c mov ax,0200 ; still decimal +\c mov ax,0200d ; explicitly decimal +\c mov ax,0d200 ; also decimal +\c mov ax,0c8h ; hex +\c mov ax,$0c8 ; hex again: the 0 is required +\c mov ax,0xc8 ; hex yet again +\c mov ax,0hc8 ; still hex +\c mov ax,310q ; octal +\c mov ax,310o ; octal again +\c mov ax,0o310 ; octal yet again +\c mov ax,0q310 ; hex yet again +\c mov ax,11001000b ; binary +\c mov ax,1100_1000b ; same binary constant +\c mov ax,0b1100_1000 ; same binary constant yet again \S{strings} \I{Strings}\i{Character Strings} @@ -1526,7 +1590,7 @@ For example: \c{__utf16__} and \c{__utf32__} can be applied either to strings passed to the \c{DB} family instructions, or to character constants in -an expression context. +an expression context. \S{fltconst} \I{floating-point, constants}Floating-Point Constants @@ -1762,7 +1826,7 @@ invent one using the macro processor. \H{strict} \i\c{STRICT}: Inhibiting Optimization When assembling with the optimizer set to level 2 or higher (see -\k{opt-On}), NASM will use size specifiers (\c{BYTE}, \c{WORD}, +\k{opt-O}), NASM will use size specifiers (\c{BYTE}, \c{WORD}, \c{DWORD}, \c{QWORD}, \c{TWORD}, \c{OWORD} or \c{YWORD}), but will give them the smallest possible size. The keyword \c{STRICT} can be used to inhibit optimization and force a particular operand to be @@ -1813,52 +1877,7 @@ NASM rejects these examples by means of a concept called a \e{critical expression}, which is defined to be an expression whose value is required to be computable in the first pass, and which must therefore depend only on symbols defined before it. The argument to -the \c{TIMES} prefix is a critical expression; for the same reason, -the arguments to the \i\c{RESB} family of pseudo-instructions are -also critical expressions. - -Critical expressions can crop up in other contexts as well: consider -the following code. - -\c mov ax,symbol1 -\c symbol1 equ symbol2 -\c symbol2: - -On the first pass, NASM cannot determine the value of \c{symbol1}, -because \c{symbol1} is defined to be equal to \c{symbol2} which NASM -hasn't seen yet. On the second pass, therefore, when it encounters -the line \c{mov ax,symbol1}, it is unable to generate the code for -it because it still doesn't know the value of \c{symbol1}. On the -next line, it would see the \i\c{EQU} again and be able to determine -the value of \c{symbol1}, but by then it would be too late. - -NASM avoids this problem by defining the right-hand side of an -\c{EQU} statement to be a critical expression, so the definition of -\c{symbol1} would be rejected in the first pass. - -There is a related issue involving \i{forward references}: consider -this code fragment. - -\c mov eax,[ebx+offset] -\c offset equ 10 - -NASM, on pass one, must calculate the size of the instruction \c{mov -eax,[ebx+offset]} without knowing the value of \c{offset}. It has no -way of knowing that \c{offset} is small enough to fit into a -one-byte offset field and that it could therefore get away with -generating a shorter form of the \i{effective-address} encoding; for -all it knows, in pass one, \c{offset} could be a symbol in the code -segment, and it might need the full four-byte form. So it is forced -to compute the size of the instruction to accommodate a four-byte -address part. In pass two, having made this decision, it is now -forced to honour it and keep the instruction large, so the code -generated in this case is not as small as it could have been. This -problem can be solved by defining \c{offset} before using it, or by -forcing byte size in the effective address by coding \c{[byte -ebx+offset]}. - -Note that use of the \c{-On} switch (with n>=2) makes some of the above -no longer true (see \k{opt-On}). +the \c{TIMES} prefix is a critical expression. \H{locallab} \i{Local Labels} @@ -2028,13 +2047,13 @@ You can \i{pre-define} single-line macros using the `-d' option on the NASM command line: see \k{opt-d}. -\S{xdefine} Enhancing \c{%define}: \I\c{%ixdefine}\i\c{%xdefine} +\S{xdefine} Resolving \c{%define}: \I\c{%ixdefine}\i\c{%xdefine} To have a reference to an embedded single-line macro resolved at the -time that it is embedded, as opposed to when the calling macro is -expanded, you need a different mechanism to the one offered by -\c{%define}. The solution is to use \c{%xdefine}, or it's -\I{case sensitive}case-insensitive counterpart \c{%ixdefine}. +time that the embedding macro is \e{defined}, as opposed to when the +embedding macro is \e{expanded}, you need a different mechanism to the +one offered by \c{%define}. The solution is to use \c{%xdefine}, or +it's \I{case sensitive}case-insensitive counterpart \c{%ixdefine}. Suppose you have the following code: @@ -2074,6 +2093,27 @@ as that is what the embedded macro \c{isTrue} expanded to at the time that \c{isFalse} was defined. +\S{indmacro} \i{Macro Indirection}: \I\c{%[}\c{%[...]} + +The \c{%[...]} construct can be used to expand macros in contexts +where macro expansion would otherwise not occur, including in the +names other macros. For example, if you have a set of macros named +\c{Foo16}, \c{Foo32} and \c{Foo64}, you could write: + +\c mov ax,Foo%[__BITS__] ; The Foo value + +to use the builtin macro \c{__BITS__} (see \k{bitsm}) to automatically +select between them. Similarly, the two statements: + +\c %xdefine Bar Quux ; Expands due to %xdefine +\c %define Bar %[Quux] ; Expands due to %[...] + +have, in fact, exactly the same effect. + +\c{%[...]} concatenates to adjacent tokens in the same way that +multi-line macro parameters do, see \k{concat} for details. + + \S{concat%+} Concatenating Single Line Macro Tokens: \i\c{%+} Individual tokens in single line macros can be concatenated, to produce @@ -2145,6 +2185,7 @@ instruction has been used as a label in older code. For example: \c %idefine pause $%? ; Hide the PAUSE instruction + \S{undef} Undefining Single-Line Macros: \i\c{%undef} Single-line macros can be removed with the \c{%undef} directive. For @@ -2210,24 +2251,24 @@ is equivalent to This can be used, for example, with the \c{%!} construct (see \k{getenv}): -\c %defstr PATH %!PATH ; The operating system PATH variable +\c %defstr PATH %!PATH ; The operating system PATH variable \H{strlen} \i{String Manipulation in Macros} It's often useful to be able to handle strings in macros. NASM -supports two simple string handling macro operators from which +supports a few simple string handling macro operators from which more complex operations can be constructed. All the string operators define or redefine a value (either a string -or a numeric value) to a single-line macro. +or a numeric value) to a single-line macro. When producing a string +value, it may change the style of quoting of the input string or +strings, and possibly use \c{\\}-escapes inside \c{`}-quoted strings. \S{strcat} \i{Concatenating Strings}: \i\c{%strcat} The \c{%strcat} operator concatenates quoted strings and assign them to -a single-line macro. In doing so, it may change the type of quotes -and possibly use \c{\\}-escapes inside \c{`}-quoted strings in order to -make sure the string is still a valid quoted string. +a single-line macro. For example: @@ -2236,9 +2277,9 @@ For example: ... would assign the value \c{'Alpha: 12" screen'} to \c{alpha}. Similarly: -\c %strcat beta '"', "'" +\c %strcat beta '"foo"\', "'bar'" -... would assign the value \c{`"'`} to \c{beta}. +... would assign the value \c{`"foo"\\'bar'`} to \c{beta}. The use of commas to separate strings is permitted but optional. @@ -2609,11 +2650,11 @@ iterated through in reverse order. \S{concat} \i{Concatenating Macro Parameters} -NASM can concatenate macro parameters on to other text surrounding -them. This allows you to declare a family of symbols, for example, -in a macro definition. If, for example, you wanted to generate a -table of key codes along with offsets into the table, you could code -something like +NASM can concatenate macro parameters and macro indirection constructs +on to other text surrounding them. This allows you to declare a family +of symbols, for example, in a macro definition. If, for example, you +wanted to generate a table of key codes along with offsets into the +table, you could code something like \c %macro keytab_entry 2 \c @@ -2659,6 +2700,12 @@ real names of macro-local labels means that the two usages \c{%\{%foo\}bar} and \c{%%foobar} would both expand to the same thing anyway; nevertheless, the capability is there.) +The single-line macro indirection construct, \c{%[...]} +(\k{indmacro}), behaves the same way as macro parameters for the +purpose of concatenation. + +See also the \c{%+} operator, \k{concat%+}. + \S{mlmaccc} \i{Condition Codes as Macro Parameters} @@ -2730,7 +2777,7 @@ For example: removes the previously defined macro \c{foo}, but -\c %unmacro bar 1-3 +\c %macro bar 1-3 \c ; Do something \c %endmacro \c %unmacro bar 1 @@ -3045,7 +3092,7 @@ be gradually used up and other applications to start crashing. These commands allow you to split your sources into multiple files. -\S{include} \i\c{%include}: \i{Including Other Files} +\S{include} \i\c{%include}: \i{Including Other Files} Using, once again, a very similar syntax to the C preprocessor, NASM's preprocessor lets you include other source files into your @@ -3084,7 +3131,7 @@ on the NASM command line (see \k{opt-p}). The \c{%pathsearch} directive takes a single-line macro name and a filename, and declare or redefines the specified single-line macro to -be the include-path-resolved verson of the filename, if the file +be the include-path-resolved version of the filename, if the file exists (otherwise, it is passed unchanged.) For example, @@ -3124,9 +3171,9 @@ package. The standard macro packages are part of NASM, and are described in \k{macropkg}. Unlike the \c{%include} directive, package names for the \c{%use} -directive do not require quotes, but quotes are permitted; using -quotes will prevent unwanted macro expansion. Thus, the following -lines are equivalent, unless \c{altreg} is defined as a macro: +directive do not require quotes, but quotes are permitted. In NASM +2.04 and 2.05 the unquoted form would be macro-expanded; this is no +longer true. Thus, the following lines are equivalent: \c %use altreg \c %use 'altreg' @@ -3156,18 +3203,21 @@ define labels that are local to a particular context on the stack. contexts}\I{removing contexts}Creating and Removing Contexts The \c{%push} directive is used to create a new context and place it -on the top of the context stack. \c{%push} requires one argument, +on the top of the context stack. \c{%push} takes an optional argument, which is the name of the context. For example: \c %push foobar -This pushes a new context called \c{foobar} on the stack. You can -have several contexts on the stack with the same name: they can -still be distinguished. +This pushes a new context called \c{foobar} on the stack. You can have +several contexts on the stack with the same name: they can still be +distinguished. If no name is given, the context is unnamed (this is +normally used when both the \c{%push} and the \c{%pop} are inside a +single macro definition.) -The directive \c{%pop}, requiring no arguments, removes the top +The directive \c{%pop}, taking one optional argument, removes the top context from the context stack and destroys it, along with any -labels associated with it. +labels associated with it. If an argument is given, it must match the +name of the current context, otherwise it will issue an error. \S{ctxlocal} \i{Context-Local Labels} @@ -3444,7 +3494,7 @@ the construction of an appropriately sized ENTER instruction as shown in the example. -\H{pperror} Reporting \i{User-Defined Errors}: \i\c{%error} and \i\c{%warning} +\H{pperror} Reporting \i{User-Defined Errors}: \i\c{%error}, \i\c{%warning}, \i\c{%fatal} The preprocessor directive \c{%error} will cause NASM to report an error if it occurs in assembled code. So if other users are going to @@ -3475,8 +3525,24 @@ Similarly, \c{%warning} issues a warning, but allows assembly to continue: \c %define F1 \c %endif -It is optional for the message string after \c{%error} or \c{%warning} -to be quoted. +\c{%error} and \c{%warning} are issued only on the final assembly +pass. This makes them safe to use in conjunction with tests that +depend on symbol values. + +\c{%fatal} terminates assembly immediately, regardless of pass. This +is useful when there is no point in continuing the assembly further, +and doing so is likely just going to cause a spew of confusing error +messages. + +It is optional for the message string after \c{%error}, \c{%warning} +or \c{%fatal} to be quoted. If it is \e{not}, then single-line macros +are expanded in it, which can be used to display more information to +the user. For example: + +\c %if foo > 64 +\c %assign foo_over foo-64 +\c %error foo is foo_over bytes too large +\c %endif \H{otherpreproc} \i{Other Preprocessor Directives} @@ -3484,11 +3550,8 @@ to be quoted. NASM also has preprocessor directives which allow access to information from external sources. Currently they include: -The following preprocessor directive is supported to allow NASM to -correctly handle output of the cpp C language preprocessor. - -\b\c{%line} enables NASM to correctly handle the output of the cpp -C language preprocessor (see \k{line}). +\b\c{%line} enables NASM to correctly handle the output of another +preprocessor (see \k{line}). \b\c{%!} enables NASM to read in the value of an environment variable, which can then be used in your program (see \k{getenv}). @@ -3686,22 +3749,22 @@ started at 42 seconds after midnight on January 1, 2010 in Moscow assuming, of course, a properly configured environment with a correct clock: -\c __DATE__ "2010-01-01" -\c __TIME__ "00:00:42" -\c __DATE_NUM__ 20100101 -\c __TIME_NUM__ 000042 -\c __UTC_DATE__ "2009-12-31" -\c __UTC_TIME__ "21:00:42" -\c __UTC_DATE_NUM__ 20091231 -\c __UTC_TIME_NUM__ 210042 -\c __POSIX_TIME__ 1262293242 +\c __DATE__ "2010-01-01" +\c __TIME__ "00:00:42" +\c __DATE_NUM__ 20100101 +\c __TIME_NUM__ 000042 +\c __UTC_DATE__ "2009-12-31" +\c __UTC_TIME__ "21:00:42" +\c __UTC_DATE_NUM__ 20091231 +\c __UTC_TIME_NUM__ 210042 +\c __POSIX_TIME__ 1262293242 \S{use_def} \I\c{__USE_*__}\c{__USE_}\e{package}\c{__}: Package Include Test -When a standard macro package is included with the \c{%use} directive -(see \k{use}), a single-line macro of the form +When a standard macro package (see \k{macropkg}) is included with the +\c{%use} directive (see \k{use}), a single-line macro of the form \c{__USE_}\e{package}\c{__} is automatically defined. This allows testing if a particular package is invoked or not. @@ -3709,6 +3772,18 @@ For example, if the \c{altreg} package is included (see \k{pkg_altreg}), then the macro \c{__USE_ALTREG__} is defined. +\S{pass_macro} \i\c{__PASS__}: Assembly Pass + +The macro \c{__PASS__} is defined to be \c{1} on preparatory passes, +and \c{2} on the final pass. In preprocess-only mode, it is set to +\c{3}, and when running only to generate dependencies (due to the +\c{-M} or \c{-MG} option, see \k{opt-M}) it is set to \c{0}. + +\e{Avoid using this macro if at all possible. It is tremendously easy +to generate very strange errors by misusing it, and the semantics may +change in future versions of NASM.} + + \S{struc} \i\c{STRUC} and \i\c{ENDSTRUC}: \i{Declaring Structure} Data Types The core of NASM contains no intrinsic means of defining data @@ -3716,13 +3791,15 @@ structures; instead, the preprocessor is sufficiently powerful that data structures can be implemented as a set of macros. The macros \c{STRUC} and \c{ENDSTRUC} are used to define a structure data type. -\c{STRUC} takes one parameter, which is the name of the data type. -This name is defined as a symbol with the value zero, and also has -the suffix \c{_size} appended to it and is then defined as an -\c{EQU} giving the size of the structure. Once \c{STRUC} has been -issued, you are defining the structure, and should define fields -using the \c{RESB} family of pseudo-instructions, and then invoke -\c{ENDSTRUC} to finish the definition. +\c{STRUC} takes one or two parameters. The first parameter is the name +of the data type. The second, optional parameter is the base offset of +the structure. The name of the data type is defined as a symbol with +the value of the base offset, and the name of the data type with the +suffix \c{_size} appended to it is defined as an \c{EQU} giving the +size of the structure. Once \c{STRUC} has been issued, you are +defining the structure, and should define fields using the \c{RESB} +family of pseudo-instructions, and then invoke \c{ENDSTRUC} to finish +the definition. For example, to define a structure called \c{mytype} containing a longword, a word, a byte and a string of bytes, you might code @@ -3741,8 +3818,8 @@ from the beginning of a \c{mytype} structure to the longword field), \c{mt_word} as 4, \c{mt_byte} as 6, \c{mt_str} as 7, \c{mytype_size} as 39, and \c{mytype} itself as zero. -The reason why the structure type name is defined at zero is a side -effect of allowing structures to work with the local label +The reason why the structure type name is defined at zero by default +is a side effect of allowing structures to work with the local label mechanism: if your structure members tend to have the same names in more than one structure, you can define the above structure like this: @@ -3766,6 +3843,26 @@ so code such as \c{mov ax,[mystruc.mt_word]} is not valid. correct syntax is \c{mov ax,[mystruc+mt_word]} or \c{mov ax,[mystruc+mytype.word]}. +Sometimes you only have the address of the structure displaced by an +offset. For example, consider this standard stack frame setup: + +\c push ebp +\c mov ebp, esp +\c sub esp, 40 + +In this case, you could access an element by subtracting the offset: + +\c mov [ebp - 40 + mytype.word], ax + +However, if you do not want to repeat this offset, you can use -40 as +a base offset: + +\c struc mytype, -40 + +And access an element this way: + +\c mov [ebp + mytype.word], ax + \S{istruc} \i\c{ISTRUC}, \i\c{AT} and \i\c{IEND}: Declaring \i{Instances of Structures} @@ -4375,7 +4472,7 @@ is also useful for \i{operating system} and \i{boot loader} development. The \c{bin} format supports \i{multiple section names}. For details of -how nasm handles sections in the \c{bin} format, see \k{multisec}. +how NASM handles sections in the \c{bin} format, see \k{multisec}. Using the \c{bin} format puts NASM by default into 16-bit mode (see \k{bits}). In order to use \c{bin} to write 32-bit or 64-bit code, @@ -4432,57 +4529,83 @@ bin}\I{segment alignment, in bin}\I{alignment, in bin sections} \S{multisec} \i\c{Multisection}\I{bin, multisection} support for the BIN format. -The \c{bin} format allows the use of multiple sections, of arbitrary names, +The \c{bin} format allows the use of multiple sections, of arbitrary names, besides the "known" \c{.text}, \c{.data}, and \c{.bss} names. -\b Sections may be designated \i\c{progbits} or \i\c{nobits}. Default -is \c{progbits} (except \c{.bss}, which defaults to \c{nobits}, +\b Sections may be designated \i\c{progbits} or \i\c{nobits}. Default +is \c{progbits} (except \c{.bss}, which defaults to \c{nobits}, of course). -\b Sections can be aligned at a specified boundary following the previous -section with \c{align=}, or at an arbitrary byte-granular position with +\b Sections can be aligned at a specified boundary following the previous +section with \c{align=}, or at an arbitrary byte-granular position with \i\c{start=}. -\b Sections can be given a virtual start address, which will be used -for the calculation of all memory references within that section +\b Sections can be given a virtual start address, which will be used +for the calculation of all memory references within that section with \i\c{vstart=}. -\b Sections can be ordered using \i\c{follows=}\c{<section>} or -\i\c{vfollows=}\c{<section>} as an alternative to specifying an explicit +\b Sections can be ordered using \i\c{follows=}\c{<section>} or +\i\c{vfollows=}\c{<section>} as an alternative to specifying an explicit start address. -\b Arguments to \c{org}, \c{start}, \c{vstart}, and \c{align=} are -critical expressions. See \k{crit}. E.g. \c{align=(1 << ALIGN_SHIFT)} +\b Arguments to \c{org}, \c{start}, \c{vstart}, and \c{align=} are +critical expressions. See \k{crit}. E.g. \c{align=(1 << ALIGN_SHIFT)} - \c{ALIGN_SHIFT} must be defined before it is used here. \b Any code which comes before an explicit \c{SECTION} directive is directed by default into the \c{.text} section. -\b If an \c{ORG} statement is not given, \c{ORG 0} is used +\b If an \c{ORG} statement is not given, \c{ORG 0} is used by default. -\b The \c{.bss} section will be placed after the last \c{progbits} -section, unless \c{start=}, \c{vstart=}, \c{follows=}, or \c{vfollows=} +\b The \c{.bss} section will be placed after the last \c{progbits} +section, unless \c{start=}, \c{vstart=}, \c{follows=}, or \c{vfollows=} has been specified. -\b All sections are aligned on dword boundaries, unless a different +\b All sections are aligned on dword boundaries, unless a different alignment has been specified. \b Sections may not overlap. -\b NASM creates the \c{section.<secname>.start} for each section, +\b NASM creates the \c{section.<secname>.start} for each section, which may be used in your code. \S{map}\i{Map files} -Map files can be generated in \c{-f bin} format by means of the \c{[map]} -option. Map types of \c{all} (default), \c{brief}, \c{sections}, \c{segments}, -or \c{symbols} may be specified. Output may be directed to \c{stdout} +Map files can be generated in \c{-f bin} format by means of the \c{[map]} +option. Map types of \c{all} (default), \c{brief}, \c{sections}, \c{segments}, +or \c{symbols} may be specified. Output may be directed to \c{stdout} (default), \c{stderr}, or a specified file. E.g. \c{[map symbols myfile.map]}. No "user form" exists, the square brackets must be used. +\H{ithfmt} \i\c{ith}: \i{Intel Hex} Output + +The \c{ith} file format produces Intel hex-format files. Just as the +\c{bin} format, this is a flat memory image format with no support for +relocation or linking. It is usually used with ROM programmers and +similar utilities. + +All extensions supported by the \c{bin} file format is also supported by +the \c{ith} file format. + +\c{ith} provides a default output file-name extension of \c{.ith}. + + +\H{srecfmt} \i\c{srec}: \i{Motorola S-Records} Output + +The \c{srec} file format produces Motorola S-records files. Just as the +\c{bin} format, this is a flat memory image format with no support for +relocation or linking. It is usually used with ROM programmers and +similar utilities. + +All extensions supported by the \c{bin} file format is also supported by +the \c{srec} file format. + +\c{srec} provides a default output file-name extension of \c{.srec}. + + \H{objfmt} \i\c{obj}: \i{Microsoft OMF}\I{OMF} Object Files The \c{obj} file format (NASM calls it \c{obj} rather than \c{omf} @@ -4925,7 +5048,7 @@ still be perfectly possible. Registering custom exception handler on the other hand requires certain "magic." As of version 2.03 additional directive is implemented, \c{safeseh}, which instructs the assembler to produce appropriately -formatted input data for above mentioned "safe exception handler +formatted input data for above mentioned "safe exception handler table." Its typical use would be: \c section .text @@ -4954,14 +5077,14 @@ table." Its typical use would be: \c ret \c text: db 'OK to rethrow, CANCEL to generate core dump',0 \c caption:db 'SEGV',0 -\c +\c \c section .drectve info \c db '/defaultlib:user32.lib /defaultlib:msvcrt.lib ' As you might imagine, it's perfectly possible to produce .exe binary with "safe exception handler table" and yet engage unregistered exception handler. Indeed, handler is engaged by simply manipulating -\c{[fs:0]} location at run-time, something linker has no power over, +\c{[fs:0]} location at run-time, something linker has no power over, run-time that is. It should be explicitly mentioned that such failure to register handler's entry point with \c{safeseh} directive has undesired side effect at run-time. If exception is raised and @@ -4981,7 +5104,7 @@ later can still be linked by earlier versions or non-Microsoft linkers. \H{win64fmt} \i\c{win64}: Microsoft Win64 Object Files -The \c{win64} output format generates Microsoft Win64 object files, +The \c{win64} output format generates Microsoft Win64 object files, which is nearly 100% identical to the \c{win32} object format (\k{win32fmt}) with the exception that it is meant to target 64-bit code and the x86-64 platform altogether. This object file is used exactly the same as the \c{win32} @@ -5139,7 +5262,7 @@ leaf function: \c main_end: \c text: db 'OK to rethrow, CANCEL to generate core dump',0 \c caption:db 'SEGV',0 -\c +\c \c section .pdata rdata align=4 \c dd main wrt ..imagebase \c dd main_end wrt ..imagebase @@ -5219,7 +5342,7 @@ custom language-specific exception handler would look like this: \c context->R15 = rsp[-1]; \c } \c context->Rsp = (ULONG64)rsp; -\c +\c \c memcpy (disp->ContextRecord,context,sizeof(CONTEXT)); \c RtlVirtualUnwind(UNW_FLAG_NHANDLER,disp->ImageBase, \c dips->ControlPc,disp->FunctionEntry,disp->ContextRecord, @@ -5271,7 +5394,7 @@ Like the \c{obj} format, \c{elf} allows you to specify additional information on the \c{SECTION} directive line, to control the type and properties of sections you declare. Section types and properties are generated automatically by NASM for the \i{standard section -names} \i\c{.text}, \i\c{.data} and \i\c{.bss}, but may still be +names}, but may still be overridden by these qualifiers. The available qualifiers are: @@ -5297,17 +5420,30 @@ contents given, such as a BSS section. \I{section alignment, in elf}\I{alignment, in elf sections}alignment requirements of the section. +\b \i\c{tls} defines the section to be one which contains +thread local variables. + The defaults assumed by NASM if you do not specify the above qualifiers are: -\c section .text progbits alloc exec nowrite align=16 -\c section .rodata progbits alloc noexec nowrite align=4 -\c section .data progbits alloc noexec write align=4 -\c section .bss nobits alloc noexec write align=4 -\c section other progbits alloc noexec nowrite align=1 +\I\c{.text} \I\c{.rodata} \I\c{.lrodata} \I\c{.data} \I\c{.ldata} +\I\c{.bss} \I\c{.lbss} \I\c{.tdata} \I\c{.tbss} \I\c\{.comment} + +\c section .text progbits alloc exec nowrite align=16 +\c section .rodata progbits alloc noexec nowrite align=4 +\c section .lrodata progbits alloc noexec nowrite align=4 +\c section .data progbits alloc noexec write align=4 +\c section .ldata progbits alloc noexec write align=4 +\c section .bss nobits alloc noexec write align=4 +\c section .lbss nobits alloc noexec write align=4 +\c section .tdata progbits alloc noexec write align=4 tls +\c section .tbss nobits alloc noexec write align=4 tls +\c section .comment progbits noalloc noexec nowrite align=1 +\c section other progbits alloc noexec nowrite align=1 -(Any section name other than \c{.text}, \c{.rodata}, \c{.data} and -\c{.bss} is treated by default like \c{other} in the above code.) +(Any section name other than those in the above table + is treated by default like \c{other} in the above table. + Please note that section names are case sensitive.) \S{elfwrt} \i{Position-Independent Code}\I{PIC}: \c{elf} Special @@ -5316,7 +5452,7 @@ Symbols and \i\c{WRT} The \c{ELF} specification contains enough features to allow position-independent code (PIC) to be written, which makes \i{ELF shared libraries} very flexible. However, it also means NASM has to -be able to generate a variety of strange relocation types in ELF +be able to generate a variety of ELF specific relocation types in ELF object files, if it is to be an assembler which can write PIC. Since \c{ELF} does not support segment-base references, the \c{WRT} @@ -5367,6 +5503,28 @@ peculiarity of the dynamic linker. A fuller explanation of how to use these relocation types to write shared libraries entirely in NASM is given in \k{picdll}. +\S{elftls} \i{Thread Local Storage}\I{TLS}: \c{elf} Special +Symbols and \i\c{WRT} + +\b In ELF32 mode, referring to an external or global symbol using +\c{wrt ..tlsie} \I\c{..tlsie} +causes the linker to build an entry \e{in} the GOT containing the +offset of the symbol within the TLS block, so you can access the value +of the symbol with code such as: + +\c mov eax,[tid wrt ..tlsie] +\c mov [gs:eax],ebx + + +\b In ELF64 mode, referring to an external or global symbol using +\c{wrt ..gottpoff} \I\c{..gottpoff} +causes the linker to build an entry \e{in} the GOT containing the +offset of the symbol within the TLS block, so you can access the value +of the symbol with code such as: + +\c mov rax,[rel tid wrt ..gottpoff] +\c mov rcx,[fs:rax] + \S{elfglob} \c{elf} Extensions to the \c{GLOBAL} Directive\I{GLOBAL, elf extensions to}\I{GLOBAL, aoutb extensions to} @@ -5502,10 +5660,10 @@ NASM supports this format, just in case it is useful, as \c{as86}. \c{as86} provides a default output file-name extension of \c{.o}. \c{as86} is a very simple object format (from the NASM user's point -of view). It supports no special directives, no special symbols, no -use of \c{SEG} or \c{WRT}, and no extensions to any standard -directives. It supports only the three \i{standard section names} -\i\c{.text}, \i\c{.data} and \i\c{.bss}. +of view). It supports no special directives, no use of \c{SEG} or \c{WRT}, +and no extensions to any standard directives. It supports only the three +\i{standard section names} \i\c{.text}, \i\c{.data} and \i\c{.bss}. The +only special symbol supported is \c{..start}. \H{rdffmt} \I{RDOFF}\i\c{rdf}: \i{Relocatable Dynamic Object File @@ -5585,7 +5743,7 @@ or \i\c{object} to the directive: \S{rdfimpt} \c{rdf} Extensions to the \c{EXTERN} directive\I{EXTERN, rdf extensions to} -By default the \c{EXTERN} directive in \c{RDOFF} declares a "pure external" +By default the \c{EXTERN} directive in \c{RDOFF} declares a "pure external" symbol (i.e. the static linker will complain if such a symbol is not resolved). To declare an "imported" symbol, which must be resolved later during a dynamic linking phase, \c{RDOFF} offers an additional \c{import} modifier. As in @@ -5605,7 +5763,7 @@ a hint as to where to find requested symbols. The \c{dbg} output format is not built into NASM in the default configuration. If you are building your own NASM executable from the -sources, you can define \i\c{OF_DBG} in \c{outform.h} or on the +sources, you can define \i\c{OF_DBG} in \c{output/outform.h} or on the compiler command line, and obtain the \c{dbg} output format. The \c{dbg} format does not output an object file as such; instead, @@ -7113,7 +7271,7 @@ string instructions (\c{LODSx}, \c{STOSx} and so on) or the parameters, might seem to have no easy way to make them perform 32-bit addressing when assembled in a 16-bit segment. -This is the purpose of NASM's \i\c{a16} and \i\c{a32} prefixes. If +This is the purpose of NASM's \i\c{a16}, \i\c{a32} and \i\c{a64} prefixes. If you are coding \c{LODSB} in a 16-bit segment but it is supposed to be accessing a string in a 32-bit segment, you should load the desired address into \c{ESI} and then code @@ -7125,7 +7283,7 @@ The prefix forces the addressing size to 32 bits, meaning that a string in a 16-bit segment when coding in a 32-bit one, the corresponding \c{a16} prefix can be used. -The \c{a16} and \c{a32} prefixes can be applied to any instruction +The \c{a16}, \c{a32} and \c{a64} prefixes can be applied to any instruction in NASM's instruction table, but most of them can generate all the useful forms without them. The prefixes are necessary only for instructions with implicit addressing: @@ -7137,8 +7295,8 @@ instructions with implicit addressing: \c{OUTSx}, and \c{XLATB}. Also, the various push and pop instructions (\c{PUSHA} and \c{POPF} as well as -the more usual \c{PUSH} and \c{POP}) can accept \c{a16} or \c{a32} -prefixes to force a particular one of \c{SP} or \c{ESP} to be used +the more usual \c{PUSH} and \c{POP}) can accept \c{a16}, \c{a32} or \c{a64} +prefixes to force a particular one of \c{SP}, \c{ESP} or \c{RSP} to be used as a stack pointer, in case the stack segment in use is a different size from the code segment. @@ -7277,7 +7435,7 @@ Integer return values are passed in \c{RAX} and \c{RDX}, in that order. Floating point is done using SSE registers, except for \c{long double}. Floating-point arguments are passed in \c{XMM0} to \c{XMM7}; return is \c{XMM0} and \c{XMM1}. \c{long double} are passed on the -stack, and returned in \c{ST(0)} and \c{ST(1)}. +stack, and returned in \c{ST0} and \c{ST1}. All SSE and x87 registers are destroyed by function calls. @@ -7337,7 +7495,7 @@ instruction which leaves room for a 32-bit offset. You need to code \I\c{BYTE}\c{ADD ESP,BYTE 8} if you want the space-efficient form of the instruction. This isn't a bug, it's user error: if you prefer to have NASM produce the more efficient code automatically enable -optimization with the \c{-On} option (see \k{opt-On}). +optimization with the \c{-O} option (see \k{opt-O}). \S{jmprange} My Jumps are Out of Range\I{out of range, jumps} @@ -7358,7 +7516,7 @@ over a \c{JMP NEAR}; this is a sensible solution for processors below a 386, but hardly efficient on processors which have good branch prediction \e{and} could have used \c{JNE NEAR} instead. So, once again, it's up to the user, not the assembler, to decide what -instructions should be generated. See \k{opt-On}. +instructions should be generated. See \k{opt-O}. \S{proborg} \i\c{ORG} Doesn't Work diff --git a/doc/rdsrc.pl b/doc/rdsrc.pl index c4069b1e..de3a862f 100644 --- a/doc/rdsrc.pl +++ b/doc/rdsrc.pl @@ -1,4 +1,37 @@ #!/usr/bin/perl +## -------------------------------------------------------------------------- +## +## Copyright 1996-2009 The NASM Authors - All Rights Reserved +## See the file AUTHORS included with the NASM distribution for +## the specific copyright holders. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following +## conditions are met: +## +## * Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above +## copyright notice, this list of conditions and the following +## disclaimer in the documentation and/or other materials provided +## with the distribution. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## -------------------------------------------------------------------------- + # Read the source-form of the NASM manual and generate the various # output forms. @@ -104,6 +137,7 @@ $pname = "para000000"; @pnames = @pflags = (); $para = undef; while (defined($_ = <STDIN>)) { + $_ = &untabify($_); &check_include($_); } &got_para($para); @@ -151,6 +185,26 @@ if ($out_format eq 'txt') { die "$0: unknown output format: $out_format\n"; } +sub untabify($) { + my($s) = @_; + my $o = ''; + my($c, $i, $p); + + $p = 0; + for ($i = 0; $i < length($s); $i++) { + $c = substr($s, $i, 1); + if ($c eq "\t") { + do { + $o .= ' '; + $p++; + } while ($p & 7); + } else { + $o .= $c; + $p++; + } + } + return $o; +} sub check_include { local $_ = shift; if (/\\& (\S+)/) { @@ -1,11 +1,38 @@ -/* eval.c expression evaluator for the Netwide Assembler +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: * - * initial version 27/iii/95 by Simon Tatham + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * eval.c expression evaluator for the Netwide Assembler */ #include "compiler.h" @@ -1,9 +1,38 @@ -/* eval.h header file for eval.c +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * eval.h header file for eval.c */ #ifndef NASM_EVAL_H @@ -1,3 +1,36 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + /* * exprlib.c * @@ -1,11 +1,38 @@ -/* float.c floating-point constant support for the Netwide Assembler +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: * - * initial version 13/ix/96 by Simon Tatham + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * float.c floating-point constant support for the Netwide Assembler */ #include "compiler.h" @@ -1,10 +1,39 @@ -/* float.h header file for the floating-point constant module of - * the Netwide Assembler +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * ----------------------------------------------------------------------- */ + +/* + * float.h header file for the floating-point constant module of + * the Netwide Assembler */ #ifndef NASM_FLOAT_H @@ -1,3 +1,36 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + /* * hashtbl.c * @@ -156,8 +189,11 @@ void *hash_iterate(const struct hash_table *head, struct hash_tbl_node *np = *iterator; struct hash_tbl_node *ep = head->table + head->size; - if (!np) + if (!np) { np = head->table; + if (!np) + return NULL; /* Uninitialized table */ + } while (np < ep) { if (np->key) { @@ -1,3 +1,36 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + /* * hashtbl.h * @@ -1,9 +1,38 @@ -; insns.dat table of instructions for the Netwide Assembler +;; -------------------------------------------------------------------------- +;; +;; Copyright 1996-2009 The NASM Authors - All Rights Reserved +;; See the file AUTHORS included with the NASM distribution for +;; the specific copyright holders. +;; +;; Redistribution and use in source and binary forms, with or without +;; modification, are permitted provided that the following +;; conditions are met: +;; +;; * Redistributions of source code must retain the above copyright +;; notice, this list of conditions and the following disclaimer. +;; * Redistributions in binary form must reproduce the above +;; copyright notice, this list of conditions and the following +;; disclaimer in the documentation and/or other materials provided +;; with the distribution. +;; +;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +;; CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +;; INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +;; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +;; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;; NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +;; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +;; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +;; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +;; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;; +;; -------------------------------------------------------------------------- + ; -; The Netwide Assembler is copyright (C) 1996 Simon Tatham and -; Julian Hall. All rights reserved. The software is -; redistributable under the license given in the file "LICENSE" -; distributed in the NASM archive. +; insns.dat table of instructions for the Netwide Assembler ; ; Format of file: All four fields must be present on every functional ; line. Hence `void' for no-operand instructions, and `\0' for such @@ -16,7 +45,7 @@ ; ; Comments with a pound sign after the semicolon generate section ; subheaders in the NASM documentation. - +; ;# Special instructions... DB ignore ignore ignore @@ -57,16 +86,16 @@ ADC reg32,mem \321\1\x13\110 386,SM ADC reg32,reg32 \321\1\x13\110 386 ADC reg64,mem \324\1\x13\110 X64,SM ADC reg64,reg64 \324\1\x13\110 X64 -ADC rm16,imm8 \320\1\x83\202\15 8086 -ADC rm32,imm8 \321\1\x83\202\15 386 -ADC rm64,imm8 \324\1\x83\202\15 X64 +ADC rm16,imm8 \320\1\x83\202\275 8086 +ADC rm32,imm8 \321\1\x83\202\275 386 +ADC rm64,imm8 \324\1\x83\202\275 X64 ADC reg_al,imm \1\x14\21 8086,SM -ADC reg_ax,sbyte16 \320\1\x83\202\15 8086,SM,ND +ADC reg_ax,sbyte16 \320\1\x83\202\275 8086,SM ADC reg_ax,imm \320\1\x15\31 8086,SM -ADC reg_eax,sbyte32 \321\1\x83\202\15 386,SM,ND +ADC reg_eax,sbyte32 \321\1\x83\202\275 386,SM ADC reg_eax,imm \321\1\x15\41 386,SM -ADC reg_rax,sbyte64 \324\1\x83\202\15 X64,SM,ND -ADC reg_rax,imm \324\1\x15\41 X64,SM +ADC reg_rax,sbyte64 \324\1\x83\202\275 X64,SM +ADC reg_rax,imm \324\1\x15\255 X64,SM ADC rm8,imm \1\x80\202\21 8086,SM ADC rm16,imm \320\145\x81\202\141 8086,SM ADC rm32,imm \321\155\x81\202\151 386,SM @@ -90,16 +119,16 @@ ADD reg32,mem \321\1\x03\110 386,SM ADD reg32,reg32 \321\1\x03\110 386 ADD reg64,mem \324\1\x03\110 X64,SM ADD reg64,reg64 \324\1\x03\110 X64 -ADD rm16,imm8 \320\1\x83\200\15 8086 -ADD rm32,imm8 \321\1\x83\200\15 386 -ADD rm64,imm8 \324\1\x83\200\15 X64 +ADD rm16,imm8 \320\1\x83\200\275 8086 +ADD rm32,imm8 \321\1\x83\200\275 386 +ADD rm64,imm8 \324\1\x83\200\275 X64 ADD reg_al,imm \1\x04\21 8086,SM -ADD reg_ax,sbyte16 \320\1\x83\200\15 8086,SM,ND +ADD reg_ax,sbyte16 \320\1\x83\200\275 8086,SM ADD reg_ax,imm \320\1\x05\31 8086,SM -ADD reg_eax,sbyte32 \321\1\x83\200\15 386,SM,ND +ADD reg_eax,sbyte32 \321\1\x83\200\275 386,SM ADD reg_eax,imm \321\1\x05\41 386,SM -ADD reg_rax,sbyte64 \324\1\x83\200\15 X64,SM,ND -ADD reg_rax,imm \324\1\x05\41 X64,SM +ADD reg_rax,sbyte64 \324\1\x83\200\275 X64,SM +ADD reg_rax,imm \324\1\x05\255 X64,SM ADD rm8,imm \1\x80\200\21 8086,SM ADD rm16,imm \320\145\x81\200\141 8086,SM ADD rm32,imm \321\155\x81\200\151 386,SM @@ -123,16 +152,16 @@ AND reg32,mem \321\1\x23\110 386,SM AND reg32,reg32 \321\1\x23\110 386 AND reg64,mem \324\1\x23\110 X64,SM AND reg64,reg64 \324\1\x23\110 X64 -AND rm16,imm8 \320\1\x83\204\15 8086 -AND rm32,imm8 \321\1\x83\204\15 386 -AND rm64,imm8 \324\1\x83\204\15 X64 +AND rm16,imm8 \320\1\x83\204\275 8086 +AND rm32,imm8 \321\1\x83\204\275 386 +AND rm64,imm8 \324\1\x83\204\275 X64 AND reg_al,imm \1\x24\21 8086,SM -AND reg_ax,sbyte16 \320\1\x83\204\15 8086,SM,ND +AND reg_ax,sbyte16 \320\1\x83\204\275 8086,SM AND reg_ax,imm \320\1\x25\31 8086,SM -AND reg_eax,sbyte32 \321\1\x83\204\15 386,SM,ND +AND reg_eax,sbyte32 \321\1\x83\204\275 386,SM AND reg_eax,imm \321\1\x25\41 386,SM -AND reg_rax,sbyte64 \324\1\x83\204\15 X64,SM,ND -AND reg_rax,imm \324\1\x25\41 X64,SM +AND reg_rax,sbyte64 \324\1\x83\204\275 X64,SM +AND reg_rax,imm \324\1\x25\255 X64,SM AND rm8,imm \1\x80\204\21 8086,SM AND rm16,imm \320\145\x81\204\141 8086,SM AND rm32,imm \321\155\x81\204\151 386,SM @@ -251,16 +280,16 @@ CMP reg32,mem \321\1\x3B\110 386,SM CMP reg32,reg32 \321\1\x3B\110 386 CMP reg64,mem \324\1\x3B\110 X64,SM CMP reg64,reg64 \324\1\x3B\110 X64 -CMP rm16,imm8 \320\1\x83\207\15 8086 -CMP rm32,imm8 \321\1\x83\207\15 386 -CMP rm64,imm8 \324\1\x83\207\15 X64 +CMP rm16,imm8 \320\1\x83\207\275 8086 +CMP rm32,imm8 \321\1\x83\207\275 386 +CMP rm64,imm8 \324\1\x83\207\275 X64 CMP reg_al,imm \1\x3C\21 8086,SM -CMP reg_ax,sbyte16 \320\1\x83\207\15 8086,SM,ND +CMP reg_ax,sbyte16 \320\1\x83\207\275 8086,SM CMP reg_ax,imm \320\1\x3D\31 8086,SM -CMP reg_eax,sbyte32 \321\1\x83\207\15 386,SM,ND +CMP reg_eax,sbyte32 \321\1\x83\207\275 386,SM CMP reg_eax,imm \321\1\x3D\41 386,SM -CMP reg_rax,sbyte64 \324\1\x83\207\15 X64,SM,ND -CMP reg_rax,imm \324\1\x3D\41 X64,SM +CMP reg_rax,sbyte64 \324\1\x83\207\275 X64,SM +CMP reg_rax,imm \324\1\x3D\255 X64,SM CMP rm8,imm \1\x80\207\21 8086,SM CMP rm16,imm \320\145\x81\207\141 8086,SM CMP rm32,imm \321\155\x81\207\151 386,SM @@ -328,7 +357,7 @@ FBLD mem \1\xDF\204 8086,FPU FBSTP mem80 \1\xDF\206 8086,FPU FBSTP mem \1\xDF\206 8086,FPU FCHS void \2\xD9\xE0 8086,FPU -FCLEX void \3\x9B\xDB\xE2 8086,FPU +FCLEX void \341\2\xDB\xE2 8086,FPU FCMOVB fpureg \1\xDA\10\xC0 P6,FPU FCMOVB fpu0,fpureg \1\xDA\11\xC0 P6,FPU FCMOVB void \2\xDA\xC1 P6,FPU,ND @@ -372,7 +401,7 @@ FCOMP void \2\xD8\xD9 8086,FPU,ND FCOMPP void \2\xDE\xD9 8086,FPU FCOS void \2\xD9\xFF 386,FPU FDECSTP void \2\xD9\xF6 8086,FPU -FDISI void \3\x9B\xDB\xE1 8086,FPU +FDISI void \341\2\xDB\xE1 8086,FPU FDIV mem32 \1\xD8\206 8086,FPU FDIV mem64 \1\xDC\206 8086,FPU FDIV fpureg|to \1\xDC\10\xF8 8086,FPU @@ -394,7 +423,7 @@ FDIVRP fpureg \1\xDE\10\xF0 8086,FPU FDIVRP fpureg,fpu0 \1\xDE\10\xF0 8086,FPU FDIVRP void \2\xDE\xF1 8086,FPU,ND FEMMS void \2\x0F\x0E PENT,3DNOW -FENI void \3\x9B\xDB\xE0 8086,FPU +FENI void \341\2\xDB\xE0 8086,FPU FFREE fpureg \1\xDD\10\xC0 8086,FPU FFREE void \2\xDD\xC1 8086,FPU FFREEP fpureg \1\xDF\10\xC0 286,FPU,UNDOC @@ -415,7 +444,7 @@ FILD mem64 \1\xDF\205 8086,FPU FIMUL mem32 \1\xDA\201 8086,FPU FIMUL mem16 \1\xDE\201 8086,FPU FINCSTP void \2\xD9\xF7 8086,FPU -FINIT void \3\x9B\xDB\xE3 8086,FPU +FINIT void \341\2\xDB\xE3 8086,FPU FIST mem32 \1\xDB\202 8086,FPU FIST mem16 \1\xDF\202 8086,FPU FISTP mem32 \1\xDB\203 8086,FPU @@ -468,7 +497,7 @@ FPREM1 void \2\xD9\xF5 386,FPU FPTAN void \2\xD9\xF2 8086,FPU FRNDINT void \2\xD9\xFC 8086,FPU FRSTOR mem \1\xDD\204 8086,FPU -FSAVE mem \2\x9B\xDD\206 8086,FPU +FSAVE mem \341\1\xDD\206 8086,FPU FSCALE void \2\xD9\xFD 8086,FPU FSETPM void \2\xDB\xE4 286,FPU FSIN void \2\xD9\xFE 386,FPU @@ -478,15 +507,15 @@ FST mem32 \1\xD9\202 8086,FPU FST mem64 \1\xDD\202 8086,FPU FST fpureg \1\xDD\10\xD0 8086,FPU FST void \2\xDD\xD1 8086,FPU,ND -FSTCW mem \2\x9B\xD9\207 8086,FPU,SW -FSTENV mem \2\x9B\xD9\206 8086,FPU +FSTCW mem \341\1\xD9\207 8086,FPU,SW +FSTENV mem \341\1\xD9\206 8086,FPU FSTP mem32 \1\xD9\203 8086,FPU FSTP mem64 \1\xDD\203 8086,FPU FSTP mem80 \1\xDB\207 8086,FPU FSTP fpureg \1\xDD\10\xD8 8086,FPU FSTP void \2\xDD\xD9 8086,FPU,ND -FSTSW mem \2\x9B\xDD\207 8086,FPU,SW -FSTSW reg_ax \3\x9B\xDF\xE0 286,FPU +FSTSW mem \341\1\xDD\207 8086,FPU,SW +FSTSW reg_ax \341\2\xDF\xE0 286,FPU FSUB mem32 \1\xD8\204 8086,FPU FSUB mem64 \1\xDC\204 8086,FPU FSUB fpureg|to \1\xDC\10\xE8 8086,FPU @@ -581,8 +610,9 @@ IMUL reg32,imm8 \321\1\x6B\100\15 386 IMUL reg32,sbyte32 \321\1\x6B\100\15 386,SM,ND IMUL reg32,imm32 \321\1\x69\100\41 386 IMUL reg32,imm \321\155\x69\100\151 386,SM,ND +IMUL reg64,imm8 \324\1\x6B\100\15 X64 IMUL reg64,sbyte64 \324\1\x6B\100\15 X64,SM,ND -IMUL reg64,imm32 \324\1\x69\100\41 X64 +IMUL reg64,imm32 \324\1\x69\100\255 X64 IMUL reg64,imm \324\155\x69\100\251 X64,SM,ND IN reg_al,imm \1\xE4\25 8086,SB IN reg_ax,imm \320\1\xE5\25 8086,SB @@ -618,6 +648,7 @@ IRETQ void \324\1\xCF X64 IRETW void \320\1\xCF 8086 JCXZ imm \310\1\xE3\50 8086,NOLONG JECXZ imm \311\1\xE3\50 386 +JRCXZ imm \313\1\xE3\50 X64 JMP imm|short \1\xEB\50 8086 JMP imm \371\1\xEB\50 8086,ND JMP imm \322\1\xE9\64 8086 @@ -645,7 +676,7 @@ JMP mem32|near \321\1\xFF\204 386,NOLONG JMP mem64|near \323\1\xFF\204 X64 JMP reg16 \320\1\xFF\204 8086 JMP reg32 \321\1\xFF\204 386,NOLONG -JMP reg64 \324\1\xFF\204 X64 +JMP reg64 \323\1\xFF\204 X64 JMP mem \322\1\xFF\204 8086 JMP mem16 \320\1\xFF\204 8086 JMP mem32 \321\1\xFF\204 386,NOLONG @@ -655,7 +686,6 @@ JMPE imm16 \320\2\x0F\xB8\64 IA64 JMPE imm32 \321\2\x0F\xB8\64 IA64 JMPE rm16 \320\2\x0F\x00\206 IA64 JMPE rm32 \321\2\x0F\x00\206 IA64 -JRCXZ imm \1\xE3\50 X64 LAHF void \1\x9F 8086 LAR reg16,mem \320\2\x0F\x02\110 286,PROT,SW LAR reg16,reg16 \320\2\x0F\x02\110 286,PROT @@ -780,11 +810,11 @@ MOV reg8,imm \10\xB0\21 8086,SM MOV reg16,imm \320\10\xB8\31 8086,SM MOV reg32,imm \321\10\xB8\41 386,SM MOV reg64,imm \324\10\xB8\55 X64,SM -MOV reg64,imm32 \324\1\xC7\200\41 X64 +MOV reg64,imm32 \324\1\xC7\200\255 X64 MOV rm8,imm \1\xC6\200\21 8086,SM MOV rm16,imm \320\1\xC7\200\31 8086,SM MOV rm32,imm \321\1\xC7\200\41 386,SM -MOV rm64,imm \324\1\xC7\200\41 X64,SM +MOV rm64,imm \324\1\xC7\200\255 X64,SM MOV mem,imm8 \1\xC6\200\21 8086,SM MOV mem,imm16 \320\1\xC7\200\31 8086,SM MOV mem,imm32 \321\1\xC7\200\41 386,SM @@ -852,16 +882,16 @@ OR reg32,mem \321\1\x0B\110 386,SM OR reg32,reg32 \321\1\x0B\110 386 OR reg64,mem \324\1\x0B\110 X64,SM OR reg64,reg64 \324\1\x0B\110 X64 -OR rm16,imm8 \320\1\x83\201\15 8086 -OR rm32,imm8 \321\1\x83\201\15 386 -OR rm64,imm8 \324\1\x83\201\15 X64 +OR rm16,imm8 \320\1\x83\201\275 8086 +OR rm32,imm8 \321\1\x83\201\275 386 +OR rm64,imm8 \324\1\x83\201\275 X64 OR reg_al,imm \1\x0C\21 8086,SM -OR reg_ax,sbyte16 \320\1\x83\201\15 8086,SM,ND +OR reg_ax,sbyte16 \320\1\x83\201\275 8086,SM OR reg_ax,imm \320\1\x0D\31 8086,SM -OR reg_eax,sbyte32 \321\1\x83\201\15 386,SM,ND +OR reg_eax,sbyte32 \321\1\x83\201\275 386,SM OR reg_eax,imm \321\1\x0D\41 386,SM -OR reg_rax,sbyte64 \324\1\x83\201\15 X64,SM,ND -OR reg_rax,imm \324\1\x0D\41 X64,SM +OR reg_rax,sbyte64 \324\1\x83\201\275 X64,SM +OR reg_rax,imm \324\1\x0D\255 X64,SM OR rm8,imm \1\x80\201\21 8086,SM OR rm16,imm \320\145\x81\201\141 8086,SM OR rm32,imm \321\155\x81\201\151 386,SM @@ -937,8 +967,8 @@ POP rm16 \320\1\x8F\200 8086 POP rm32 \321\1\x8F\200 386,NOLONG POP rm64 \323\1\x8F\200 X64 POP reg_cs \1\x0F 8086,UNDOC,ND -POP reg_dess \4 8086,NOLONG -POP reg_fsgs \1\x0F\5 386 +POP reg_dess \345 8086,NOLONG +POP reg_fsgs \1\x0F\347 386 POPA void \322\1\x61 186,NOLONG POPAD void \321\1\x61 386,NOLONG POPAW void \320\1\x61 186,NOLONG @@ -985,10 +1015,10 @@ PUSH reg64 \323\10\x50 X64 PUSH rm16 \320\1\xFF\206 8086 PUSH rm32 \321\1\xFF\206 386,NOLONG PUSH rm64 \323\1\xFF\206 X64 -PUSH reg_cs \6 8086,NOLONG -PUSH reg_dess \6 8086,NOLONG -PUSH reg_fsgs \1\x0F\7 386 -PUSH imm8 \1\x6A\14 186 +PUSH reg_cs \344 8086,NOLONG +PUSH reg_dess \344 8086,NOLONG +PUSH reg_fsgs \1\x0F\346 386 +PUSH imm8 \1\x6A\274 186 PUSH imm16 \320\144\x68\140 186,AR0,SZ PUSH imm32 \321\154\x68\150 386,NOLONG,AR0,SZ PUSH imm32 \321\154\x68\150 386,NOLONG,SD @@ -1107,16 +1137,16 @@ SBB reg32,mem \321\1\x1B\110 386,SM SBB reg32,reg32 \321\1\x1B\110 386 SBB reg64,mem \324\1\x1B\110 X64,SM SBB reg64,reg64 \324\1\x1B\110 X64 -SBB rm16,imm8 \320\1\x83\203\15 8086 -SBB rm32,imm8 \321\1\x83\203\15 386 -SBB rm64,imm8 \324\1\x83\203\15 X64 +SBB rm16,imm8 \320\1\x83\203\275 8086 +SBB rm32,imm8 \321\1\x83\203\275 386 +SBB rm64,imm8 \324\1\x83\203\275 X64 SBB reg_al,imm \1\x1C\21 8086,SM -SBB reg_ax,sbyte16 \320\1\x83\203\15 8086,SM,ND +SBB reg_ax,sbyte16 \320\1\x83\203\275 8086,SM SBB reg_ax,imm \320\1\x1D\31 8086,SM -SBB reg_eax,sbyte32 \321\1\x83\203\15 386,SM,ND +SBB reg_eax,sbyte32 \321\1\x83\203\275 386,SM SBB reg_eax,imm \321\1\x1D\41 386,SM -SBB reg_rax,sbyte64 \324\1\x83\203\15 X64,SM,ND -SBB reg_rax,imm \324\1\x1D\41 X64,SM +SBB reg_rax,sbyte64 \324\1\x83\203\275 X64,SM +SBB reg_rax,imm \324\1\x1D\255 X64,SM SBB rm8,imm \1\x80\203\21 8086,SM SBB rm16,imm \320\145\x81\203\141 8086,SM SBB rm32,imm \321\155\x81\203\151 386,SM @@ -1223,16 +1253,16 @@ SUB reg32,mem \321\1\x2B\110 386,SM SUB reg32,reg32 \321\1\x2B\110 386 SUB reg64,mem \324\1\x2B\110 X64,SM SUB reg64,reg64 \324\1\x2B\110 X64 -SUB rm16,imm8 \320\1\x83\205\15 8086 -SUB rm32,imm8 \321\1\x83\205\15 386 -SUB rm64,imm8 \324\1\x83\205\15 X64 +SUB rm16,imm8 \320\1\x83\205\275 8086 +SUB rm32,imm8 \321\1\x83\205\275 386 +SUB rm64,imm8 \324\1\x83\205\275 X64 SUB reg_al,imm \1\x2C\21 8086,SM -SUB reg_ax,sbyte16 \320\1\x83\205\15 8086,SM,ND +SUB reg_ax,sbyte16 \320\1\x83\205\275 8086,SM SUB reg_ax,imm \320\1\x2D\31 8086,SM -SUB reg_eax,sbyte32 \321\1\x83\205\15 386,SM,ND +SUB reg_eax,sbyte32 \321\1\x83\205\275 386,SM SUB reg_eax,imm \321\1\x2D\41 386,SM -SUB reg_rax,sbyte64 \324\1\x83\205\15 X64,SM,ND -SUB reg_rax,imm \324\1\x2D\41 X64,SM +SUB reg_rax,sbyte64 \324\1\x83\205\275 X64,SM +SUB reg_rax,imm \324\1\x2D\255 X64,SM SUB rm8,imm \1\x80\205\21 8086,SM SUB rm16,imm \320\145\x81\205\141 8086,SM SUB rm32,imm \321\155\x81\205\151 386,SM @@ -1263,11 +1293,11 @@ TEST reg64,mem \324\1\x85\110 X64,SM TEST reg_al,imm \1\xA8\21 8086,SM TEST reg_ax,imm \320\1\xA9\31 8086,SM TEST reg_eax,imm \321\1\xA9\41 386,SM -TEST reg_rax,imm \324\1\xA9\41 X64,SM +TEST reg_rax,imm \324\1\xA9\255 X64,SM TEST rm8,imm \1\xF6\200\21 8086,SM TEST rm16,imm \320\1\xF7\200\31 8086,SM TEST rm32,imm \321\1\xF7\200\41 386,SM -TEST rm64,imm \324\1\xF7\200\41 X64,SM +TEST rm64,imm \324\1\xF7\200\255 X64,SM TEST mem,imm8 \1\xF6\200\21 8086,SM TEST mem,imm16 \320\1\xF7\200\31 8086,SM TEST mem,imm32 \321\1\xF7\200\41 386,SM @@ -1294,8 +1324,7 @@ VERR reg16 \2\x0F\x00\204 286,PROT VERW mem \2\x0F\x00\205 286,PROT VERW mem16 \2\x0F\x00\205 286,PROT VERW reg16 \2\x0F\x00\205 286,PROT -WAIT void \1\x9B 8086 -FWAIT void \1\x9B 8086 +FWAIT void \341 8086 WBINVD void \2\x0F\x09 486,PRIV WRSHR rm32 \321\2\x0F\x37\200 P6,CYRIX,SMM WRMSR void \2\x0F\x30 PENT,PRIV @@ -1354,16 +1383,16 @@ XOR reg32,mem \321\1\x33\110 386,SM XOR reg32,reg32 \321\1\x33\110 386 XOR reg64,mem \324\1\x33\110 X64,SM XOR reg64,reg64 \324\1\x33\110 X64 -XOR rm16,imm8 \320\1\x83\206\15 8086 -XOR rm32,imm8 \321\1\x83\206\15 386 -XOR rm64,imm8 \324\1\x83\206\15 X64 +XOR rm16,imm8 \320\1\x83\206\275 8086 +XOR rm32,imm8 \321\1\x83\206\275 386 +XOR rm64,imm8 \324\1\x83\206\275 X64 XOR reg_al,imm \1\x34\21 8086,SM -XOR reg_ax,sbyte16 \320\1\x83\206\15 8086,SM,ND +XOR reg_ax,sbyte16 \320\1\x83\206\275 8086,SM XOR reg_ax,imm \320\1\x35\31 8086,SM -XOR reg_eax,sbyte32 \321\1\x83\206\15 386,SM,ND +XOR reg_eax,sbyte32 \321\1\x83\206\275 386,SM XOR reg_eax,imm \321\1\x35\41 386,SM -XOR reg_rax,sbyte64 \324\1\x83\206\15 X64,SM,ND -XOR reg_rax,imm \324\1\x35\41 X64,SM +XOR reg_rax,sbyte64 \324\1\x83\206\275 X64,SM +XOR reg_rax,imm \324\1\x35\255 X64,SM XOR rm8,imm \1\x80\206\21 8086,SM XOR rm16,imm \320\145\x81\206\141 8086,SM XOR rm32,imm \321\155\x81\206\151 386,SM @@ -1416,13 +1445,18 @@ CMPPS xmmreg,xmmreg,imm \360\2\x0F\xC2\110\26 KATMAI,SSE,SB,AR2 CMPSS xmmreg,mem,imm \363\2\x0F\xC2\110\26 KATMAI,SSE,SB,AR2 CMPSS xmmreg,xmmreg,imm \363\2\x0F\xC2\110\26 KATMAI,SSE,SB,AR2 COMISS xmmreg,xmmrm \360\2\x0F\x2F\110 KATMAI,SSE -CVTPI2PS xmmreg,mmxrm \360\2\x0F\x2A\110 KATMAI,SSE,MMX -CVTPS2PI mmxreg,xmmrm \360\2\x0F\x2D\110 KATMAI,SSE,MMX -CVTSI2SS xmmreg,mem \363\2\x0F\x2A\110 KATMAI,SSE,SD,AR1 -CVTSI2SS xmmreg,reg32 \363\2\x0F\x2A\110 KATMAI,SSE -CVTSS2SI reg32,xmmrm \363\2\x0F\x2D\110 KATMAI,SSE -CVTTPS2PI mmxreg,xmmrm \360\2\x0F\x2C\110 KATMAI,SSE,MMX -CVTTSS2SI reg32,xmmrm \363\2\x0F\x2C\110 KATMAI,SSE +CVTPI2PS xmmreg,mmxrm \360\2\x0F\x2A\110 KATMAI,SSE,MMX,SQ +CVTPS2PI mmxreg,xmmrm \360\2\x0F\x2D\110 KATMAI,SSE,MMX,SQ +CVTSI2SS xmmreg,mem \363\2\x0F\x2A\110 KATMAI,SSE,SD,AR1,ND +CVTSI2SS xmmreg,rm32 \363\2\x0F\x2A\110 KATMAI,SSE,SD,AR1 +CVTSI2SS xmmreg,rm64 \324\363\2\x0F\x2A\110 X64,SSE,SQ,AR1 +CVTSS2SI reg32,xmmreg \363\2\x0F\x2D\110 KATMAI,SSE,SD,AR1 +CVTSS2SI reg32,mem \363\2\x0F\x2D\110 KATMAI,SSE,SD,AR1 +CVTSS2SI reg64,xmmreg \324\363\2\x0F\x2D\110 X64,SSE,SD,AR1 +CVTSS2SI reg64,mem \324\363\2\x0F\x2D\110 X64,SSE,SD,AR1 +CVTTPS2PI mmxreg,xmmrm \360\2\x0F\x2C\110 KATMAI,SSE,MMX,SQ +CVTTSS2SI reg32,xmmrm \363\2\x0F\x2C\110 KATMAI,SSE,SD,AR1 +CVTTSS2SI reg64,xmmrm \324\363\2\x0F\x2C\110 X64,SSE,SD,AR1 DIVPS xmmreg,xmmrm \360\2\x0F\x5E\110 KATMAI,SSE DIVSS xmmreg,xmmrm \363\2\x0F\x5E\110 KATMAI,SSE LDMXCSR mem \2\x0F\xAE\202 KATMAI,SSE,SD @@ -1499,10 +1533,9 @@ PAVGW mmxreg,mmxrm \360\323\2\x0F\xE3\110 KATMAI,MMX,SQ PEXTRW reg32,mmxreg,imm \360\2\x0F\xC5\110\26 KATMAI,MMX,SB,AR2 ; PINSRW is documented as using a reg32, but it's really using only 16 bit ; -- accept either, but be truthful in disassembly -PINSRW mmxreg,reg16,imm \360\2\x0F\xC4\110\26 KATMAI,MMX,SB,AR2 -PINSRW mmxreg,reg32,imm \360\2\x0F\xC4\110\26 KATMAI,MMX,SB,AR2,ND PINSRW mmxreg,mem,imm \360\2\x0F\xC4\110\26 KATMAI,MMX,SB,AR2 -PINSRW mmxreg,mem16,imm \360\2\x0F\xC4\110\26 KATMAI,MMX,SB,AR2,ND +PINSRW mmxreg,rm16,imm \360\2\x0F\xC4\110\26 KATMAI,MMX,SB,AR2 +PINSRW mmxreg,reg32,imm \360\2\x0F\xC4\110\26 KATMAI,MMX,SB,AR2 PMAXSW mmxreg,mmxrm \360\323\2\x0F\xEE\110 KATMAI,MMX,SQ PMAXUB mmxreg,mmxrm \360\323\2\x0F\xDE\110 KATMAI,MMX,SQ PMINSW mmxreg,mmxrm \360\323\2\x0F\xEA\110 KATMAI,MMX,SQ @@ -1538,14 +1571,14 @@ MOVD xmmreg,mem \361\2\x0F\x6E\110 WILLAMETTE,SSE2,SD MOVDQA xmmreg,xmmreg \361\2\x0F\x6F\110 WILLAMETTE,SSE2 MOVDQA mem,xmmreg \361\2\x0F\x7F\101 WILLAMETTE,SSE2,SO MOVDQA xmmreg,mem \361\2\x0F\x6F\110 WILLAMETTE,SSE2,SO -MOVDQA xmmreg,xmmreg \361\2\x0F\x7F\110 WILLAMETTE,SSE2 +MOVDQA xmmreg,xmmreg \361\2\x0F\x7F\101 WILLAMETTE,SSE2 MOVDQU xmmreg,xmmreg \363\2\x0F\x6F\110 WILLAMETTE,SSE2 MOVDQU mem,xmmreg \363\2\x0F\x7F\101 WILLAMETTE,SSE2,SO MOVDQU xmmreg,mem \363\2\x0F\x6F\110 WILLAMETTE,SSE2,SO -MOVDQU xmmreg,xmmreg \363\2\x0F\x7F\110 WILLAMETTE,SSE2 -MOVDQ2Q mmxreg,xmmreg \360\332\2\x0F\xD6\110 WILLAMETTE,SSE2 +MOVDQU xmmreg,xmmreg \363\2\x0F\x7F\101 WILLAMETTE,SSE2 +MOVDQ2Q mmxreg,xmmreg \362\2\x0F\xD6\110 WILLAMETTE,SSE2 MOVQ xmmreg,xmmreg \363\2\x0F\x7E\110 WILLAMETTE,SSE2 -MOVQ xmmreg,xmmreg \361\2\x0F\xD6\110 WILLAMETTE,SSE2 +MOVQ xmmreg,xmmreg \361\2\x0F\xD6\101 WILLAMETTE,SSE2 MOVQ mem,xmmreg \361\2\x0F\xD6\101 WILLAMETTE,SSE2,SQ MOVQ xmmreg,mem \363\2\x0F\x7E\110 WILLAMETTE,SSE2,SQ MOVQ xmmreg,rm64 \361\324\2\x0F\x6E\110 X64,SSE2 @@ -1557,7 +1590,7 @@ PACKUSWB xmmreg,xmmrm \361\2\x0F\x67\110 WILLAMETTE,SSE2,SO PADDB xmmreg,xmmrm \361\2\x0F\xFC\110 WILLAMETTE,SSE2,SO PADDW xmmreg,xmmrm \361\2\x0F\xFD\110 WILLAMETTE,SSE2,SO PADDD xmmreg,xmmrm \361\2\x0F\xFE\110 WILLAMETTE,SSE2,SO -PADDQ mmxreg,mmxrm \360\323\2\x0F\xD4\110 WILLAMETTE,SSE2,SO +PADDQ mmxreg,mmxrm \360\2\x0F\xD4\110 WILLAMETTE,MMX,SQ PADDQ xmmreg,xmmrm \361\2\x0F\xD4\110 WILLAMETTE,SSE2,SO PADDSB xmmreg,xmmrm \361\2\x0F\xEC\110 WILLAMETTE,SSE2,SO PADDSW xmmreg,xmmrm \361\2\x0F\xED\110 WILLAMETTE,SSE2,SO @@ -1577,7 +1610,7 @@ PEXTRW reg32,xmmreg,imm \361\2\x0F\xC5\110\26 WILLAMETTE,SSE2,SB,AR2 PINSRW xmmreg,reg16,imm \361\2\x0F\xC4\110\26 WILLAMETTE,SSE2,SB,AR2 PINSRW xmmreg,reg32,imm \361\2\x0F\xC4\110\26 WILLAMETTE,SSE2,SB,AR2,ND PINSRW xmmreg,mem,imm \361\2\x0F\xC4\110\26 WILLAMETTE,SSE2,SB,AR2 -PINSRW xmmreg,mem16,imm \361\2\x0F\xC4\110\26 WILLAMETTE,SSE2,SB,AR2,ND +PINSRW xmmreg,mem16,imm \361\2\x0F\xC4\110\26 WILLAMETTE,SSE2,SB,AR2 PMADDWD xmmreg,xmmrm \361\2\x0F\xF5\110 WILLAMETTE,SSE2,SO PMAXSW xmmreg,xmmrm \361\2\x0F\xEE\110 WILLAMETTE,SSE2,SO PMAXUB xmmreg,xmmrm \361\2\x0F\xDE\110 WILLAMETTE,SSE2,SO @@ -1595,8 +1628,8 @@ PSHUFD xmmreg,xmmreg,imm \361\2\x0F\x70\110\22 WILLAMETTE,SSE2,SB,AR2 PSHUFD xmmreg,mem,imm \361\2\x0F\x70\110\22 WILLAMETTE,SSE2,SM2,SB,AR2 PSHUFHW xmmreg,xmmreg,imm \363\2\x0F\x70\110\22 WILLAMETTE,SSE2,SB,AR2 PSHUFHW xmmreg,mem,imm \363\2\x0F\x70\110\22 WILLAMETTE,SSE2,SM2,SB,AR2 -PSHUFLW xmmreg,xmmreg,imm \360\332\2\x0F\x70\110\22 WILLAMETTE,SSE2,SB,AR2 -PSHUFLW xmmreg,mem,imm \360\332\2\x0F\x70\110\22 WILLAMETTE,SSE2,SM2,SB,AR2 +PSHUFLW xmmreg,xmmreg,imm \362\2\x0F\x70\110\22 WILLAMETTE,SSE2,SB,AR2 +PSHUFLW xmmreg,mem,imm \362\2\x0F\x70\110\22 WILLAMETTE,SSE2,SM2,SB,AR2 PSLLDQ xmmreg,imm \361\2\x0F\x73\207\25 WILLAMETTE,SSE2,SB,AR1 PSLLW xmmreg,xmmrm \361\2\x0F\xF1\110 WILLAMETTE,SSE2,SO PSLLW xmmreg,imm \361\2\x0F\x71\206\25 WILLAMETTE,SSE2,SB,AR1 @@ -1660,23 +1693,30 @@ CMPUNORDSD xmmreg,xmmrm \362\2\x0F\xC2\110\1\x03 WILLAMETTE,SSE2 CMPPD xmmreg,xmmrm,imm \361\2\x0F\xC2\110\26 WILLAMETTE,SSE2,SM2,SB,AR2 CMPSD xmmreg,xmmrm,imm \362\2\x0F\xC2\110\26 WILLAMETTE,SSE2,SB,AR2 COMISD xmmreg,xmmrm \361\2\x0F\x2F\110 WILLAMETTE,SSE2 -CVTDQ2PD xmmreg,xmmrm \363\2\x0F\xE6\110 WILLAMETTE,SSE2 +CVTDQ2PD xmmreg,xmmrm \363\2\x0F\xE6\110 WILLAMETTE,SSE2,SQ CVTDQ2PS xmmreg,xmmrm \360\2\x0F\x5B\110 WILLAMETTE,SSE2,SO CVTPD2DQ xmmreg,xmmrm \362\2\x0F\xE6\110 WILLAMETTE,SSE2,SO -CVTPD2PI mmxreg,xmmrm \361\2\x0F\x2D\110 WILLAMETTE,SSE2 +CVTPD2PI mmxreg,xmmrm \361\2\x0F\x2D\110 WILLAMETTE,SSE2,SO CVTPD2PS xmmreg,xmmrm \361\2\x0F\x5A\110 WILLAMETTE,SSE2,SO -CVTPI2PD xmmreg,mmxrm \361\2\x0F\x2A\110 WILLAMETTE,SSE2 +CVTPI2PD xmmreg,mmxrm \361\2\x0F\x2A\110 WILLAMETTE,SSE2,SQ CVTPS2DQ xmmreg,xmmrm \361\2\x0F\x5B\110 WILLAMETTE,SSE2,SO -CVTPS2PD xmmreg,xmmrm \360\2\x0F\x5A\110 WILLAMETTE,SSE2 -CVTSD2SI reg32,xmmrm \362\2\x0F\x2D\110 WILLAMETTE,SSE2 -CVTSD2SS xmmreg,xmmrm \362\2\x0F\x5A\110 WILLAMETTE,SSE2 -CVTSI2SD xmmreg,reg32 \362\2\x0F\x2A\110 WILLAMETTE,SSE2 -CVTSI2SD xmmreg,mem \362\2\x0F\x2A\110 WILLAMETTE,SSE2 -CVTSS2SD xmmreg,xmmrm \363\2\x0F\x5A\110 WILLAMETTE,SSE2 -CVTTPD2PI mmxreg,xmmrm \361\2\x0F\x2C\110 WILLAMETTE,SSE2 +CVTPS2PD xmmreg,xmmrm \360\2\x0F\x5A\110 WILLAMETTE,SSE2,SQ +CVTSD2SI reg32,xmmreg \362\2\x0F\x2D\110 WILLAMETTE,SSE2,SQ,AR1 +CVTSD2SI reg32,mem \362\2\x0F\x2D\110 WILLAMETTE,SSE2,SQ,AR1 +CVTSD2SI reg64,xmmreg \324\362\2\x0F\x2D\110 X64,SSE2,SQ,AR1 +CVTSD2SI reg64,mem \324\362\2\x0F\x2D\110 X64,SSE2,SQ,AR1 +CVTSD2SS xmmreg,xmmrm \362\2\x0F\x5A\110 WILLAMETTE,SSE2,SQ +CVTSI2SD xmmreg,mem \362\2\x0F\x2A\110 WILLAMETTE,SSE2,SD,AR1,ND +CVTSI2SD xmmreg,rm32 \362\2\x0F\x2A\110 WILLAMETTE,SSE2,SD,AR1 +CVTSI2SD xmmreg,rm64 \324\362\2\x0F\x2A\110 X64,SSE2,SQ,AR1 +CVTSS2SD xmmreg,xmmrm \363\2\x0F\x5A\110 WILLAMETTE,SSE2,SD +CVTTPD2PI mmxreg,xmmrm \361\2\x0F\x2C\110 WILLAMETTE,SSE2,SO CVTTPD2DQ xmmreg,xmmrm \361\2\x0F\xE6\110 WILLAMETTE,SSE2,SO CVTTPS2DQ xmmreg,xmmrm \363\2\x0F\x5B\110 WILLAMETTE,SSE2,SO -CVTTSD2SI reg32,xmmrm \362\2\x0F\x2C\110 WILLAMETTE,SSE2 +CVTTSD2SI reg32,xmmreg \362\2\x0F\x2C\110 WILLAMETTE,SSE2,SQ,AR1 +CVTTSD2SI reg32,mem \362\2\x0F\x2C\110 WILLAMETTE,SSE2,SQ,AR1 +CVTTSD2SI reg64,xmmreg \324\362\2\x0F\x2C\110 X64,SSE2,SQ,AR1 +CVTTSD2SI reg64,mem \324\362\2\x0F\x2C\110 X64,SSE2,SQ,AR1 DIVPD xmmreg,xmmrm \361\2\x0F\x5E\110 WILLAMETTE,SSE2,SO DIVSD xmmreg,xmmrm \362\2\x0F\x5E\110 WILLAMETTE,SSE2 MAXPD xmmreg,xmmrm \361\2\x0F\x5F\110 WILLAMETTE,SSE2,SO @@ -1684,7 +1724,7 @@ MAXSD xmmreg,xmmrm \362\2\x0F\x5F\110 WILLAMETTE,SSE2 MINPD xmmreg,xmmrm \361\2\x0F\x5D\110 WILLAMETTE,SSE2,SO MINSD xmmreg,xmmrm \362\2\x0F\x5D\110 WILLAMETTE,SSE2 MOVAPD xmmreg,xmmreg \361\2\x0F\x28\110 WILLAMETTE,SSE2 -MOVAPD xmmreg,xmmreg \361\2\x0F\x29\110 WILLAMETTE,SSE2 +MOVAPD xmmreg,xmmreg \361\2\x0F\x29\101 WILLAMETTE,SSE2 MOVAPD mem,xmmreg \361\2\x0F\x29\101 WILLAMETTE,SSE2,SO MOVAPD xmmreg,mem \361\2\x0F\x28\110 WILLAMETTE,SSE2,SO MOVHPD mem,xmmreg \361\2\x0F\x17\101 WILLAMETTE,SSE2 @@ -1694,11 +1734,11 @@ MOVLPD xmmreg,mem \361\2\x0F\x12\110 WILLAMETTE,SSE2 MOVMSKPD reg32,xmmreg \361\2\x0F\x50\110 WILLAMETTE,SSE2 MOVMSKPD reg64,xmmreg \361\324\2\x0F\x50\110 X64,SSE2 MOVSD xmmreg,xmmreg \362\2\x0F\x10\110 WILLAMETTE,SSE2 -MOVSD xmmreg,xmmreg \362\2\x0F\x11\110 WILLAMETTE,SSE2 +MOVSD xmmreg,xmmreg \362\2\x0F\x11\101 WILLAMETTE,SSE2 MOVSD mem,xmmreg \362\2\x0F\x11\101 WILLAMETTE,SSE2 MOVSD xmmreg,mem \362\2\x0F\x10\110 WILLAMETTE,SSE2 MOVUPD xmmreg,xmmreg \361\2\x0F\x10\110 WILLAMETTE,SSE2 -MOVUPD xmmreg,xmmreg \361\2\x0F\x11\110 WILLAMETTE,SSE2 +MOVUPD xmmreg,xmmreg \361\2\x0F\x11\101 WILLAMETTE,SSE2 MOVUPD mem,xmmreg \361\2\x0F\x11\101 WILLAMETTE,SSE2,SO MOVUPD xmmreg,mem \361\2\x0F\x10\110 WILLAMETTE,SSE2,SO MULPD xmmreg,xmmrm \361\2\x0F\x59\110 WILLAMETTE,SSE2,SO @@ -1745,9 +1785,9 @@ VMWRITE reg64,rm64 \323\360\2\x0F\x79\110 X64,VMX,SQ VMXOFF void \3\x0F\x01\xC4 VMX VMXON mem \363\2\x0F\xC7\206 VMX ;# Extended Page Tables VMX instructions -INVEPT reg32,mem [rm: 66 0f 38 80 /r] VMX,SO,NOLONG +INVEPT reg32,mem [rm: 66 0f 38 80 /r] VMX,SO,NOLONG INVEPT reg64,mem [rm: o64nw 66 0f 38 80 /r] VMX,SO,LONG -INVVPID reg32,mem [rm: 66 0f 38 81 /r] VMX,SO,NOLONG +INVVPID reg32,mem [rm: 66 0f 38 81 /r] VMX,SO,NOLONG INVVPID reg64,mem [rm: o64nw 66 0f 38 81 /r] VMX,SO,LONG ;# Tejas New Instructions (SSSE3) @@ -1793,9 +1833,9 @@ MOVNTSD mem,xmmreg \362\2\x0F\x2B\101 SSE4A,AMD,SQ MOVNTSS mem,xmmreg \363\2\x0F\x2B\101 SSE4A,AMD,SD ;# New instructions in Barcelona -LZCNT reg16,rm16 \320\363\2\x0F\xBD\110 P6,AMD -LZCNT reg32,rm32 \321\363\2\x0F\xBD\110 P6,AMD -LZCNT reg64,rm64 \324\363\2\x0F\xBD\110 P6,AMD +LZCNT reg16,rm16 \320\333\2\x0F\xBD\110 P6,AMD +LZCNT reg32,rm32 \321\333\2\x0F\xBD\110 P6,AMD +LZCNT reg64,rm64 \324\333\2\x0F\xBD\110 X64,AMD ;# Penryn New Instructions (SSE4.1) BLENDPD xmmreg,xmmrm,imm \361\3\x0F\x3A\x0D\110\26 SSE41 @@ -1817,15 +1857,18 @@ PEXTRB reg32,xmmreg,imm \361\3\x0F\x3A\x14\101\26 SSE41 PEXTRB mem8,xmmreg,imm \361\3\x0F\x3A\x14\101\26 SSE41 PEXTRB reg64,xmmreg,imm \324\361\3\x0F\x3A\x14\101\26 SSE41,X64 PEXTRD rm32,xmmreg,imm \361\3\x0F\x3A\x16\101\26 SSE41 -PEXTRQ rm64,xmmreg,imm \361\3\x0F\x3A\x16\101\26 SSE41,X64 +PEXTRQ rm64,xmmreg,imm \324\361\3\x0F\x3A\x16\101\26 SSE41,X64 PEXTRW reg32,xmmreg,imm \361\3\x0F\x3A\x15\101\26 SSE41 PEXTRW mem16,xmmreg,imm \361\3\x0F\x3A\x15\101\26 SSE41 PEXTRW reg64,xmmreg,imm \324\361\3\x0F\x3A\x15\101\26 SSE41,X64 PHMINPOSUW xmmreg,xmmrm \361\3\x0F\x38\x41\110 SSE41 -PINSRB xmmreg,reg32,imm \361\3\x0F\x3A\x20\110\26 SSE41 -PINSRB xmmreg,mem8,imm \361\3\x0F\x3A\x20\110\26 SSE41 -PINSRD xmmreg,rm32,imm \361\3\x0F\x3A\x22\110\26 SSE41 -PINSRQ xmmreg,rm64,imm \324\361\3\x0F\x3A\x22\110\26 SSE41,X64 +PINSRB xmmreg,mem,imm \361\3\x0F\x3A\x20\110\26 SSE41,SB,AR2 +PINSRB xmmreg,rm8,imm \325\361\3\x0F\x3A\x20\110\26 SSE41,SB,AR2 +PINSRB xmmreg,reg32,imm \361\3\x0F\x3A\x20\110\26 SSE41,SB,AR2 +PINSRD xmmreg,mem,imm \361\3\x0F\x3A\x22\110\26 SSE41,SB,AR2 +PINSRD xmmreg,rm32,imm \361\3\x0F\x3A\x22\110\26 SSE41,SB,AR2 +PINSRQ xmmreg,mem,imm \324\361\3\x0F\x3A\x22\110\26 SSE41,X64,SB,AR2 +PINSRQ xmmreg,rm64,imm \324\361\3\x0F\x3A\x22\110\26 SSE41,X64,SB,AR2 PMAXSB xmmreg,xmmrm \361\3\x0F\x38\x3C\110 SSE41 PMAXSD xmmreg,xmmrm \361\3\x0F\x38\x3D\110 SSE41 PMAXUD xmmreg,xmmrm \361\3\x0F\x38\x3F\110 SSE41 @@ -1855,19 +1898,19 @@ ROUNDSD xmmreg,xmmrm,imm \361\3\x0F\x3A\x0B\110\26 SSE41 ROUNDSS xmmreg,xmmrm,imm \361\3\x0F\x3A\x0A\110\26 SSE41 ;# Nehalem New Instructions (SSE4.2) -CRC32 reg32,rm8 \362\3\x0F\x38\1\xF0\110 SSE42 -CRC32 reg32,rm16 \362\3\x0F\x38\1\xF1\110 SSE42 -CRC32 reg32,rm32 \362\3\x0F\x38\1\xF1\110 SSE42 -CRC32 reg64,rm8 \324\362\3\x0F\x38\1\xF0\110 SSE42,X64 -CRC32 reg64,rm64 \324\362\3\x0F\x38\1\xF1\110 SSE42,X64 +CRC32 reg32,rm8 \332\3\x0F\x38\xF0\110 SSE42 +CRC32 reg32,rm16 \320\332\3\x0F\x38\xF1\110 SSE42 +CRC32 reg32,rm32 \321\332\3\x0F\x38\xF1\110 SSE42 +CRC32 reg64,rm8 \324\332\3\x0F\x38\xF0\110 SSE42,X64 +CRC32 reg64,rm64 \324\332\3\x0F\x38\xF1\110 SSE42,X64 PCMPESTRI xmmreg,xmmrm,imm \361\3\x0F\x3A\x61\110\26 SSE42 PCMPESTRM xmmreg,xmmrm,imm \361\3\x0F\x3A\x60\110\26 SSE42 PCMPISTRI xmmreg,xmmrm,imm \361\3\x0F\x3A\x63\110\26 SSE42 PCMPISTRM xmmreg,xmmrm,imm \361\3\x0F\x3A\x62\110\26 SSE42 PCMPGTQ xmmreg,xmmrm \361\3\x0F\x38\x37\110 SSE42 -POPCNT reg16,rm16 \320\363\2\x0F\xB8\110 NEHALEM -POPCNT reg32,rm32 \321\363\2\x0F\xB8\110 NEHALEM -POPCNT reg64,rm32 \324\363\2\x0F\xB8\110 NEHALEM,X64 +POPCNT reg16,rm16 \320\333\2\x0F\xB8\110 NEHALEM,SW +POPCNT reg32,rm32 \321\333\2\x0F\xB8\110 NEHALEM,SD +POPCNT reg64,rm64 \324\333\2\x0F\xB8\110 NEHALEM,SQ,X64 ;# AMD SSE5 instructions @@ -2178,8 +2221,8 @@ ROUNDSD xmmreg,xmmrm,imm \361\3\x0F\x3A\x08\110\26 SSE5,AMD GETSEC void \2\x0F\x37 KATMAI ;# Geode (Cyrix) 3DNow! additions -PFRCP mmxreg,mmxrm \323\2\x0F\x0F\110\1\x86 PENT,3DNOW,SQ,CYRIX -PFRSQRT mmxreg,mmxrm \323\2\x0F\x0F\110\1\x87 PENT,3DNOW,SQ,CYRIX +PFRCPV mmxreg,mmxrm \323\2\x0F\x0F\110\1\x86 PENT,3DNOW,SQ,CYRIX +PFRSQRTV mmxreg,mmxrm \323\2\x0F\x0F\110\1\x87 PENT,3DNOW,SQ,CYRIX ;# Intel new instructions in ??? ; Is NEHALEM right here? @@ -2191,482 +2234,258 @@ MOVBE mem32,reg32 [mr: o32 0f 38 f1 /r] NEHALEM,SM MOVBE mem64,reg64 [mr: o64 0f 38 f1 /r] NEHALEM,SM ;# Intel AES instructions -AESENC xmmreg,xmmrm [rm: 66 0f 38 dc /r] WESTMERE,SO -AESENCLAST xmmreg,xmmrm [rm: 66 0f 38 dd /r] WESTMERE,SO -AESDEC xmmreg,xmmrm [rm: 66 0f 38 de /r] WESTMERE,SO -AESDECLAST xmmreg,xmmrm [rm: 66 0f 38 df /r] WESTMERE,SO -AESIMC xmmreg,xmmrm [rm: 66 0f 38 db /r] WESTMERE,SO -AESKEYGENASSIST xmmreg,xmmrm,imm [rmi: 66 0f 3a df /r ib] WESTMERE,SO +AESENC xmmreg,xmmrm [rm: 66 0f 38 dc /r] SSE,WESTMERE,SO +AESENCLAST xmmreg,xmmrm [rm: 66 0f 38 dd /r] SSE,WESTMERE,SO +AESDEC xmmreg,xmmrm [rm: 66 0f 38 de /r] SSE,WESTMERE,SO +AESDECLAST xmmreg,xmmrm [rm: 66 0f 38 df /r] SSE,WESTMERE,SO +AESIMC xmmreg,xmmrm [rm: 66 0f 38 db /r] SSE,WESTMERE,SO +AESKEYGENASSIST xmmreg,xmmrm,imm [rmi: 66 0f 3a df /r ib] SSE,WESTMERE,SO ;# Intel AVX AES instructions -VAESENC xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 dc /r] AVX,SANDYBRIDGE,SO -VAESENC xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 dc /r] AVX,SANDYBRIDGE,SO -VAESENCLAST xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 dd /r] AVX,SANDYBRIDGE,SO -VAESENCLAST xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 dd /r] AVX,SANDYBRIDGE,SO -VAESDEC xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 de /r] AVX,SANDYBRIDGE,SO -VAESDEC xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 de /r] AVX,SANDYBRIDGE,SO -VAESDECLAST xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 df /r] AVX,SANDYBRIDGE,SO -VAESDECLAST xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 df /r] AVX,SANDYBRIDGE,SO +VAESENC xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 dc /r] AVX,SANDYBRIDGE,SO +VAESENCLAST xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 dd /r] AVX,SANDYBRIDGE,SO +VAESDEC xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 de /r] AVX,SANDYBRIDGE,SO +VAESDECLAST xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 df /r] AVX,SANDYBRIDGE,SO VAESIMC xmmreg,xmmrm [rm: vex.128.66.0f38 db /r] AVX,SANDYBRIDGE,SO -VAESKEYGENASSIST xmmreg,xmmrm,imm [rmi: vex.128.66.0f3a df /r ib] AVX,SANDYBRIDGE,SO +VAESKEYGENASSIST xmmreg,xmmrm,imm [rmi: vex.128.66.0f3a df /r ib] AVX,SANDYBRIDGE,SO ;# Intel AVX instructions -VADDPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 58 /r] AVX,SANDYBRIDGE,SO -VADDPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 58 /r] AVX,SANDYBRIDGE,SO -VADDPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 58 /r] AVX,SANDYBRIDGE,SY -VADDPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 58 /r] AVX,SANDYBRIDGE,SY -VADDPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 58 /r] AVX,SANDYBRIDGE,SO -VADDPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 58 /r] AVX,SANDYBRIDGE,SO -VADDPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 58 /r] AVX,SANDYBRIDGE,SY -VADDPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 58 /r] AVX,SANDYBRIDGE,SY -VADDSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f 58 /r] AVX,SANDYBRIDGE,SQ -VADDSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f 58 /r] AVX,SANDYBRIDGE,SQ -VADDSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f 58 /r] AVX,SANDYBRIDGE,SD -VADDSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f 58 /r] AVX,SANDYBRIDGE,SD -VADDSUBPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f d0 /r] AVX,SANDYBRIDGE,SO -VADDSUBPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f d0 /r] AVX,SANDYBRIDGE,SO -VADDSUBPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f d0 /r] AVX,SANDYBRIDGE,SY -VADDSUBPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f d0 /r] AVX,SANDYBRIDGE,SY -VADDSUBPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f f0 /r] AVX,SANDYBRIDGE,SO -VADDSUBPS xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f f0 /r] AVX,SANDYBRIDGE,SO -VADDSUBPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.f2.0f f0 /r] AVX,SANDYBRIDGE,SY -VADDSUBPS ymmreg,ymmrm [r+vm: vex.nds.256.f2.0f f0 /r] AVX,SANDYBRIDGE,SY -VANDPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 54 /r] AVX,SANDYBRIDGE,SO -VANDPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 54 /r] AVX,SANDYBRIDGE,SO -VANDPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 54 /r] AVX,SANDYBRIDGE,SY -VANDPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 54 /r] AVX,SANDYBRIDGE,SY -VANDPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 54 /r] AVX,SANDYBRIDGE,SO -VANDPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 54 /r] AVX,SANDYBRIDGE,SO -VANDPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 54 /r] AVX,SANDYBRIDGE,SY -VANDPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 54 /r] AVX,SANDYBRIDGE,SY -VANDNPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 55 /r] AVX,SANDYBRIDGE,SO -VANDNPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 55 /r] AVX,SANDYBRIDGE,SO -VANDNPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 55 /r] AVX,SANDYBRIDGE,SY -VANDNPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 55 /r] AVX,SANDYBRIDGE,SY -VANDNPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 55 /r] AVX,SANDYBRIDGE,SO -VANDNPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 55 /r] AVX,SANDYBRIDGE,SO -VANDNPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 55 /r] AVX,SANDYBRIDGE,SY -VANDNPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 55 /r] AVX,SANDYBRIDGE,SY -VBLENDPD xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 0d /r ib] AVX,SANDYBRIDGE,SO -VBLENDPD xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 0d /r ib] AVX,SANDYBRIDGE,SO -VBLENDPD ymmreg,ymmreg,ymmrm,imm [rvmi: vex.nds.256.66.0f3a 0d /r ib] AVX,SANDYBRIDGE,SY -VBLENDPD ymmreg,ymmrm,imm [r+vmi: vex.nds.256.66.0f3a 0d /r ib] AVX,SANDYBRIDGE,SY -VBLENDPS xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 0c /r ib] AVX,SANDYBRIDGE,SO -VBLENDPS xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 0c /r ib] AVX,SANDYBRIDGE,SO -VBLENDPS ymmreg,ymmreg,ymmrm,imm [rvmi: vex.nds.256.66.0f3a 0c /r ib] AVX,SANDYBRIDGE,SY -VBLENDPS ymmreg,ymmrm,imm [r+vmi: vex.nds.256.66.0f3a 0c /r ib] AVX,SANDYBRIDGE,SY -VBLENDVPD xmmreg,xmmreg,xmmrm,xmmrm [rvms: vex.nds.128.66.0f3a 4b /r /is4] AVX,SANDYBRIDGE,SO +VADDPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 58 /r] AVX,SANDYBRIDGE,SO +VADDPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f 58 /r] AVX,SANDYBRIDGE,SY +VADDPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f 58 /r] AVX,SANDYBRIDGE,SO +VADDPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f 58 /r] AVX,SANDYBRIDGE,SY +VADDSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f 58 /r] AVX,SANDYBRIDGE,SQ +VADDSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f 58 /r] AVX,SANDYBRIDGE,SD +VADDSUBPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f d0 /r] AVX,SANDYBRIDGE,SO +VADDSUBPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f d0 /r] AVX,SANDYBRIDGE,SY +VADDSUBPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f d0 /r] AVX,SANDYBRIDGE,SO +VADDSUBPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.f2.0f d0 /r] AVX,SANDYBRIDGE,SY +VANDPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 54 /r] AVX,SANDYBRIDGE,SO +VANDPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f 54 /r] AVX,SANDYBRIDGE,SY +VANDPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f 54 /r] AVX,SANDYBRIDGE,SO +VANDPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f 54 /r] AVX,SANDYBRIDGE,SY +VANDNPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 55 /r] AVX,SANDYBRIDGE,SO +VANDNPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f 55 /r] AVX,SANDYBRIDGE,SY +VANDNPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f 55 /r] AVX,SANDYBRIDGE,SO +VANDNPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f 55 /r] AVX,SANDYBRIDGE,SY +VBLENDPD xmmreg,xmmreg*,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 0d /r ib] AVX,SANDYBRIDGE,SO +VBLENDPD ymmreg,ymmreg*,ymmrm,imm [rvmi: vex.nds.256.66.0f3a 0d /r ib] AVX,SANDYBRIDGE,SY +VBLENDPS xmmreg,xmmreg*,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 0c /r ib] AVX,SANDYBRIDGE,SO +VBLENDPS ymmreg,ymmreg*,ymmrm,imm [rvmi: vex.nds.256.66.0f3a 0c /r ib] AVX,SANDYBRIDGE,SY +VBLENDVPD xmmreg,xmmreg,xmmrm,xmmreg [rvms: vex.nds.128.66.0f3a 4b /r /is4] AVX,SANDYBRIDGE,SO VBLENDVPD xmmreg,xmmrm,xmm0 [rm-: vex.128.66.0f38 15 /r] AVX,SANDYBRIDGE,SO -VBLENDVPD ymmreg,ymmreg,ymmrm,ymmrm [rvms: vex.nds.256.66.0f3a 4b /r /is4] AVX,SANDYBRIDGE,SY +VBLENDVPD ymmreg,ymmreg,ymmrm,ymmreg [rvms: vex.nds.256.66.0f3a 4b /r /is4] AVX,SANDYBRIDGE,SY VBLENDVPD ymmreg,ymmrm,ymm0 [rm-: vex.256.66.0f38 15 /r] AVX,SANDYBRIDGE,SY -VBLENDVPS xmmreg,xmmreg,xmmrm,xmmrm [rvms: vex.nds.128.66.0f3a 4a /r /is4] AVX,SANDYBRIDGE,SO +VBLENDVPS xmmreg,xmmreg,xmmrm,xmmreg [rvms: vex.nds.128.66.0f3a 4a /r /is4] AVX,SANDYBRIDGE,SO VBLENDVPS xmmreg,xmmrm,xmm0 [rm-: vex.128.66.0f38 14 /r] AVX,SANDYBRIDGE,SO -VBLENDVPS ymmreg,ymmreg,ymmrm,ymmrm [rvms: vex.nds.256.66.0f3a 4a /r /is4] AVX,SANDYBRIDGE,SY +VBLENDVPS ymmreg,ymmreg,ymmrm,ymmreg [rvms: vex.nds.256.66.0f3a 4a /r /is4] AVX,SANDYBRIDGE,SY VBLENDVPD ymmreg,ymmrm,ymm0 [rm-: vex.256.66.0f38 14 /r] AVX,SANDYBRIDGE,SY VBROADCASTSS xmmreg,mem [rm: vex.128.66.0f38 18 /r] AVX,SANDYBRIDGE,SD VBROADCASTSS ymmreg,mem [rm: vex.256.66.0f38 18 /r] AVX,SANDYBRIDGE,SD VBROADCASTSD ymmreg,mem [rm: vex.256.66.0f38 19 /r] AVX,SANDYBRIDGE,SQ VBROADCASTF128 ymmreg,mem [rm: vex.256.66.0f38 1a /r] AVX,SANDYBRIDGE,SO ; Specific aliases first, then the generic version, to keep the disassembler happy... -VCMPEQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 00] AVX,SANDYBRIDGE,SO -VCMPEQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 00] AVX,SANDYBRIDGE,SO -VCMPEQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 00] AVX,SANDYBRIDGE,SY -VCMPEQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 00] AVX,SANDYBRIDGE,SY -VCMPLTPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 01] AVX,SANDYBRIDGE,SO -VCMPLTPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 01] AVX,SANDYBRIDGE,SO -VCMPLTPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 01] AVX,SANDYBRIDGE,SY -VCMPLTPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 01] AVX,SANDYBRIDGE,SY -VCMPLEPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 02] AVX,SANDYBRIDGE,SO -VCMPLEPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 02] AVX,SANDYBRIDGE,SO -VCMPLEPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 02] AVX,SANDYBRIDGE,SY -VCMPLEPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 02] AVX,SANDYBRIDGE,SY -VCMPUNORDPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 03] AVX,SANDYBRIDGE,SO -VCMPUNORDPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 03] AVX,SANDYBRIDGE,SO -VCMPUNORDPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 03] AVX,SANDYBRIDGE,SY -VCMPUNORDPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 03] AVX,SANDYBRIDGE,SY -VCMPNEQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 04] AVX,SANDYBRIDGE,SO -VCMPNEQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 04] AVX,SANDYBRIDGE,SO -VCMPNEQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 04] AVX,SANDYBRIDGE,SY -VCMPNEQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 04] AVX,SANDYBRIDGE,SY -VCMPNLTPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 05] AVX,SANDYBRIDGE,SO -VCMPNLTPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 05] AVX,SANDYBRIDGE,SO -VCMPNLTPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 05] AVX,SANDYBRIDGE,SY -VCMPNLTPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 05] AVX,SANDYBRIDGE,SY -VCMPNLEPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 06] AVX,SANDYBRIDGE,SO -VCMPNLEPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 06] AVX,SANDYBRIDGE,SO -VCMPNLEPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 06] AVX,SANDYBRIDGE,SY -VCMPNLEPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 06] AVX,SANDYBRIDGE,SY -VCMPORDPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 07] AVX,SANDYBRIDGE,SO -VCMPORDPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 07] AVX,SANDYBRIDGE,SO -VCMPORDPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 07] AVX,SANDYBRIDGE,SY -VCMPORDPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 07] AVX,SANDYBRIDGE,SY -VCMPEQ_UQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 08] AVX,SANDYBRIDGE,SO -VCMPEQ_UQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 08] AVX,SANDYBRIDGE,SO -VCMPEQ_UQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 08] AVX,SANDYBRIDGE,SY -VCMPEQ_UQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 08] AVX,SANDYBRIDGE,SY -VCMPNGEPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 09] AVX,SANDYBRIDGE,SO -VCMPNGEPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 09] AVX,SANDYBRIDGE,SO -VCMPNGEPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 09] AVX,SANDYBRIDGE,SY -VCMPNGEPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 09] AVX,SANDYBRIDGE,SY -VCMPNGTPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 0a] AVX,SANDYBRIDGE,SO -VCMPNGTPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 0a] AVX,SANDYBRIDGE,SO -VCMPNGTPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 0a] AVX,SANDYBRIDGE,SY -VCMPNGTPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 0a] AVX,SANDYBRIDGE,SY -VCMPFALSEPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 0b] AVX,SANDYBRIDGE,SO -VCMPFALSEPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 0b] AVX,SANDYBRIDGE,SO -VCMPFALSEPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 0b] AVX,SANDYBRIDGE,SY -VCMPFALSEPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 0b] AVX,SANDYBRIDGE,SY -VCMPNEQ_OQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 0c] AVX,SANDYBRIDGE,SO -VCMPNEQ_OQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 0c] AVX,SANDYBRIDGE,SO -VCMPNEQ_OQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 0c] AVX,SANDYBRIDGE,SY -VCMPNEQ_OQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 0c] AVX,SANDYBRIDGE,SY -VCMPGEPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 0d] AVX,SANDYBRIDGE,SO -VCMPGEPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 0d] AVX,SANDYBRIDGE,SO -VCMPGEPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 0d] AVX,SANDYBRIDGE,SY -VCMPGEPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 0d] AVX,SANDYBRIDGE,SY -VCMPGTPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 0e] AVX,SANDYBRIDGE,SO -VCMPGTPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 0e] AVX,SANDYBRIDGE,SO -VCMPGTPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 0e] AVX,SANDYBRIDGE,SY -VCMPGTPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 0e] AVX,SANDYBRIDGE,SY -VCMPTRUEPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 0f] AVX,SANDYBRIDGE,SO -VCMPTRUEPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 0f] AVX,SANDYBRIDGE,SO -VCMPTRUEPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 0f] AVX,SANDYBRIDGE,SY -VCMPTRUEPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 0f] AVX,SANDYBRIDGE,SY -VCMPEQ_OSPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 10] AVX,SANDYBRIDGE,SO -VCMPEQ_OSPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 10] AVX,SANDYBRIDGE,SO -VCMPEQ_OSPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 10] AVX,SANDYBRIDGE,SY -VCMPEQ_OSPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 10] AVX,SANDYBRIDGE,SY -VCMPLT_OQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 11] AVX,SANDYBRIDGE,SO -VCMPLT_OQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 11] AVX,SANDYBRIDGE,SO -VCMPLT_OQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 11] AVX,SANDYBRIDGE,SY -VCMPLT_OQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 11] AVX,SANDYBRIDGE,SY -VCMPLE_OQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 12] AVX,SANDYBRIDGE,SO -VCMPLE_OQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 12] AVX,SANDYBRIDGE,SO -VCMPLE_OQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 12] AVX,SANDYBRIDGE,SY -VCMPLE_OQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 12] AVX,SANDYBRIDGE,SY -VCMPUNORD_SPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 13] AVX,SANDYBRIDGE,SO -VCMPUNORD_SPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 13] AVX,SANDYBRIDGE,SO -VCMPUNORD_SPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 13] AVX,SANDYBRIDGE,SY -VCMPUNORD_SPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 13] AVX,SANDYBRIDGE,SY -VCMPNEQ_USPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 14] AVX,SANDYBRIDGE,SO -VCMPNEQ_USPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 14] AVX,SANDYBRIDGE,SO -VCMPNEQ_USPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 14] AVX,SANDYBRIDGE,SY -VCMPNEQ_USPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 14] AVX,SANDYBRIDGE,SY -VCMPNLT_UQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 15] AVX,SANDYBRIDGE,SO -VCMPNLT_UQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 15] AVX,SANDYBRIDGE,SO -VCMPNLT_UQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 15] AVX,SANDYBRIDGE,SY -VCMPNLT_UQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 15] AVX,SANDYBRIDGE,SY -VCMPNLE_UQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 16] AVX,SANDYBRIDGE,SO -VCMPNLE_UQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 16] AVX,SANDYBRIDGE,SO -VCMPNLE_UQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 16] AVX,SANDYBRIDGE,SY -VCMPNLE_UQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 16] AVX,SANDYBRIDGE,SY -VCMPORD_SPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 17] AVX,SANDYBRIDGE,SO -VCMPORD_SPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 17] AVX,SANDYBRIDGE,SO -VCMPORD_SPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 17] AVX,SANDYBRIDGE,SY -VCMPORS_SPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 17] AVX,SANDYBRIDGE,SY -VCMPEQ_USPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 18] AVX,SANDYBRIDGE,SO -VCMPEQ_USPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 18] AVX,SANDYBRIDGE,SO -VCMPEQ_USPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 18] AVX,SANDYBRIDGE,SY -VCMPEQ_USPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 18] AVX,SANDYBRIDGE,SY -VCMPNGE_UQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 19] AVX,SANDYBRIDGE,SO -VCMPNGE_UQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 19] AVX,SANDYBRIDGE,SO -VCMPNGE_UQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 19] AVX,SANDYBRIDGE,SY -VCMPNGE_UQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 19] AVX,SANDYBRIDGE,SY -VCMPNGT_UQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 1a] AVX,SANDYBRIDGE,SO -VCMPNGT_UQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 1a] AVX,SANDYBRIDGE,SO -VCMPNGT_UQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 1a] AVX,SANDYBRIDGE,SY -VCMPNGT_UQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 1a] AVX,SANDYBRIDGE,SY -VCMPFALSE_OSPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 1b] AVX,SANDYBRIDGE,SO -VCMPFALSE_OSPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 1b] AVX,SANDYBRIDGE,SO -VCMPFALSE_OSPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 1b] AVX,SANDYBRIDGE,SY -VCMPFALSE_OSPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 1b] AVX,SANDYBRIDGE,SY -VCMPNEQ_OSPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 1c] AVX,SANDYBRIDGE,SO -VCMPNEQ_OSPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 1c] AVX,SANDYBRIDGE,SO -VCMPNEQ_OSPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 1c] AVX,SANDYBRIDGE,SY -VCMPNEQ_OSPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 1c] AVX,SANDYBRIDGE,SY -VCMPGE_OQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 1d] AVX,SANDYBRIDGE,SO -VCMPGE_OQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 1d] AVX,SANDYBRIDGE,SO -VCMPGE_OQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 1d] AVX,SANDYBRIDGE,SY -VCMPGE_OQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 1d] AVX,SANDYBRIDGE,SY -VCMPGT_OQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 1e] AVX,SANDYBRIDGE,SO -VCMPGT_OQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 1e] AVX,SANDYBRIDGE,SO -VCMPGT_OQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 1e] AVX,SANDYBRIDGE,SY -VCMPGT_OQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 1e] AVX,SANDYBRIDGE,SY -VCMPTRUE_USPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 1f] AVX,SANDYBRIDGE,SO -VCMPTRUE_USPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 1f] AVX,SANDYBRIDGE,SO -VCMPTRUE_USPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 1f] AVX,SANDYBRIDGE,SY -VCMPTRUE_USPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 1f] AVX,SANDYBRIDGE,SY -VCMPPD xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f c2 /r ib] AVX,SANDYBRIDGE,SO -VCMPPD xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f c2 /r ib] AVX,SANDYBRIDGE,SO -VCMPPD ymmreg,ymmreg,ymmrm,imm [rvmi: vex.nds.256.66.0f c2 /r ib] AVX,SANDYBRIDGE,SY -VCMPPD ymmreg,ymmrm,imm [r+vmi: vex.nds.256.66.0f c2 /r ib] AVX,SANDYBRIDGE,SY +VCMPEQPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 00] AVX,SANDYBRIDGE,SO +VCMPEQPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 00] AVX,SANDYBRIDGE,SY +VCMPLTPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 01] AVX,SANDYBRIDGE,SO +VCMPLTPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 01] AVX,SANDYBRIDGE,SY +VCMPLEPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 02] AVX,SANDYBRIDGE,SO +VCMPLEPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 02] AVX,SANDYBRIDGE,SY +VCMPUNORDPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 03] AVX,SANDYBRIDGE,SO +VCMPUNORDPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 03] AVX,SANDYBRIDGE,SY +VCMPNEQPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 04] AVX,SANDYBRIDGE,SO +VCMPNEQPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 04] AVX,SANDYBRIDGE,SY +VCMPNLTPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 05] AVX,SANDYBRIDGE,SO +VCMPNLTPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 05] AVX,SANDYBRIDGE,SY +VCMPNLEPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 06] AVX,SANDYBRIDGE,SO +VCMPNLEPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 06] AVX,SANDYBRIDGE,SY +VCMPORDPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 07] AVX,SANDYBRIDGE,SO +VCMPORDPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 07] AVX,SANDYBRIDGE,SY +VCMPEQ_UQPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 08] AVX,SANDYBRIDGE,SO +VCMPEQ_UQPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 08] AVX,SANDYBRIDGE,SY +VCMPNGEPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 09] AVX,SANDYBRIDGE,SO +VCMPNGEPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 09] AVX,SANDYBRIDGE,SY +VCMPNGTPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 0a] AVX,SANDYBRIDGE,SO +VCMPNGTPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 0a] AVX,SANDYBRIDGE,SY +VCMPFALSEPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 0b] AVX,SANDYBRIDGE,SO +VCMPFALSEPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 0b] AVX,SANDYBRIDGE,SY +VCMPNEQ_OQPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 0c] AVX,SANDYBRIDGE,SO +VCMPNEQ_OQPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 0c] AVX,SANDYBRIDGE,SY +VCMPGEPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 0d] AVX,SANDYBRIDGE,SO +VCMPGEPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 0d] AVX,SANDYBRIDGE,SY +VCMPGTPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 0e] AVX,SANDYBRIDGE,SO +VCMPGTPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 0e] AVX,SANDYBRIDGE,SY +VCMPTRUEPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 0f] AVX,SANDYBRIDGE,SO +VCMPTRUEPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 0f] AVX,SANDYBRIDGE,SY +VCMPEQ_OSPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 10] AVX,SANDYBRIDGE,SO +VCMPEQ_OSPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 10] AVX,SANDYBRIDGE,SY +VCMPLT_OQPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 11] AVX,SANDYBRIDGE,SO +VCMPLT_OQPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 11] AVX,SANDYBRIDGE,SY +VCMPLE_OQPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 12] AVX,SANDYBRIDGE,SO +VCMPLE_OQPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 12] AVX,SANDYBRIDGE,SY +VCMPUNORD_SPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 13] AVX,SANDYBRIDGE,SO +VCMPUNORD_SPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 13] AVX,SANDYBRIDGE,SY +VCMPNEQ_USPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 14] AVX,SANDYBRIDGE,SO +VCMPNEQ_USPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 14] AVX,SANDYBRIDGE,SY +VCMPNLT_UQPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 15] AVX,SANDYBRIDGE,SO +VCMPNLT_UQPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 15] AVX,SANDYBRIDGE,SY +VCMPNLE_UQPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 16] AVX,SANDYBRIDGE,SO +VCMPNLE_UQPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 16] AVX,SANDYBRIDGE,SY +VCMPORD_SPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 17] AVX,SANDYBRIDGE,SO +VCMPORD_SPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 17] AVX,SANDYBRIDGE,SY +VCMPEQ_USPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 18] AVX,SANDYBRIDGE,SO +VCMPEQ_USPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 18] AVX,SANDYBRIDGE,SY +VCMPNGE_UQPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 19] AVX,SANDYBRIDGE,SO +VCMPNGE_UQPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 19] AVX,SANDYBRIDGE,SY +VCMPNGT_UQPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 1a] AVX,SANDYBRIDGE,SO +VCMPNGT_UQPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 1a] AVX,SANDYBRIDGE,SY +VCMPFALSE_OSPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 1b] AVX,SANDYBRIDGE,SO +VCMPFALSE_OSPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 1b] AVX,SANDYBRIDGE,SY +VCMPNEQ_OSPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 1c] AVX,SANDYBRIDGE,SO +VCMPNEQ_OSPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 1c] AVX,SANDYBRIDGE,SY +VCMPGE_OQPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 1d] AVX,SANDYBRIDGE,SO +VCMPGE_OQPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 1d] AVX,SANDYBRIDGE,SY +VCMPGT_OQPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 1e] AVX,SANDYBRIDGE,SO +VCMPGT_OQPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 1e] AVX,SANDYBRIDGE,SY +VCMPTRUE_USPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f c2 /r 1f] AVX,SANDYBRIDGE,SO +VCMPTRUE_USPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f c2 /r 1f] AVX,SANDYBRIDGE,SY +VCMPPD xmmreg,xmmreg*,xmmrm,imm [rvmi: vex.nds.128.66.0f c2 /r ib] AVX,SANDYBRIDGE,SO +VCMPPD ymmreg,ymmreg*,ymmrm,imm [rvmi: vex.nds.256.66.0f c2 /r ib] AVX,SANDYBRIDGE,SY ; Specific aliases first, then the generic version, to keep the disassembler happy... -VCMPEQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 00] AVX,SANDYBRIDGE,SO -VCMPEQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 00] AVX,SANDYBRIDGE,SO -VCMPEQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 00] AVX,SANDYBRIDGE,SY -VCMPEQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 00] AVX,SANDYBRIDGE,SY -VCMPLTPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 01] AVX,SANDYBRIDGE,SO -VCMPLTPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 01] AVX,SANDYBRIDGE,SO -VCMPLTPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 01] AVX,SANDYBRIDGE,SY -VCMPLTPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 01] AVX,SANDYBRIDGE,SY -VCMPLEPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 02] AVX,SANDYBRIDGE,SO -VCMPLEPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 02] AVX,SANDYBRIDGE,SO -VCMPLEPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 02] AVX,SANDYBRIDGE,SY -VCMPLEPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 02] AVX,SANDYBRIDGE,SY -VCMPUNORDPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 03] AVX,SANDYBRIDGE,SO -VCMPUNORDPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 03] AVX,SANDYBRIDGE,SO -VCMPUNORDPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 03] AVX,SANDYBRIDGE,SY -VCMPUNORDPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 03] AVX,SANDYBRIDGE,SY -VCMPNEQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 04] AVX,SANDYBRIDGE,SO -VCMPNEQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 04] AVX,SANDYBRIDGE,SO -VCMPNEQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 04] AVX,SANDYBRIDGE,SY -VCMPNEQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 04] AVX,SANDYBRIDGE,SY -VCMPNLTPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 05] AVX,SANDYBRIDGE,SO -VCMPNLTPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 05] AVX,SANDYBRIDGE,SO -VCMPNLTPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 05] AVX,SANDYBRIDGE,SY -VCMPNLTPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 05] AVX,SANDYBRIDGE,SY -VCMPNLEPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 06] AVX,SANDYBRIDGE,SO -VCMPNLEPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 06] AVX,SANDYBRIDGE,SO -VCMPNLEPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 06] AVX,SANDYBRIDGE,SY -VCMPNLEPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 06] AVX,SANDYBRIDGE,SY -VCMPORDPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 07] AVX,SANDYBRIDGE,SO -VCMPORDPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 07] AVX,SANDYBRIDGE,SO -VCMPORDPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 07] AVX,SANDYBRIDGE,SY -VCMPORDPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 07] AVX,SANDYBRIDGE,SY -VCMPEQ_UQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 08] AVX,SANDYBRIDGE,SO -VCMPEQ_UQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 08] AVX,SANDYBRIDGE,SO -VCMPEQ_UQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 08] AVX,SANDYBRIDGE,SY -VCMPEQ_UQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 08] AVX,SANDYBRIDGE,SY -VCMPNGEPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 09] AVX,SANDYBRIDGE,SO -VCMPNGEPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 09] AVX,SANDYBRIDGE,SO -VCMPNGEPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 09] AVX,SANDYBRIDGE,SY -VCMPNGEPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 09] AVX,SANDYBRIDGE,SY -VCMPNGTPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 0a] AVX,SANDYBRIDGE,SO -VCMPNGTPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 0a] AVX,SANDYBRIDGE,SO -VCMPNGTPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 0a] AVX,SANDYBRIDGE,SY -VCMPNGTPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 0a] AVX,SANDYBRIDGE,SY -VCMPFALSEPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 0b] AVX,SANDYBRIDGE,SO -VCMPFALSEPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 0b] AVX,SANDYBRIDGE,SO -VCMPFALSEPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 0b] AVX,SANDYBRIDGE,SY -VCMPFALSEPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 0b] AVX,SANDYBRIDGE,SY -VCMPNEQ_OQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 0c] AVX,SANDYBRIDGE,SO -VCMPNEQ_OQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 0c] AVX,SANDYBRIDGE,SO -VCMPNEQ_OQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 0c] AVX,SANDYBRIDGE,SY -VCMPNEQ_OQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 0c] AVX,SANDYBRIDGE,SY -VCMPGEPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 0d] AVX,SANDYBRIDGE,SO -VCMPGEPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 0d] AVX,SANDYBRIDGE,SO -VCMPGEPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 0d] AVX,SANDYBRIDGE,SY -VCMPGEPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 0d] AVX,SANDYBRIDGE,SY -VCMPGTPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 0e] AVX,SANDYBRIDGE,SO -VCMPGTPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 0e] AVX,SANDYBRIDGE,SO -VCMPGTPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 0e] AVX,SANDYBRIDGE,SY -VCMPGTPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 0e] AVX,SANDYBRIDGE,SY -VCMPTRUEPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 0f] AVX,SANDYBRIDGE,SO -VCMPTRUEPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 0f] AVX,SANDYBRIDGE,SO -VCMPTRUEPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 0f] AVX,SANDYBRIDGE,SY -VCMPTRUEPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 0f] AVX,SANDYBRIDGE,SY -VCMPEQ_OSPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 10] AVX,SANDYBRIDGE,SO -VCMPEQ_OSPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 10] AVX,SANDYBRIDGE,SO -VCMPEQ_OSPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 10] AVX,SANDYBRIDGE,SY -VCMPEQ_OSPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 10] AVX,SANDYBRIDGE,SY -VCMPLT_OQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 11] AVX,SANDYBRIDGE,SO -VCMPLT_OQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 11] AVX,SANDYBRIDGE,SO -VCMPLT_OQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 11] AVX,SANDYBRIDGE,SY -VCMPLT_OQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 11] AVX,SANDYBRIDGE,SY -VCMPLE_OQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 12] AVX,SANDYBRIDGE,SO -VCMPLE_OQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 12] AVX,SANDYBRIDGE,SO -VCMPLE_OQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 12] AVX,SANDYBRIDGE,SY -VCMPLE_OQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 12] AVX,SANDYBRIDGE,SY -VCMPUNORD_SPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 13] AVX,SANDYBRIDGE,SO -VCMPUNORD_SPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 13] AVX,SANDYBRIDGE,SO -VCMPUNORD_SPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 13] AVX,SANDYBRIDGE,SY -VCMPUNORD_SPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 13] AVX,SANDYBRIDGE,SY -VCMPNEQ_USPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 14] AVX,SANDYBRIDGE,SO -VCMPNEQ_USPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 14] AVX,SANDYBRIDGE,SO -VCMPNEQ_USPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 14] AVX,SANDYBRIDGE,SY -VCMPNEQ_USPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 14] AVX,SANDYBRIDGE,SY -VCMPNLT_UQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 15] AVX,SANDYBRIDGE,SO -VCMPNLT_UQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 15] AVX,SANDYBRIDGE,SO -VCMPNLT_UQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 15] AVX,SANDYBRIDGE,SY -VCMPNLT_UQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 15] AVX,SANDYBRIDGE,SY -VCMPNLE_UQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 16] AVX,SANDYBRIDGE,SO -VCMPNLE_UQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 16] AVX,SANDYBRIDGE,SO -VCMPNLE_UQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 16] AVX,SANDYBRIDGE,SY -VCMPNLE_UQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 16] AVX,SANDYBRIDGE,SY -VCMPORD_SPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 17] AVX,SANDYBRIDGE,SO -VCMPORD_SPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 17] AVX,SANDYBRIDGE,SO -VCMPORD_SPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 17] AVX,SANDYBRIDGE,SY -VCMPORS_SPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 17] AVX,SANDYBRIDGE,SY -VCMPEQ_USPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 18] AVX,SANDYBRIDGE,SO -VCMPEQ_USPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 18] AVX,SANDYBRIDGE,SO -VCMPEQ_USPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 18] AVX,SANDYBRIDGE,SY -VCMPEQ_USPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 18] AVX,SANDYBRIDGE,SY -VCMPNGE_UQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 19] AVX,SANDYBRIDGE,SO -VCMPNGE_UQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 19] AVX,SANDYBRIDGE,SO -VCMPNGE_UQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 19] AVX,SANDYBRIDGE,SY -VCMPNGE_UQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 19] AVX,SANDYBRIDGE,SY -VCMPNGT_UQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 1a] AVX,SANDYBRIDGE,SO -VCMPNGT_UQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 1a] AVX,SANDYBRIDGE,SO -VCMPNGT_UQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 1a] AVX,SANDYBRIDGE,SY -VCMPNGT_UQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 1a] AVX,SANDYBRIDGE,SY -VCMPFALSE_OSPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 1b] AVX,SANDYBRIDGE,SO -VCMPFALSE_OSPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 1b] AVX,SANDYBRIDGE,SO -VCMPFALSE_OSPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 1b] AVX,SANDYBRIDGE,SY -VCMPFALSE_OSPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 1b] AVX,SANDYBRIDGE,SY -VCMPNEQ_OSPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 1c] AVX,SANDYBRIDGE,SO -VCMPNEQ_OSPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 1c] AVX,SANDYBRIDGE,SO -VCMPNEQ_OSPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 1c] AVX,SANDYBRIDGE,SY -VCMPNEQ_OSPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 1c] AVX,SANDYBRIDGE,SY -VCMPGE_OQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 1d] AVX,SANDYBRIDGE,SO -VCMPGE_OQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 1d] AVX,SANDYBRIDGE,SO -VCMPGE_OQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 1d] AVX,SANDYBRIDGE,SY -VCMPGE_OQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 1d] AVX,SANDYBRIDGE,SY -VCMPGT_OQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 1e] AVX,SANDYBRIDGE,SO -VCMPGT_OQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 1e] AVX,SANDYBRIDGE,SO -VCMPGT_OQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 1e] AVX,SANDYBRIDGE,SY -VCMPGT_OQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 1e] AVX,SANDYBRIDGE,SY -VCMPTRUE_USPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 1f] AVX,SANDYBRIDGE,SO -VCMPTRUE_USPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 1f] AVX,SANDYBRIDGE,SO -VCMPTRUE_USPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 1f] AVX,SANDYBRIDGE,SY -VCMPTRUE_USPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 1f] AVX,SANDYBRIDGE,SY -VCMPPS xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.0f c2 /r ib] AVX,SANDYBRIDGE,SO -VCMPPS xmmreg,xmmrm,imm [r+vmi: vex.nds.128.0f c2 /r ib] AVX,SANDYBRIDGE,SO -VCMPPS ymmreg,ymmreg,ymmrm,imm [rvmi: vex.nds.256.0f c2 /r ib] AVX,SANDYBRIDGE,SY -VCMPPS ymmreg,ymmrm,imm [r+vmi: vex.nds.256.0f c2 /r ib] AVX,SANDYBRIDGE,SY +VCMPEQPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 00] AVX,SANDYBRIDGE,SO +VCMPEQPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 00] AVX,SANDYBRIDGE,SY +VCMPLTPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 01] AVX,SANDYBRIDGE,SO +VCMPLTPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 01] AVX,SANDYBRIDGE,SY +VCMPLEPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 02] AVX,SANDYBRIDGE,SO +VCMPLEPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 02] AVX,SANDYBRIDGE,SY +VCMPUNORDPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 03] AVX,SANDYBRIDGE,SO +VCMPUNORDPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 03] AVX,SANDYBRIDGE,SY +VCMPNEQPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 04] AVX,SANDYBRIDGE,SO +VCMPNEQPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 04] AVX,SANDYBRIDGE,SY +VCMPNLTPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 05] AVX,SANDYBRIDGE,SO +VCMPNLTPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 05] AVX,SANDYBRIDGE,SY +VCMPNLEPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 06] AVX,SANDYBRIDGE,SO +VCMPNLEPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 06] AVX,SANDYBRIDGE,SY +VCMPORDPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 07] AVX,SANDYBRIDGE,SO +VCMPORDPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 07] AVX,SANDYBRIDGE,SY +VCMPEQ_UQPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 08] AVX,SANDYBRIDGE,SO +VCMPEQ_UQPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 08] AVX,SANDYBRIDGE,SY +VCMPNGEPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 09] AVX,SANDYBRIDGE,SO +VCMPNGEPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 09] AVX,SANDYBRIDGE,SY +VCMPNGTPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 0a] AVX,SANDYBRIDGE,SO +VCMPNGTPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 0a] AVX,SANDYBRIDGE,SY +VCMPFALSEPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 0b] AVX,SANDYBRIDGE,SO +VCMPFALSEPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 0b] AVX,SANDYBRIDGE,SY +VCMPNEQ_OQPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 0c] AVX,SANDYBRIDGE,SO +VCMPNEQ_OQPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 0c] AVX,SANDYBRIDGE,SY +VCMPGEPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 0d] AVX,SANDYBRIDGE,SO +VCMPGEPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 0d] AVX,SANDYBRIDGE,SY +VCMPGTPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 0e] AVX,SANDYBRIDGE,SO +VCMPGTPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 0e] AVX,SANDYBRIDGE,SY +VCMPTRUEPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 0f] AVX,SANDYBRIDGE,SO +VCMPTRUEPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 0f] AVX,SANDYBRIDGE,SY +VCMPEQ_OSPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 10] AVX,SANDYBRIDGE,SO +VCMPEQ_OSPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 10] AVX,SANDYBRIDGE,SY +VCMPLT_OQPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 11] AVX,SANDYBRIDGE,SO +VCMPLT_OQPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 11] AVX,SANDYBRIDGE,SY +VCMPLE_OQPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 12] AVX,SANDYBRIDGE,SO +VCMPLE_OQPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 12] AVX,SANDYBRIDGE,SY +VCMPUNORD_SPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 13] AVX,SANDYBRIDGE,SO +VCMPUNORD_SPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 13] AVX,SANDYBRIDGE,SY +VCMPNEQ_USPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 14] AVX,SANDYBRIDGE,SO +VCMPNEQ_USPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 14] AVX,SANDYBRIDGE,SY +VCMPNLT_UQPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 15] AVX,SANDYBRIDGE,SO +VCMPNLT_UQPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 15] AVX,SANDYBRIDGE,SY +VCMPNLE_UQPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 16] AVX,SANDYBRIDGE,SO +VCMPNLE_UQPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 16] AVX,SANDYBRIDGE,SY +VCMPORD_SPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 17] AVX,SANDYBRIDGE,SO +VCMPORD_SPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 17] AVX,SANDYBRIDGE,SY +VCMPEQ_USPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 18] AVX,SANDYBRIDGE,SO +VCMPEQ_USPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 18] AVX,SANDYBRIDGE,SY +VCMPNGE_UQPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 19] AVX,SANDYBRIDGE,SO +VCMPNGE_UQPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 19] AVX,SANDYBRIDGE,SY +VCMPNGT_UQPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 1a] AVX,SANDYBRIDGE,SO +VCMPNGT_UQPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 1a] AVX,SANDYBRIDGE,SY +VCMPFALSE_OSPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 1b] AVX,SANDYBRIDGE,SO +VCMPFALSE_OSPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 1b] AVX,SANDYBRIDGE,SY +VCMPNEQ_OSPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 1c] AVX,SANDYBRIDGE,SO +VCMPNEQ_OSPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 1c] AVX,SANDYBRIDGE,SY +VCMPGE_OQPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 1d] AVX,SANDYBRIDGE,SO +VCMPGE_OQPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 1d] AVX,SANDYBRIDGE,SY +VCMPGT_OQPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 1e] AVX,SANDYBRIDGE,SO +VCMPGT_OQPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 1e] AVX,SANDYBRIDGE,SY +VCMPTRUE_USPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f c2 /r 1f] AVX,SANDYBRIDGE,SO +VCMPTRUE_USPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f c2 /r 1f] AVX,SANDYBRIDGE,SY +VCMPPS xmmreg,xmmreg*,xmmrm,imm [rvmi: vex.nds.128.0f c2 /r ib] AVX,SANDYBRIDGE,SO +VCMPPS ymmreg,ymmreg*,ymmrm,imm [rvmi: vex.nds.256.0f c2 /r ib] AVX,SANDYBRIDGE,SY ; Specific aliases first, then the generic version, to keep the disassembler happy... -VCMPEQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 00] AVX,SANDYBRIDGE,SQ -VCMPEQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 00] AVX,SANDYBRIDGE,SQ -VCMPLTSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 01] AVX,SANDYBRIDGE,SQ -VCMPLTSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 01] AVX,SANDYBRIDGE,SQ -VCMPLESD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 02] AVX,SANDYBRIDGE,SQ -VCMPLESD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 02] AVX,SANDYBRIDGE,SQ -VCMPUNORDSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 03] AVX,SANDYBRIDGE,SQ -VCMPUNORDSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 03] AVX,SANDYBRIDGE,SQ -VCMPNEQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 04] AVX,SANDYBRIDGE,SQ -VCMPNEQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 04] AVX,SANDYBRIDGE,SQ -VCMPNLTSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 05] AVX,SANDYBRIDGE,SQ -VCMPNLTSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 05] AVX,SANDYBRIDGE,SQ -VCMPNLESD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 06] AVX,SANDYBRIDGE,SQ -VCMPNLESD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 06] AVX,SANDYBRIDGE,SQ -VCMPORDSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 07] AVX,SANDYBRIDGE,SQ -VCMPORDSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 07] AVX,SANDYBRIDGE,SQ -VCMPEQ_UQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 08] AVX,SANDYBRIDGE,SQ -VCMPEQ_UQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 08] AVX,SANDYBRIDGE,SQ -VCMPNGESD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 09] AVX,SANDYBRIDGE,SQ -VCMPNGESD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 09] AVX,SANDYBRIDGE,SQ -VCMPNGTSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 0a] AVX,SANDYBRIDGE,SQ -VCMPNGTSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 0a] AVX,SANDYBRIDGE,SQ -VCMPFALSESD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 0b] AVX,SANDYBRIDGE,SQ -VCMPFALSESD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 0b] AVX,SANDYBRIDGE,SQ -VCMPNEQ_OQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 0c] AVX,SANDYBRIDGE,SQ -VCMPNEQ_OQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 0c] AVX,SANDYBRIDGE,SQ -VCMPGESD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 0d] AVX,SANDYBRIDGE,SQ -VCMPGESD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 0d] AVX,SANDYBRIDGE,SQ -VCMPGTSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 0e] AVX,SANDYBRIDGE,SQ -VCMPGTSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 0e] AVX,SANDYBRIDGE,SQ -VCMPTRUESD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 0f] AVX,SANDYBRIDGE,SQ -VCMPTRUESD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 0f] AVX,SANDYBRIDGE,SQ -VCMPEQ_OSSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 10] AVX,SANDYBRIDGE,SQ -VCMPEQ_OSSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 10] AVX,SANDYBRIDGE,SQ -VCMPLT_OQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 11] AVX,SANDYBRIDGE,SQ -VCMPLT_OQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 11] AVX,SANDYBRIDGE,SQ -VCMPLE_OQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 12] AVX,SANDYBRIDGE,SQ -VCMPLE_OQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 12] AVX,SANDYBRIDGE,SQ -VCMPUNORD_SSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 13] AVX,SANDYBRIDGE,SQ -VCMPUNORD_SSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 13] AVX,SANDYBRIDGE,SQ -VCMPNEQ_USSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 14] AVX,SANDYBRIDGE,SQ -VCMPNEQ_USSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 14] AVX,SANDYBRIDGE,SQ -VCMPNLT_UQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 15] AVX,SANDYBRIDGE,SQ -VCMPNLT_UQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 15] AVX,SANDYBRIDGE,SQ -VCMPNLE_UQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 16] AVX,SANDYBRIDGE,SQ -VCMPNLE_UQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 16] AVX,SANDYBRIDGE,SQ -VCMPORD_SSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 17] AVX,SANDYBRIDGE,SQ -VCMPORD_SSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 17] AVX,SANDYBRIDGE,SQ -VCMPEQ_USSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 18] AVX,SANDYBRIDGE,SQ -VCMPEQ_USSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 18] AVX,SANDYBRIDGE,SQ -VCMPNGE_UQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 19] AVX,SANDYBRIDGE,SQ -VCMPNGE_UQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 19] AVX,SANDYBRIDGE,SQ -VCMPNGT_UQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 1a] AVX,SANDYBRIDGE,SQ -VCMPNGT_UQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 1a] AVX,SANDYBRIDGE,SQ -VCMPFALSE_OSSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 1b] AVX,SANDYBRIDGE,SQ -VCMPFALSE_OSSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 1b] AVX,SANDYBRIDGE,SQ -VCMPNEQ_OSSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 1c] AVX,SANDYBRIDGE,SQ -VCMPNEQ_OSSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 1c] AVX,SANDYBRIDGE,SQ -VCMPGE_OQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 1d] AVX,SANDYBRIDGE,SQ -VCMPGE_OQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 1d] AVX,SANDYBRIDGE,SQ -VCMPGT_OQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 1e] AVX,SANDYBRIDGE,SQ -VCMPGT_OQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 1e] AVX,SANDYBRIDGE,SQ -VCMPTRUE_USSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 1f] AVX,SANDYBRIDGE,SQ -VCMPTRUE_USSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 1f] AVX,SANDYBRIDGE,SQ -VCMPSD xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.f2.0f c2 /r ib] AVX,SANDYBRIDGE,SQ -VCMPSD xmmreg,xmmrm,imm [r+vmi: vex.nds.128.f2.0f c2 /r ib] AVX,SANDYBRIDGE,SQ +VCMPEQSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 00] AVX,SANDYBRIDGE,SQ +VCMPLTSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 01] AVX,SANDYBRIDGE,SQ +VCMPLESD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 02] AVX,SANDYBRIDGE,SQ +VCMPUNORDSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 03] AVX,SANDYBRIDGE,SQ +VCMPNEQSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 04] AVX,SANDYBRIDGE,SQ +VCMPNLTSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 05] AVX,SANDYBRIDGE,SQ +VCMPNLESD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 06] AVX,SANDYBRIDGE,SQ +VCMPORDSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 07] AVX,SANDYBRIDGE,SQ +VCMPEQ_UQSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 08] AVX,SANDYBRIDGE,SQ +VCMPNGESD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 09] AVX,SANDYBRIDGE,SQ +VCMPNGTSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 0a] AVX,SANDYBRIDGE,SQ +VCMPFALSESD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 0b] AVX,SANDYBRIDGE,SQ +VCMPNEQ_OQSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 0c] AVX,SANDYBRIDGE,SQ +VCMPGESD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 0d] AVX,SANDYBRIDGE,SQ +VCMPGTSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 0e] AVX,SANDYBRIDGE,SQ +VCMPTRUESD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 0f] AVX,SANDYBRIDGE,SQ +VCMPEQ_OSSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 10] AVX,SANDYBRIDGE,SQ +VCMPLT_OQSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 11] AVX,SANDYBRIDGE,SQ +VCMPLE_OQSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 12] AVX,SANDYBRIDGE,SQ +VCMPUNORD_SSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 13] AVX,SANDYBRIDGE,SQ +VCMPNEQ_USSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 14] AVX,SANDYBRIDGE,SQ +VCMPNLT_UQSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 15] AVX,SANDYBRIDGE,SQ +VCMPNLE_UQSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 16] AVX,SANDYBRIDGE,SQ +VCMPORD_SSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 17] AVX,SANDYBRIDGE,SQ +VCMPEQ_USSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 18] AVX,SANDYBRIDGE,SQ +VCMPNGE_UQSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 19] AVX,SANDYBRIDGE,SQ +VCMPNGT_UQSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 1a] AVX,SANDYBRIDGE,SQ +VCMPFALSE_OSSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 1b] AVX,SANDYBRIDGE,SQ +VCMPNEQ_OSSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 1c] AVX,SANDYBRIDGE,SQ +VCMPGE_OQSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 1d] AVX,SANDYBRIDGE,SQ +VCMPGT_OQSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 1e] AVX,SANDYBRIDGE,SQ +VCMPTRUE_USSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 1f] AVX,SANDYBRIDGE,SQ +VCMPSD xmmreg,xmmreg*,xmmrm,imm [rvmi: vex.nds.128.f2.0f c2 /r ib] AVX,SANDYBRIDGE,SQ ; Specific aliases first, then the generic version, to keep the disassembler happy... -VCMPEQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 00] AVX,SANDYBRIDGE,SD -VCMPEQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 00] AVX,SANDYBRIDGE,SD -VCMPLTSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 01] AVX,SANDYBRIDGE,SD -VCMPLTSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 01] AVX,SANDYBRIDGE,SD -VCMPLESS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 02] AVX,SANDYBRIDGE,SD -VCMPLESS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 02] AVX,SANDYBRIDGE,SD -VCMPUNORDSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 03] AVX,SANDYBRIDGE,SD -VCMPUNORDSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 03] AVX,SANDYBRIDGE,SD -VCMPNEQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 04] AVX,SANDYBRIDGE,SD -VCMPNEQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 04] AVX,SANDYBRIDGE,SD -VCMPNLTSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 05] AVX,SANDYBRIDGE,SD -VCMPNLTSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 05] AVX,SANDYBRIDGE,SD -VCMPNLESS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 06] AVX,SANDYBRIDGE,SD -VCMPNLESS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 06] AVX,SANDYBRIDGE,SD -VCMPORDSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 07] AVX,SANDYBRIDGE,SD -VCMPORDSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 07] AVX,SANDYBRIDGE,SD -VCMPEQ_UQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 08] AVX,SANDYBRIDGE,SD -VCMPEQ_UQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 08] AVX,SANDYBRIDGE,SD -VCMPNGESS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 09] AVX,SANDYBRIDGE,SD -VCMPNGESS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 09] AVX,SANDYBRIDGE,SD -VCMPNGTSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 0a] AVX,SANDYBRIDGE,SD -VCMPNGTSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 0a] AVX,SANDYBRIDGE,SD -VCMPFALSESS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 0b] AVX,SANDYBRIDGE,SD -VCMPFALSESS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 0b] AVX,SANDYBRIDGE,SD -VCMPNEQ_OQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 0c] AVX,SANDYBRIDGE,SD -VCMPNEQ_OQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 0c] AVX,SANDYBRIDGE,SD -VCMPGESS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 0d] AVX,SANDYBRIDGE,SD -VCMPGESS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 0d] AVX,SANDYBRIDGE,SD -VCMPGTSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 0e] AVX,SANDYBRIDGE,SD -VCMPGTSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 0e] AVX,SANDYBRIDGE,SD -VCMPTRUESS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 0f] AVX,SANDYBRIDGE,SD -VCMPTRUESS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 0f] AVX,SANDYBRIDGE,SD -VCMPEQ_OSSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 10] AVX,SANDYBRIDGE,SD -VCMPEQ_OSSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 10] AVX,SANDYBRIDGE,SD -VCMPLT_OQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 11] AVX,SANDYBRIDGE,SD -VCMPLT_OQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 11] AVX,SANDYBRIDGE,SD -VCMPLE_OQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 12] AVX,SANDYBRIDGE,SD -VCMPLE_OQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 12] AVX,SANDYBRIDGE,SD -VCMPUNORD_SSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 13] AVX,SANDYBRIDGE,SD -VCMPUNORD_SSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 13] AVX,SANDYBRIDGE,SD -VCMPNEQ_USSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 14] AVX,SANDYBRIDGE,SD -VCMPNEQ_USSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 14] AVX,SANDYBRIDGE,SD -VCMPNLT_UQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 15] AVX,SANDYBRIDGE,SD -VCMPNLT_UQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 15] AVX,SANDYBRIDGE,SD -VCMPNLE_UQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 16] AVX,SANDYBRIDGE,SD -VCMPNLE_UQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 16] AVX,SANDYBRIDGE,SD -VCMPORD_SSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 17] AVX,SANDYBRIDGE,SD -VCMPORD_SSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 17] AVX,SANDYBRIDGE,SD -VCMPEQ_USSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 18] AVX,SANDYBRIDGE,SD -VCMPEQ_USSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 18] AVX,SANDYBRIDGE,SD -VCMPNGE_UQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 19] AVX,SANDYBRIDGE,SD -VCMPNGE_UQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 19] AVX,SANDYBRIDGE,SD -VCMPNGT_UQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 1a] AVX,SANDYBRIDGE,SD -VCMPNGT_UQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 1a] AVX,SANDYBRIDGE,SD -VCMPFALSE_OSSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 1b] AVX,SANDYBRIDGE,SD -VCMPFALSE_OSSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 1b] AVX,SANDYBRIDGE,SD -VCMPNEQ_OSSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 1c] AVX,SANDYBRIDGE,SD -VCMPNEQ_OSSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 1c] AVX,SANDYBRIDGE,SD -VCMPGE_OQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 1d] AVX,SANDYBRIDGE,SD -VCMPGE_OQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 1d] AVX,SANDYBRIDGE,SD -VCMPGT_OQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 1e] AVX,SANDYBRIDGE,SD -VCMPGT_OQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 1e] AVX,SANDYBRIDGE,SD -VCMPTRUE_USSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 1f] AVX,SANDYBRIDGE,SD -VCMPTRUE_USSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 1f] AVX,SANDYBRIDGE,SD -VCMPSS xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.f3.0f c2 /r ib] AVX,SANDYBRIDGE,SD -VCMPSS xmmreg,xmmrm,imm [r+vmi: vex.nds.128.f3.0f c2 /r ib] AVX,SANDYBRIDGE,SD +VCMPEQSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 00] AVX,SANDYBRIDGE,SD +VCMPLTSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 01] AVX,SANDYBRIDGE,SD +VCMPLESS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 02] AVX,SANDYBRIDGE,SD +VCMPUNORDSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 03] AVX,SANDYBRIDGE,SD +VCMPNEQSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 04] AVX,SANDYBRIDGE,SD +VCMPNLTSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 05] AVX,SANDYBRIDGE,SD +VCMPNLESS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 06] AVX,SANDYBRIDGE,SD +VCMPORDSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 07] AVX,SANDYBRIDGE,SD +VCMPEQ_UQSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 08] AVX,SANDYBRIDGE,SD +VCMPNGESS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 09] AVX,SANDYBRIDGE,SD +VCMPNGTSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 0a] AVX,SANDYBRIDGE,SD +VCMPFALSESS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 0b] AVX,SANDYBRIDGE,SD +VCMPNEQ_OQSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 0c] AVX,SANDYBRIDGE,SD +VCMPGESS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 0d] AVX,SANDYBRIDGE,SD +VCMPGTSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 0e] AVX,SANDYBRIDGE,SD +VCMPTRUESS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 0f] AVX,SANDYBRIDGE,SD +VCMPEQ_OSSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 10] AVX,SANDYBRIDGE,SD +VCMPLT_OQSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 11] AVX,SANDYBRIDGE,SD +VCMPLE_OQSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 12] AVX,SANDYBRIDGE,SD +VCMPUNORD_SSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 13] AVX,SANDYBRIDGE,SD +VCMPNEQ_USSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 14] AVX,SANDYBRIDGE,SD +VCMPNLT_UQSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 15] AVX,SANDYBRIDGE,SD +VCMPNLE_UQSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 16] AVX,SANDYBRIDGE,SD +VCMPORD_SSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 17] AVX,SANDYBRIDGE,SD +VCMPEQ_USSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 18] AVX,SANDYBRIDGE,SD +VCMPNGE_UQSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 19] AVX,SANDYBRIDGE,SD +VCMPNGT_UQSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 1a] AVX,SANDYBRIDGE,SD +VCMPFALSE_OSSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 1b] AVX,SANDYBRIDGE,SD +VCMPNEQ_OSSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 1c] AVX,SANDYBRIDGE,SD +VCMPGE_OQSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 1d] AVX,SANDYBRIDGE,SD +VCMPGT_OQSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 1e] AVX,SANDYBRIDGE,SD +VCMPTRUE_USSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 1f] AVX,SANDYBRIDGE,SD +VCMPSS xmmreg,xmmreg*,xmmrm,imm [rvmi: vex.nds.128.f3.0f c2 /r ib] AVX,SANDYBRIDGE,SD VCOMISD xmmreg,xmmrm [rm: vex.128.66.0f 2f /r] AVX,SANDYBRIDGE,SQ VCOMISS xmmreg,xmmrm [rm: vex.128.0f 2f /r] AVX,SANDYBRIDGE,SD VCVTDQ2PD xmmreg,xmmrm [rm: vex.128.f3.0f e6 /r] AVX,SANDYBRIDGE,SQ @@ -2687,22 +2506,14 @@ VCVTPS2PD xmmreg,xmmrm [rm: vex.128.0f 5a /r] AVX,SANDYBRIDGE,SQ VCVTPS2PD ymmreg,xmmrm [rm: vex.256.0f 5a /r] AVX,SANDYBRIDGE,SO VCVTSD2SI reg32,xmmrm [rm: vex.128.f2.0f.w0 2d /r] AVX,SANDYBRIDGE,SQ VCVTSD2SI reg64,xmmrm [rm: vex.128.f2.0f.w1 2d /r] AVX,SANDYBRIDGE,SQ,LONG -VCVTSD2SS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f 5a /r] AVX,SANDYBRIDGE,SQ -VCVTSD2SS xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f 5a /r] AVX,SANDYBRIDGE,SQ -VCVTSI2SD xmmreg,xmmreg,rm32 [rvm: vex.nds.128.f2.0f.w0 2a /r] AVX,SANDYBRIDGE -VCVTSI2SD xmmreg,rm32 [r+vm: vex.nds.128.f2.0f.w0 2a /r] AVX,SANDYBRIDGE -VCVTSI2SD xmmreg,xmmreg,rm64 [rvm: vex.nds.128.f2.0f.w1 2a /r] AVX,SANDYBRIDGE,LONG -VCVTSI2SD xmmreg,rm64 [r+vm: vex.nds.128.f2.0f.w1 2a /r] AVX,SANDYBRIDGE,LONG -VCVTSI2SD xmmreg,xmmreg,rm32 [rvm: vex.nds.128.f3.0f.w0 2a /r] AVX,SANDYBRIDGE -VCVTSI2SD xmmreg,rm32 [r+vm: vex.nds.128.f3.0f.w0 2a /r] AVX,SANDYBRIDGE -VCVTSI2SD xmmreg,xmmreg,rm64 [rvm: vex.nds.128.f3.0f.w1 2a /r] AVX,SANDYBRIDGE,LONG -VCVTSI2SD xmmreg,rm64 [r+vm: vex.nds.128.f3.0f.w1 2a /r] AVX,SANDYBRIDGE,LONG -VCVTSI2SS xmmreg,xmmreg,rm32 [rvm: vex.nds.128.f3.0f.w0 2a /r] AVX,SANDYBRIDGE -VCVTSI2SS xmmreg,rm32 [r+vm: vex.nds.128.f3.0f.w0 2a /r] AVX,SANDYBRIDGE -VCVTSI2SS xmmreg,xmmreg,rm64 [rvm: vex.nds.128.f3.0f.w1 2a /r] AVX,SANDYBRIDGE,LONG -VCVTSI2SS xmmreg,rm64 [r+vm: vex.nds.128.f3.0f.w1 2a /r] AVX,SANDYBRIDGE,LONG -VCVTSS2SD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f 5a /r] AVX,SANDYBRIDGE,SD -VCVTSS2SD xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f 5a /r] AVX,SANDYBRIDGE,SD +VCVTSD2SS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f 5a /r] AVX,SANDYBRIDGE,SQ +VCVTSI2SD xmmreg,xmmreg*,rm32 [rvm: vex.nds.128.f2.0f.w0 2a /r] AVX,SANDYBRIDGE +VCVTSI2SD xmmreg,xmmreg*,mem [rvm: vex.nds.128.f2.0f.w0 2a /r] AVX,SANDYBRIDGE,SD,AR2,ND +VCVTSI2SD xmmreg,xmmreg*,rm64 [rvm: vex.nds.128.f2.0f.w1 2a /r] AVX,SANDYBRIDGE,LONG +VCVTSI2SS xmmreg,xmmreg*,rm32 [rvm: vex.nds.128.f3.0f.w0 2a /r] AVX,SANDYBRIDGE +VCVTSI2SS xmmreg,xmmreg*,mem [rvm: vex.nds.128.f3.0f.w0 2a /r] AVX,SANDYBRIDGE,SD,AR2,ND +VCVTSI2SS xmmreg,xmmreg*,rm64 [rvm: vex.nds.128.f3.0f.w1 2a /r] AVX,SANDYBRIDGE,LONG +VCVTSS2SD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f 5a /r] AVX,SANDYBRIDGE,SD VCVTSS2SI reg32,xmmrm [rm: vex.128.f3.0f.w0 2d /r] AVX,SANDYBRIDGE,SD VCVTSS2SI reg64,xmmrm [rm: vex.128.f3.0f.w1 2d /r] AVX,SANDYBRIDGE,SD,LONG VCVTTPD2DQ xmmreg,xmmreg [rm: vex.128.66.0f e6 /r] AVX,SANDYBRIDGE @@ -2715,45 +2526,27 @@ VCVTTSD2SI reg32,xmmrm [rm: vex.128.f2.0f.w0 2c /r] AVX,SANDYBRIDGE,SQ VCVTTSD2SI reg64,xmmrm [rm: vex.128.f2.0f.w1 2c /r] AVX,SANDYBRIDGE,SQ,LONG VCVTTSS2SI reg32,xmmrm [rm: vex.128.f3.0f.w0 2c /r] AVX,SANDYBRIDGE,SD VCVTTSS2SI reg64,xmmrm [rm: vex.128.f3.0f.w1 2c /r] AVX,SANDYBRIDGE,SD,LONG -VDIVPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 5e /r] AVX,SANDYBRIDGE,SO -VDIVPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 5e /r] AVX,SANDYBRIDGE,SO -VDIVPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 5e /r] AVX,SANDYBRIDGE,SY -VDIVPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 5e /r] AVX,SANDYBRIDGE,SY -VDIVPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 5e /r] AVX,SANDYBRIDGE,SO -VDIVPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 5e /r] AVX,SANDYBRIDGE,SO -VDIVPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 5e /r] AVX,SANDYBRIDGE,SY -VDIVPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 5e /r] AVX,SANDYBRIDGE,SY -VDIVSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f 5e /r] AVX,SANDYBRIDGE,SQ -VDIVSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f 5e /r] AVX,SANDYBRIDGE,SQ -VDIVSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f 5e /r] AVX,SANDYBRIDGE,SD -VDIVSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f 5e /r] AVX,SANDYBRIDGE,SD -VDPPD xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 41 /r ib] AVX,SANDYBRIDGE,SO -VDPPD xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 41 /r ib] AVX,SANDYBRIDGE,SO -VDPPS xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 40 /r ib] AVX,SANDYBRIDGE,SO -VDPPS xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 40 /r ib] AVX,SANDYBRIDGE,SO -VDPPS ymmreg,ymmreg,ymmrm,imm [rvmi: vex.nds.256.66.0f3a 40 /r ib] AVX,SANDYBRIDGE,SY -VDPPS ymmreg,ymmrm,imm [r+vmi: vex.nds.256.66.0f3a 40 /r ib] AVX,SANDYBRIDGE,SY +VDIVPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 5e /r] AVX,SANDYBRIDGE,SO +VDIVPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f 5e /r] AVX,SANDYBRIDGE,SY +VDIVPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f 5e /r] AVX,SANDYBRIDGE,SO +VDIVPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f 5e /r] AVX,SANDYBRIDGE,SY +VDIVSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f 5e /r] AVX,SANDYBRIDGE,SQ +VDIVSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f 5e /r] AVX,SANDYBRIDGE,SD +VDPPD xmmreg,xmmreg*,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 41 /r ib] AVX,SANDYBRIDGE,SO +VDPPS xmmreg,xmmreg*,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 40 /r ib] AVX,SANDYBRIDGE,SO +VDPPS ymmreg,ymmreg*,ymmrm,imm [rvmi: vex.nds.256.66.0f3a 40 /r ib] AVX,SANDYBRIDGE,SY VEXTRACTF128 xmmrm,xmmreg,imm [mri: vex.256.66.0f3a 19 /r ib] AVX,SANDYBRIDGE,SO VEXTRACTPS rm32,xmmreg,imm [mri: vex.128.66.0f3a 17 /r ib] AVX,SANDYBRIDGE,SD -VHADDPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 7c /r] AVX,SANDYBRIDGE,SO -VHADDPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 7c /r] AVX,SANDYBRIDGE,SO -VHADDPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 7c /r] AVX,SANDYBRIDGE,SY -VHADDPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 7c /r] AVX,SANDYBRIDGE,SY -VHADDPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f 7c /r] AVX,SANDYBRIDGE,SO -VHADDPS xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f 7c /r] AVX,SANDYBRIDGE,SO -VHADDPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.f2.0f 7c /r] AVX,SANDYBRIDGE,SY -VHADDPS ymmreg,ymmrm [r+vm: vex.nds.256.f2.0f 7c /r] AVX,SANDYBRIDGE,SY -VHSUBPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 7d /r] AVX,SANDYBRIDGE,SO -VHSUBPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 7d /r] AVX,SANDYBRIDGE,SO -VHSUBPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 7d /r] AVX,SANDYBRIDGE,SY -VHSUBPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 7d /r] AVX,SANDYBRIDGE,SY -VHSUBPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f 7d /r] AVX,SANDYBRIDGE,SO -VHSUBPS xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f 7d /r] AVX,SANDYBRIDGE,SO -VHSUBPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.f2.0f 7d /r] AVX,SANDYBRIDGE,SY -VHSUBPS ymmreg,ymmrm [r+vm: vex.nds.256.f2.0f 7d /r] AVX,SANDYBRIDGE,SY +VHADDPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 7c /r] AVX,SANDYBRIDGE,SO +VHADDPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f 7c /r] AVX,SANDYBRIDGE,SY +VHADDPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f 7c /r] AVX,SANDYBRIDGE,SO +VHADDPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.f2.0f 7c /r] AVX,SANDYBRIDGE,SY +VHSUBPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 7d /r] AVX,SANDYBRIDGE,SO +VHSUBPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f 7d /r] AVX,SANDYBRIDGE,SY +VHSUBPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f 7d /r] AVX,SANDYBRIDGE,SO +VHSUBPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.f2.0f 7d /r] AVX,SANDYBRIDGE,SY VINSERTF128 ymmreg,ymmreg,xmmrm,imm [rvmi: vex.nds.256.66.0f3a 18 /r ib] AVX,SANDYBRIDGE,SO -VINSERTPS xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 21 /r ib] AVX,SANDYBRIDGE,SD -VINSERTPS xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 21 /r ib] AVX,SANDYBRIDGE,SD +VINSERTPS xmmreg,xmmreg*,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 21 /r ib] AVX,SANDYBRIDGE,SD VLDDQU xmmreg,mem [rm: vex.128.f2.0f f0 /r] AVX,SANDYBRIDGE,SO VLDQQU ymmreg,mem [rm: vex.256.f2.0f f0 /r] AVX,SANDYBRIDGE,SY VLDDQU ymmreg,mem [rm: vex.256.f2.0f f0 /r] AVX,SANDYBRIDGE,SY @@ -2767,30 +2560,18 @@ VMASKMOVPD xmmreg,xmmreg,mem [rvm: vex.nds.128.66.0f38 2d /r] AVX,SANDYBRIDGE, VMASKMOVPD ymmreg,ymmreg,mem [rvm: vex.nds.256.66.0f38 2d /r] AVX,SANDYBRIDGE,SY VMASKMOVPD mem,xmmreg,xmmreg [mvr: vex.nds.128.66.0f38 2f /r] AVX,SANDYBRIDGE,SO VMASKMOVPD mem,ymmreg,ymmreg [mvr: vex.nds.256.66.0f38 2f /r] AVX,SANDYBRIDGE,SY -VMAXPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 5f /r] AVX,SANDYBRIDGE,SO -VMAXPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 5f /r] AVX,SANDYBRIDGE,SO -VMAXPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 5f /r] AVX,SANDYBRIDGE,SY -VMAXPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 5f /r] AVX,SANDYBRIDGE,SY -VMAXPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 5f /r] AVX,SANDYBRIDGE,SO -VMAXPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 5f /r] AVX,SANDYBRIDGE,SO -VMAXPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 5f /r] AVX,SANDYBRIDGE,SY -VMAXPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 5f /r] AVX,SANDYBRIDGE,SY -VMAXSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f 5f /r] AVX,SANDYBRIDGE,SQ -VMAXSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f 5f /r] AVX,SANDYBRIDGE,SQ -VMAXSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f 5f /r] AVX,SANDYBRIDGE,SD -VMAXSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f 5f /r] AVX,SANDYBRIDGE,SD -VMINPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 5d /r] AVX,SANDYBRIDGE,SO -VMINPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 5d /r] AVX,SANDYBRIDGE,SO -VMINPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 5d /r] AVX,SANDYBRIDGE,SY -VMINPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 5d /r] AVX,SANDYBRIDGE,SY -VMINPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 5d /r] AVX,SANDYBRIDGE,SO -VMINPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 5d /r] AVX,SANDYBRIDGE,SO -VMINPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 5d /r] AVX,SANDYBRIDGE,SY -VMINPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 5d /r] AVX,SANDYBRIDGE,SY -VMINSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f 5d /r] AVX,SANDYBRIDGE,SQ -VMINSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f 5d /r] AVX,SANDYBRIDGE,SQ -VMINSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f 5d /r] AVX,SANDYBRIDGE,SD -VMINSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f 5d /r] AVX,SANDYBRIDGE,SD +VMAXPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 5f /r] AVX,SANDYBRIDGE,SO +VMAXPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f 5f /r] AVX,SANDYBRIDGE,SY +VMAXPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f 5f /r] AVX,SANDYBRIDGE,SO +VMAXPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f 5f /r] AVX,SANDYBRIDGE,SY +VMAXSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f 5f /r] AVX,SANDYBRIDGE,SQ +VMAXSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f 5f /r] AVX,SANDYBRIDGE,SD +VMINPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 5d /r] AVX,SANDYBRIDGE,SO +VMINPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f 5d /r] AVX,SANDYBRIDGE,SY +VMINPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f 5d /r] AVX,SANDYBRIDGE,SO +VMINPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f 5d /r] AVX,SANDYBRIDGE,SY +VMINSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f 5d /r] AVX,SANDYBRIDGE,SQ +VMINSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f 5d /r] AVX,SANDYBRIDGE,SD VMOVAPD xmmreg,xmmrm [rm: vex.128.66.0f 28 /r] AVX,SANDYBRIDGE,SO VMOVAPD xmmrm,xmmreg [mr: vex.128.66.0f 29 /r] AVX,SANDYBRIDGE,SO VMOVAPD ymmreg,ymmrm [rm: vex.256.66.0f 28 /r] AVX,SANDYBRIDGE,SY @@ -2821,21 +2602,15 @@ VMOVQQU ymmreg,ymmrm [rm: vex.256.f3.0f 6f /r] AVX,SANDYBRIDGE,SY VMOVQQU ymmrm,ymmreg [mr: vex.256.f3.0f 7f /r] AVX,SANDYBRIDGE,SY VMOVDQU ymmreg,ymmrm [rm: vex.256.f3.0f 6f /r] AVX,SANDYBRIDGE,SY VMOVDQU ymmrm,ymmreg [mr: vex.256.f3.0f 7f /r] AVX,SANDYBRIDGE,SY -VMOVHLPS xmmreg,xmmreg,xmmreg [rvm: vex.nds.128.0f 12 /r] AVX,SANDYBRIDGE -VMOVHLPS xmmreg,xmmreg [r+vm: vex.nds.128.0f 12 /r] AVX,SANDYBRIDGE -VMOVHPD xmmreg,xmmreg,mem [rvm: vex.nds.128.66.0f 16 /r] AVX,SANDYBRIDGE,SQ -VMOVHPD xmmreg,mem [r+vm: vex.nds.128.66.0f 16 /r] AVX,SANDYBRIDGE,SQ +VMOVHLPS xmmreg,xmmreg*,xmmreg [rvm: vex.nds.128.0f 12 /r] AVX,SANDYBRIDGE +VMOVHPD xmmreg,xmmreg*,mem [rvm: vex.nds.128.66.0f 16 /r] AVX,SANDYBRIDGE,SQ VMOVHPD mem,xmmreg [mr: vex.128.66.0f 17 /r] AVX,SANDYBRIDGE,SQ -VMOVHPS xmmreg,xmmreg,mem [rvm: vex.nds.128.0f 16 /r] AVX,SANDYBRIDGE,SQ -VMOVHPS xmmreg,mem [r+vm: vex.nds.128.0f 16 /r] AVX,SANDYBRIDGE,SQ +VMOVHPS xmmreg,xmmreg*,mem [rvm: vex.nds.128.0f 16 /r] AVX,SANDYBRIDGE,SQ VMOVHPS mem,xmmreg [mr: vex.128.0f 17 /r] AVX,SANDYBRIDGE,SQ -VMOVLHPS xmmreg,xmmreg,xmmreg [rvm: vex.nds.128.0f 16 /r] AVX,SANDYBRIDGE -VMOVLHPS xmmreg,xmmreg [r+vm: vex.nds.128.0f 16 /r] AVX,SANDYBRIDGE -VMOVLPD xmmreg,xmmreg,mem [rvm: vex.nds.128.66.0f 12 /r] AVX,SANDYBRIDGE,SQ -VMOVLPD xmmreg,mem [r+vm: vex.nds.128.66.0f 12 /r] AVX,SANDYBRIDGE,SQ +VMOVLHPS xmmreg,xmmreg*,xmmreg [rvm: vex.nds.128.0f 16 /r] AVX,SANDYBRIDGE +VMOVLPD xmmreg,xmmreg*,mem [rvm: vex.nds.128.66.0f 12 /r] AVX,SANDYBRIDGE,SQ VMOVLPD mem,xmmreg [mr: vex.128.66.0f 13 /r] AVX,SANDYBRIDGE,SQ -VMOVLPS xmmreg,xmmreg,mem [rvm: vex.nds.128.0f 12 /r] AVX,SANDYBRIDGE,SQ -VMOVLPS xmmreg,mem [r+vm: vex.nds.128.0f 12 /r] AVX,SANDYBRIDGE,SQ +VMOVLPS xmmreg,xmmreg*,mem [rvm: vex.nds.128.0f 12 /r] AVX,SANDYBRIDGE,SQ VMOVLPS mem,xmmreg [mr: vex.128.0f 13 /r] AVX,SANDYBRIDGE,SQ VMOVMSKPD reg64,xmmreg [rm: vex.128.66.0f 50 /r] AVX,SANDYBRIDGE,LONG VMOVMSKPD reg32,xmmreg [rm: vex.128.66.0f 50 /r] AVX,SANDYBRIDGE @@ -2854,21 +2629,17 @@ VMOVNTPD mem,xmmreg [mr: vex.128.66.0f 2b /r] AVX,SANDYBRIDGE,SO VMOVNTPD mem,ymmreg [mr: vex.256.66.0f 2b /r] AVX,SANDYBRIDGE,SY VMOVNTPS mem,xmmreg [mr: vex.128.0f 2b /r] AVX,SANDYBRIDGE,SO VMOVNTPS mem,ymmreg [mr: vex.256.0f 2b /r] AVX,SANDYBRIDGE,SO -VMOVSD xmmreg,xmmreg,xmmreg [rvm: vex.nds.128.f2.0f 10 /r] AVX,SANDYBRIDGE -VMOVSD xmmreg,xmmreg [r+vm: vex.nds.128.f2.0f 10 /r] AVX,SANDYBRIDGE +VMOVSD xmmreg,xmmreg*,xmmreg [rvm: vex.nds.128.f2.0f 10 /r] AVX,SANDYBRIDGE VMOVSD xmmreg,mem [rm: vex.128.f2.0f 10 /r] AVX,SANDYBRIDGE,SQ -VMOVSD xmmreg,xmmreg,xmmreg [mvr: vex.nds.128.f2.0f 11 /r] AVX,SANDYBRIDGE -VMOVSD xmmreg,xmmreg [m+vr: vex.nds.128.f2.0f 11 /r] AVX,SANDYBRIDGE +VMOVSD xmmreg,xmmreg*,xmmreg [mvr: vex.nds.128.f2.0f 11 /r] AVX,SANDYBRIDGE VMOVSD mem,xmmreg [mr: vex.128.f2.0f 11 /r] AVX,SANDYBRIDGE,SQ VMOVSHDUP xmmreg,xmmrm [rm: vex.128.f3.0f 16 /r] AVX,SANDYBRIDGE,SO VMOVSHDUP ymmreg,ymmrm [rm: vex.256.f3.0f 16 /r] AVX,SANDYBRIDGE,SY VMOVSLDUP xmmreg,xmmrm [rm: vex.128.f3.0f 12 /r] AVX,SANDYBRIDGE,SO VMOVSLDUP ymmreg,ymmrm [rm: vex.256.f3.0f 12 /r] AVX,SANDYBRIDGE,SY -VMOVSS xmmreg,xmmreg,xmmreg [rvm: vex.nds.128.f3.0f 10 /r] AVX,SANDYBRIDGE -VMOVSS xmmreg,xmmreg [r+vm: vex.nds.128.f3.0f 10 /r] AVX,SANDYBRIDGE +VMOVSS xmmreg,xmmreg*,xmmreg [rvm: vex.nds.128.f3.0f 10 /r] AVX,SANDYBRIDGE VMOVSS xmmreg,mem [rm: vex.128.f3.0f 10 /r] AVX,SANDYBRIDGE,SQ -VMOVSS xmmreg,xmmreg,xmmreg [mvr: vex.nds.128.f3.0f 11 /r] AVX,SANDYBRIDGE -VMOVSS xmmreg,xmmreg [m+vr: vex.nds.128.f3.0f 11 /r] AVX,SANDYBRIDGE +VMOVSS xmmreg,xmmreg*,xmmreg [mvr: vex.nds.128.f3.0f 11 /r] AVX,SANDYBRIDGE VMOVSS mem,xmmreg [mr: vex.128.f3.0f 11 /r] AVX,SANDYBRIDGE,SQ VMOVUPD xmmreg,xmmrm [rm: vex.128.66.0f 10 /r] AVX,SANDYBRIDGE,SO VMOVUPD xmmrm,xmmreg [mr: vex.128.66.0f 11 /r] AVX,SANDYBRIDGE,SO @@ -2878,89 +2649,51 @@ VMOVUPS xmmreg,xmmrm [rm: vex.128.0f 10 /r] AVX,SANDYBRIDGE,SO VMOVUPS xmmrm,xmmreg [mr: vex.128.0f 11 /r] AVX,SANDYBRIDGE,SO VMOVUPS ymmreg,ymmrm [rm: vex.256.0f 10 /r] AVX,SANDYBRIDGE,SY VMOVUPS ymmrm,ymmreg [mr: vex.256.0f 11 /r] AVX,SANDYBRIDGE,SY -VMPSADBW xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 42 /r ib] AVX,SANDYBRIDGE,SO -VMPSADBW xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 42 /r ib] AVX,SANDYBRIDGE,SO -VMULPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 59 /r] AVX,SANDYBRIDGE,SO -VMULPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 59 /r] AVX,SANDYBRIDGE,SO -VMULPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 59 /r] AVX,SANDYBRIDGE,SY -VMULPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 59 /r] AVX,SANDYBRIDGE,SY -VMULPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 59 /r] AVX,SANDYBRIDGE,SO -VMULPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 59 /r] AVX,SANDYBRIDGE,SO -VMULPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 59 /r] AVX,SANDYBRIDGE,SY -VMULPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 59 /r] AVX,SANDYBRIDGE,SY -VMULSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f 59 /r] AVX,SANDYBRIDGE,SQ -VMULSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f 59 /r] AVX,SANDYBRIDGE,SQ -VMULSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f 59 /r] AVX,SANDYBRIDGE,SD -VMULSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f 59 /r] AVX,SANDYBRIDGE,SD -VORPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 56 /r] AVX,SANDYBRIDGE,SO -VORPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 56 /r] AVX,SANDYBRIDGE,SO -VORPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 56 /r] AVX,SANDYBRIDGE,SY -VORPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 56 /r] AVX,SANDYBRIDGE,SY -VORPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 56 /r] AVX,SANDYBRIDGE,SO -VORPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 56 /r] AVX,SANDYBRIDGE,SO -VORPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 56 /r] AVX,SANDYBRIDGE,SY -VORPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 56 /r] AVX,SANDYBRIDGE,SY +VMPSADBW xmmreg,xmmreg*,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 42 /r ib] AVX,SANDYBRIDGE,SO +VMULPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 59 /r] AVX,SANDYBRIDGE,SO +VMULPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f 59 /r] AVX,SANDYBRIDGE,SY +VMULPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f 59 /r] AVX,SANDYBRIDGE,SO +VMULPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f 59 /r] AVX,SANDYBRIDGE,SY +VMULSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f 59 /r] AVX,SANDYBRIDGE,SQ +VMULSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f 59 /r] AVX,SANDYBRIDGE,SD +VORPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 56 /r] AVX,SANDYBRIDGE,SO +VORPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f 56 /r] AVX,SANDYBRIDGE,SY +VORPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f 56 /r] AVX,SANDYBRIDGE,SO +VORPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f 56 /r] AVX,SANDYBRIDGE,SY VPABSB xmmreg,xmmrm [rm: vex.128.66.0f38 1c /r] AVX,SANDYBRIDGE,SO VPABSW xmmreg,xmmrm [rm: vex.128.66.0f38 1d /r] AVX,SANDYBRIDGE,SO VPABSD xmmreg,xmmrm [rm: vex.128.66.0f38 1e /r] AVX,SANDYBRIDGE,SO -VPACKSSWB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 63 /r] AVX,SANDYBRIDGE,SO -VPACKSSWB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 63 /r] AVX,SANDYBRIDGE,SO -VPACKSSDW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 6b /r] AVX,SANDYBRIDGE,SO -VPACKSSDW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 6b /r] AVX,SANDYBRIDGE,SO -VPACKUSWB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 67 /r] AVX,SANDYBRIDGE,SO -VPACKUSWB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 67 /r] AVX,SANDYBRIDGE,SO -VPACKUSDW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 2b /r] AVX,SANDYBRIDGE,SO -VPACKUSDW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 2b /r] AVX,SANDYBRIDGE,SO -VPADDB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f fc /r] AVX,SANDYBRIDGE,SO -VPADDB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f fc /r] AVX,SANDYBRIDGE,SO -VPADDW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f fd /r] AVX,SANDYBRIDGE,SO -VPADDW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f fd /r] AVX,SANDYBRIDGE,SO -VPADDD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f fe /r] AVX,SANDYBRIDGE,SO -VPADDD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f fe /r] AVX,SANDYBRIDGE,SO -VPADDQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f d4 /r] AVX,SANDYBRIDGE,SO -VPADDQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f d4 /r] AVX,SANDYBRIDGE,SO -VPADDSB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f ec /r] AVX,SANDYBRIDGE,SO -VPADDSB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f ec /r] AVX,SANDYBRIDGE,SO -VPADDSW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f ed /r] AVX,SANDYBRIDGE,SO -VPADDSW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f ed /r] AVX,SANDYBRIDGE,SO -VPADDUSB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f dc /r] AVX,SANDYBRIDGE,SO -VPADDUSB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f dc /r] AVX,SANDYBRIDGE,SO -VPADDUSW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f dd /r] AVX,SANDYBRIDGE,SO -VPADDUSW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f dd /r] AVX,SANDYBRIDGE,SO -VPALIGNR xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 0f /r ib] AVX,SANDYBRIDGE,SO -VPALIGNR xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 0f /r ib] AVX,SANDYBRIDGE,SO -VPAND xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f db /r] AVX,SANDYBRIDGE,SO -VPAND xmmreg,xmmrm [r+vm: vex.nds.128.66.0f db /r] AVX,SANDYBRIDGE,SO -VPANDN xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f df /r] AVX,SANDYBRIDGE,SO -VPANDN xmmreg,xmmrm [r+vm: vex.nds.128.66.0f df /r] AVX,SANDYBRIDGE,SO -VPAVGB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f e0 /r] AVX,SANDYBRIDGE,SO -VPAVGB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f e0 /r] AVX,SANDYBRIDGE,SO -VPAVGW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f e3 /r] AVX,SANDYBRIDGE,SO -VPAVGW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f e3 /r] AVX,SANDYBRIDGE,SO -VPBLENDVB xmmreg,xmmreg,xmmrm,xmmreg [rvms: vex.nds.128.66.0f3a 4c /r /is4] AVX,SANDYBRIDGE,SO -VPBLENDVB xmmreg,xmmrm,xmmreg [r+vms: vex.nds.128.66.0f3a 4c /r /is4] AVX,SANDYBRIDGE,SO -VPBLENDW xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 0e /r ib] AVX,SANDYBRIDGE,SO -VPBLENDW xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 0e /r ib] AVX,SANDYBRIDGE,SO +VPACKSSWB xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 63 /r] AVX,SANDYBRIDGE,SO +VPACKSSDW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 6b /r] AVX,SANDYBRIDGE,SO +VPACKUSWB xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 67 /r] AVX,SANDYBRIDGE,SO +VPACKUSDW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 2b /r] AVX,SANDYBRIDGE,SO +VPADDB xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f fc /r] AVX,SANDYBRIDGE,SO +VPADDW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f fd /r] AVX,SANDYBRIDGE,SO +VPADDD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f fe /r] AVX,SANDYBRIDGE,SO +VPADDQ xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f d4 /r] AVX,SANDYBRIDGE,SO +VPADDSB xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f ec /r] AVX,SANDYBRIDGE,SO +VPADDSW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f ed /r] AVX,SANDYBRIDGE,SO +VPADDUSB xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f dc /r] AVX,SANDYBRIDGE,SO +VPADDUSW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f dd /r] AVX,SANDYBRIDGE,SO +VPALIGNR xmmreg,xmmreg*,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 0f /r ib] AVX,SANDYBRIDGE,SO +VPAND xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f db /r] AVX,SANDYBRIDGE,SO +VPANDN xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f df /r] AVX,SANDYBRIDGE,SO +VPAVGB xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f e0 /r] AVX,SANDYBRIDGE,SO +VPAVGW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f e3 /r] AVX,SANDYBRIDGE,SO +VPBLENDVB xmmreg,xmmreg*,xmmrm,xmmreg [rvms: vex.nds.128.66.0f3a 4c /r /is4] AVX,SANDYBRIDGE,SO +VPBLENDW xmmreg,xmmreg*,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 0e /r ib] AVX,SANDYBRIDGE,SO VPCMPESTRI xmmreg,xmmrm,imm [rmi: vex.128.66.0f3a 61 /r ib] AVX,SANDYBRIDGE,SO VPCMPESTRM xmmreg,xmmrm,imm [rmi: vex.128.66.0f3a 60 /r ib] AVX,SANDYBRIDGE,SO VPCMPISTRI xmmreg,xmmrm,imm [rmi: vex.128.66.0f3a 63 /r ib] AVX,SANDYBRIDGE,SO VPCMPISTRM xmmreg,xmmrm,imm [rmi: vex.128.66.0f3a 62 /r ib] AVX,SANDYBRIDGE,SO -VPCMPEQB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 74 /r] AVX,SANDYBRIDGE,SO -VPCMPEQB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 74 /r] AVX,SANDYBRIDGE,SO -VPCMPEQW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 75 /r] AVX,SANDYBRIDGE,SO -VPCMPEQW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 75 /r] AVX,SANDYBRIDGE,SO -VPCMPEQD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 76 /r] AVX,SANDYBRIDGE,SO -VPCMPEQD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 76 /r] AVX,SANDYBRIDGE,SO -VPCMPEQQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 29 /r] AVX,SANDYBRIDGE,SO -VPCMPEQQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 29 /r] AVX,SANDYBRIDGE,SO -VPCMPGTB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 64 /r] AVX,SANDYBRIDGE,SO -VPCMPGTB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 64 /r] AVX,SANDYBRIDGE,SO -VPCMPGTW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 65 /r] AVX,SANDYBRIDGE,SO -VPCMPGTW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 65 /r] AVX,SANDYBRIDGE,SO -VPCMPGTD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 66 /r] AVX,SANDYBRIDGE,SO -VPCMPGTD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 66 /r] AVX,SANDYBRIDGE,SO -VPCMPGTQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 37 /r] AVX,SANDYBRIDGE,SO -VPCMPGTQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 37 /r] AVX,SANDYBRIDGE,SO +VPCMPEQB xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 74 /r] AVX,SANDYBRIDGE,SO +VPCMPEQW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 75 /r] AVX,SANDYBRIDGE,SO +VPCMPEQD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 76 /r] AVX,SANDYBRIDGE,SO +VPCMPEQQ xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 29 /r] AVX,SANDYBRIDGE,SO +VPCMPGTB xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 64 /r] AVX,SANDYBRIDGE,SO +VPCMPGTW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 65 /r] AVX,SANDYBRIDGE,SO +VPCMPGTD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 66 /r] AVX,SANDYBRIDGE,SO +VPCMPGTQ xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 37 /r] AVX,SANDYBRIDGE,SO VPERMILPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 0d /r] AVX,SANDYBRIDGE,SO VPERMILPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f38 0d /r] AVX,SANDYBRIDGE,SY VPERMILPD xmmreg,xmmrm,imm [rmi: vex.128.66.0f3a 05 /r ib] AVX,SANDYBRIDGE,SO @@ -3014,59 +2747,37 @@ VPEXTRW mem,xmmreg,imm [mri: vex.128.66.0f3a.w0 15 /r ib] AVX,SANDYBRIDGE,SW VPEXTRD reg64,xmmreg,imm [mri: vex.128.66.0f3a.w0 16 /r ib] AVX,SANDYBRIDGE,LONG VPEXTRD rm32,xmmreg,imm [mri: vex.128.66.0f3a.w0 16 /r ib] AVX,SANDYBRIDGE,SD VPEXTRQ rm64,xmmreg,imm [mri: vex.128.66.0f3a.w1 16 /r ib] AVX,SANDYBRIDGE,SQ,LONG -VPHADDW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 01 /r] AVX,SANDYBRIDGE,SO -VPHADDW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 01 /r] AVX,SANDYBRIDGE,SO -VPHADDD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 02 /r] AVX,SANDYBRIDGE,SO -VPHADDD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 02 /r] AVX,SANDYBRIDGE,SO -VPHADDSW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 03 /r] AVX,SANDYBRIDGE,SO -VPHADDSW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 03 /r] AVX,SANDYBRIDGE,SO +VPHADDW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 01 /r] AVX,SANDYBRIDGE,SO +VPHADDD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 02 /r] AVX,SANDYBRIDGE,SO +VPHADDSW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 03 /r] AVX,SANDYBRIDGE,SO VPHMINPOSUW xmmreg,xmmrm [rm: vex.128.66.0f38 41 /r] AVX,SANDYBRIDGE,SO -VPHSUBW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 05 /r] AVX,SANDYBRIDGE,SO -VPHSUBW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 05 /r] AVX,SANDYBRIDGE,SO -VPHSUBD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 06 /r] AVX,SANDYBRIDGE,SO -VPHSUBD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 06 /r] AVX,SANDYBRIDGE,SO -VPHSUBSW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 07 /r] AVX,SANDYBRIDGE,SO -VPHSUBSW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 07 /r] AVX,SANDYBRIDGE,SO -VPINSRB xmmreg,xmmreg,reg32,imm [rvmi: vex.nds.128.66.0f3a 20 /r ib] AVX,SANDYBRIDGE -VPINSRB xmmreg,reg32,imm [r+vmi: vex.nds.128.66.0f3a 20 /r ib] AVX,SANDYBRIDGE -VPINSRB xmmreg,xmmreg,mem,imm [rvmi: vex.nds.128.66.0f3a 20 /r ib] AVX,SANDYBRIDGE,SB -VPINSRB xmmreg,reg32,mem,imm [r+vmi: vex.nds.128.66.0f3a 20 /r ib] AVX,SANDYBRIDGE,SB -VPINSRW xmmreg,xmmreg,reg32,imm [rvmi: vex.nds.128.66.0f c4 /r ib] AVX,SANDYBRIDGE -VPINSRW xmmreg,reg32,imm [r+vmi: vex.nds.128.66.0f c4 /r ib] AVX,SANDYBRIDGE -VPINSRW xmmreg,xmmreg,mem,imm [rvmi: vex.nds.128.66.0f c4 /r ib] AVX,SANDYBRIDGE,SW -VPINSRW xmmreg,reg32,mem,imm [r+vmi: vex.nds.128.66.0f c4 /r ib] AVX,SANDYBRIDGE,SW -VPINSRD xmmreg,xmmreg,rm32,imm [rvmi: vex.nds.128.66.0f3a.w0 22 /r ib] AVX,SANDYBRIDGE,SD -VPINSRD xmmreg,rm32,imm [r+vmi: vex.nds.128.66.0f3a.w0 22 /r ib] AVX,SANDYBRIDGE,SD -VPINSRQ xmmreg,xmmreg,rm64,imm [rvmi: vex.nds.128.66.0f3a.w1 22 /r ib] AVX,SANDYBRIDGE,SQ,LONG -VPINSRQ xmmreg,rm64,imm [r+vmi: vex.nds.128.66.0f3a.w1 22 /r ib] AVX,SANDYBRIDGE,SD,LONG -VPMADDWD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f f5 /r] AVX,SANDYBRIDGE,SO -VPMADDWD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f f5 /r] AVX,SANDYBRIDGE,SO -VPMADDUBSW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 04 /r] AVX,SANDYBRIDGE,SO -VPMADDUBSW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 04 /r] AVX,SANDYBRIDGE,SO -VPMAXSB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 3c /r] AVX,SANDYBRIDGE,SO -VPMAXSB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 3c /r] AVX,SANDYBRIDGE,SO -VPMAXSW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f ee /r] AVX,SANDYBRIDGE,SO -VPMAXSW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f ee /r] AVX,SANDYBRIDGE,SO -VPMAXSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 3d /r] AVX,SANDYBRIDGE,SO -VPMAXSD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 3d /r] AVX,SANDYBRIDGE,SO -VPMAXUB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f de /r] AVX,SANDYBRIDGE,SO -VPMAXUB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f de /r] AVX,SANDYBRIDGE,SO -VPMAXUW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 3e /r] AVX,SANDYBRIDGE,SO -VPMAXUW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 3e /r] AVX,SANDYBRIDGE,SO -VPMAXUD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 3f /r] AVX,SANDYBRIDGE,SO -VPMAXUD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 3f /r] AVX,SANDYBRIDGE,SO -VPMINSB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 38 /r] AVX,SANDYBRIDGE,SO -VPMINSB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 38 /r] AVX,SANDYBRIDGE,SO -VPMINSW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f ea /r] AVX,SANDYBRIDGE,SO -VPMINSW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f ea /r] AVX,SANDYBRIDGE,SO -VPMINSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 39 /r] AVX,SANDYBRIDGE,SO -VPMINSD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 39 /r] AVX,SANDYBRIDGE,SO -VPMINUB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f da /r] AVX,SANDYBRIDGE,SO -VPMINUB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f da /r] AVX,SANDYBRIDGE,SO -VPMINUW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 3a /r] AVX,SANDYBRIDGE,SO -VPMINUW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 3a /r] AVX,SANDYBRIDGE,SO -VPMINUD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 3b /r] AVX,SANDYBRIDGE,SO -VPMINUD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 3b /r] AVX,SANDYBRIDGE,SO +VPHSUBW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 05 /r] AVX,SANDYBRIDGE,SO +VPHSUBD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 06 /r] AVX,SANDYBRIDGE,SO +VPHSUBSW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 07 /r] AVX,SANDYBRIDGE,SO +VPINSRB xmmreg,xmmreg*,mem,imm [rvmi: vex.nds.128.66.0f3a 20 /r ib] AVX,SANDYBRIDGE,SB,AR3 +VPINSRB xmmreg,xmmreg*,rm8,imm [rvmi: vex.nds.128.66.0f3a 20 /r ib] AVX,SANDYBRIDGE,SB,AR3 +VPINSRB xmmreg,xmmreg*,reg32,imm [rvmi: vex.nds.128.66.0f3a 20 /r ib] AVX,SANDYBRIDGE,SB,AR3 +VPINSRW xmmreg,xmmreg*,mem,imm [rvmi: vex.nds.128.66.0f c4 /r ib] AVX,SANDYBRIDGE,SB,AR3 +VPINSRW xmmreg,xmmreg*,rm16,imm [rvmi: vex.nds.128.66.0f c4 /r ib] AVX,SANDYBRIDGE,SB,AR3 +VPINSRW xmmreg,xmmreg*,reg32,imm [rvmi: vex.nds.128.66.0f c4 /r ib] AVX,SANDYBRIDGE,SB,AR3 +VPINSRD xmmreg,xmmreg*,mem,imm [rvmi: vex.nds.128.66.0f3a.w0 22 /r ib] AVX,SANDYBRIDGE,SB,AR3 +VPINSRD xmmreg,xmmreg*,rm32,imm [rvmi: vex.nds.128.66.0f3a.w0 22 /r ib] AVX,SANDYBRIDGE,SB,AR3 +VPINSRQ xmmreg,xmmreg*,mem,imm [rvmi: vex.nds.128.66.0f3a.w1 22 /r ib] AVX,SANDYBRIDGE,SB,AR3,LONG +VPINSRQ xmmreg,xmmreg*,rm64,imm [rvmi: vex.nds.128.66.0f3a.w1 22 /r ib] AVX,SANDYBRIDGE,SB,AR3,LONG +VPMADDWD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f f5 /r] AVX,SANDYBRIDGE,SO +VPMADDUBSW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 04 /r] AVX,SANDYBRIDGE,SO +VPMAXSB xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 3c /r] AVX,SANDYBRIDGE,SO +VPMAXSW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f ee /r] AVX,SANDYBRIDGE,SO +VPMAXSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 3d /r] AVX,SANDYBRIDGE,SO +VPMAXUB xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f de /r] AVX,SANDYBRIDGE,SO +VPMAXUW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 3e /r] AVX,SANDYBRIDGE,SO +VPMAXUD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 3f /r] AVX,SANDYBRIDGE,SO +VPMINSB xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 38 /r] AVX,SANDYBRIDGE,SO +VPMINSW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f ea /r] AVX,SANDYBRIDGE,SO +VPMINSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 39 /r] AVX,SANDYBRIDGE,SO +VPMINUB xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f da /r] AVX,SANDYBRIDGE,SO +VPMINUW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 3a /r] AVX,SANDYBRIDGE,SO +VPMINUD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 3b /r] AVX,SANDYBRIDGE,SO VPMOVMSKB reg64,xmmreg [rm: vex.128.66.0f d7 /r] AVX,SANDYBRIDGE,LONG VPMOVMSKB reg32,xmmreg [rm: vex.128.66.0f d7 /r] AVX,SANDYBRIDGE VPMOVSXBW xmmreg,xmmrm [rm: vex.128.66.0f38 20 /r] AVX,SANDYBRIDGE,SQ @@ -3081,259 +2792,316 @@ VPMOVZXBQ xmmreg,xmmrm [rm: vex.128.66.0f38 32 /r] AVX,SANDYBRIDGE,SW VPMOVZXWD xmmreg,xmmrm [rm: vex.128.66.0f38 33 /r] AVX,SANDYBRIDGE,SQ VPMOVZXWQ xmmreg,xmmrm [rm: vex.128.66.0f38 34 /r] AVX,SANDYBRIDGE,SD VPMOVZXDQ xmmreg,xmmrm [rm: vex.128.66.0f38 35 /r] AVX,SANDYBRIDGE,SQ -VPMULHUW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f e4 /r] AVX,SANDYBRIDGE,SO -VPMULHUW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f e4 /r] AVX,SANDYBRIDGE,SO -VPMULHRSW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 0b /r] AVX,SANDYBRIDGE,SO -VPMULHRSW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 0b /r] AVX,SANDYBRIDGE,SO -VPMULHW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f e5 /r] AVX,SANDYBRIDGE,SO -VPMULHW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f e5 /r] AVX,SANDYBRIDGE,SO -VPMULLW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f d5 /r] AVX,SANDYBRIDGE,SO -VPMULLW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f d5 /r] AVX,SANDYBRIDGE,SO -VPMULLD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 40 /r] AVX,SANDYBRIDGE,SO -VPMULLD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 40 /r] AVX,SANDYBRIDGE,SO -VPMULUDQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f f4 /r] AVX,SANDYBRIDGE,SO -VPMULUDQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f f4 /r] AVX,SANDYBRIDGE,SO -VPMULDQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 28 /r] AVX,SANDYBRIDGE,SO -VPMULDQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 28 /r] AVX,SANDYBRIDGE,SO -VPOR xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f eb /r] AVX,SANDYBRIDGE,SO -VPOR xmmreg,xmmrm [r+vm: vex.nds.128.66.0f eb /r] AVX,SANDYBRIDGE,SO -VPSADBW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f f6 /r] AVX,SANDYBRIDGE,SO -VPSADBW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f f6 /r] AVX,SANDYBRIDGE,SO -VPSHUFB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 00 /r] AVX,SANDYBRIDGE,SO -VPSHUFB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 00 /r] AVX,SANDYBRIDGE,SO +VPMULHUW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f e4 /r] AVX,SANDYBRIDGE,SO +VPMULHRSW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 0b /r] AVX,SANDYBRIDGE,SO +VPMULHW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f e5 /r] AVX,SANDYBRIDGE,SO +VPMULLW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f d5 /r] AVX,SANDYBRIDGE,SO +VPMULLD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 40 /r] AVX,SANDYBRIDGE,SO +VPMULUDQ xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f f4 /r] AVX,SANDYBRIDGE,SO +VPMULDQ xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 28 /r] AVX,SANDYBRIDGE,SO +VPOR xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f eb /r] AVX,SANDYBRIDGE,SO +VPSADBW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f f6 /r] AVX,SANDYBRIDGE,SO +VPSHUFB xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 00 /r] AVX,SANDYBRIDGE,SO VPSHUFD xmmreg,xmmrm,imm [rmi: vex.128.66.0f 70 /r ib] AVX,SANDYBRIDGE,SO VPSHUFHW xmmreg,xmmrm,imm [rmi: vex.128.f3.0f 70 /r ib] AVX,SANDYBRIDGE,SO VPSHUFLW xmmreg,xmmrm,imm [rmi: vex.128.f2.0f 70 /r ib] AVX,SANDYBRIDGE,SO -VPSIGNB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 08 /r] AVX,SANDYBRIDGE,SO -VPSIGNB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 08 /r] AVX,SANDYBRIDGE,SO -VPSIGNW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 09 /r] AVX,SANDYBRIDGE,SO -VPSIGNW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 09 /r] AVX,SANDYBRIDGE,SO -VPSIGND xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 0a /r] AVX,SANDYBRIDGE,SO -VPSIGND xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 0a /r] AVX,SANDYBRIDGE,SO -VPSLLDQ xmmreg,xmmreg,imm [vmi: vex.ndd.128.66.0f 73 /7 ib] AVX,SANDYBRIDGE -VPSLLDQ xmmreg,imm [v+mi: vex.ndd.128.66.0f 73 /7 ib] AVX,SANDYBRIDGE -VPSRLDQ xmmreg,xmmreg,imm [vmi: vex.ndd.128.66.0f 73 /3 ib] AVX,SANDYBRIDGE -VPSRLDQ xmmreg,imm [v+mi: vex.ndd.128.66.0f 73 /3 ib] AVX,SANDYBRIDGE -VPSLLW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f f1 /r] AVX,SANDYBRIDGE,SO -VPSLLW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f f1 /r] AVX,SANDYBRIDGE,SO -VPSLLW xmmreg,xmmreg,imm [vmi: vex.ndd.128.66.0f 71 /6 ib] AVX,SANDYBRIDGE -VPSLLW xmmreg,imm [v+mi: vex.ndd.128.66.0f 71 /6 ib] AVX,SANDYBRIDGE -VPSLLD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f f2 /r] AVX,SANDYBRIDGE,SO -VPSLLD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f f2 /r] AVX,SANDYBRIDGE,SO -VPSLLD xmmreg,xmmreg,imm [vmi: vex.ndd.128.66.0f 72 /6 ib] AVX,SANDYBRIDGE -VPSLLD xmmreg,imm [v+mi: vex.ndd.128.66.0f 72 /6 ib] AVX,SANDYBRIDGE -VPSLLQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f f3 /r] AVX,SANDYBRIDGE,SO -VPSLLQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f f3 /r] AVX,SANDYBRIDGE,SO -VPSLLQ xmmreg,xmmreg,imm [vmi: vex.ndd.128.66.0f 73 /6 ib] AVX,SANDYBRIDGE -VPSLLQ xmmreg,imm [v+mi: vex.ndd.128.66.0f 73 /6 ib] AVX,SANDYBRIDGE -VPSRAW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f e1 /r] AVX,SANDYBRIDGE,SO -VPSRAW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f e1 /r] AVX,SANDYBRIDGE,SO -VPSRAW xmmreg,xmmreg,imm [vmi: vex.ndd.128.66.0f 71 /4 ib] AVX,SANDYBRIDGE -VPSRAW xmmreg,imm [v+mi: vex.ndd.128.66.0f 71 /4 ib] AVX,SANDYBRIDGE -VPSRAD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f e2 /r] AVX,SANDYBRIDGE,SO -VPSRAD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f e2 /r] AVX,SANDYBRIDGE,SO -VPSRAD xmmreg,xmmreg,imm [vmi: vex.ndd.128.66.0f 72 /4 ib] AVX,SANDYBRIDGE -VPSRAD xmmreg,imm [v+mi: vex.ndd.128.66.0f 72 /4 ib] AVX,SANDYBRIDGE -VPSRLW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f d1 /r] AVX,SANDYBRIDGE,SO -VPSRLW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f d1 /r] AVX,SANDYBRIDGE,SO -VPSRLW xmmreg,xmmreg,imm [vmi: vex.ndd.128.66.0f 71 /2 ib] AVX,SANDYBRIDGE -VPSRLW xmmreg,imm [v+mi: vex.ndd.128.66.0f 71 /2 ib] AVX,SANDYBRIDGE -VPSRLD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f d2 /r] AVX,SANDYBRIDGE,SO -VPSRLD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f d2 /r] AVX,SANDYBRIDGE,SO -VPSRLD xmmreg,xmmreg,imm [vmi: vex.ndd.128.66.0f 72 /2 ib] AVX,SANDYBRIDGE -VPSRLD xmmreg,imm [v+mi: vex.ndd.128.66.0f 72 /2 ib] AVX,SANDYBRIDGE -VPSRLQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f d3 /r] AVX,SANDYBRIDGE,SO -VPSRLQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f d3 /r] AVX,SANDYBRIDGE,SO -VPSRLQ xmmreg,xmmreg,imm [vmi: vex.ndd.128.66.0f 73 /2 ib] AVX,SANDYBRIDGE -VPSRLQ xmmreg,imm [v+mi: vex.ndd.128.66.0f 73 /2 ib] AVX,SANDYBRIDGE +VPSIGNB xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 08 /r] AVX,SANDYBRIDGE,SO +VPSIGNW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 09 /r] AVX,SANDYBRIDGE,SO +VPSIGND xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f38 0a /r] AVX,SANDYBRIDGE,SO +VPSLLDQ xmmreg,xmmreg*,imm [vmi: vex.ndd.128.66.0f 73 /7 ib] AVX,SANDYBRIDGE +VPSRLDQ xmmreg,xmmreg*,imm [vmi: vex.ndd.128.66.0f 73 /3 ib] AVX,SANDYBRIDGE +VPSLLW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f f1 /r] AVX,SANDYBRIDGE,SO +VPSLLW xmmreg,xmmreg*,imm [vmi: vex.ndd.128.66.0f 71 /6 ib] AVX,SANDYBRIDGE +VPSLLD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f f2 /r] AVX,SANDYBRIDGE,SO +VPSLLD xmmreg,xmmreg*,imm [vmi: vex.ndd.128.66.0f 72 /6 ib] AVX,SANDYBRIDGE +VPSLLQ xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f f3 /r] AVX,SANDYBRIDGE,SO +VPSLLQ xmmreg,xmmreg*,imm [vmi: vex.ndd.128.66.0f 73 /6 ib] AVX,SANDYBRIDGE +VPSRAW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f e1 /r] AVX,SANDYBRIDGE,SO +VPSRAW xmmreg,xmmreg*,imm [vmi: vex.ndd.128.66.0f 71 /4 ib] AVX,SANDYBRIDGE +VPSRAD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f e2 /r] AVX,SANDYBRIDGE,SO +VPSRAD xmmreg,xmmreg*,imm [vmi: vex.ndd.128.66.0f 72 /4 ib] AVX,SANDYBRIDGE +VPSRLW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f d1 /r] AVX,SANDYBRIDGE,SO +VPSRLW xmmreg,xmmreg*,imm [vmi: vex.ndd.128.66.0f 71 /2 ib] AVX,SANDYBRIDGE +VPSRLD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f d2 /r] AVX,SANDYBRIDGE,SO +VPSRLD xmmreg,xmmreg*,imm [vmi: vex.ndd.128.66.0f 72 /2 ib] AVX,SANDYBRIDGE +VPSRLQ xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f d3 /r] AVX,SANDYBRIDGE,SO +VPSRLQ xmmreg,xmmreg*,imm [vmi: vex.ndd.128.66.0f 73 /2 ib] AVX,SANDYBRIDGE VPTEST xmmreg,xmmrm [rm: vex.128.66.0f38 17 /r] AVX,SANDYBRIDGE,SO VPTEST ymmreg,ymmrm [rm: vex.256.66.0f38 17 /r] AVX,SANDYBRIDGE,SY -VPSUBB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f f8 /r] AVX,SANDYBRIDGE,SO -VPSUBB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f f8 /r] AVX,SANDYBRIDGE,SO -VPSUBW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f f9 /r] AVX,SANDYBRIDGE,SO -VPSUBW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f f9 /r] AVX,SANDYBRIDGE,SO -VPSUBD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f fa /r] AVX,SANDYBRIDGE,SO -VPSUBD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f fa /r] AVX,SANDYBRIDGE,SO -VPSUBQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f fb /r] AVX,SANDYBRIDGE,SO -VPSUBQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f fb /r] AVX,SANDYBRIDGE,SO -VPSUBSB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f e8 /r] AVX,SANDYBRIDGE,SO -VPSUBSB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f e8 /r] AVX,SANDYBRIDGE,SO -VPSUBSW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f e9 /r] AVX,SANDYBRIDGE,SO -VPSUBSW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f e9 /r] AVX,SANDYBRIDGE,SO -VPSUBUSB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f d8 /r] AVX,SANDYBRIDGE,SO -VPSUBUSB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f d8 /r] AVX,SANDYBRIDGE,SO -VPSUBUSW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f d9 /r] AVX,SANDYBRIDGE,SO -VPSUBUSW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f d9 /r] AVX,SANDYBRIDGE,SO -VPUNPCKHBW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 68 /r] AVX,SANDYBRIDGE,SO -VPUNPCKHBW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 68 /r] AVX,SANDYBRIDGE,SO -VPUNPCKHWD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 69 /r] AVX,SANDYBRIDGE,SO -VPUNPCKHWD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 69 /r] AVX,SANDYBRIDGE,SO -VPUNPCKHDQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 6a /r] AVX,SANDYBRIDGE,SO -VPUNPCKHDQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 6a /r] AVX,SANDYBRIDGE,SO -VPUNPCKHQDQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 6d /r] AVX,SANDYBRIDGE,SO -VPUNPCKHQDQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 6d /r] AVX,SANDYBRIDGE,SO -VPUNPCKLBW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 60 /r] AVX,SANDYBRIDGE,SO -VPUNPCKLBW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 60 /r] AVX,SANDYBRIDGE,SO -VPUNPCKLWD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 61 /r] AVX,SANDYBRIDGE,SO -VPUNPCKLWD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 61 /r] AVX,SANDYBRIDGE,SO -VPUNPCKLDQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 62 /r] AVX,SANDYBRIDGE,SO -VPUNPCKLDQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 62 /r] AVX,SANDYBRIDGE,SO -VPUNPCKLQDQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 6c /r] AVX,SANDYBRIDGE,SO -VPUNPCKLQDQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 6c /r] AVX,SANDYBRIDGE,SO -VPXOR xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f ef /r] AVX,SANDYBRIDGE,SO -VPXOR xmmreg,xmmrm [r+vm: vex.nds.128.66.0f ef /r] AVX,SANDYBRIDGE,SO +VPSUBB xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f f8 /r] AVX,SANDYBRIDGE,SO +VPSUBW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f f9 /r] AVX,SANDYBRIDGE,SO +VPSUBD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f fa /r] AVX,SANDYBRIDGE,SO +VPSUBQ xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f fb /r] AVX,SANDYBRIDGE,SO +VPSUBSB xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f e8 /r] AVX,SANDYBRIDGE,SO +VPSUBSW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f e9 /r] AVX,SANDYBRIDGE,SO +VPSUBUSB xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f d8 /r] AVX,SANDYBRIDGE,SO +VPSUBUSW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f d9 /r] AVX,SANDYBRIDGE,SO +VPUNPCKHBW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 68 /r] AVX,SANDYBRIDGE,SO +VPUNPCKHWD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 69 /r] AVX,SANDYBRIDGE,SO +VPUNPCKHDQ xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 6a /r] AVX,SANDYBRIDGE,SO +VPUNPCKHQDQ xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 6d /r] AVX,SANDYBRIDGE,SO +VPUNPCKLBW xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 60 /r] AVX,SANDYBRIDGE,SO +VPUNPCKLWD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 61 /r] AVX,SANDYBRIDGE,SO +VPUNPCKLDQ xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 62 /r] AVX,SANDYBRIDGE,SO +VPUNPCKLQDQ xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 6c /r] AVX,SANDYBRIDGE,SO +VPXOR xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f ef /r] AVX,SANDYBRIDGE,SO VRCPPS xmmreg,xmmrm [rm: vex.128.0f 53 /r] AVX,SANDYBRIDGE,SO VRCPPS ymmreg,ymmrm [rm: vex.256.0f 53 /r] AVX,SANDYBRIDGE,SY -VRCPSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f 53 /r] AVX,SANDYBRIDGE,SD -VRCPSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f 53 /r] AVX,SANDYBRIDGE,SD +VRCPSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f 53 /r] AVX,SANDYBRIDGE,SD VRSQRTPS xmmreg,xmmrm [rm: vex.128.0f 52 /r] AVX,SANDYBRIDGE,SO VRSQRTPS ymmreg,ymmrm [rm: vex.256.0f 52 /r] AVX,SANDYBRIDGE,SY -VRSQRTSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f 52 /r] AVX,SANDYBRIDGE,SD -VRSQRTSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f 52 /r] AVX,SANDYBRIDGE,SD +VRSQRTSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f 52 /r] AVX,SANDYBRIDGE,SD VROUNDPD xmmreg,xmmrm,imm [rmi: vex.128.66.0f3a 09 /r ib] AVX,SANDYBRIDGE,SO VROUNDPD ymmreg,ymmrm,imm [rmi: vex.256.66.0f3a 09 /r ib] AVX,SANDYBRIDGE,SY VROUNDPS xmmreg,xmmrm,imm [rmi: vex.128.66.0f3a 08 /r ib] AVX,SANDYBRIDGE,SO VROUNDPS ymmreg,ymmrm,imm [rmi: vex.256.66.0f3a 08 /r ib] AVX,SANDYBRIDGE,SY -VROUNDSD xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 0b /r ib] AVX,SANDYBRIDGE,SQ -VROUNDSD xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 0b /r ib] AVX,SANDYBRIDGE,SQ -VROUNDSS xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 0a /r ib] AVX,SANDYBRIDGE,SD -VROUNDSS xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 0a /r ib] AVX,SANDYBRIDGE,SD -VSHUFPD xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f c6 /r ib] AVX,SANDYBRIDGE,SO -VSHUFPD xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f c6 /r ib] AVX,SANDYBRIDGE,SO -VSHUFPD ymmreg,ymmreg,ymmrm,imm [rvmi: vex.nds.256.66.0f c6 /r ib] AVX,SANDYBRIDGE,SY -VSHUFPD ymmreg,ymmrm,imm [r+vmi: vex.nds.256.66.0f c6 /r ib] AVX,SANDYBRIDGE,SY -VSHUFPS xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.0f c6 /r ib] AVX,SANDYBRIDGE,SO -VSHUFPS xmmreg,xmmrm,imm [r+vmi: vex.nds.128.0f c6 /r ib] AVX,SANDYBRIDGE,SO -VSHUFPS ymmreg,ymmreg,ymmrm,imm [rvmi: vex.nds.256.0f c6 /r ib] AVX,SANDYBRIDGE,SY -VSHUFPS ymmreg,ymmrm,imm [r+vmi: vex.nds.256.0f c6 /r ib] AVX,SANDYBRIDGE,SY +VROUNDSD xmmreg,xmmreg*,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 0b /r ib] AVX,SANDYBRIDGE,SQ +VROUNDSS xmmreg,xmmreg*,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 0a /r ib] AVX,SANDYBRIDGE,SD +VSHUFPD xmmreg,xmmreg*,xmmrm,imm [rvmi: vex.nds.128.66.0f c6 /r ib] AVX,SANDYBRIDGE,SO +VSHUFPD ymmreg,ymmreg*,ymmrm,imm [rvmi: vex.nds.256.66.0f c6 /r ib] AVX,SANDYBRIDGE,SY +VSHUFPS xmmreg,xmmreg*,xmmrm,imm [rvmi: vex.nds.128.0f c6 /r ib] AVX,SANDYBRIDGE,SO +VSHUFPS ymmreg,ymmreg*,ymmrm,imm [rvmi: vex.nds.256.0f c6 /r ib] AVX,SANDYBRIDGE,SY VSQRTPD xmmreg,xmmrm [rm: vex.128.66.0f 51 /r] AVX,SANDYBRIDGE,SO VSQRTPD ymmreg,ymmrm [rm: vex.256.66.0f 51 /r] AVX,SANDYBRIDGE,SY VSQRTPS xmmreg,xmmrm [rm: vex.128.0f 51 /r] AVX,SANDYBRIDGE,SO VSQRTPS ymmreg,ymmrm [rm: vex.256.0f 51 /r] AVX,SANDYBRIDGE,SY -VSQRTSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f 51 /r] AVX,SANDYBRIDGE,SQ -VSQRTSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f 51 /r] AVX,SANDYBRIDGE,SQ -VSQRTSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f 51 /r] AVX,SANDYBRIDGE,SD -VSQRTSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f 51 /r] AVX,SANDYBRIDGE,SD +VSQRTSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f 51 /r] AVX,SANDYBRIDGE,SQ +VSQRTSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f 51 /r] AVX,SANDYBRIDGE,SD VSTMXCSR mem [m: vex.128.0f ae /3] AVX,SANDYBRIDGE,SD -VSUBPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 5c /r] AVX,SANDYBRIDGE,SO -VSUBPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 5c /r] AVX,SANDYBRIDGE,SO -VSUBPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 5c /r] AVX,SANDYBRIDGE,SY -VSUBPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 5c /r] AVX,SANDYBRIDGE,SY -VSUBPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 5c /r] AVX,SANDYBRIDGE,SO -VSUBPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 5c /r] AVX,SANDYBRIDGE,SO -VSUBPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 5c /r] AVX,SANDYBRIDGE,SY -VSUBPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 5c /r] AVX,SANDYBRIDGE,SY -VSUBSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f 5c /r] AVX,SANDYBRIDGE,SQ -VSUBSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f 5c /r] AVX,SANDYBRIDGE,SQ -VSUBSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f 5c /r] AVX,SANDYBRIDGE,SD -VSUBSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f 5c /r] AVX,SANDYBRIDGE,SD +VSUBPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 5c /r] AVX,SANDYBRIDGE,SO +VSUBPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f 5c /r] AVX,SANDYBRIDGE,SY +VSUBPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f 5c /r] AVX,SANDYBRIDGE,SO +VSUBPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f 5c /r] AVX,SANDYBRIDGE,SY +VSUBSD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f2.0f 5c /r] AVX,SANDYBRIDGE,SQ +VSUBSS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.f3.0f 5c /r] AVX,SANDYBRIDGE,SD VTESTPS xmmreg,xmmrm [rm: vex.128.66.0f38 0e /r] AVX,SANDYBRIDGE,SO VTESTPS ymmreg,ymmrm [rm: vex.256.66.0f38 0e /r] AVX,SANDYBRIDGE,SY VTESTPD xmmreg,xmmrm [rm: vex.128.66.0f38 0f /r] AVX,SANDYBRIDGE,SO VTESTPD ymmreg,ymmrm [rm: vex.256.66.0f38 0f /r] AVX,SANDYBRIDGE,SY VUCOMISD xmmreg,xmmrm [rm: vex.128.66.0f 2e /r] AVX,SANDYBRIDGE,SQ VUCOMISS xmmreg,xmmrm [rm: vex.128.0f 2e /r] AVX,SANDYBRIDGE,SD -VUNPCKHPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 15 /r] AVX,SANDYBRIDGE,SO -VUNPCKHPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 15 /r] AVX,SANDYBRIDGE,SO -VUNPCKHPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 15 /r] AVX,SANDYBRIDGE,SY -VUNPCKHPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 15 /r] AVX,SANDYBRIDGE,SY -VUNPCKHPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 15 /r] AVX,SANDYBRIDGE,SO -VUNPCKHPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 15 /r] AVX,SANDYBRIDGE,SO -VUNPCKHPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 15 /r] AVX,SANDYBRIDGE,SY -VUNPCKHPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 15 /r] AVX,SANDYBRIDGE,SY -VUNPCKLPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 14 /r] AVX,SANDYBRIDGE,SO -VUNPCKLPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 14 /r] AVX,SANDYBRIDGE,SO -VUNPCKLPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 14 /r] AVX,SANDYBRIDGE,SY -VUNPCKLPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 14 /r] AVX,SANDYBRIDGE,SY -VUNPCKLPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 14 /r] AVX,SANDYBRIDGE,SO -VUNPCKLPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 14 /r] AVX,SANDYBRIDGE,SO -VUNPCKLPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 14 /r] AVX,SANDYBRIDGE,SY -VUNPCKLPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 14 /r] AVX,SANDYBRIDGE,SY -VXORPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 57 /r] AVX,SANDYBRIDGE,SO -VXORPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 57 /r] AVX,SANDYBRIDGE,SO -VXORPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 57 /r] AVX,SANDYBRIDGE,SY -VXORPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 57 /r] AVX,SANDYBRIDGE,SY -VXORPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 57 /r] AVX,SANDYBRIDGE,SO -VXORPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 57 /r] AVX,SANDYBRIDGE,SO -VXORPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 57 /r] AVX,SANDYBRIDGE,SY -VXORPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 57 /r] AVX,SANDYBRIDGE,SY +VUNPCKHPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 15 /r] AVX,SANDYBRIDGE,SO +VUNPCKHPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f 15 /r] AVX,SANDYBRIDGE,SY +VUNPCKHPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f 15 /r] AVX,SANDYBRIDGE,SO +VUNPCKHPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f 15 /r] AVX,SANDYBRIDGE,SY +VUNPCKLPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 14 /r] AVX,SANDYBRIDGE,SO +VUNPCKLPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f 14 /r] AVX,SANDYBRIDGE,SY +VUNPCKLPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f 14 /r] AVX,SANDYBRIDGE,SO +VUNPCKLPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f 14 /r] AVX,SANDYBRIDGE,SY +VXORPD xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f 57 /r] AVX,SANDYBRIDGE,SO +VXORPD ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.66.0f 57 /r] AVX,SANDYBRIDGE,SY +VXORPS xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.0f 57 /r] AVX,SANDYBRIDGE,SO +VXORPS ymmreg,ymmreg*,ymmrm [rvm: vex.nds.256.0f 57 /r] AVX,SANDYBRIDGE,SY VZEROALL void [ vex.256.0f 77] AVX,SANDYBRIDGE VZEROUPPER void [ vex.128.0f 77] AVX,SANDYBRIDGE ;# Intel Carry-Less Multiplication instructions (CLMUL) -; Again, no idea what CPU flag for these... -PCLMULLQLQDQ xmmreg,xmmrm [rm: 66 0f 3a 44 /r 00] SSE,SANDYBRIDGE,SO -PCLMULHQLQDQ xmmreg,xmmrm [rm: 66 0f 3a 44 /r 01] SSE,SANDYBRIDGE,SO -PCLMULLQHQDQ xmmreg,xmmrm [rm: 66 0f 3a 44 /r 10] SSE,SANDYBRIDGE,SO -PCLMULHQHQDQ xmmreg,xmmrm [rm: 66 0f 3a 44 /r 11] SSE,SANDYBRIDGE,SO -PCLMULQDQ xmmreg,xmmrm,imm [rmi: 66 0f 3a 44 /r ib] SSE,SANDYBRIDGE,SO +PCLMULLQLQDQ xmmreg,xmmrm [rm: 66 0f 3a 44 /r 00] SSE,WESTMERE,SO +PCLMULHQLQDQ xmmreg,xmmrm [rm: 66 0f 3a 44 /r 01] SSE,WESTMERE,SO +PCLMULLQHQDQ xmmreg,xmmrm [rm: 66 0f 3a 44 /r 10] SSE,WESTMERE,SO +PCLMULHQHQDQ xmmreg,xmmrm [rm: 66 0f 3a 44 /r 11] SSE,WESTMERE,SO +PCLMULQDQ xmmreg,xmmrm,imm [rmi: 66 0f 3a 44 /r ib] SSE,WESTMERE,SO + +;# Intel AVX Carry-Less Multiplication instructions (CLMUL) +VPCLMULLQLQDQ xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f3a 44 /r 00] AVX,SANDYBRIDGE,SO +VPCLMULHQLQDQ xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f3a 44 /r 01] AVX,SANDYBRIDGE,SO +VPCLMULLQHQDQ xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f3a 44 /r 10] AVX,SANDYBRIDGE,SO +VPCLMULHQHQDQ xmmreg,xmmreg*,xmmrm [rvm: vex.nds.128.66.0f3a 44 /r 11] AVX,SANDYBRIDGE,SO +VPCLMULQDQ xmmreg,xmmreg*,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 44 /r ib] AVX,SANDYBRIDGE,SO ;# Intel Fused Multiply-Add instructions (FMA) -; Sandybridge is probably wrong for these... -VFMADDPD xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.128.66.0f3a.w0 69 /r /is4] FMA,SANDYBRIDGE,SO -VFMADDPD xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.128.66.0f3a.w1 69 /r /is4] FMA,SANDYBRIDGE,SO -VFMADDPD ymmreg,ymmreg,ymmrm,ymmreg [rsmv: vex.nds.256.66.0f3a.w0 69 /r /is4] FMA,SANDYBRIDGE,SY -VFMADDPD ymmreg,ymmreg,ymmreg,ymmrm [rsvm: vex.nds.256.66.0f3a.w1 69 /r /is4] FMA,SANDYBRIDGE,SY -VFMADDPS xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.128.66.0f3a.w0 68 /r /is4] FMA,SANDYBRIDGE,SO -VFMADDPS xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.128.66.0f3a.w1 68 /r /is4] FMA,SANDYBRIDGE,SO -VFMADDPS ymmreg,ymmreg,ymmrm,ymmreg [rsmv: vex.nds.256.66.0f3a.w0 68 /r /is4] FMA,SANDYBRIDGE,SY -VFMADDPS ymmreg,ymmreg,ymmreg,ymmrm [rsvm: vex.nds.256.66.0f3a.w1 68 /r /is4] FMA,SANDYBRIDGE,SY -VFMADDSD xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.128.66.0f3a.w0 6b /r /is4] FMA,SANDYBRIDGE,SQ -VFMADDSD xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.128.66.0f3a.w1 6b /r /is4] FMA,SANDYBRIDGE,SQ -VFMADDSS xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.128.66.0f3a.w0 6a /r /is4] FMA,SANDYBRIDGE,SD -VFMADDSS xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.128.66.0f3a.w1 6a /r /is4] FMA,SANDYBRIDGE,SD -VFMADDSUBPD xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.128.66.0f3a.w0 5d /r /is4] FMA,SANDYBRIDGE,SO -VFMADDSUBPD xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.128.66.0f3a.w1 5d /r /is4] FMA,SANDYBRIDGE,SO -VFMADDSUBPD ymmreg,ymmreg,ymmrm,ymmreg [rsmv: vex.nds.256.66.0f3a.w0 5d /r /is4] FMA,SANDYBRIDGE,SY -VFMADDSUBPD ymmreg,ymmreg,ymmreg,ymmrm [rsvm: vex.nds.256.66.0f3a.w1 5d /r /is4] FMA,SANDYBRIDGE,SY -VFMADDSUBPS xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.128.66.0f3a.w0 5c /r /is4] FMA,SANDYBRIDGE,SO -VFMADDSUBPS xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.128.66.0f3a.w1 5c /r /is4] FMA,SANDYBRIDGE,SO -VFMADDSUBPS ymmreg,ymmreg,ymmrm,ymmreg [rsmv: vex.nds.256.66.0f3a.w0 5c /r /is4] FMA,SANDYBRIDGE,SY -VFMADDSUBPS ymmreg,ymmreg,ymmreg,ymmrm [rsvm: vex.nds.256.66.0f3a.w1 5c /r /is4] FMA,SANDYBRIDGE,SY -VFMSUBADDPD xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.128.66.0f3a.w0 5f /r /is4] FMA,SANDYBRIDGE,SO -VFMSUBADDPD xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.128.66.0f3a.w1 5f /r /is4] FMA,SANDYBRIDGE,SO -VFMSUBADDPD ymmreg,ymmreg,ymmrm,ymmreg [rsmv: vex.nds.256.66.0f3a.w0 5f /r /is4] FMA,SANDYBRIDGE,SY -VFMSUBADDPD ymmreg,ymmreg,ymmreg,ymmrm [rsvm: vex.nds.256.66.0f3a.w1 5f /r /is4] FMA,SANDYBRIDGE,SY -VFMSUBADDPS xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.128.66.0f3a.w0 5e /r /is4] FMA,SANDYBRIDGE,SO -VFMSUBADDPS xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.128.66.0f3a.w1 5e /r /is4] FMA,SANDYBRIDGE,SO -VFMSUBADDPS ymmreg,ymmreg,ymmrm,ymmreg [rsmv: vex.nds.256.66.0f3a.w0 5e /r /is4] FMA,SANDYBRIDGE,SY -VFMSUBADDPS ymmreg,ymmreg,ymmreg,ymmrm [rsvm: vex.nds.256.66.0f3a.w1 5e /r /is4] FMA,SANDYBRIDGE,SY -VFMSUBPD xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.128.66.0f3a.w0 6d /r /is4] FMA,SANDYBRIDGE,SO -VFMSUBPD xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.128.66.0f3a.w1 6d /r /is4] FMA,SANDYBRIDGE,SO -VFMSUBPD ymmreg,ymmreg,ymmrm,ymmreg [rsmv: vex.nds.256.66.0f3a.w0 6d /r /is4] FMA,SANDYBRIDGE,SY -VFMSUBPD ymmreg,ymmreg,ymmreg,ymmrm [rsvm: vex.nds.256.66.0f3a.w1 6d /r /is4] FMA,SANDYBRIDGE,SY -VFMSUBPS xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.128.66.0f3a.w0 6c /r /is4] FMA,SANDYBRIDGE,SO -VFMSUBPS xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.128.66.0f3a.w1 6c /r /is4] FMA,SANDYBRIDGE,SO -VFMSUBPS ymmreg,ymmreg,ymmrm,ymmreg [rsmv: vex.nds.256.66.0f3a.w0 6c /r /is4] FMA,SANDYBRIDGE,SY -VFMSUBPS ymmreg,ymmreg,ymmreg,ymmrm [rsvm: vex.nds.256.66.0f3a.w1 6c /r /is4] FMA,SANDYBRIDGE,SY -VFMSUBSD xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.128.66.0f3a.w0 6f /r /is4] FMA,SANDYBRIDGE,SQ -VFMSUBSD xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.128.66.0f3a.w1 6f /r /is4] FMA,SANDYBRIDGE,SQ -VFMSUBSS xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.128.66.0f3a.w0 6e /r /is4] FMA,SANDYBRIDGE,SD -VFMSUBSS xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.128.66.0f3a.w1 6e /r /is4] FMA,SANDYBRIDGE,SD -VFNMADDPD xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.128.66.0f3a.w0 79 /r /is4] FMA,SANDYBRIDGE,SO -VFNMADDPD xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.128.66.0f3a.w1 79 /r /is4] FMA,SANDYBRIDGE,SO -VFNMADDPD xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.256.66.0f3a.w0 79 /r /is4] FMA,SANDYBRIDGE,SY -VFNMADDPD xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.256.66.0f3a.w1 79 /r /is4] FMA,SANDYBRIDGE,SY -VFNMADDPS xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.128.66.0f3a.w0 78 /r /is4] FMA,SANDYBRIDGE,SO -VFNMADDPS xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.128.66.0f3a.w1 78 /r /is4] FMA,SANDYBRIDGE,SO -VFNMADDPS xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.256.66.0f3a.w0 78 /r /is4] FMA,SANDYBRIDGE,SY -VFNMADDPS xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.256.66.0f3a.w1 78 /r /is4] FMA,SANDYBRIDGE,SY -VFNMADDSD xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.128.66.0f3a.w0 7b /r /is4] FMA,SANDYBRIDGE,SQ -VFNMADDSD xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.128.66.0f3a.w1 7b /r /is4] FMA,SANDYBRIDGE,SQ -VFNMADDSS xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.128.66.0f3a.w0 7a /r /is4] FMA,SANDYBRIDGE,SD -VFNMADDSS xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.128.66.0f3a.w1 7a /r /is4] FMA,SANDYBRIDGE,SD -VFNMSUBPD xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.128.66.0f3a.w0 7d /r /is4] FMA,SANDYBRIDGE,SO -VFNMSUBPD xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.128.66.0f3a.w1 7d /r /is4] FMA,SANDYBRIDGE,SO -VFNMSUBPD xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.256.66.0f3a.w0 7d /r /is4] FMA,SANDYBRIDGE,SY -VFNMSUBPD xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.256.66.0f3a.w1 7d /r /is4] FMA,SANDYBRIDGE,SY -VFNMSUBPS xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.128.66.0f3a.w0 7c /r /is4] FMA,SANDYBRIDGE,SO -VFNMSUBPS xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.128.66.0f3a.w1 7c /r /is4] FMA,SANDYBRIDGE,SO -VFNMSUBPS xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.256.66.0f3a.w0 7c /r /is4] FMA,SANDYBRIDGE,SY -VFNMSUBPS xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.256.66.0f3a.w1 7c /r /is4] FMA,SANDYBRIDGE,SY -VFNMSUBSD xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.128.66.0f3a.w0 7f /r /is4] FMA,SANDYBRIDGE,SQ -VFNMSUBSD xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.128.66.0f3a.w1 7f /r /is4] FMA,SANDYBRIDGE,SQ -VFNMSUBSS xmmreg,xmmreg,xmmrm,xmmreg [rsmv: vex.nds.128.66.0f3a.w0 7e /r /is4] FMA,SANDYBRIDGE,SD -VFNMSUBSS xmmreg,xmmreg,xmmreg,xmmrm [rsvm: vex.nds.128.66.0f3a.w1 7e /r /is4] FMA,SANDYBRIDGE,SD +VFMADD132PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 98 /r] FMA,FUTURE,SO +VFMADD132PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 98 /r] FMA,FUTURE,SY +VFMADD132PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 98 /r] FMA,FUTURE,SO +VFMADD132PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 98 /r] FMA,FUTURE,SY +VFMADD312PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 98 /r] FMA,FUTURE,SO +VFMADD312PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 98 /r] FMA,FUTURE,SY +VFMADD312PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 98 /r] FMA,FUTURE,SO +VFMADD312PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 98 /r] FMA,FUTURE,SY +VFMADD213PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 a8 /r] FMA,FUTURE,SO +VFMADD213PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 a8 /r] FMA,FUTURE,SY +VFMADD213PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 a8 /r] FMA,FUTURE,SO +VFMADD213PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 a8 /r] FMA,FUTURE,SY +VFMADD123PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 a8 /r] FMA,FUTURE,SO +VFMADD123PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 a8 /r] FMA,FUTURE,SY +VFMADD123PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 a8 /r] FMA,FUTURE,SO +VFMADD123PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 a8 /r] FMA,FUTURE,SY +VFMADD231PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 b8 /r] FMA,FUTURE,SO +VFMADD231PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 b8 /r] FMA,FUTURE,SY +VFMADD231PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 b8 /r] FMA,FUTURE,SO +VFMADD231PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 b8 /r] FMA,FUTURE,SY +VFMADD321PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 b8 /r] FMA,FUTURE,SO +VFMADD321PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 b8 /r] FMA,FUTURE,SY +VFMADD321PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 b8 /r] FMA,FUTURE,SO +VFMADD321PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 b8 /r] FMA,FUTURE,SY +VFMADDSUB132PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 96 /r] FMA,FUTURE,SO +VFMADDSUB132PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 96 /r] FMA,FUTURE,SY +VFMADDSUB132PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 96 /r] FMA,FUTURE,SO +VFMADDSUB132PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 96 /r] FMA,FUTURE,SY +VFMADDSUB312PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 96 /r] FMA,FUTURE,SO +VFMADDSUB312PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 96 /r] FMA,FUTURE,SY +VFMADDSUB312PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 96 /r] FMA,FUTURE,SO +VFMADDSUB312PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 96 /r] FMA,FUTURE,SY +VFMADDSUB213PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 a6 /r] FMA,FUTURE,SO +VFMADDSUB213PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 a6 /r] FMA,FUTURE,SY +VFMADDSUB213PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 a6 /r] FMA,FUTURE,SO +VFMADDSUB213PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 a6 /r] FMA,FUTURE,SY +VFMADDSUB123PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 a6 /r] FMA,FUTURE,SO +VFMADDSUB123PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 a6 /r] FMA,FUTURE,SY +VFMADDSUB123PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 a6 /r] FMA,FUTURE,SO +VFMADDSUB123PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 a6 /r] FMA,FUTURE,SY +VFMADDSUB231PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 b6 /r] FMA,FUTURE,SO +VFMADDSUB231PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 b6 /r] FMA,FUTURE,SY +VFMADDSUB231PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 b6 /r] FMA,FUTURE,SO +VFMADDSUB231PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 b6 /r] FMA,FUTURE,SY +VFMADDSUB321PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 b6 /r] FMA,FUTURE,SO +VFMADDSUB321PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 b6 /r] FMA,FUTURE,SY +VFMADDSUB321PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 b6 /r] FMA,FUTURE,SO +VFMADDSUB321PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 b6 /r] FMA,FUTURE,SY +VFMSUB132PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9a /r] FMA,FUTURE,SO +VFMSUB132PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 9a /r] FMA,FUTURE,SY +VFMSUB132PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9a /r] FMA,FUTURE,SO +VFMSUB132PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 9a /r] FMA,FUTURE,SY +VFMSUB312PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9a /r] FMA,FUTURE,SO +VFMSUB312PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 9a /r] FMA,FUTURE,SY +VFMSUB312PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9a /r] FMA,FUTURE,SO +VFMSUB312PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 9a /r] FMA,FUTURE,SY +VFMSUB213PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 aa /r] FMA,FUTURE,SO +VFMSUB213PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 aa /r] FMA,FUTURE,SY +VFMSUB213PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 aa /r] FMA,FUTURE,SO +VFMSUB213PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 aa /r] FMA,FUTURE,SY +VFMSUB123PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 aa /r] FMA,FUTURE,SO +VFMSUB123PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 aa /r] FMA,FUTURE,SY +VFMSUB123PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 aa /r] FMA,FUTURE,SO +VFMSUB123PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 aa /r] FMA,FUTURE,SY +VFMSUB231PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 ba /r] FMA,FUTURE,SO +VFMSUB231PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 ba /r] FMA,FUTURE,SY +VFMSUB231PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 ba /r] FMA,FUTURE,SO +VFMSUB231PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 ba /r] FMA,FUTURE,SY +VFMSUB321PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 ba /r] FMA,FUTURE,SO +VFMSUB321PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 ba /r] FMA,FUTURE,SY +VFMSUB321PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 ba /r] FMA,FUTURE,SO +VFMSUB321PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 ba /r] FMA,FUTURE,SY +VFMSUBADD132PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 97 /r] FMA,FUTURE,SO +VFMSUBADD132PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 97 /r] FMA,FUTURE,SY +VFMSUBADD132PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 97 /r] FMA,FUTURE,SO +VFMSUBADD132PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 97 /r] FMA,FUTURE,SY +VFMSUBADD312PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 97 /r] FMA,FUTURE,SO +VFMSUBADD312PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 97 /r] FMA,FUTURE,SY +VFMSUBADD312PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 97 /r] FMA,FUTURE,SO +VFMSUBADD312PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 97 /r] FMA,FUTURE,SY +VFMSUBADD213PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 a7 /r] FMA,FUTURE,SO +VFMSUBADD213PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 a7 /r] FMA,FUTURE,SY +VFMSUBADD213PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 a7 /r] FMA,FUTURE,SO +VFMSUBADD213PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 a7 /r] FMA,FUTURE,SY +VFMSUBADD123PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 a7 /r] FMA,FUTURE,SO +VFMSUBADD123PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 a7 /r] FMA,FUTURE,SY +VFMSUBADD123PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 a7 /r] FMA,FUTURE,SO +VFMSUBADD123PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 a7 /r] FMA,FUTURE,SY +VFMSUBADD231PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 b7 /r] FMA,FUTURE,SO +VFMSUBADD231PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 b7 /r] FMA,FUTURE,SY +VFMSUBADD231PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 b7 /r] FMA,FUTURE,SO +VFMSUBADD231PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 b7 /r] FMA,FUTURE,SY +VFMSUBADD321PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 b7 /r] FMA,FUTURE,SO +VFMSUBADD321PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 b7 /r] FMA,FUTURE,SY +VFMSUBADD321PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 b7 /r] FMA,FUTURE,SO +VFMSUBADD321PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 b7 /r] FMA,FUTURE,SY +VFNMADD132PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9c /r] FMA,FUTURE,SO +VFNMADD132PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 9c /r] FMA,FUTURE,SY +VFNMADD132PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9c /r] FMA,FUTURE,SO +VFNMADD132PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 9c /r] FMA,FUTURE,SY +VFNMADD312PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9c /r] FMA,FUTURE,SO +VFNMADD312PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 9c /r] FMA,FUTURE,SY +VFNMADD312PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9c /r] FMA,FUTURE,SO +VFNMADD312PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 9c /r] FMA,FUTURE,SY +VFNMADD213PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 ac /r] FMA,FUTURE,SO +VFNMADD213PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 ac /r] FMA,FUTURE,SY +VFNMADD213PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 ac /r] FMA,FUTURE,SO +VFNMADD213PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 ac /r] FMA,FUTURE,SY +VFNMADD123PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 ac /r] FMA,FUTURE,SO +VFNMADD123PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 ac /r] FMA,FUTURE,SY +VFNMADD123PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 ac /r] FMA,FUTURE,SO +VFNMADD123PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 ac /r] FMA,FUTURE,SY +VFNMADD231PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 bc /r] FMA,FUTURE,SO +VFNMADD231PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 bc /r] FMA,FUTURE,SY +VFNMADD231PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 bc /r] FMA,FUTURE,SO +VFNMADD231PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 bc /r] FMA,FUTURE,SY +VFNMADD321PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 bc /r] FMA,FUTURE,SO +VFNMADD321PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 bc /r] FMA,FUTURE,SY +VFNMADD321PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 bc /r] FMA,FUTURE,SO +VFNMADD321PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 bc /r] FMA,FUTURE,SY +VFNMSUB132PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9e /r] FMA,FUTURE,SO +VFNMSUB132PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 9e /r] FMA,FUTURE,SY +VFNMSUB132PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9e /r] FMA,FUTURE,SO +VFNMSUB132PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 9e /r] FMA,FUTURE,SY +VFNMSUB312PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9e /r] FMA,FUTURE,SO +VFNMSUB312PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 9e /r] FMA,FUTURE,SY +VFNMSUB312PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9e /r] FMA,FUTURE,SO +VFNMSUB312PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 9e /r] FMA,FUTURE,SY +VFNMSUB213PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 ae /r] FMA,FUTURE,SO +VFNMSUB213PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 ae /r] FMA,FUTURE,SY +VFNMSUB213PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 ae /r] FMA,FUTURE,SO +VFNMSUB213PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 ae /r] FMA,FUTURE,SY +VFNMSUB123PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 ae /r] FMA,FUTURE,SO +VFNMSUB123PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 ae /r] FMA,FUTURE,SY +VFNMSUB123PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 ae /r] FMA,FUTURE,SO +VFNMSUB123PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 ae /r] FMA,FUTURE,SY +VFNMSUB231PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 be /r] FMA,FUTURE,SO +VFNMSUB231PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 be /r] FMA,FUTURE,SY +VFNMSUB231PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 be /r] FMA,FUTURE,SO +VFNMSUB231PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 be /r] FMA,FUTURE,SY +VFNMSUB321PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 be /r] FMA,FUTURE,SO +VFNMSUB321PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 be /r] FMA,FUTURE,SY +VFNMSUB321PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 be /r] FMA,FUTURE,SO +VFNMSUB321PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 be /r] FMA,FUTURE,SY +VFMADD132SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 99 /r] FMA,FUTURE,SD +VFMADD132SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 99 /r] FMA,FUTURE,SQ +VFMADD312SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 99 /r] FMA,FUTURE,SD +VFMADD312SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 99 /r] FMA,FUTURE,SQ +VFMADD213SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 a9 /r] FMA,FUTURE,SD +VFMADD213SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 a9 /r] FMA,FUTURE,SQ +VFMADD123SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 a9 /r] FMA,FUTURE,SD +VFMADD123SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 a9 /r] FMA,FUTURE,SQ +VFMADD231SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 b9 /r] FMA,FUTURE,SD +VFMADD231SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 b9 /r] FMA,FUTURE,SQ +VFMADD321SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 b9 /r] FMA,FUTURE,SD +VFMADD321SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 b9 /r] FMA,FUTURE,SQ +VFMSUB132SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9b /r] FMA,FUTURE,SD +VFMSUB132SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9b /r] FMA,FUTURE,SQ +VFMSUB312SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9b /r] FMA,FUTURE,SD +VFMSUB312SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9b /r] FMA,FUTURE,SQ +VFMSUB213SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 ab /r] FMA,FUTURE,SD +VFMSUB213SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 ab /r] FMA,FUTURE,SQ +VFMSUB123SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 ab /r] FMA,FUTURE,SD +VFMSUB123SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 ab /r] FMA,FUTURE,SQ +VFMSUB231SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 bb /r] FMA,FUTURE,SD +VFMSUB231SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 bb /r] FMA,FUTURE,SQ +VFMSUB321SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 bb /r] FMA,FUTURE,SD +VFMSUB321SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 bb /r] FMA,FUTURE,SQ +VFNMADD132SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9d /r] FMA,FUTURE,SD +VFNMADD132SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9d /r] FMA,FUTURE,SQ +VFNMADD312SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9d /r] FMA,FUTURE,SD +VFNMADD312SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9d /r] FMA,FUTURE,SQ +VFNMADD213SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 ad /r] FMA,FUTURE,SD +VFNMADD213SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 ad /r] FMA,FUTURE,SQ +VFNMADD123SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 ad /r] FMA,FUTURE,SD +VFNMADD123SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 ad /r] FMA,FUTURE,SQ +VFNMADD231SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 bd /r] FMA,FUTURE,SD +VFNMADD231SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 bd /r] FMA,FUTURE,SQ +VFNMADD321SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 bd /r] FMA,FUTURE,SD +VFNMADD321SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 bd /r] FMA,FUTURE,SQ +VFNMSUB132SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9f /r] FMA,FUTURE,SD +VFNMSUB132SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9f /r] FMA,FUTURE,SQ +VFNMSUB312SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9f /r] FMA,FUTURE,SD +VFNMSUB312SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9f /r] FMA,FUTURE,SQ +VFNMSUB213SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 af /r] FMA,FUTURE,SD +VFNMSUB213SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 af /r] FMA,FUTURE,SQ +VFNMSUB123SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 af /r] FMA,FUTURE,SD +VFNMSUB123SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 af /r] FMA,FUTURE,SQ +VFNMSUB231SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 bf /r] FMA,FUTURE,SD +VFNMSUB231SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 bf /r] FMA,FUTURE,SQ +VFNMSUB321SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 bf /r] FMA,FUTURE,SD +VFNMSUB321SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 bf /r] FMA,FUTURE,SQ ;# VIA (Centaur) security instructions XSTORE void \3\x0F\xA7\xC0 PENT,CYRIX @@ -3346,6 +3114,217 @@ MONTMUL void \336\3\x0F\xA6\xC0 PENT,CYRIX XSHA1 void \336\3\x0F\xA6\xC8 PENT,CYRIX XSHA256 void \336\3\x0F\xA6\xD0 PENT,CYRIX +;# AMD XOP, FMA4 and CVT16 instructions (SSE5) +; +; based on pub number 43479 revision 3.03 date May 2009 +; +VCVTPH2PS xmmreg,xmmrm*,imm [rmi: xop.m8.w0.l0 a0 /r ib] AMD,SSE5,SQ +VCVTPH2PS ymmreg,xmmrm,imm [rmi: xop.m8.w0.l1 a0 /r ib] AMD,SSE5,SO +VCVTPH2PS ymmreg,ymmrm*,imm [rmi: xop.m8.w0.l1 a0 /r ib] AMD,SSE5,SO + +VCVTPS2PH xmmrm,xmmreg*,imm [mri: xop.m8.w0.l0 a1 /r ib] AMD,SSE5,SQ +VCVTPS2PH xmmrm,ymmreg,imm [mri: xop.m8.w0.l1 a1 /r ib] AMD,SSE5,SO +VCVTPS2PH ymmrm,ymmreg*,imm [mri: xop.m8.w0.l1 a1 /r ib] AMD,SSE5,SO + +VFMADDPD xmmreg,xmmreg*,xmmrm,xmmreg [rvms: vex.m3.w0.nds.l0.p1 69 /r /is4] AMD,SSE5,SO +VFMADDPD ymmreg,ymmreg*,ymmrm,ymmreg [rvms: vex.m3.w0.nds.l1.p1 69 /r /is4] AMD,SSE5,SY +VFMADDPD xmmreg,xmmreg*,xmmreg,xmmrm [rvsm: vex.m3.w1.nds.l0.p1 69 /r /is4] AMD,SSE5,SO +VFMADDPD ymmreg,ymmreg*,ymmreg,ymmrm [rvsm: vex.m3.w1.nds.l1.p1 69 /r /is4] AMD,SSE5,SY + +VFMADDPS xmmreg,xmmreg*,xmmrm,xmmreg [rvms: vex.m3.w0.nds.l0.p1 68 /r /is4] AMD,SSE5,SO +VFMADDPS ymmreg,ymmreg*,ymmrm,ymmreg [rvms: vex.m3.w0.nds.l1.p1 68 /r /is4] AMD,SSE5,SY +VFMADDPS xmmreg,xmmreg*,xmmreg,xmmrm [rvsm: vex.m3.w1.nds.l0.p1 68 /r /is4] AMD,SSE5,SO +VFMADDPS ymmreg,ymmreg*,ymmreg,ymmrm [rvsm: vex.m3.w1.nds.l1.p1 68 /r /is4] AMD,SSE5,SY + +VFMADDSD xmmreg,xmmreg*,xmmrm,xmmreg [rvms: vex.m3.w0.nds.l0.p1 6b /r /is4] AMD,SSE5,SQ +VFMADDSD xmmreg,xmmreg*,xmmreg,xmmrm [rvsm: vex.m3.w1.nds.l0.p1 6b /r /is4] AMD,SSE5,SQ + +VFMADDSS xmmreg,xmmreg*,xmmrm,xmmreg [rvms: vex.m3.w0.nds.l0.p1 6a /r /is4] AMD,SSE5,SD +VFMADDSS xmmreg,xmmreg*,xmmreg,xmmrm [rvsm: vex.m3.w1.nds.l0.p1 6a /r /is4] AMD,SSE5,SD + +VFMADDSUBPD xmmreg,xmmreg*,xmmrm,xmmreg [rvms: vex.m3.w0.nds.l0.p1 5d /r /is4] AMD,SSE5,SO +VFMADDSUBPD ymmreg,ymmreg*,ymmrm,ymmreg [rvms: vex.m3.w0.nds.l1.p1 5d /r /is4] AMD,SSE5,SY +VFMADDSUBPD xmmreg,xmmreg*,xmmreg,xmmrm [rvsm: vex.m3.w1.nds.l0.p1 5d /r /is4] AMD,SSE5,SO +VFMADDSUBPD ymmreg,ymmreg*,ymmreg,ymmrm [rvsm: vex.m3.w1.nds.l1.p1 5d /r /is4] AMD,SSE5,SY + +VFMADDSUBPS xmmreg,xmmreg*,xmmrm,xmmreg [rvms: vex.m3.w0.nds.l0.p1 5c /r /is4] AMD,SSE5,SO +VFMADDSUBPS ymmreg,ymmreg*,ymmrm,ymmreg [rvms: vex.m3.w0.nds.l1.p1 5c /r /is4] AMD,SSE5,SY +VFMADDSUBPS xmmreg,xmmreg*,xmmreg,xmmrm [rvsm: vex.m3.w1.nds.l0.p1 5c /r /is4] AMD,SSE5,SO +VFMADDSUBPS ymmreg,ymmreg*,ymmreg,ymmrm [rvsm: vex.m3.w1.nds.l1.p1 5c /r /is4] AMD,SSE5,SY + +VFMSUBADDPD xmmreg,xmmreg*,xmmrm,xmmreg [rvms: vex.m3.w0.nds.l0.p1 5f /r /is4] AMD,SSE5,SO +VFMSUBADDPD ymmreg,ymmreg*,ymmrm,ymmreg [rvms: vex.m3.w0.nds.l1.p1 5f /r /is4] AMD,SSE5,SY +VFMSUBADDPD xmmreg,xmmreg*,xmmreg,xmmrm [rvsm: vex.m3.w1.nds.l0.p1 5f /r /is4] AMD,SSE5,SO +VFMSUBADDPD ymmreg,ymmreg*,ymmreg,ymmrm [rvsm: vex.m3.w1.nds.l1.p1 5f /r /is4] AMD,SSE5,SY + +VFMSUBADDPS xmmreg,xmmreg*,xmmrm,xmmreg [rvms: vex.m3.w0.nds.l0.p1 5e /r /is4] AMD,SSE5,SO +VFMSUBADDPS ymmreg,ymmreg*,ymmrm,ymmreg [rvms: vex.m3.w0.nds.l1.p1 5e /r /is4] AMD,SSE5,SY +VFMSUBADDPS xmmreg,xmmreg*,xmmreg,xmmrm [rvsm: vex.m3.w1.nds.l0.p1 5e /r /is4] AMD,SSE5,SO +VFMSUBADDPS ymmreg,ymmreg*,ymmreg,ymmrm [rvsm: vex.m3.w1.nds.l1.p1 5e /r /is4] AMD,SSE5,SY + +VFMSUBPD xmmreg,xmmreg*,xmmrm,xmmreg [rvms: vex.m3.w0.nds.l0.p1 6d /r /is4] AMD,SSE5,SO +VFMSUBPD ymmreg,ymmreg*,ymmrm,ymmreg [rvms: vex.m3.w0.nds.l1.p1 6d /r /is4] AMD,SSE5,SY +VFMSUBPD xmmreg,xmmreg*,xmmreg,xmmrm [rvsm: vex.m3.w1.nds.l0.p1 6d /r /is4] AMD,SSE5,SO +VFMSUBPD ymmreg,ymmreg*,ymmreg,ymmrm [rvsm: vex.m3.w1.nds.l1.p1 6d /r /is4] AMD,SSE5,SY + +VFMSUBPS xmmreg,xmmreg*,xmmrm,xmmreg [rvms: vex.m3.w0.nds.l0.p1 6c /r /is4] AMD,SSE5,SO +VFMSUBPS ymmreg,ymmreg*,ymmrm,ymmreg [rvms: vex.m3.w0.nds.l1.p1 6c /r /is4] AMD,SSE5,SY +VFMSUBPS xmmreg,xmmreg*,xmmreg,xmmrm [rvsm: vex.m3.w1.nds.l0.p1 6c /r /is4] AMD,SSE5,SO +VFMSUBPS ymmreg,ymmreg*,ymmreg,ymmrm [rvsm: vex.m3.w1.nds.l1.p1 6c /r /is4] AMD,SSE5,SY + +VFMSUBSD xmmreg,xmmreg*,xmmrm,xmmreg [rvms: vex.m3.w0.nds.l0.p1 6f /r /is4] AMD,SSE5,SQ +VFMSUBSD xmmreg,xmmreg*,xmmreg,xmmrm [rvsm: vex.m3.w1.nds.l0.p1 6f /r /is4] AMD,SSE5,SQ + +VFMSUBSS xmmreg,xmmreg*,xmmrm,xmmreg [rvms: vex.m3.w0.nds.l0.p1 6e /r /is4] AMD,SSE5,SD +VFMSUBSS xmmreg,xmmreg*,xmmreg,xmmrm [rvsm: vex.m3.w1.nds.l0.p1 6e /r /is4] AMD,SSE5,SD + +VFNMADDPD xmmreg,xmmreg*,xmmrm,xmmreg [rvms: vex.m3.w0.nds.l0.p1 79 /r /is4] AMD,SSE5,SO +VFNMADDPD ymmreg,ymmreg*,ymmrm,ymmreg [rvms: vex.m3.w0.nds.l1.p1 79 /r /is4] AMD,SSE5,SY +VFNMADDPD xmmreg,xmmreg*,xmmreg,xmmrm [rvsm: vex.m3.w1.nds.l0.p1 79 /r /is4] AMD,SSE5,SO +VFNMADDPD ymmreg,ymmreg*,ymmreg,ymmrm [rvsm: vex.m3.w1.nds.l1.p1 79 /r /is4] AMD,SSE5,SY + +VFNMADDPS xmmreg,xmmreg*,xmmrm,xmmreg [rvms: vex.m3.w0.nds.l0.p1 78 /r /is4] AMD,SSE5,SO +VFNMADDPS ymmreg,ymmreg*,ymmrm,ymmreg [rvms: vex.m3.w0.nds.l1.p1 78 /r /is4] AMD,SSE5,SY +VFNMADDPS xmmreg,xmmreg*,xmmreg,xmmrm [rvsm: vex.m3.w1.nds.l0.p1 78 /r /is4] AMD,SSE5,SO +VFNMADDPS ymmreg,ymmreg*,ymmreg,ymmrm [rvsm: vex.m3.w1.nds.l1.p1 78 /r /is4] AMD,SSE5,SY + +VFNMADDSD xmmreg,xmmreg*,xmmrm,xmmreg [rvms: vex.m3.w0.nds.l0.p1 7b /r /is4] AMD,SSE5,SQ +VFNMADDSD xmmreg,xmmreg*,xmmreg,xmmrm [rvms: vex.m3.w1.nds.l0.p1 7b /r /is4] AMD,SSE5,SQ + +VFNMADDSS xmmreg,xmmreg*,xmmrm,xmmreg [rvms: vex.m3.w0.nds.l0.p1 7a /r /is4] AMD,SSE5,SD +VFNMADDSS xmmreg,xmmreg*,xmmreg,xmmrm [rvms: vex.m3.w1.nds.l0.p1 7a /r /is4] AMD,SSE5,SD + +VFNMSUBPD xmmreg,xmmreg*,xmmrm,xmmreg [rvms: vex.m3.w0.nds.l0.p1 7d /r /is4] AMD,SSE5,SO +VFNMSUBPD ymmreg,ymmreg*,ymmrm,ymmreg [rvms: vex.m3.w0.nds.l1.p1 7d /r /is4] AMD,SSE5,SY +VFNMSUBPD xmmreg,xmmreg*,xmmreg,xmmrm [rvsm: vex.m3.w1.nds.l0.p1 7d /r /is4] AMD,SSE5,SO +VFNMSUBPD ymmreg,ymmreg*,ymmreg,ymmrm [rvsm: vex.m3.w1.nds.l1.p1 7d /r /is4] AMD,SSE5,SY + +VFNMSUBPS xmmreg,xmmreg*,xmmrm,xmmreg [rvms: vex.m3.w0.nds.l0.p1 7c /r /is4] AMD,SSE5,SO +VFNMSUBPS ymmreg,ymmreg*,ymmrm,ymmreg [rvms: vex.m3.w0.nds.l1.p1 7c /r /is4] AMD,SSE5,SY +VFNMSUBPS xmmreg,xmmreg*,xmmreg,xmmrm [rvsm: vex.m3.w1.nds.l0.p1 7c /r /is4] AMD,SSE5,SO +VFNMSUBPS ymmreg,ymmreg*,ymmreg,ymmrm [rvsm: vex.m3.w1.nds.l1.p1 7c /r /is4] AMD,SSE5,SY + +VFNMSUBSD xmmreg,xmmreg*,xmmrm,xmmreg [rvms: vex.m3.w0.nds.l0.p1 7f /r /is4] AMD,SSE5,SQ +VFNMSUBSD xmmreg,xmmreg*,xmmreg,xmmrm [rvsm: vex.m3.w1.nds.l0.p1 7f /r /is4] AMD,SSE5,SQ + +VFNMSUBSS xmmreg,xmmreg*,xmmrm,xmmreg [rvms: vex.m3.w0.nds.l0.p1 7e /r /is4] AMD,SSE5,SD +VFNMSUBSS xmmreg,xmmreg*,xmmreg,xmmrm [rvsm: vex.m3.w1.nds.l0.p1 7e /r /is4] AMD,SSE5,SD + +VFRCZPD xmmreg,xmmrm* [rm: xop.m9.w0.l0.p0 81 /r] AMD,SSE5,SO +VFRCZPD ymmreg,ymmrm* [rm: xop.m9.w0.l1.p0 81 /r] AMD,SSE5,SY + +VFRCZPS xmmreg,xmmrm* [rm: xop.m9.w0.l0.p0 80 /r] AMD,SSE5,SO +VFRCZPS ymmreg,ymmrm* [rm: xop.m9.w0.l1.p0 80 /r] AMD,SSE5,SY + +VFRCZSD xmmreg,xmmrm* [rm: xop.m9.w0.l0.p0 83 /r] AMD,SSE5,SQ + +VFRCZSS xmmreg,xmmrm* [rm: xop.m9.w0.l0.p0 82 /r] AMD,SSE5,SD +; +; fixed: spec mention imm[7:4] though it should be /is4 even in spec +VPCMOV xmmreg,xmmreg*,xmmrm,xmmreg [rvms: xop.m8.w0.nds.l0.p0 a2 /r /is4] AMD,SSE5,SO +VPCMOV ymmreg,ymmreg*,ymmrm,ymmreg [rvms: xop.m8.w0.nds.l1.p0 a2 /r /is4] AMD,SSE5,SY +VPCMOV xmmreg,xmmreg*,xmmreg,xmmrm [rvsm: xop.m8.w1.nds.l0.p0 a2 /r /is4] AMD,SSE5,SO +VPCMOV ymmreg,ymmreg*,ymmreg,ymmrm [rvsm: xop.m8.w1.nds.l1.p0 a2 /r /is4] AMD,SSE5,SY + +VPCOMB xmmreg,xmmreg*,xmmrm,imm [rvmi: xop.m8.w0.nds.l0.p0 cc /r ib] AMD,SSE5,SO +VPCOMD xmmreg,xmmreg*,xmmrm,imm [rvmi: xop.m8.w0.nds.l0.p0 ce /r ib] AMD,SSE5,SO +VPCOMQ xmmreg,xmmreg*,xmmrm,imm [rvmi: xop.m8.w0.nds.l0.p0 cf /r ib] AMD,SSE5,SO +; +; fixed: spec mention only 3 operands in mnemonics +VPCOMUB xmmreg,xmmreg*,xmmrm,imm [rvmi: xop.m8.w0.nds.l0.p0 ec /r ib] AMD,SSE5,SO +VPCOMUD xmmreg,xmmreg*,xmmrm,imm [rvmi: xop.m8.w0.nds.l0.p0 ee /r ib] AMD,SSE5,SO +VPCOMUQ xmmreg,xmmreg*,xmmrm,imm [rvmi: xop.m8.w0.nds.l0.p0 ef /r ib] AMD,SSE5,SO +; +; fixed: spec point wrong VPCOMB in mnemonic +VPCOMUW xmmreg,xmmreg*,xmmrm,imm [rvmi: xop.m8.w0.nds.l0.p0 ed /r ib] AMD,SSE5,SO +VPCOMW xmmreg,xmmreg*,xmmrm,imm [rvmi: xop.m8.w0.nds.l0.p0 cd /r ib] AMD,SSE5,SO + +VPHADDBD xmmreg,xmmrm* [rm: xop.m9.w0.l0.p0 c2 /r] AMD,SSE5,SO +VPHADDBQ xmmreg,xmmrm* [rm: xop.m9.w0.l0.p0 c3 /r] AMD,SSE5,SO +VPHADDBW xmmreg,xmmrm* [rm: xop.m9.w0.l0.p0 c1 /r] AMD,SSE5,SO +VPHADDDQ xmmreg,xmmrm* [rm: xop.m9.w0.l0.p0 cb /r] AMD,SSE5,SO +; +; fixed: spec has ymmreg for l0 +VPHADDUBD xmmreg,xmmrm* [rm: xop.m9.w0.l0.p0 d2 /r] AMD,SSE5,SO +VPHADDUBQ xmmreg,xmmrm* [rm: xop.m9.w0.l0.p0 d3 /r] AMD,SSE5,SO +VPHADDUBWD xmmreg,xmmrm* [rm: xop.m9.w0.l0.p0 d1 /r] AMD,SSE5,SO +; +; fixed: opcode db +VPHADDUDQ xmmreg,xmmrm* [rm: xop.m9.w0.l0.p0 db /r] AMD,SSE5,SO +VPHADDUWD xmmreg,xmmrm* [rm: xop.m9.w0.l0.p0 d6 /r] AMD,SSE5,SO +VPHADDUWQ xmmreg,xmmrm* [rm: xop.m9.w0.l0.p0 d7 /r] AMD,SSE5,SO +; +; fixed: spec has ymmreg for l0 +VPHADDWD xmmreg,xmmrm* [rm: xop.m9.w0.l0.p0 c6 /r] AMD,SSE5,SO +VPHADDWQ xmmreg,xmmrm* [rm: xop.m9.w0.l0.p0 d7 /r] AMD,SSE5,SO + +VPHSUBBW xmmreg,xmmrm* [rm: xop.m9.w0.l0.p0 e1 /r] AMD,SSE5,SO +VPHSUBDQ xmmreg,xmmrm* [rm: xop.m9.w0.l0.p0 e3 /r] AMD,SSE5,SO +VPHSUBWD xmmreg,xmmrm* [rm: xop.m9.w0.l0.p0 e2 /r] AMD,SSE5,SO + +VPMACSDD xmmreg,xmmreg*,xmmrm,xmmreg [rvms: xop.m8.w0.nds.l0.p0 9e /r /is4] AMD,SSE5,SO +VPMACSDQH xmmreg,xmmreg*,xmmrm,xmmreg [rvms: xop.m8.w0.nds.l0.p0 97 /r /is4] AMD,SSE5,SO +VPMACSDQL xmmreg,xmmreg*,xmmrm,xmmreg [rvms: xop.m8.w0.nds.l0.p0 9f /r /is4] AMD,SSE5,SO +VPMACSSDD xmmreg,xmmreg*,xmmrm,xmmreg [rvms: xop.m8.w0.nds.l0.p0 8e /r /is4] AMD,SSE5,SO +VPMACSSDQH xmmreg,xmmreg*,xmmrm,xmmreg [rvms: xop.m8.w0.nds.l0.p0 8f /r /is4] AMD,SSE5,SO +VPMACSSDQL xmmreg,xmmreg*,xmmrm,xmmreg [rvms: xop.m8.w0.nds.l0.p0 87 /r /is4] AMD,SSE5,SO +VPMACSSWD xmmreg,xmmreg*,xmmrm,xmmreg [rvms: xop.m8.w0.nds.l0.p0 86 /r /is4] AMD,SSE5,SO +VPMACSSWW xmmreg,xmmreg*,xmmrm,xmmreg [rvms: xop.m8.w0.nds.l0.p0 85 /r /is4] AMD,SSE5,SO +VPMACSWD xmmreg,xmmreg*,xmmrm,xmmreg [rvms: xop.m8.w0.nds.l0.p0 96 /r /is4] AMD,SSE5,SO +VPMACSWW xmmreg,xmmreg*,xmmrm,xmmreg [rvms: xop.m8.w0.nds.l0.p0 95 /r /is4] AMD,SSE5,SO +VPMADCSSWD xmmreg,xmmreg*,xmmrm,xmmreg [rvms: xop.m8.w0.nds.l0.p0 a6 /r /is4] AMD,SSE5,SO +VPMADCSWD xmmreg,xmmreg*,xmmrm,xmmreg [rvms: xop.m8.w0.nds.l0.p0 b6 /r /is4] AMD,SSE5,SO + +VPPERM xmmreg,xmmreg*,xmmreg,xmmrm [rvsm: xop.m8.w1.nds.l0.p0 a3 /r /is4] AMD,SSE5,SO +VPPERM xmmreg,xmmreg*,xmmrm,xmmreg [rvms: xop.m8.w0.nds.l0.p0 a3 /r /is4] AMD,SSE5,SO + +VPROTB xmmreg,xmmrm*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 90 /r] AMD,SSE5,SO +VPROTB xmmreg,xmmreg*,xmmrm [rvm: xop.m9.w1.nds.l0.p0 90 /r] AMD,SSE5,SO +; +; fixed: spec point xmmreg instead of reg/mem +VPROTB xmmreg,xmmrm*,imm [rmi: xop.m8.w0.l0.p0 c0 /r ib] AMD,SSE5 + +VPROTD xmmreg,xmmrm*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 92 /r] AMD,SSE5,SO +VPROTD xmmreg,xmmreg*,xmmrm [rvm: xop.m9.w1.nds.l0.p0 92 /r] AMD,SSE5,SO +; +; fixed: spec error /r is needed +VPROTD xmmreg,xmmrm*,imm [rmi: xop.m8.w0.l0.p0 c2 /r ib] AMD,SSE5,SO +VPROTQ xmmreg,xmmrm*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 93 /r] AMD,SSE5,SO +VPROTQ xmmreg,xmmreg*,xmmrm [rvm: xop.m9.w1.nds.l0.p0 93 /r] AMD,SSE5,SO +; +; fixed: spec error /r is needed +VPROTQ xmmreg,xmmrm*,imm [rmi: xop.m8.w0.l0.p0 c3 /r ib] AMD,SSE5,SO +VPROTW xmmreg,xmmrm*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 91 /r] AMD,SSE5,SO +VPROTW xmmreg,xmmreg*,xmmrm [rvm: xop.m9.w1.nds.l0.p0 91 /r] AMD,SSE5,SO +VPROTW xmmreg,xmmrm*,imm [rmi: xop.m8.w0.l0.p0 c1 /r ib] AMD,SSE5,SO + +VPSHAB xmmreg,xmmrm*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 98 /r] AMD,SSE5,SO +VPSHAB xmmreg,xmmreg*,xmmrm [rvm: xop.m9.w1.nds.l0.p0 98 /r] AMD,SSE5,SO + +VPSHAD xmmreg,xmmrm*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 9a /r] AMD,SSE5,SO +VPSHAD xmmreg,xmmreg*,xmmrm [rvm: xop.m9.w1.nds.l0.p0 9a /r] AMD,SSE5,SO + +VPSHAQ xmmreg,xmmrm*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 9b /r] AMD,SSE5,SO +VPSHAQ xmmreg,xmmreg*,xmmrm [rvm: xop.m9.w1.nds.l0.p0 9b /r] AMD,SSE5,SO + +VPSHAW xmmreg,xmmrm*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 99 /r] AMD,SSE5,SO +VPSHAW xmmreg,xmmreg*,xmmrm [rvm: xop.m9.w1.nds.l0.p0 99 /r] AMD,SSE5,SO + +VPSHLB xmmreg,xmmrm*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 94 /r] AMD,SSE5,SO +VPSHLB xmmreg,xmmreg*,xmmrm [rvm: xop.m9.w1.nds.l0.p0 94 /r] AMD,SSE5,SO + +; +; fixed: spec has ymmreg for l0 +VPSHLD xmmreg,xmmrm*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 96 /r] AMD,SSE5,SO +VPSHLD xmmreg,xmmreg*,xmmrm [rvm: xop.m9.w1.nds.l0.p0 96 /r] AMD,SSE5,SO + +VPSHLQ xmmreg,xmmrm*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 97 /r] AMD,SSE5,SO +VPSHLQ xmmreg,xmmreg*,xmmrm [rvm: xop.m9.w1.nds.l0.p0 97 /r] AMD,SSE5,SO + +VPSHLW xmmreg,xmmrm*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 95 /r] AMD,SSE5,SO +VPSHLW xmmreg,xmmreg*,xmmrm [rvm: xop.m9.w1.nds.l0.p0 95 /r] AMD,SSE5,SO + + ;# Systematic names for the hinting nop instructions ; These should be last in the file HINT_NOP0 rm16 \320\2\x0F\x18\200 P6,UNDOC @@ -32,7 +32,7 @@ struct disasm_index { /* Tables for the assembler and disassembler, respectively */ extern const struct itemplate * const nasm_instructions[]; extern const struct disasm_index itable[256]; -extern const struct disasm_index * const itable_VEX[32][8]; +extern const struct disasm_index * const itable_vex[2][32][8]; /* Common table for the byte codes */ extern const uint8_t nasm_bytecodes[]; @@ -123,6 +123,7 @@ extern const uint8_t nasm_bytecodes[]; #define IF_NEHALEM 0x0B000000UL /* Nehalem instruction */ #define IF_WESTMERE 0x0C000000UL /* Westmere instruction */ #define IF_SANDYBRIDGE 0x0D000000UL /* Sandy Bridge instruction */ +#define IF_FUTURE 0x0E000000UL /* Future processor (not yet disclosed) */ #define IF_X64 (IF_LONG|IF_X86_64) #define IF_IA64 0x0F000000UL /* IA64 instructions (in x86 mode) */ #define IF_CYRIX 0x10000000UL /* Cyrix-specific instruction */ @@ -1,11 +1,41 @@ #!/usr/bin/perl +## -------------------------------------------------------------------------- +## +## Copyright 1996-2009 The NASM Authors - All Rights Reserved +## See the file AUTHORS included with the NASM distribution for +## the specific copyright holders. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following +## conditions are met: +## +## * Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above +## copyright notice, this list of conditions and the following +## disclaimer in the documentation and/or other materials provided +## with the distribution. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## -------------------------------------------------------------------------- + # -# insns.pl produce insnsa.c, insnsd.c, insnsi.h, insnsn.c from insns.dat +# insns.pl # -# The Netwide Assembler is copyright (C) 1996 Simon Tatham and -# Julian Hall. All rights reserved. The software is -# redistributable under the license given in the file "LICENSE" -# distributed in the NASM archive. +# Parse insns.dat and produce generated source code files # Opcode prefixes which need their own opcode tables # LONGER PREFIXES FIRST! @@ -14,15 +44,23 @@ # This should match MAX_OPERANDS from nasm.h $MAX_OPERANDS = 5; -# Add VEX prefixes +# Add VEX/XOP prefixes +@vex_class = ( 'vex', 'xop' ); +$vex_classes = scalar(@vex_class); @vexlist = (); -for ($m = 0; $m < 32; $m++) { - for ($lp = 0; $lp < 8; $lp++) { - push(@vexlist, sprintf("VEX%02X%01X", $m, $lp)); +%vexmap = (); +for ($c = 0; $c < $vex_classes; $c++) { + $vexmap{$vex_class[$c]} = $c; + for ($m = 0; $m < 32; $m++) { + for ($lp = 0; $lp < 8; $lp++) { + push(@vexlist, sprintf("%s%02X%01X", $vex_class[$c], $m, $lp)); + } } } @disasm_prefixes = (@vexlist, @disasm_prefixes); +@bytecode_count = (0) x 256; + print STDERR "Reading insns.dat...\n"; @args = (); @@ -48,38 +86,78 @@ open (F, $fname) || die "unable to open $fname"; $line = 0; $insns = 0; while (<F>) { - $line++; - chomp; - next if ( /^\s*(\;.*|)$/ ); # comments or blank lines - - unless (/^\s*(\S+)\s+(\S+)\s+(\S+|\[.*\])\s+(\S+)\s*$/) { - warn "line $line does not contain four fields\n"; - next; - } - @fields = ($1, $2, $3, $4); - ($formatted, $nd) = format_insn(@fields); - if ($formatted) { - $insns++; - $aname = "aa_$fields[0]"; - push @$aname, $formatted; - } - if ( $fields[0] =~ /cc$/ ) { - # Conditional instruction - $k_opcodes_cc{$fields[0]}++; - } else { - # Unconditional instruction - $k_opcodes{$fields[0]}++; - } - if ($formatted && !$nd) { - push @big, $formatted; - my @sseq = startseq($fields[2]); - foreach $i (@sseq) { - if (!defined($dinstables{$i})) { - $dinstables{$i} = []; + $line++; + chomp; + next if ( /^\s*(\;.*|)$/ ); # comments or blank lines + + unless (/^\s*(\S+)\s+(\S+)\s+(\S+|\[.*\])\s+(\S+)\s*$/) { + warn "line $line does not contain four fields\n"; + next; + } + @fields = ($1, $2, $3, $4); + @field_list = ([@fields, 0]); + + if ($fields[1] =~ /\*/) { + # This instruction has relaxed form(s) + if ($fields[2] !~ /^\[/) { + warn "line $line has an * operand but uses raw bytecodes\n"; + next; + } + + $opmask = 0; + @ops = split(/,/, $fields[1]); + for ($oi = 0; $oi < scalar @ops; $oi++) { + if ($ops[$oi] =~ /\*$/) { + if ($oi == 0) { + warn "line $line has a first operand with a *\n"; + next; + } + $opmask |= 1 << $oi; + } + } + + for ($oi = 1; $oi < (1 << scalar @ops); $oi++) { + if (($oi & ~$opmask) == 0) { + my @xops = (); + my $omask = ~$oi; + for ($oj = 0; $oj < scalar(@ops); $oj++) { + if ($omask & 1) { + push(@xops, $ops[$oj]); + } + $omask >>= 1; + } + push(@field_list, [$fields[0], join(',', @xops), + $fields[2], $fields[3], $oi]); + } + } + } + + foreach $fptr (@field_list) { + @fields = @$fptr; + ($formatted, $nd) = format_insn(@fields); + if ($formatted) { + $insns++; + $aname = "aa_$fields[0]"; + push @$aname, $formatted; + } + if ( $fields[0] =~ /cc$/ ) { + # Conditional instruction + $k_opcodes_cc{$fields[0]}++; + } else { + # Unconditional instruction + $k_opcodes{$fields[0]}++; + } + if ($formatted && !$nd) { + push @big, $formatted; + my @sseq = startseq($fields[2], $fields[4]); + foreach $i (@sseq) { + if (!defined($dinstables{$i})) { + $dinstables{$i} = []; + } + push(@{$dinstables{$i}}, $#big); + } } - push(@{$dinstables{$i}}, $#big); } - } } close F; @@ -134,6 +212,20 @@ if ( !defined($output) || $output eq 'b') { } print B "};\n"; + print B "\n"; + print B "/*\n"; + print B " * Bytecode frequencies (including reuse):\n"; + print B " *\n"; + for ($i = 0; $i < 32; $i++) { + print B " *"; + for ($j = 0; $j < 256; $j += 32) { + print B " |" if ($j); + printf B " %3o:%4d", $i+$j, $bytecode_count[$i+$j]; + } + print B "\n"; + } + print B " */\n"; + close B; } @@ -227,20 +319,26 @@ if ( !defined($output) || $output eq 'd' ) { print D "};\n"; } - print D "\nconst struct disasm_index * const itable_VEX[32][8] = {\n "; - for ($m = 0; $m < 32; $m++) { - print D " {\n"; - for ($lp = 0; $lp < 8; $lp++) { - $vp = sprintf("VEX%02X%01X", $m, $lp); - if ($is_prefix{$vp}) { - printf D " itable_%s,\n", $vp; - } else { - print D " NULL,\n"; + printf D "\nconst struct disasm_index * const itable_vex[%d][32][8] =\n", + $vex_classes; + print D "{\n"; + for ($c = 0; $c < $vex_classes; $c++) { + print D " {\n"; + for ($m = 0; $m < 32; $m++) { + print D " {\n"; + for ($lp = 0; $lp < 8; $lp++) { + $vp = sprintf("%s%02X%01X", $vex_class[$c], $m, $lp); + if ($is_prefix{$vp}) { + printf D " itable_%s,\n", $vp; + } else { + print D " NULL,\n"; + } } + print D " },\n"; } - print D " },"; + print D " },\n"; } - print D "\n};\n"; + print D "};\n"; close D; } @@ -262,7 +360,7 @@ if ( !defined($output) || $output eq 'i' ) { foreach $i (@opcodes, @opcodes_cc) { print I "\tI_${i},\n"; $len = length($i); - $len++ if ( $i =~ /cc$/ ); # Condition codes can be 3 characters long + $len++ if ( $i =~ /cc$/ ); # Condition codes can be 3 characters long $maxlen = $len if ( $len > $maxlen ); } print I "\tI_none = -1\n"; @@ -299,14 +397,40 @@ if ( !defined($output) || $output eq 'n' ) { printf STDERR "Done: %d instructions\n", $insns; -sub format_insn(@) { - my ($opcode, $operands, $codes, $flags) = @_; +# Count primary bytecodes, for statistics +sub count_bytecodes(@) { + my $skip = 0; + foreach my $bc (@_) { + if ($skip) { + $skip--; + next; + } + $bytecode_count[$bc]++; + if ($bc >= 01 && $bc <= 04) { + $skip = $bc; + } elsif (($bc & ~03) == 010) { + $skip = 1; + } elsif (($bc & ~013) == 0144) { + $skip = 1; + } elsif ($bc == 0172) { + $skip = 1; + } elsif ($bc >= 0260 && $bc <= 0270) { + $skip = 2; + } elsif ($bc == 0330) { + $skip = 1; + } + } +} + +sub format_insn($$$$$) { + my ($opcode, $operands, $codes, $flags, $relax) = @_; my $num, $nd = 0; my @bytecode; return (undef, undef) if $operands eq "ignore"; # format the operands + $operands =~ s/\*//g; $operands =~ s/:/|colon,/g; $operands =~ s/mem(\d+)/mem|bits$1/g; $operands =~ s/mem/memory/g; @@ -333,9 +457,10 @@ sub format_insn(@) { $flags =~ s/(\|IF_ND|IF_ND\|)//, $nd = 1 if $flags =~ /IF_ND/; $flags = "IF_" . $flags; - @bytecode = (decodify($codes), 0); + @bytecode = (decodify($codes, $relax), 0); push(@bytecode_list, [@bytecode]); $codes = hexstr(@bytecode); + count_bytecodes(@bytecode); ("{I_$opcode, $num, {$operands}, \@\@CODES-$codes\@\@, $flags},", $nd); } @@ -373,14 +498,14 @@ sub addprefix ($@) { # # Turn a code string into a sequence of bytes # -sub decodify($) { +sub decodify($$) { # Although these are C-syntax strings, by convention they should have # only octal escapes (for directives) and hexadecimal escapes # (for verbatim bytes) - my($codestr) = @_; + my($codestr, $relax) = @_; if ($codestr =~ /^\s*\[([^\]]*)\]\s*$/) { - return byte_code_compile($1); + return byte_code_compile($1, $relax); } my $c = $codestr; @@ -416,81 +541,83 @@ sub hexstr(@) { # Here we determine the range of possible starting bytes for a given # instruction. We need only consider the codes: -# \1 \2 \3 mean literal bytes, of course -# \4 \5 \6 \7 mean PUSH/POP of segment registers: special case +# \[1234] mean literal bytes, of course # \1[0123] mean byte plus register value # \330 means byte plus condition code # \0 or \340 mean give up and return empty set +# \34[4567] mean PUSH/POP of segment registers: special case # \17[234] skip is4 control byte # \26x \270 skip VEX control bytes -sub startseq($) { - my ($codestr) = @_; - my $word, @range; - my @codes = (); - my $c = $codestr; - my $c0, $c1, $i; - my $prefix = ''; - - @codes = decodify($codestr); - - while ($c0 = shift(@codes)) { - $c1 = $codes[0]; - if ($c0 == 01 || $c0 == 02 || $c0 == 03) { - # Fixed byte string - my $fbs = $prefix; - while (1) { - if ($c0 == 01 || $c0 == 02 || $c0 == 03) { - while ($c0--) { - $fbs .= sprintf("%02X", shift(@codes)); - } - } else { - last; - } - $c0 = shift(@codes); - } - - foreach $pfx (@disasm_prefixes) { - if (substr($fbs, 0, length($pfx)) eq $pfx) { - $prefix = $pfx; - $fbs = substr($fbs, length($pfx)); - last; - } - } - - if ($fbs ne '') { - return ($prefix.substr($fbs,0,2)); - } - - unshift(@codes, $c0); - } elsif ($c0 == 04) { - return addprefix($prefix, 0x07, 0x17, 0x1F); - } elsif ($c0 == 05) { - return addprefix($prefix, 0xA1, 0xA9); - } elsif ($c0 == 06) { - return addprefix($prefix, 0x06, 0x0E, 0x16, 0x1E); - } elsif ($c0 == 07) { - return addprefix($prefix, 0xA0, 0xA8); - } elsif ($c0 >= 010 && $c0 <= 013) { - return addprefix($prefix, $c1..($c1+7)); - } elsif (($c0 & ~013) == 0144) { - return addprefix($prefix, $c1, $c1|2); - } elsif ($c0 == 0330) { - return addprefix($prefix, $c1..($c1+15)); - } elsif ($c0 == 0 || $c0 == 0340) { - return $prefix; - } elsif (($c0 & ~3) == 0260 || $c0 == 0270) { - my $m,$wlp,$vxp; - $m = shift(@codes); - $wlp = shift(@codes); - $prefix .= sprintf('VEX%02X%01X', $m, $wlp & 7); - } elsif ($c0 >= 0172 && $c0 <= 174) { - shift(@codes); # Skip is4 control byte - } else { - # We really need to be able to distinguish "forbidden" - # and "ignorable" codes here - } - } - return $prefix; +sub startseq($$) { + my ($codestr, $relax) = @_; + my $word, @range; + my @codes = (); + my $c = $codestr; + my $c0, $c1, $i; + my $prefix = ''; + + @codes = decodify($codestr, $relax); + + while ($c0 = shift(@codes)) { + $c1 = $codes[0]; + if ($c0 >= 01 && $c0 <= 04) { + # Fixed byte string + my $fbs = $prefix; + while (1) { + if ($c0 >= 01 && $c0 <= 04) { + while ($c0--) { + $fbs .= sprintf("%02X", shift(@codes)); + } + } else { + last; + } + $c0 = shift(@codes); + } + + foreach $pfx (@disasm_prefixes) { + if (substr($fbs, 0, length($pfx)) eq $pfx) { + $prefix = $pfx; + $fbs = substr($fbs, length($pfx)); + last; + } + } + + if ($fbs ne '') { + return ($prefix.substr($fbs,0,2)); + } + + unshift(@codes, $c0); + } elsif ($c0 >= 010 && $c0 <= 013) { + return addprefix($prefix, $c1..($c1+7)); + } elsif (($c0 & ~013) == 0144) { + return addprefix($prefix, $c1, $c1|2); + } elsif ($c0 == 0330) { + return addprefix($prefix, $c1..($c1+15)); + } elsif ($c0 == 0 || $c0 == 0340) { + return $prefix; + } elsif ($c0 == 0344) { + return addprefix($prefix, 0x06, 0x0E, 0x16, 0x1E); + } elsif ($c0 == 0345) { + return addprefix($prefix, 0x07, 0x17, 0x1F); + } elsif ($c0 == 0346) { + return addprefix($prefix, 0xA0, 0xA8); + } elsif ($c0 == 0347) { + return addprefix($prefix, 0xA1, 0xA9); + } elsif (($c0 & ~3) == 0260 || $c0 == 0270) { + my $c,$m,$wlp; + $m = shift(@codes); + $wlp = shift(@codes); + $c = ($m >> 6); + $m = $m & 31; + $prefix .= sprintf('%s%02X%01X', $vex_class[$c], $m, $wlp & 7); + } elsif ($c0 >= 0172 && $c0 <= 174) { + shift(@codes); # Skip is4 control byte + } else { + # We really need to be able to distinguish "forbidden" + # and "ignorable" codes here + } + } + return $prefix; } # @@ -514,8 +641,8 @@ sub startseq($) { # For an operand that should be filled into more than one field, # enter it as e.g. "r+v". # -sub byte_code_compile($) { - my($str) = @_; +sub byte_code_compile($$) { + my($str, $relax) = @_; my $opr; my $opc; my @codes = (); @@ -523,6 +650,7 @@ sub byte_code_compile($) { my %oppos = (); my $i; my $op, $oq; + my $opex; unless ($str =~ /^(([^\s:]*)\:|)\s*(.*\S)\s*$/) { die "$fname: $line: cannot parse: [$str]\n"; @@ -536,6 +664,10 @@ sub byte_code_compile($) { if ($c eq '+') { $op--; } else { + if ($relax & 1) { + $op--; + } + $relax >>= 1; $oppos{$c} = $op++; } } @@ -564,6 +696,8 @@ sub byte_code_compile($) { push(@codes, 0334); } elsif ($op eq 'repe') { push(@codes, 0335); + } elsif ($op eq 'nohi') { # Use spl/bpl/sil/dil even without REX + push(@codes, 0325); } elsif ($prefix_ok && $op =~ /^(66|f2|f3|np)$/) { # 66/F2/F3 prefix used as an opcode extension, or np = no prefix if ($op eq '66') { @@ -576,7 +710,8 @@ sub byte_code_compile($) { push(@codes, 0360); } } elsif ($op =~ /^[0-9a-f]{2}$/) { - if (defined($litix) && $litix+$codes[$litix]+1 == scalar @codes) { + if (defined($litix) && $litix+$codes[$litix]+1 == scalar @codes && + $codes[$litix] < 4) { $codes[$litix]++; push(@codes, hex $op); } else { @@ -588,21 +723,26 @@ sub byte_code_compile($) { if (!defined($oppos{'r'}) || !defined($oppos{'m'})) { die "$fname: $line: $op requires r and m operands\n"; } - push(@codes, 0100 + ($oppos{'m'} << 3) + $oppos{'r'}); + $opex = (($oppos{'m'} & 4) ? 06 : 0) | + (($oppos{'r'} & 4) ? 05 : 0); + push(@codes, $opex) if ($opex); + push(@codes, 0100 + (($oppos{'m'} & 3) << 3) + ($oppos{'r'} & 3)); $prefix_ok = 0; } elsif ($op =~ m:^/([0-7])$:) { if (!defined($oppos{'m'})) { die "$fname: $line: $op requires m operand\n"; } - push(@codes, 0200 + ($oppos{'m'} << 3) + $1); + push(@codes, 06) if ($oppos{'m'} & 4); + push(@codes, 0200 + (($oppos{'m'} & 3) << 3) + $1); $prefix_ok = 0; - } elsif ($op =~ /^vex(|\..*)$/) { + } elsif ($op =~ /^(vex|xop)(|\..*)$/) { + my $c = $vexmap{$1}; my ($m,$w,$l,$p) = (undef,2,undef,0); my $has_nds = 0; - foreach $oq (split(/\./, $op)) { - if ($oq eq 'vex') { - # prefix - } elsif ($oq eq '128' || $oq eq 'l0') { + my @subops = split(/\./, $op); + shift @subops; # Drop prefix + foreach $oq (@subops) { + if ($oq eq '128' || $oq eq 'l0') { $l = 0; } elsif ($oq eq '256' || $oq eq 'l1') { $l = 1; @@ -614,11 +754,13 @@ sub byte_code_compile($) { $w = 2; } elsif ($oq eq 'ww') { $w = 3; - } elsif ($oq eq '66') { + } elsif ($oq eq 'p0') { + $p = 0; + } elsif ($oq eq '66' || $oq eq 'p1') { $p = 1; - } elsif ($oq eq 'f3') { + } elsif ($oq eq 'f3' || $oq eq 'p2') { $p = 2; - } elsif ($oq eq 'f2') { + } elsif ($oq eq 'f2' || $oq eq 'p3') { $p = 3; } elsif ($oq eq '0f') { $m = 1; @@ -628,7 +770,7 @@ sub byte_code_compile($) { $m = 3; } elsif ($oq =~ /^m([0-9]+)$/) { $m = $1+0; - } elsif ($oq eq 'nds' || $oq eq 'ndd') { + } elsif ($oq eq 'nds' || $oq eq 'ndd' || $oq eq 'dds') { if (!defined($oppos{'v'})) { die "$fname: $line: vex.$oq without 'v' operand\n"; } @@ -643,8 +785,8 @@ sub byte_code_compile($) { if (defined($oppos{'v'}) && !$has_nds) { die "$fname: $line: 'v' operand without vex.nds or vex.ndd\n"; } - push(@codes, defined($oppos{'v'}) ? 0260+$oppos{'v'} : 0270, - $m, ($w << 3)+($l << 2)+$p); + push(@codes, defined($oppos{'v'}) ? 0260+($oppos{'v'} & 3) : 0270, + ($c << 6)+$m, ($w << 3)+($l << 2)+$p); $prefix_ok = 0; } elsif ($op =~ /^\/drex([01])$/) { my $oc0 = $1; @@ -657,56 +799,79 @@ sub byte_code_compile($) { # this at (roughly) the position of the drex byte itself. # This allows us to match the AMD documentation and still # do the right thing. - unshift(@codes, 0160+$oppos{'d'}+($oc0 ? 4 : 0)); - } elsif ($op =~ /^(ib\,s|ib|ib\,w|iw|iwd|id|iwdq|rel|rel8|rel16|rel32|iq|seg|ibw|ibd|ibd,s)$/) { + unshift(@codes, 0160+($oppos{'d'} & 3)+($oc0 ? 4 : 0)); + unshift(@codes, 05) if ($oppos{'d'} & 4); + } elsif ($op =~ /^(ib\,s|ib|ibx|ib\,w|iw|iwd|id|idx|iwdq|rel|rel8|rel16|rel32|iq|seg|ibw|ibd|ibd,s)$/) { if (!defined($oppos{'i'})) { die "$fname: $line: $op without 'i' operand\n"; } if ($op eq 'ib,s') { # Signed imm8 - push(@codes, 014+$oppos{'i'}); + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 014+($oppos{'i'} & 3)); } elsif ($op eq 'ib') { # imm8 - push(@codes, 020+$oppos{'i'}); + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 020+($oppos{'i'} & 3)); } elsif ($op eq 'ib,u') { # Unsigned imm8 - push(@codes, 024+$oppos{'i'}); + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 024+($oppos{'i'} & 3)); } elsif ($op eq 'iw') { # imm16 - push(@codes, 030+$oppos{'i'}); + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 030+($oppos{'i'} & 3)); + } elsif ($op eq 'ibx') { # imm8 sign-extended to opsize + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 0274+($oppos{'i'} & 3)); } elsif ($op eq 'iwd') { # imm16 or imm32, depending on opsize - push(@codes, 034+$oppos{'i'}); + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 034+($oppos{'i'} & 3)); } elsif ($op eq 'id') { # imm32 - push(@codes, 040+$oppos{'i'}); + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 040+($oppos{'i'} & 3)); + } elsif ($op eq 'idx') { # imm32 extended to 64 bits + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 0254+($oppos{'i'} & 3)); } elsif ($op eq 'iwdq') { # imm16/32/64, depending on opsize - push(@codes, 044+$oppos{'i'}); + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 044+($oppos{'i'} & 3)); } elsif ($op eq 'rel8') { - push(@codes, 050+$oppos{'i'}); + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 050+($oppos{'i'} & 3)); } elsif ($op eq 'iq') { - push(@codes, 054+$oppos{'i'}); + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 054+($oppos{'i'} & 3)); } elsif ($op eq 'rel16') { - push(@codes, 060+$oppos{'i'}); + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 060+($oppos{'i'} & 3)); } elsif ($op eq 'rel') { # 16 or 32 bit relative operand - push(@codes, 064+$oppos{'i'}); + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 064+($oppos{'i'} & 3)); } elsif ($op eq 'rel32') { - push(@codes, 070+$oppos{'i'}); + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 070+($oppos{'i'} & 3)); } elsif ($op eq 'seg') { - push(@codes, 074+$oppos{'i'}); + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 074+($oppos{'i'} & 3)); } elsif ($op eq 'ibw') { # imm16 that can be bytified if (!defined($s_pos)) { die "$fname: $line: $op without a +s byte\n"; } $codes[$s_pos] += 0144; - push(@codes, 0140+$oppos{'i'}); + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 0140+($oppos{'i'} & 3)); } elsif ($op eq 'ibd') { # imm32 that can be bytified if (!defined($s_pos)) { die "$fname: $line: $op without a +s byte\n"; } $codes[$s_pos] += 0154; - push(@codes, 0150+$oppos{'i'}); + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 0150+($oppos{'i'} & 3)); } elsif ($op eq 'ibd,s') { # imm32 that can be bytified, sign extended to 64 bits if (!defined($s_pos)) { die "$fname: $line: $op without a +s byte\n"; } $codes[$s_pos] += 0154; - push(@codes, 0250+$oppos{'i'}); + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 0250+($oppos{'i'} & 3)); } $prefix_ok = 0; } elsif ($op eq '/is4') { @@ -734,7 +899,8 @@ sub byte_code_compile($) { die "$fname: $line: $op without 'i' operand\n"; } $s_pos = scalar @codes; - push(@codes, $oppos{'i'}, hex $1); + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, $oppos{'i'} & 3, hex $1); $prefix_ok = 0; } elsif ($op =~ /^([0-9a-f]{2})\+c$/) { push(@codes, 0330, hex $1); @@ -1,9 +1,38 @@ -/* labels.c label handling for the Netwide Assembler +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * labels.c label handling for the Netwide Assembler */ #include "compiler.h" @@ -41,15 +70,16 @@ #define END_BLOCK -2 #define BOGUS_VALUE -4 -#define PERMTS_SIZE 4096 /* size of text blocks */ -#if (PERMTS_SIZE > IDLEN_MAX) -#error "IPERMTS_SIZE must be less than or equal to IDLEN_MAX" +#define PERMTS_SIZE 16384 /* size of text blocks */ +#if (PERMTS_SIZE < IDLEN_MAX) +#error "IPERMTS_SIZE must be greater than or equal to IDLEN_MAX" #endif /* values for label.defn.is_global */ -#define DEFINED_BIT 1 -#define GLOBAL_BIT 2 -#define EXTERN_BIT 4 +#define DEFINED_BIT 1 +#define GLOBAL_BIT 2 +#define EXTERN_BIT 4 +#define COMMON_BIT 8 #define NOT_DEFINED_YET 0 #define TYPE_MASK 3 @@ -77,7 +107,7 @@ struct permts { /* permanent text storage */ char data[PERMTS_SIZE]; /* ... the data block itself */ }; -extern bool global_offset_changed; /* defined in nasm.c */ +extern int64_t global_offset_changed; /* defined in nasm.c */ static struct hash_table ltab; /* labels hash table */ static union label *ldata; /* all label data blocks */ @@ -209,7 +239,9 @@ void redefine_label(char *label, int32_t segment, int64_t offset, char *special, prevlabel = lptr->defn.label; } - global_offset_changed |= (lptr->defn.offset != offset); + if (lptr->defn.offset != offset) + global_offset_changed++; + lptr->defn.offset = offset; lptr->defn.segment = segment; @@ -270,9 +302,10 @@ void define_label(char *label, int32_t segment, int64_t offset, char *special, if (isextrn) lptr->defn.is_global |= EXTERN_BIT; - if (!islocalchar(label[0]) && is_norm) /* not local, but not special either */ + if (!islocalchar(label[0]) && is_norm) { + /* not local, but not special either */ prevlabel = lptr->defn.label; - else if (islocal(label) && !*prevlabel) { + } else if (islocal(label) && !*prevlabel) { error(ERR_NONFATAL, "attempt to define a local label before any" " non-local labels"); } @@ -321,26 +354,32 @@ void define_common(char *label, int32_t segment, int32_t size, char *special, union label *lptr; lptr = find_label(label, 1); - if (lptr->defn.is_global & DEFINED_BIT) { - error(ERR_NONFATAL, "symbol `%s' redefined", label); - return; + if ((lptr->defn.is_global & DEFINED_BIT) && + (passn == 1 || !(lptr->defn.is_global & COMMON_BIT))) { + error(ERR_NONFATAL, "symbol `%s' redefined", label); + return; } - lptr->defn.is_global |= DEFINED_BIT; + lptr->defn.is_global |= DEFINED_BIT|COMMON_BIT; - if (!islocalchar(label[0])) /* not local, but not special either */ + if (!islocalchar(label[0])) { prevlabel = lptr->defn.label; - else + } else { error(ERR_NONFATAL, "attempt to define a local label as a " "common variable"); + return; + } lptr->defn.segment = segment; lptr->defn.offset = 0; + if (pass0 == 0) + return; + ofmt->symdef(lptr->defn.label, segment, size, 2, - special ? special : lptr->defn.special); + special ? special : lptr->defn.special); ofmt->current_dfmt->debug_deflabel(lptr->defn.label, segment, size, 2, - special ? special : lptr->defn. - special); + special ? special : lptr->defn. + special); } void declare_as_global(char *label, char *special, efunc error) @@ -362,9 +401,11 @@ void declare_as_global(char *label, char *special, efunc error) case GLOBAL_SYMBOL: break; case LOCAL_SYMBOL: - if (!lptr->defn.is_global & EXTERN_BIT) - error(ERR_NONFATAL, "symbol `%s': GLOBAL directive must" - " appear before symbol definition", label); + if (!(lptr->defn.is_global & EXTERN_BIT)) { + error(ERR_WARNING, "symbol `%s': GLOBAL directive " + "after symbol definition is an experimental feature", label); + lptr->defn.is_global = GLOBAL_SYMBOL; + } break; } } @@ -428,6 +469,8 @@ static char *perm_copy(const char *string) char *p; int len = strlen(string)+1; + nasm_assert(len <= PERMTS_SIZE); + if (perm_tail->size - perm_tail->usage < len) { perm_tail->next = (struct permts *)nasm_malloc(sizeof(struct permts)); @@ -1,9 +1,38 @@ -/* labels.h header file for labels.c +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * labels.h header file for labels.c */ #ifndef LABELS_H @@ -1,11 +1,38 @@ -/* listing.c listing file generator for the Netwide Assembler +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: * - * initial version 2/vii/97 by Simon Tatham + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * listing.c listing file generator for the Netwide Assembler */ #include "compiler.h" @@ -38,7 +65,9 @@ static char xdigit[] = "0123456789ABCDEF"; #define HEX(a,b) (*(a)=xdigit[((b)>>4)&15],(a)[1]=xdigit[(b)&15]); static char listline[LIST_MAX_LEN]; -static int listlinep; +static bool listlinep; + +static char listerror[LIST_MAX_LEN]; static char listdata[2 * LIST_INDENT]; /* we need less than that actually */ static int32_t listoffset; @@ -55,6 +84,8 @@ static FILE *listfp; static void list_emit(void) { + int i; + if (!listlinep && !listdata[0]) return; @@ -78,18 +109,35 @@ static void list_emit(void) putc('\n', listfp); listlinep = false; listdata[0] = '\0'; + + if (listerror[0]) { + fprintf(listfp, "%6"PRId32" ", ++listlineno); + for (i = 0; i < LIST_HEXBIT; i++) + putc('*', listfp); + + if (listlevel_e) + fprintf(listfp, " %s<%d>", (listlevel < 10 ? " " : ""), + listlevel_e); + else + fprintf(listfp, " "); + + fprintf(listfp, " %s\n", listerror); + listerror[0] = '\0'; + } } static void list_init(char *fname, efunc error) { listfp = fopen(fname, "w"); if (!listfp) { - error(ERR_NONFATAL, "unable to open listing file `%s'", fname); + error(ERR_NONFATAL, "unable to open listing file `%s'", + fname); return; } *listline = '\0'; listlineno = 0; + *listerror = '\0'; listp = true; listlevel = 0; suppress = 0; @@ -316,11 +364,24 @@ static void list_downlevel(int type) } } +static void list_error(int severity, const char *pfx, const char *msg) +{ + if (!listfp) + return; + + snprintf(listerror, sizeof listerror, "%s%s", pfx, msg); + + if ((severity & ERR_MASK) >= ERR_FATAL) + list_emit(); +} + + ListGen nasmlist = { list_init, list_cleanup, list_output, list_line, list_uplevel, - list_downlevel + list_downlevel, + list_error }; @@ -1,9 +1,38 @@ -/* listing.h header file for listing.c +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * listing.h header file for listing.c */ #ifndef NASM_LISTING_H @@ -1,11 +1,40 @@ #!/usr/bin/perl +## -------------------------------------------------------------------------- +## +## Copyright 1996-2009 The NASM Authors - All Rights Reserved +## See the file AUTHORS included with the NASM distribution for +## the specific copyright holders. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following +## conditions are met: +## +## * Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above +## copyright notice, this list of conditions and the following +## disclaimer in the documentation and/or other materials provided +## with the distribution. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## -------------------------------------------------------------------------- + # # macros.pl produce macros.c from standard.mac # -# The Netwide Assembler is copyright (C) 1996 Simon Tatham and -# Julian Hall. All rights reserved. The software is -# redistributable under the license given in the file "LICENSE" -# distributed in the NASM archive. require 'phash.ph'; require 'pptok.ph'; @@ -47,7 +76,7 @@ print OUT "\n"; print OUT "#include \"tables.h\"\n"; print OUT "#include \"nasmlib.h\"\n"; print OUT "#include \"hashtbl.h\"\n"; -print OUT "#include \"outform.h\"\n"; +print OUT "#include \"output/outform.h\"\n"; print OUT "\n"; print OUT "#if 1\n"; print OUT "const unsigned char nasm_stdmac[] = {"; @@ -66,6 +95,12 @@ foreach $fname ( @ARGV ) { while (<INPUT>) { $line++; chomp; + while (/^(.*)\\$/) { + $_ = $1; + $_ .= <INPUT>; + chomp; + $line++; + } if (m/^\s*\*END\*TASM\*MACROS\*\s*$/) { $tasm_count = $index; print OUT " /* End of TASM macros */\n"; diff --git a/macros/altreg.mac b/macros/altreg.mac index 83d69679..16134cdc 100644 --- a/macros/altreg.mac +++ b/macros/altreg.mac @@ -1,3 +1,36 @@ +;; -------------------------------------------------------------------------- +;; +;; Copyright 1996-2009 The NASM Authors - All Rights Reserved +;; See the file AUTHORS included with the NASM distribution for +;; the specific copyright holders. +;; +;; Redistribution and use in source and binary forms, with or without +;; modification, are permitted provided that the following +;; conditions are met: +;; +;; * Redistributions of source code must retain the above copyright +;; notice, this list of conditions and the following disclaimer. +;; * Redistributions in binary form must reproduce the above +;; copyright notice, this list of conditions and the following +;; disclaimer in the documentation and/or other materials provided +;; with the distribution. +;; +;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +;; CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +;; INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +;; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +;; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;; NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +;; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +;; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +;; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +;; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;; +;; -------------------------------------------------------------------------- + ;; ;; altreg.mac ;; diff --git a/macros/smartalign.mac b/macros/smartalign.mac index b79a8549..51779c64 100644 --- a/macros/smartalign.mac +++ b/macros/smartalign.mac @@ -1,3 +1,36 @@ +;; -------------------------------------------------------------------------- +;; +;; Copyright 1996-2009 The NASM Authors - All Rights Reserved +;; See the file AUTHORS included with the NASM distribution for +;; the specific copyright holders. +;; +;; Redistribution and use in source and binary forms, with or without +;; modification, are permitted provided that the following +;; conditions are met: +;; +;; * Redistributions of source code must retain the above copyright +;; notice, this list of conditions and the following disclaimer. +;; * Redistributions in binary form must reproduce the above +;; copyright notice, this list of conditions and the following +;; disclaimer in the documentation and/or other materials provided +;; with the distribution. +;; +;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +;; CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +;; INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +;; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +;; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;; NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +;; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +;; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +;; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +;; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;; +;; -------------------------------------------------------------------------- + ; ; Smart alignment macros ; @@ -8,31 +41,13 @@ USE: smartalign %define __ALIGN_JMP_THRESHOLD__ 16 %define __ALIGN_16BIT_1B__ 0x90 - %define __ALIGN_16BIT_2B__ 0x90,0x90 - %define __ALIGN_16BIT_3B__ 0x90,0x90,0x90 - %define __ALIGN_16BIT_4B__ 0x90,0x90,0x90,0x90 - %define __ALIGN_16BIT_5B__ 0x90,0x90,0x90,0x90,0x90 - %define __ALIGN_16BIT_6B__ 0x90,0x90,0x90,0x90,0x90,0x90 - %define __ALIGN_16BIT_7B__ 0x90,0x90,0x90,0x90,0x90,0x90,0x90 - %define __ALIGN_16BIT_8B__ 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90 + %define __ALIGN_16BIT_GROUP__ 1 %define __ALIGN_32BIT_1B__ 0x90 - %define __ALIGN_32BIT_2B__ 0x90,0x90 - %define __ALIGN_32BIT_3B__ 0x90,0x90,0x90 - %define __ALIGN_32BIT_4B__ 0x90,0x90,0x90,0x90 - %define __ALIGN_32BIT_5B__ 0x90,0x90,0x90,0x90,0x90 - %define __ALIGN_32BIT_6B__ 0x90,0x90,0x90,0x90,0x90,0x90 - %define __ALIGN_32BIT_7B__ 0x90,0x90,0x90,0x90,0x90,0x90,0x90 - %define __ALIGN_32BIT_8B__ 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90 + %define __ALIGN_32BIT_GROUP__ 1 %define __ALIGN_64BIT_1B__ 0x90 - %define __ALIGN_64BIT_2B__ 0x90,0x90 - %define __ALIGN_64BIT_3B__ 0x90,0x90,0x90 - %define __ALIGN_64BIT_4B__ 0x90,0x90,0x90,0x90 - %define __ALIGN_64BIT_5B__ 0x90,0x90,0x90,0x90,0x90 - %define __ALIGN_64BIT_6B__ 0x90,0x90,0x90,0x90,0x90,0x90 - %define __ALIGN_64BIT_7B__ 0x90,0x90,0x90,0x90,0x90,0x90,0x90 - %define __ALIGN_64BIT_8B__ 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90 + %define __ALIGN_64BIT_GROUP__ 1 %elifidni %1,generic %define __ALIGN_JMP_THRESHOLD__ 8 @@ -40,10 +55,11 @@ USE: smartalign %define __ALIGN_16BIT_2B__ 0x89,0xf6 %define __ALIGN_16BIT_3B__ 0x8d,0x74,0x00 %define __ALIGN_16BIT_4B__ 0x8d,0xb4,0x00,0x00 - %define __ALIGN_16BIT_5B__ 0x90,0x8d,0xb4,0x00,0x00 - %define __ALIGN_16BIT_6B__ 0x89,0xf6,0x8d,0xbd,0x00,0x00 - %define __ALIGN_16BIT_7B__ 0x8d,0x74,0x00,0x8d,0xbd,0x00,0x00 + %define __ALIGN_16BIT_5B__ 0x8d,0xb4,0x00,0x00,0x90 + %define __ALIGN_16BIT_6B__ 0x8d,0xb4,0x00,0x00,0x89,0xff + %define __ALIGN_16BIT_7B__ 0x8d,0xb4,0x00,0x00,0x8d,0x7d,0x00 %define __ALIGN_16BIT_8B__ 0x8d,0xb4,0x00,0x00,0x8d,0xbd,0x00,0x00 + %define __ALIGN_16BIT_GROUP__ 8 %define __ALIGN_32BIT_1B__ 0x90 %define __ALIGN_32BIT_2B__ 0x89,0xf6 @@ -52,16 +68,13 @@ USE: smartalign %define __ALIGN_32BIT_5B__ 0x90,0x8d,0x74,0x26,0x00 %define __ALIGN_32BIT_6B__ 0x8d,0xb6,0x00,0x00,0x00,0x00 %define __ALIGN_32BIT_7B__ 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00 - %undef __ALIGN_32BIT_8B__ + %define __ALIGN_32BIT_GROUP__ 7 %define __ALIGN_64BIT_1B__ 0x90 %define __ALIGN_64BIT_2B__ 0x66,0x90 %define __ALIGN_64BIT_3B__ 0x66,0x66,0x90 %define __ALIGN_64BIT_4B__ 0x66,0x66,0x66,0x90 - %define __ALIGN_64BIT_5B__ 0x66,0x66,0x90,0x66,0x90 - %define __ALIGN_64BIT_6B__ 0x66,0x66,0x90,0x66,0x66,0x90 - %define __ALIGN_64BIT_7B__ 0x66,0x66,0x66,0x90,0x66,0x66,0x90 - %define __ALIGN_64BIT_8B__ 0x66,0x66,0x66,0x90,0x66,0x66,0x66,0x90 + %define __ALIGN_64BIT_GROUP__ 4 %elifidni %1,k8 %define __ALIGN_JMP_THRESHOLD__ 16 @@ -69,28 +82,19 @@ USE: smartalign %define __ALIGN_16BIT_2B__ 0x66,0x90 %define __ALIGN_16BIT_3B__ 0x66,0x66,0x90 %define __ALIGN_16BIT_4B__ 0x66,0x66,0x66,0x90 - %define __ALIGN_16BIT_5B__ 0x66,0x66,0x90,0x66,0x90 - %define __ALIGN_16BIT_6B__ 0x66,0x66,0x90,0x66,0x66,0x90 - %define __ALIGN_16BIT_7B__ 0x66,0x66,0x66,0x90,0x66,0x66,0x90 - %define __ALIGN_16BIT_8B__ 0x66,0x66,0x66,0x90,0x66,0x66,0x66,0x90 + %define __ALIGN_16BIT_GROUP__ 4 %define __ALIGN_32BIT_1B__ 0x90 %define __ALIGN_32BIT_2B__ 0x66,0x90 %define __ALIGN_32BIT_3B__ 0x66,0x66,0x90 %define __ALIGN_32BIT_4B__ 0x66,0x66,0x66,0x90 - %define __ALIGN_32BIT_5B__ 0x66,0x66,0x90,0x66,0x90 - %define __ALIGN_32BIT_6B__ 0x66,0x66,0x90,0x66,0x66,0x90 - %define __ALIGN_32BIT_7B__ 0x66,0x66,0x66,0x90,0x66,0x66,0x90 - %define __ALIGN_32BIT_8B__ 0x66,0x66,0x66,0x90,0x66,0x66,0x66,0x90 + %define __ALIGN_32BIT_GROUP__ 4 %define __ALIGN_64BIT_1B__ 0x90 %define __ALIGN_64BIT_2B__ 0x66,0x90 %define __ALIGN_64BIT_3B__ 0x66,0x66,0x90 %define __ALIGN_64BIT_4B__ 0x66,0x66,0x66,0x90 - %define __ALIGN_64BIT_5B__ 0x66,0x66,0x90,0x66,0x90 - %define __ALIGN_64BIT_6B__ 0x66,0x66,0x90,0x66,0x66,0x90 - %define __ALIGN_64BIT_7B__ 0x66,0x66,0x66,0x90,0x66,0x66,0x90 - %define __ALIGN_64BIT_8B__ 0x66,0x66,0x66,0x90,0x66,0x66,0x66,0x90 + %define __ALIGN_64BIT_GROUP__ 4 %elifidni %1,k7 %define __ALIGN_JMP_THRESHOLD__ 16 @@ -98,10 +102,7 @@ USE: smartalign %define __ALIGN_16BIT_2B__ 0x66,0x90 %define __ALIGN_16BIT_3B__ 0x66,0x66,0x90 %define __ALIGN_16BIT_4B__ 0x66,0x66,0x66,0x90 - %define __ALIGN_16BIT_5B__ 0x66,0x66,0x90,0x66,0x90 - %define __ALIGN_16BIT_6B__ 0x66,0x66,0x90,0x66,0x66,0x90 - %define __ALIGN_16BIT_7B__ 0x66,0x66,0x66,0x90,0x66,0x66,0x90 - %define __ALIGN_16BIT_8B__ 0x66,0x66,0x66,0x90,0x66,0x66,0x66,0x90 + %define __ALIGN_64BIT_GROUP__ 4 %define __ALIGN_32BIT_1B__ 0x90 %define __ALIGN_32BIT_2B__ 0x8b,0xc0 @@ -110,16 +111,13 @@ USE: smartalign %define __ALIGN_32BIT_5B__ 0x8d,0x44,0x20,0x00,0x90 %define __ALIGN_32BIT_6B__ 0x8d,0x80,0x00,0x00,0x00,0x00 %define __ALIGN_32BIT_7B__ 0x8d,0x04,0x05,0x00,0x00,0x00,0x00 - %undef __ALIGN_32BIT_8B__ + %define __ALIGN_32BIT_GROUP__ 7 %define __ALIGN_64BIT_1B__ 0x90 %define __ALIGN_64BIT_2B__ 0x66,0x90 %define __ALIGN_64BIT_3B__ 0x66,0x66,0x90 %define __ALIGN_64BIT_4B__ 0x66,0x66,0x66,0x90 - %define __ALIGN_64BIT_5B__ 0x66,0x66,0x90,0x66,0x90 - %define __ALIGN_64BIT_6B__ 0x66,0x66,0x90,0x66,0x66,0x90 - %define __ALIGN_64BIT_7B__ 0x66,0x66,0x66,0x90,0x66,0x66,0x90 - %define __ALIGN_64BIT_8B__ 0x66,0x66,0x66,0x90,0x66,0x66,0x66,0x90 + %define __ALIGN_64BIT_GROUP__ 4 %elifidni %1,p6 %define __ALIGN_JMP_THRESHOLD__ 16 @@ -127,10 +125,7 @@ USE: smartalign %define __ALIGN_16BIT_2B__ 0x66,0x90 %define __ALIGN_16BIT_3B__ 0x0f,0x1f,0x00 %define __ALIGN_16BIT_4B__ 0x0f,0x1f,0x40,0x00 - %define __ALIGN_16BIT_5B__ 0x90,0x0f,0x1f,0x40,0x00 - %define __ALIGN_16BIT_6B__ 0x0f,0x1f,0x00,0x0f,0x1f,0x00 - %define __ALIGN_16BIT_7B__ 0x0f,0x1f,0x00,0x0f,0x1f,0x40,0x00 - %define __ALIGN_16BIT_8B__ 0x0f,0x1f,0x40,0x00,0x0f,0x1f,0x40,0x00 + %define __ALIGN_16BIT_GROUP__ 4 %define __ALIGN_32BIT_1B__ 0x90 %define __ALIGN_32BIT_2B__ 0x66,0x90 @@ -140,6 +135,7 @@ USE: smartalign %define __ALIGN_32BIT_6B__ 0x66,0x0f,0x1f,0x44,0x00,0x00 %define __ALIGN_32BIT_7B__ 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00 %define __ALIGN_32BIT_8B__ 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00 + %define __ALIGN_32BIT_GROUP__ 8 %define __ALIGN_64BIT_1B__ 0x90 %define __ALIGN_64BIT_2B__ 0x66,0x90 @@ -149,6 +145,7 @@ USE: smartalign %define __ALIGN_64BIT_6B__ 0x66,0x0f,0x1f,0x44,0x00,0x00 %define __ALIGN_64BIT_7B__ 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00 %define __ALIGN_64BIT_8B__ 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00 + %define __ALIGN_64BIT_GROUP__ 8 %else %error unknown alignment mode: %1 %endif @@ -161,99 +158,21 @@ USE: smartalign %unimacro align 1-2+.nolist %imacro align 1-2+.nolist %ifnempty %2 - times ($$-$) % (%1) %2 + times (((%1) - (($-$$) % (%1))) % (%1)) %2 %else %push - %assign %$pad ($$-$) % %1 + %assign %$pad (((%1) - (($-$$) % (%1))) % (%1)) %if %$pad > __ALIGN_JMP_THRESHOLD__ jmp %$end ; We can't re-use %$pad here as $ will have changed! - times ($$-$) % %1 db 90h + times (((%1) - (($-$$) % (%1))) % (%1)) nop %$end: %else - %if __BITS__ == 16 - %ifdef __ALIGN_16BIT_8B__ - %rep %$pad / 8 - db __ALIGN_16BIT_8B__ - %endrep - %assign %$pad %$pad % 8 - %else - %rep %$pad / 7 - db __ALIGN_16BIT_7B__ - %endrep - %assign %$pad %$pad % 7 - %endif - %if %$pad == 1 - db __ALIGN_16BIT_1B__ - %elif %$pad == 2 - db __ALIGN_16BIT_2B__ - %elif %$pad == 3 - db __ALIGN_16BIT_3B__ - %elif %$pad == 4 - db __ALIGN_16BIT_4B__ - %elif %$pad == 5 - db __ALIGN_16BIT_5B__ - %elif %$pad == 6 - db __ALIGN_16BIT_6B__ - %elif %$pad == 7 - db __ALIGN_16BIT_7B__ - %endif - %elif __BITS__ == 32 - %ifdef __ALIGN_32BIT_8B__ - %rep %$pad / 8 - db __ALIGN_32BIT_8B__ - %endrep - %assign %$pad %$pad % 8 - %else - %rep %$pad / 7 - db __ALIGN_32BIT_7B__ - %endrep - %assign %$pad %$pad % 7 - %endif - %if %$pad == 1 - db __ALIGN_32BIT_1B__ - %elif %$pad == 2 - db __ALIGN_32BIT_2B__ - %elif %$pad == 3 - db __ALIGN_32BIT_3B__ - %elif %$pad == 4 - db __ALIGN_32BIT_4B__ - %elif %$pad == 5 - db __ALIGN_32BIT_5B__ - %elif %$pad == 6 - db __ALIGN_32BIT_6B__ - %elif %$pad == 7 - db __ALIGN_32BIT_7B__ - %endif - %elif __BITS__ == 64 - %ifdef __ALIGN_64BIT_8B__ - %rep %$pad / 8 - db __ALIGN_64BIT_8B__ - %endrep - %assign %$pad %$pad % 8 - %else - %rep %$pad / 7 - db __ALIGN_64BIT_7B__ - %endrep - %assign %$pad %$pad % 7 - %endif - %if %$pad == 1 - db __ALIGN_64BIT_1B__ - %elif %$pad == 2 - db __ALIGN_64BIT_2B__ - %elif %$pad == 3 - db __ALIGN_64BIT_3B__ - %elif %$pad == 4 - db __ALIGN_64BIT_4B__ - %elif %$pad == 5 - db __ALIGN_64BIT_5B__ - %elif %$pad == 6 - db __ALIGN_64BIT_6B__ - %elif %$pad == 7 - db __ALIGN_64BIT_7B__ - %endif - %else - %error "Invalid __BITS__ value" + times (%$pad / __ALIGN_%[__BITS__]BIT_GROUP__) \ + db __ALIGN_%[__BITS__]BIT_%[__ALIGN_%[__BITS__]BIT_GROUP__]B__ + %assign %$pad %$pad % __ALIGN_%[__BITS__]BIT_GROUP__ + %if %$pad > 0 + db __ALIGN_%[__BITS__]BIT_%[%$pad]B__ %endif %endif %pop diff --git a/misc/Nindent b/misc/Nindent index 7a388b46..0d75ccca 100755 --- a/misc/Nindent +++ b/misc/Nindent @@ -1,2 +1,18 @@ -#!/bin/sh - -exec indent -kr -i4 -ts8 -nut -sob -ss -ncs "$@" +#!/bin/sh +PARAM="-npro -kr -i4 -ts8 -nut -sob -l80 -ss -ncs -cp1" +RES=`indent --version` +V1=`echo $RES | cut -d' ' -f3 | cut -d'.' -f1` +V2=`echo $RES | cut -d' ' -f3 | cut -d'.' -f2` +V3=`echo $RES | cut -d' ' -f3 | cut -d'.' -f3` +if [ $V1 -gt 2 ]; then + PARAM="$PARAM -il0" +elif [ $V1 -eq 2 ]; then + if [ $V2 -gt 2 ]; then + PARAM="$PARAM -il0"; + elif [ $V2 -eq 2 ]; then + if [ $V3 -ge 10 ]; then + PARAM="$PARAM -il0" + fi + fi +fi +exec indent $PARAM "$@" @@ -1,4 +1,39 @@ #!/usr/bin/perl +## -------------------------------------------------------------------------- +## +## Copyright 1996-2009 The NASM Authors - All Rights Reserved +## See the file AUTHORS included with the NASM distribution for +## the specific copyright holders. +## +## Copyright 1996-2009 the NASM Authors - All rights reserved. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following +## conditions are met: +## +## * Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above +## copyright notice, this list of conditions and the following +## disclaimer in the documentation and/or other materials provided +## with the distribution. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## -------------------------------------------------------------------------- + # # Script to create Makefile-style dependencies. # @@ -1,9 +1,38 @@ -/* The Netwide Assembler main program module +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * The Netwide Assembler main program module */ #include "compiler.h" @@ -29,7 +58,7 @@ #include "eval.h" #include "assemble.h" #include "labels.h" -#include "outform.h" +#include "output/outform.h" #include "listing.h" struct forwrefinfo { /* info held on forward refs. */ @@ -73,7 +102,9 @@ int optimizing = -1; /* number of optimization passes to take */ static int sb, cmd_sb = 16; /* by default */ static uint32_t cmd_cpu = IF_PLEVEL; /* highest level by default */ static uint32_t cpu = IF_PLEVEL; /* passed to insn_size & assemble.c */ -bool global_offset_changed; /* referenced in labels.c */ +int64_t global_offset_changed; /* referenced in labels.c */ +int64_t prev_offset_changed; +int32_t stall_count; static struct location location; int in_abs_seg; /* Flag we are in ABSOLUTE seg */ @@ -102,37 +133,27 @@ static const char *depend_file = NULL; * Which of the suppressible warnings are suppressed. Entry zero * isn't an actual warning, but it used for -w+error/-Werror. */ -static bool suppressed[ERR_WARN_MAX+1]; - -static bool suppressed_global[ERR_WARN_MAX+1] = { - true, false, true, false, false, false, true, false, true, true, false -}; -/* - * The option names for the suppressible warnings. As before, entry - * zero does nothing. - */ -static const char *suppressed_names[ERR_WARN_MAX+1] = { - "error", "macro-params", "macro-selfref", "macro-defaults", - "orphan-labels", "number-overflow", "gnu-elf-extensions", - "float-overflow", "float-denorm", "float-underflow", "float-toolong" -}; -/* - * The explanations for the suppressible warnings. As before, entry - * zero does nothing. - */ -static const char *suppressed_what[ERR_WARN_MAX+1] = { - "treat warnings as errors", - "macro calls with wrong parameter count", - "cyclic macro references", - "macros with more default than optional parameters", - "labels alone on lines without trailing `:'", - "numeric constants does not fit in 64 bits", - "using 8- or 16-bit relocation in ELF32, a GNU extension", - "floating point overflow", - "floating point denormal", - "floating point underflow", - "too many digits in floating-point number" +static bool warning_on[ERR_WARN_MAX+1]; /* Current state */ +static bool warning_on_global[ERR_WARN_MAX+1]; /* Command-line state */ + +static const struct warning { + const char *name; + const char *help; + bool enabled; +} warnings[ERR_WARN_MAX+1] = { + {"error", "treat warnings as errors", false}, + {"macro-params", "macro calls with wrong parameter count", true}, + {"macro-selfref", "cyclic macro references", false}, + {"macro-defaults", "macros with more default than optional parameters", true}, + {"orphan-labels", "labels alone on lines without trailing `:'", true}, + {"number-overflow", "numeric constant does not fit", true}, + {"gnu-elf-extensions", "using 8- or 16-bit relocation in ELF32, a GNU extension", false}, + {"float-overflow", "floating point overflow", true}, + {"float-denorm", "floating point denormal", false}, + {"float-underflow", "floating point underflow", false}, + {"float-toolong", "too many digits in floating-point number", true}, + {"user", "%warning directives", true}, }; /* @@ -158,8 +179,8 @@ static Preproc no_pp = { #define SET_CURR_OFFS(x) (in_abs_seg?(void)(abs_offset=(x)):\ (void)(offsets=raa_write(offsets,location.segment,(x)))) -static int want_usage; -static int terminate_after_phase; +static bool want_usage; +static bool terminate_after_phase; int user_nolist = 0; /* fbk 9/2/00 */ static void nasm_fputs(const char *line, FILE * outfile) @@ -294,7 +315,7 @@ int main(int argc, char **argv) time(&official_compile_time); - pass0 = 1; + pass0 = 0; want_usage = terminate_after_phase = false; report_error = report_error_gnu; @@ -380,7 +401,7 @@ int main(int argc, char **argv) location.known = false; /* pass = 1; */ - preproc->reset(inname, 2, report_error, evaluate, &nasmlist, + preproc->reset(inname, 3, report_error, evaluate, &nasmlist, depend_ptr); while ((line = preproc->getline())) { @@ -423,7 +444,7 @@ int main(int argc, char **argv) */ ofmt->filename(inname, outname, report_error); - ofile = fopen(outname, "wb"); + ofile = fopen(outname, (ofmt->flags & OFMT_TEXT) ? "w" : "wb"); if (!ofile) { report_error(ERR_FATAL | ERR_NOFILE, "unable to open output file `%s'", outname); @@ -437,6 +458,7 @@ int main(int argc, char **argv) init_labels(); ofmt->init(ofile, report_error, define_label, evaluate); + ofmt->current_dfmt->init(ofmt, NULL, ofile, report_error); assemble_file(inname, depend_ptr); @@ -452,14 +474,12 @@ int main(int argc, char **argv) fclose (ofile); remove(outname); - if (listname[0]) - remove(listname); } } break; } - if (depend_list) + if (depend_list && !terminate_after_phase) emit_dependencies(depend_list); if (want_usage) @@ -470,10 +490,7 @@ int main(int argc, char **argv) eval_cleanup(); stdscan_cleanup(); - if (terminate_after_phase) - return 1; - else - return 0; + return terminate_after_phase; } /* @@ -613,7 +630,7 @@ static bool process_arg(char *p, char *q) char *param; int i; bool advance = false; - bool suppress; + bool do_warn; if (!p || !p[0]) return false; @@ -640,8 +657,6 @@ static bool process_arg(char *p, char *q) report_error(ERR_FATAL | ERR_NOFILE | ERR_USAGE, "unrecognised output format `%s' - " "use -hf for a list", param); - } else { - ofmt->current_dfmt = ofmt->debug_formats[0]; } break; @@ -771,8 +786,8 @@ static bool process_arg(char *p, char *q) "Warnings:\n"); for (i = 0; i <= ERR_WARN_MAX; i++) printf(" %-23s %s (default %s)\n", - suppressed_names[i], suppressed_what[i], - suppressed_global[i] ? "off" : "on"); + warnings[i].name, warnings[i].help, + warnings[i].enabled ? "on" : "off"); printf ("\nresponse files should contain command line parameters" ", one per line.\n"); @@ -799,16 +814,9 @@ static bool process_arg(char *p, char *q) break; case 'v': - { - const char *nasm_version_string = - "NASM version " NASM_VER " compiled on " __DATE__ -#ifdef DEBUG - " with -DDEBUG" -#endif - ; - puts(nasm_version_string); - exit(0); /* never need usage message here */ - } + printf("NASM version %s compiled on %s%s\n", + nasm_version, nasm_date, nasm_compile_options); + exit(0); /* never need usage message here */ break; case 'e': /* preprocess only */ @@ -822,10 +830,10 @@ static bool process_arg(char *p, char *q) case 'W': if (param[0] == 'n' && param[1] == 'o' && param[2] == '-') { - suppress = true; + do_warn = false; param += 3; } else { - suppress = false; + do_warn = true; } goto set_warning; @@ -835,21 +843,21 @@ static bool process_arg(char *p, char *q) "invalid option to `-w'"); break; } - suppress = (param[0] == '-'); + do_warn = (param[0] == '+'); param++; goto set_warning; set_warning: for (i = 0; i <= ERR_WARN_MAX; i++) - if (!nasm_stricmp(param, suppressed_names[i])) + if (!nasm_stricmp(param, warnings[i].name)) break; if (i <= ERR_WARN_MAX) - suppressed_global[i] = suppress; + warning_on_global[i] = do_warn; else if (!nasm_stricmp(param, "all")) for (i = 1; i <= ERR_WARN_MAX; i++) - suppressed_global[i] = suppress; + warning_on_global[i] = do_warn; else if (!nasm_stricmp(param, "none")) for (i = 1; i <= ERR_WARN_MAX; i++) - suppressed_global[i] = !suppress; + warning_on_global[i] = !do_warn; else report_error(ERR_NONFATAL | ERR_NOFILE | ERR_USAGE, "invalid warning `%s'", param); @@ -1068,8 +1076,11 @@ static void parse_cmdline(int argc, char **argv) { FILE *rfile; char *envreal, *envcopy = NULL, *p, *arg; + int i; *inname = *outname = *listname = *errname = '\0'; + for (i = 0; i <= ERR_WARN_MAX; i++) + warning_on_global[i] = warnings[i].enabled; /* * First, process the NASMENV environment variable. @@ -1166,8 +1177,7 @@ static void assemble_file(char *fname, StrList **depend_ptr) report_error(ERR_FATAL, "command line: " "32-bit segment size requires a higher cpu"); - pass_max = (optimizing > 0 ? optimizing : 0) + 2; /* passes 1, optimizing, then 2 */ - pass0 = !(optimizing > 0); /* start at 1 if not optimizing */ + pass_max = prev_offset_changed = (INT_MAX >> 1) + 2; /* Almost unlimited */ for (passn = 1; pass0 <= 2; passn++) { int pass1, pass2; ldfunc def_label; @@ -1185,7 +1195,7 @@ static void assemble_file(char *fname, StrList **depend_ptr) nasmlist.init(listname, report_error); } in_abs_seg = false; - global_offset_changed = false; /* set by redefine_label */ + global_offset_changed = 0; /* set by redefine_label */ location.segment = ofmt->section(NULL, pass2, &sb); globalbits = sb; if (passn > 1) { @@ -1196,7 +1206,7 @@ static void assemble_file(char *fname, StrList **depend_ptr) } preproc->reset(fname, pass1, report_error, evaluate, &nasmlist, pass1 == 2 ? depend_ptr : NULL); - memcpy(suppressed, suppressed_global, (ERR_WARN_MAX+1) * sizeof(bool)); + memcpy(warning_on, warning_on_global, (ERR_WARN_MAX+1) * sizeof(bool)); globallineno = 0; if (passn == 1) @@ -1207,8 +1217,10 @@ static void assemble_file(char *fname, StrList **depend_ptr) enum directives d; globallineno++; - /* here we parse our directives; this is not handled by the 'real' - * parser. */ + /* + * Here we parse our directives; this is not handled by the + * 'real' parser. This really should be a separate function. + */ directive = line; d = getkw(&directive, &value); if (d) { @@ -1307,61 +1319,59 @@ static void assemble_file(char *fname, StrList **depend_ptr) } /* pass == 1 */ break; case D_COMMON: /* [COMMON symbol size:special] */ + { + int64_t size; + if (*value == '$') value++; /* skip initial $ if present */ - if (pass0 == 1) { - p = value; - validid = true; - if (!isidstart(*p)) - validid = false; - while (*p && !nasm_isspace(*p)) { - if (!isidchar(*p)) - validid = false; - p++; - } - if (!validid) { - report_error(ERR_NONFATAL, - "identifier expected after COMMON"); - break; - } - if (*p) { - int64_t size; - - while (*p && nasm_isspace(*p)) - *p++ = '\0'; - q = p; - while (*q && *q != ':') - q++; - if (*q == ':') { - *q++ = '\0'; - special = q; - } else - special = NULL; - size = readnum(p, &rn_error); - if (rn_error) - report_error(ERR_NONFATAL, - "invalid size specified" - " in COMMON declaration"); - else - define_common(value, seg_alloc(), size, - special, ofmt, report_error); - } else - report_error(ERR_NONFATAL, - "no size specified in" - " COMMON declaration"); - } else if (pass0 == 2) { /* pass == 2 */ - q = value; - while (*q && *q != ':') { - if (nasm_isspace(*q)) - *q = '\0'; - q++; - } - if (*q == ':') { - *q++ = '\0'; - ofmt->symdef(value, 0L, 0L, 3, q); - } + p = value; + validid = true; + if (!isidstart(*p)) + validid = false; + while (*p && !nasm_isspace(*p)) { + if (!isidchar(*p)) + validid = false; + p++; + } + if (!validid) { + report_error(ERR_NONFATAL, + "identifier expected after COMMON"); + break; + } + if (*p) { + while (*p && nasm_isspace(*p)) + *p++ = '\0'; + q = p; + while (*q && *q != ':') + q++; + if (*q == ':') { + *q++ = '\0'; + special = q; + } else { + special = NULL; + } + size = readnum(p, &rn_error); + if (rn_error) { + report_error(ERR_NONFATAL, + "invalid size specified" + " in COMMON declaration"); + break; + } + } else { + report_error(ERR_NONFATAL, + "no size specified in" + " COMMON declaration"); + break; + } + + if (pass0 < 2) { + define_common(value, seg_alloc(), size, + special, ofmt, report_error); + } else if (pass0 == 2) { + ofmt->symdef(value, 0L, 0L, 3, special); } break; + } case D_ABSOLUTE: /* [ABSOLUTE address] */ stdscan_reset(); stdscan_bufptr = value; @@ -1409,36 +1419,35 @@ static void assemble_file(char *fname, StrList **depend_ptr) ofmt->current_dfmt->debug_directive(debugid, p); break; case D_WARNING: /* [WARNING {+|-|*}warn-name] */ - if (pass1 == 1) { - while (*value && nasm_isspace(*value)) - value++; - - switch(*value) { - case '-': validid = 0; value++; break; - case '+': validid = 1; value++; break; - case '*': validid = 2; value++; break; - default: /* - * Should this error out? - * I'll keep it so nothing breaks. - */ - validid = 1; break; - } + while (*value && nasm_isspace(*value)) + value++; + + switch(*value) { + case '-': validid = 0; value++; break; + case '+': validid = 1; value++; break; + case '*': validid = 2; value++; break; + default: validid = 1; break; + } - for (i = 1; i <= ERR_WARN_MAX; i++) - if (!nasm_stricmp(value, suppressed_names[i])) - break; - if (i <= ERR_WARN_MAX) { - switch(validid) { - case 0: suppressed[i] = true; break; - case 1: suppressed[i] = false; break; - case 2: suppressed[i] = suppressed_global[i]; - break; - } - } - else - report_error(ERR_NONFATAL, - "invalid warning id in WARNING directive"); - } + for (i = 1; i <= ERR_WARN_MAX; i++) + if (!nasm_stricmp(value, warnings[i].name)) + break; + if (i <= ERR_WARN_MAX) { + switch(validid) { + case 0: + warning_on[i] = false; + break; + case 1: + warning_on[i] = true; + break; + case 2: + warning_on[i] = warning_on_global[i]; + break; + } + } + else + report_error(ERR_NONFATAL, + "invalid warning id in WARNING directive"); break; case D_CPU: /* [CPU] */ cpu = get_cpu(value); @@ -1500,7 +1509,7 @@ static void assemble_file(char *fname, StrList **depend_ptr) parse_line(pass1, line, &output_ins, report_error, evaluate, def_label); - if (!(optimizing > 0) && pass0 == 2) { + if (optimizing > 0) { if (forwref != NULL && globallineno == forwref->lineno) { output_ins.forw_ref = true; do { @@ -1511,50 +1520,21 @@ static void assemble_file(char *fname, StrList **depend_ptr) && forwref->lineno == globallineno); } else output_ins.forw_ref = false; - } - - if (!(optimizing > 0) && output_ins.forw_ref) { - if (passn == 1) { - for (i = 0; i < output_ins.operands; i++) { - if (output_ins.oprs[i]. - opflags & OPFLAG_FORWARD) { - struct forwrefinfo *fwinf = - (struct forwrefinfo *) - saa_wstruct(forwrefs); - fwinf->lineno = globallineno; + + if (output_ins.forw_ref) { + if (passn == 1) { + for (i = 0; i < output_ins.operands; i++) { + if (output_ins.oprs[i]. + opflags & OPFLAG_FORWARD) { + struct forwrefinfo *fwinf = + (struct forwrefinfo *) + saa_wstruct(forwrefs); + fwinf->lineno = globallineno; fwinf->operand = i; - } - } - } else { /* passn > 1 */ - /* - * Hack to prevent phase error in the code - * rol ax,x - * x equ 1 - * - * If the second operand is a forward reference, - * the UNITY property of the number 1 in that - * operand is cancelled. Otherwise the above - * sequence will cause a phase error. - * - * This hack means that the above code will - * generate 286+ code. - * - * The forward reference will mean that the - * operand will not have the UNITY property on - * the first pass, so the pass behaviours will - * be consistent. - */ - - if (output_ins.operands >= 2 && - (output_ins.oprs[1].opflags & OPFLAG_FORWARD) && - !(IMMEDIATE & ~output_ins.oprs[1].type)) - { - /* Remove special properties bits */ - output_ins.oprs[1].type &= ~REG_SMASK; - } - + } + } + } } - } /* forw_ref */ @@ -1575,32 +1555,25 @@ static void assemble_file(char *fname, StrList **depend_ptr) if (output_ins.operands == 1 && (output_ins.oprs[0].type & IMMEDIATE) && output_ins.oprs[0].wrt == NO_SEG) { - int isext = - output_ins.oprs[0]. - opflags & OPFLAG_EXTERN; + bool isext = !!(output_ins.oprs[0].opflags + & OPFLAG_EXTERN); def_label(output_ins.label, output_ins.oprs[0].segment, output_ins.oprs[0].offset, NULL, false, isext, ofmt, report_error); } else if (output_ins.operands == 2 - && (output_ins.oprs[0]. - type & IMMEDIATE) + && (output_ins.oprs[0].type & IMMEDIATE) && (output_ins.oprs[0].type & COLON) - && output_ins.oprs[0].segment == - NO_SEG + && output_ins.oprs[0].segment == NO_SEG && output_ins.oprs[0].wrt == NO_SEG - && (output_ins.oprs[1]. - type & IMMEDIATE) - && output_ins.oprs[1].segment == - NO_SEG - && output_ins.oprs[1].wrt == - NO_SEG) { + && (output_ins.oprs[1].type & IMMEDIATE) + && output_ins.oprs[1].segment == NO_SEG + && output_ins.oprs[1].wrt == NO_SEG) { def_label(output_ins.label, - output_ins.oprs[0]. - offset | SEG_ABS, - output_ins.oprs[1].offset, NULL, - false, false, ofmt, + output_ins.oprs[0].offset | SEG_ABS, + output_ins.oprs[1].offset, + NULL, false, false, ofmt, report_error); } else report_error(ERR_NONFATAL, @@ -1746,33 +1719,46 @@ static void assemble_file(char *fname, StrList **depend_ptr) location.offset = offs = GET_CURR_OFFS; } /* end while (line = preproc->getline... */ - if (pass1 == 2 && global_offset_changed) + if (pass0 == 2 && global_offset_changed && !terminate_after_phase) report_error(ERR_NONFATAL, - "phase error detected at end of assembly."); + "phase error detected at end of assembly."); if (pass1 == 1) preproc->cleanup(1); - if (pass1 == 1 && terminate_after_phase) { - fclose(ofile); - remove(outname); - if (want_usage) - usage(); - exit(1); - } - if (passn >= pass_max - 2 || - (passn > 1 && !global_offset_changed)) + if ((passn > 1 && !global_offset_changed) || pass0 == 2) { pass0++; + } else if (global_offset_changed && + global_offset_changed < prev_offset_changed) { + prev_offset_changed = global_offset_changed; + stall_count = 0; + } else { + stall_count++; + } + + if (terminate_after_phase) + break; + + if ((stall_count > 997) || (passn >= pass_max)) { + /* We get here if the labels don't converge + * Example: FOO equ FOO + 1 + */ + report_error(ERR_NONFATAL, + "Can't find valid values for all labels " + "after %d passes, giving up.", passn); + report_error(ERR_NONFATAL, + "Possible causes: recursive EQUs, macro abuse."); + break; + } } preproc->cleanup(0); nasmlist.cleanup(); -#if 1 - if (optimizing > 0 && opt_verbose_info) /* -On and -Ov switches */ - fprintf(stdout, - "info:: assembly required 1+%d+1 passes\n", passn-3); -#endif -} /* exit from assemble_file (...) */ + if (!terminate_after_phase && opt_verbose_info) { + /* -On and -Ov switches */ + fprintf(stdout, "info: assembly required 1+%d+1 passes\n", passn-3); + } +} static enum directives getkw(char **directive, char **value) { @@ -1840,19 +1826,22 @@ static enum directives getkw(char **directive, char **value) static void report_error_gnu(int severity, const char *fmt, ...) { va_list ap; + char *currentfile = NULL; + int32_t lineno = 0; if (is_suppressed_warning(severity)) return; - if (severity & ERR_NOFILE) - fputs("nasm: ", error_file); - else { - char *currentfile = NULL; - int32_t lineno = 0; + if (!(severity & ERR_NOFILE)) src_get(&lineno, ¤tfile); - fprintf(error_file, "%s:%"PRId32": ", currentfile, lineno); - nasm_free(currentfile); + + if (currentfile) { + fprintf(error_file, "%s:%"PRId32": ", currentfile, lineno); + nasm_free(currentfile); + } else { + fputs("nasm: ", error_file); } + va_start(ap, fmt); report_error_common(severity, fmt, ap); va_end(ap); @@ -1876,19 +1865,22 @@ static void report_error_gnu(int severity, const char *fmt, ...) static void report_error_vc(int severity, const char *fmt, ...) { va_list ap; + char *currentfile = NULL; + int32_t lineno = 0; if (is_suppressed_warning(severity)) return; - if (severity & ERR_NOFILE) - fputs("nasm: ", error_file); - else { - char *currentfile = NULL; - int32_t lineno = 0; + if (!(severity & ERR_NOFILE)) src_get(&lineno, ¤tfile); + + if (currentfile) { fprintf(error_file, "%s(%"PRId32") : ", currentfile, lineno); nasm_free(currentfile); + } else { + fputs("nasm: ", error_file); } + va_start(ap, fmt); report_error_common(severity, fmt, ap); va_end(ap); @@ -1909,9 +1901,10 @@ static bool is_suppressed_warning(int severity) */ return (severity & ERR_MASK) == ERR_WARNING && (((severity & ERR_WARN_MASK) != 0 && - suppressed[(severity & ERR_WARN_MASK) >> ERR_WARN_SHR]) || + !warning_on[(severity & ERR_WARN_MASK) >> ERR_WARN_SHR]) || /* See if it's a pass-one only warning and we're not in pass one. */ - ((severity & ERR_PASS1) && pass0 != 1)); + ((severity & ERR_PASS1) && pass0 != 1) || + ((severity & ERR_PASS2) && pass0 != 2)); } /** @@ -1927,28 +1920,36 @@ static bool is_suppressed_warning(int severity) static void report_error_common(int severity, const char *fmt, va_list args) { + char msg[1024]; + const char *pfx; + switch (severity & (ERR_MASK|ERR_NO_SEVERITY)) { case ERR_WARNING: - fputs("warning: ", error_file); + pfx = "warning: "; break; case ERR_NONFATAL: - fputs("error: ", error_file); + pfx = "error: "; break; case ERR_FATAL: - fputs("fatal: ", error_file); + pfx = "fatal: "; break; case ERR_PANIC: - fputs("panic: ", error_file); + pfx = "panic: "; break; case ERR_DEBUG: - fputs("debug: ", error_file); + pfx = "debug: "; break; default: + pfx = ""; break; } - vfprintf(error_file, fmt, args); - putc('\n', error_file); + vsnprintf(msg, sizeof msg, fmt, args); + + fprintf(error_file, "%s%s\n", pfx, msg); + + if (*listname) + nasmlist.error(severity, pfx, msg); if (severity & ERR_USAGE) want_usage = true; @@ -1958,7 +1959,7 @@ static void report_error_common(int severity, const char *fmt, /* no further action, by definition */ break; case ERR_WARNING: - if (!suppressed[0]) /* Treat warnings as errors */ + if (warning_on[0]) /* Treat warnings as errors */ terminate_after_phase = true; break; case ERR_NONFATAL: @@ -1,11 +1,38 @@ -/* nasm.h main header file for the Netwide Assembler: inter-module interface +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: * - * initial version: 27/iii/95 by Simon Tatham + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * nasm.h main header file for the Netwide Assembler: inter-module interface */ #ifndef NASM_NASM_H @@ -15,7 +42,6 @@ #include <stdio.h> #include <inttypes.h> -#include "version.h" /* generated NASM version macros */ #include "nasmlib.h" #include "preproc.h" #include "insnsi.h" /* For enum opcode */ @@ -156,6 +182,11 @@ typedef struct { * Reverse the effects of uplevel. */ void (*downlevel) (int); + + /* + * Called on a warning or error, with the error message. + */ + void (*error)(int severity, const char *pfx, const char *msg); } ListGen; /* @@ -572,6 +603,7 @@ typedef uint32_t opflags_t; #define SBYTE16 0x00022000U /* for op r16,immediate instrs. */ #define SBYTE32 0x00042000U /* for op r32,immediate instrs. */ #define SBYTE64 0x00082000U /* for op r64,immediate instrs. */ +#define BYTENESS 0x000e0000U /* for testing for byteness */ /* special flags */ #define SAME_AS 0x40000000U @@ -599,7 +631,16 @@ enum ccode { /* condition code names */ #define REX_H 0x80 /* High register present, REX forbidden */ #define REX_D 0x0100 /* Instruction uses DREX instead of REX */ #define REX_OC 0x0200 /* DREX suffix has the OC0 bit set */ -#define REX_V 0x0400 /* Instruction uses VEX instead of REX */ +#define REX_V 0x0400 /* Instruction uses VEX/XOP instead of REX */ +#define REX_NH 0x0800 /* Instruction which doesn't use high regs */ + +/* + * REX_V "classes" (prefixes which behave like VEX) + */ +enum vex_class { + RV_VEX = 0, /* C4/C5 */ + RV_XOP = 1 /* 8F */ +}; /* * Note that because segment registers may be used as instruction @@ -612,6 +653,7 @@ enum prefixes { /* instruction prefixes */ P_A16 = PREFIX_ENUM_START, P_A32, P_A64, P_ASP, P_LOCK, P_O16, P_O32, P_O64, P_OSP, P_REP, P_REPE, P_REPNE, P_REPNZ, P_REPZ, P_TIMES, + P_WAIT, PREFIX_ENUM_LIMIT }; @@ -653,6 +695,8 @@ typedef struct operand { /* operand to an instruction */ #define OPFLAG_FORWARD 1 /* operand is a forward reference */ #define OPFLAG_EXTERN 2 /* operand is an external reference */ +#define OPFLAG_UNKNOWN 4 /* operand is an unknown reference */ + /* (always a forward reference also) */ typedef struct extop { /* extended operand */ struct extop *next; /* linked list */ @@ -673,6 +717,7 @@ typedef struct extop { /* extended operand */ Note that LOCK and REP are in the same slot. This is an x86 architectural constraint. */ enum prefix_pos { + PPS_WAIT, /* WAIT (technically not a prefix!) */ PPS_LREP, /* Lock or REP prefix */ PPS_SEG, /* Segment override prefix */ PPS_OSIZE, /* Operand size prefix */ @@ -698,7 +743,7 @@ typedef struct insn { /* an instruction itself */ bool forw_ref; /* is there a forward reference? */ int rex; /* Special REX Prefix */ int drexdst; /* Destination register for DREX/VEX suffix */ - int vex_m; /* M register for VEX prefix */ + int vex_cm; /* Class and M field for VEX prefix */ int vex_wlp; /* W, P and L information for VEX prefix */ } insn; @@ -722,13 +767,11 @@ struct ofmt { */ const char *shortname; - /* - * this is reserved for out module specific help. - * It is set to NULL in all the out modules and is not implemented - * in the main program + * Output format flags. */ - const char *helpstring; +#define OFMT_TEXT 1 /* Text file format */ + unsigned int flags; /* * this is a pointer to the first element of the debug information @@ -903,7 +946,6 @@ struct ofmt { */ struct dfmt { - /* * This is a short (one-liner) description of the type of * output generated by the driver. @@ -1031,4 +1073,13 @@ extern int globalbits; /* 16, 32 or 64-bit mode */ extern int globalrel; /* default to relative addressing? */ extern int maxbits; /* max bits supported by output */ +/* + * NASM version strings, defined in ver.c + */ +extern const char nasm_version[]; +extern const char nasm_date[]; +extern const char nasm_compile_options[]; +extern const char nasm_comment[]; +extern const char nasm_signature[]; + #endif diff --git a/nasm.spec.in b/nasm.spec.in index 17ce186e..1b705210 100644 --- a/nasm.spec.in +++ b/nasm.spec.in @@ -4,10 +4,10 @@ Summary: The Netwide Assembler, a portable x86 assembler with Intel-like syntax Name: nasm Version: @@NASM_MANGLED_VER@@ Release: 1 -License: LGPL +License: BSD Group: Development/Languages -Source: ftp://download.sourceforge.net/pub/sourceforge/nasm/nasm-%{nasm_version}.tar.bz2 -URL: http://nasm.sourceforge.net/ +Source: http://www.nasm.us/pub/nasm/releasebuilds/%{nasm_version}/nasm-%{nasm_version}.tar.bz2 +URL: http://www.nasm.us/ BuildRoot: /tmp/rpm-build-nasm Prefix: %{_prefix} BuildPrereq: perl @@ -88,12 +88,17 @@ fi %{_bindir}/rdf2bin %{_bindir}/rdf2com %{_bindir}/rdf2ihx +%{_bindir}/rdf2ith +%{_bindir}/rdf2srec %{_bindir}/rdfdump %{_bindir}/rdflib %{_bindir}/rdx %{_mandir}/man1/ldrdf.1* %{_mandir}/man1/rdf2bin.1* %{_mandir}/man1/rdf2com.1* +%{_mandir}/man1/rdf2ihx.1* +%{_mandir}/man1/rdf2ith.1* +%{_mandir}/man1/rdf2srec.1* %{_mandir}/man1/rdfdump.1* %{_mandir}/man1/rdflib.1* %{_mandir}/man1/rdx.1* @@ -1,9 +1,38 @@ -/* nasmlib.c library routines for the Netwide Assembler +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * nasmlib.c library routines for the Netwide Assembler */ #include "compiler.h" @@ -25,6 +54,9 @@ efunc nasm_malloc_error; /* Exported for the benefit of vsnprintf.c */ static FILE *logfp; #endif +/* Uninitialized -> all zero by C spec */ +const uint8_t zero_buffer[ZERO_BUF_SIZE]; + /* * Prepare a table of tolower() results. This avoids function calls * on some platforms. @@ -51,7 +83,7 @@ void nasm_set_malloc_error(efunc error) } #ifdef LOGALLOC -void *nasm_malloc_log(char *file, int line, size_t size) +void *nasm_malloc_log(const char *file, int line, size_t size) #else void *nasm_malloc(size_t size) #endif @@ -68,7 +100,7 @@ void *nasm_malloc(size_t size) } #ifdef LOGALLOC -void *nasm_zalloc_log(char *file, int line, size_t size) +void *nasm_zalloc_log(const char *file, int line, size_t size) #else void *nasm_zalloc(size_t size) #endif @@ -85,7 +117,7 @@ void *nasm_zalloc(size_t size) } #ifdef LOGALLOC -void *nasm_realloc_log(char *file, int line, void *q, size_t size) +void *nasm_realloc_log(const char *file, int line, void *q, size_t size) #else void *nasm_realloc(void *q, size_t size) #endif @@ -105,7 +137,7 @@ void *nasm_realloc(void *q, size_t size) } #ifdef LOGALLOC -void nasm_free_log(char *file, int line, void *q) +void nasm_free_log(const char *file, int line, void *q) #else void nasm_free(void *q) #endif @@ -119,7 +151,7 @@ void nasm_free(void *q) } #ifdef LOGALLOC -char *nasm_strdup_log(char *file, int line, const char *s) +char *nasm_strdup_log(const char *file, int line, const char *s) #else char *nasm_strdup(const char *s) #endif @@ -140,9 +172,9 @@ char *nasm_strdup(const char *s) } #ifdef LOGALLOC -char *nasm_strndup_log(char *file, int line, char *s, size_t len) +char *nasm_strndup_log(const char *file, int line, const char *s, size_t len) #else -char *nasm_strndup(char *s, size_t len) +char *nasm_strndup(const char *s, size_t len) #endif { char *p; @@ -161,6 +193,13 @@ char *nasm_strndup(char *s, size_t len) return p; } +no_return nasm_assert_failed(const char *file, int line, const char *msg) +{ + nasm_malloc_error(ERR_FATAL, "assertion %s failed at %s:%d", + msg, file, line); + exit(1); +} + #ifndef nasm_stricmp int nasm_stricmp(const char *s1, const char *s2) { @@ -454,6 +493,26 @@ void fwriteaddr(uint64_t data, int size, FILE * fp) #endif +size_t fwritezero(size_t bytes, FILE *fp) +{ + size_t count = 0; + size_t blksize; + size_t rv; + + while (bytes) { + blksize = (bytes < ZERO_BUF_SIZE) ? bytes : ZERO_BUF_SIZE; + + rv = fwrite(zero_buffer, 1, blksize, fp); + if (!rv) + break; + + count += rv; + bytes -= rv; + } + + return count; +} + void standard_extension(char *inname, char *outname, char *extension, efunc error) { @@ -488,8 +547,8 @@ void standard_extension(char *inname, char *outname, char *extension, * Common list of prefix names */ static const char *prefix_names[] = { - "a16", "a32", "lock", "o16", "o32", "rep", "repe", "repne", - "repnz", "repz", "times" + "a16", "a32", "a64", "asp", "lock", "o16", "o32", "o64", "osp", + "rep", "repe", "repne", "repnz", "repz", "times", "wait" }; const char *prefix_name(int token) @@ -574,7 +633,7 @@ int src_get(int32_t *xline, char **xname) return 0; } -char *nasm_strcat(char *one, char *two) +char *nasm_strcat(const char *one, const char *two) { char *rslt; int l1 = strlen(one); @@ -583,57 +642,3 @@ char *nasm_strcat(char *one, char *two) strcpy(rslt + l1, two); return rslt; } - -void null_debug_init(struct ofmt *of, void *id, FILE * fp, efunc error) -{ - (void)of; - (void)id; - (void)fp; - (void)error; -} -void null_debug_linenum(const char *filename, int32_t linenumber, int32_t segto) -{ - (void)filename; - (void)linenumber; - (void)segto; -} -void null_debug_deflabel(char *name, int32_t segment, int64_t offset, - int is_global, char *special) -{ - (void)name; - (void)segment; - (void)offset; - (void)is_global; - (void)special; -} -void null_debug_routine(const char *directive, const char *params) -{ - (void)directive; - (void)params; -} -void null_debug_typevalue(int32_t type) -{ - (void)type; -} -void null_debug_output(int type, void *param) -{ - (void)type; - (void)param; -} -void null_debug_cleanup(void) -{ -} - -struct dfmt null_debug_form = { - "Null debug format", - "null", - null_debug_init, - null_debug_linenum, - null_debug_deflabel, - null_debug_routine, - null_debug_typevalue, - null_debug_output, - null_debug_cleanup -}; - -struct dfmt *null_debug_arr[2] = { &null_debug_form, NULL }; @@ -1,9 +1,38 @@ -/* nasmlib.h header file for nasmlib.c +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * nasmlib.h header file for nasmlib.c */ #ifndef NASM_NASMLIB_H @@ -71,14 +100,15 @@ extern efunc nasm_malloc_error; #define ERR_NOFILE 0x00000010 /* don't give source file name/line */ #define ERR_USAGE 0x00000020 /* print a usage message */ #define ERR_PASS1 0x00000040 /* only print this error on pass one */ -#define ERR_NO_SEVERITY 0x00000080 /* suppress printing severity */ +#define ERR_PASS2 0x00000080 +#define ERR_NO_SEVERITY 0x00000100 /* suppress printing severity */ /* * These codes define specific types of suppressible warning. */ -#define ERR_WARN_MASK 0x0000FF00 /* the mask for this feature */ -#define ERR_WARN_SHR 8 /* how far to shift right */ +#define ERR_WARN_MASK 0xFFFFF000 /* the mask for this feature */ +#define ERR_WARN_SHR 12 /* how far to shift right */ #define WARN(x) ((x) << ERR_WARN_SHR) @@ -93,7 +123,8 @@ extern efunc nasm_malloc_error; #define ERR_WARN_FL_DENORM WARN( 8) /* FP denormal */ #define ERR_WARN_FL_UNDERFLOW WARN( 9) /* FP underflow */ #define ERR_WARN_FL_TOOLONG WARN(10) /* FP too many digits */ -#define ERR_WARN_MAX 10 /* the highest numbered one */ +#define ERR_WARN_USER WARN(11) /* %warning directives */ +#define ERR_WARN_MAX 11 /* the highest numbered one */ /* * Wrappers around malloc, realloc and free. nasm_malloc will @@ -109,14 +140,14 @@ void *nasm_zalloc(size_t); void *nasm_realloc(void *, size_t); void nasm_free(void *); char *nasm_strdup(const char *); -char *nasm_strndup(char *, size_t); +char *nasm_strndup(const char *, size_t); #else -void *nasm_malloc_log(char *, int, size_t); -void *nasm_zalloc_log(char *, int, size_t); -void *nasm_realloc_log(char *, int, void *, size_t); -void nasm_free_log(char *, int, void *); -char *nasm_strdup_log(char *, int, const char *); -char *nasm_strndup_log(char *, int, char *, size_t); +void *nasm_malloc_log(const char *, int, size_t); +void *nasm_zalloc_log(const char *, int, size_t); +void *nasm_realloc_log(const char *, int, void *, size_t); +void nasm_free_log(const char *, int, void *); +char *nasm_strdup_log(const char *, int, const char *); +char *nasm_strndup_log(const char *, int, const char *, size_t); #define nasm_malloc(x) nasm_malloc_log(__FILE__,__LINE__,x) #define nasm_zalloc(x) nasm_zalloc_log(__FILE__,__LINE__,x) #define nasm_realloc(x,y) nasm_realloc_log(__FILE__,__LINE__,x,y) @@ -126,6 +157,16 @@ char *nasm_strndup_log(char *, int, char *, size_t); #endif /* + * NASM assert failure + */ +no_return nasm_assert_failed(const char *, int, const char *); +#define nasm_assert(x) \ + do { \ + if (unlikely(!(x))) \ + nasm_assert_failed(__FILE__,__LINE__,#x); \ + } while (0) + +/* * ANSI doesn't guarantee the presence of `stricmp' or * `strcasecmp'. */ @@ -319,12 +360,12 @@ int32_t src_get_linnum(void); */ int src_get(int32_t *xline, char **xname); -char *nasm_strcat(char *one, char *two); - -void null_debug_routine(const char *directive, const char *params); -extern struct dfmt null_debug_form; -extern struct dfmt *null_debug_arr[2]; +char *nasm_strcat(const char *one, const char *two); const char *prefix_name(int); +#define ZERO_BUF_SIZE 4096 +extern const uint8_t zero_buffer[ZERO_BUF_SIZE]; +size_t fwritezero(size_t bytes, FILE *fp); + #endif @@ -1,9 +1,38 @@ -/* ndisasm.c the Netwide Disassembler main module +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * ndisasm.c the Netwide Disassembler main module */ #include "compiler.h" @@ -90,8 +119,8 @@ int main(int argc, char **argv) case 'r': case 'v': fprintf(stderr, - "NDISASM version %s compiled " __DATE__ "\n", - NASM_VER); + "NDISASM version %s compiled on %s\n", + nasm_version, nasm_date); return 0; case 'u': /* -u for -b 32, -uu for -b 64 */ if (bits < 64) @@ -273,7 +302,8 @@ int main(int argc, char **argv) if ((nextsync || synclen) && (uint32_t)offset == nextsync) { if (synclen) { - fprintf(stdout, "%08"PRIX32" skipping 0x%"PRIX32" bytes\n", offset, synclen); + fprintf(stdout, "%08"PRIX32" skipping 0x%"PRIX32" bytes\n", + offset, synclen); offset += synclen; skip(synclen, fp); } @@ -282,12 +312,12 @@ int main(int argc, char **argv) } while (p > q && (p - q >= INSN_MAX || lenread == 0)) { lendis = - disasm((uint8_t *) q, outbuf, sizeof(outbuf), bits, offset, autosync, - prefer); + disasm((uint8_t *) q, outbuf, sizeof(outbuf), bits, + offset, autosync, prefer); if (!lendis || lendis > (p - q) || ((nextsync || synclen) && (uint32_t)lendis > nextsync - offset)) - lendis = eatbyte((uint8_t *) q, outbuf, sizeof(outbuf)); + lendis = eatbyte((uint8_t *) q, outbuf, sizeof(outbuf), bits); output_ins(offset, (uint8_t *) q, lendis, outbuf); q += lendis; offset += lendis; diff --git a/outform.c b/outform.c deleted file mode 100644 index 2aa55139..00000000 --- a/outform.c +++ /dev/null @@ -1,72 +0,0 @@ -/* outform.c manages a list of output formats, and associates - * them with their relevant drivers. Also has a - * routine to find the correct driver given a name - * for it - * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. - */ - -#include "compiler.h" - -#include <stdio.h> -#include <string.h> -#include <inttypes.h> - -#define BUILD_DRIVERS_ARRAY -#include "outform.h" - -static int ndrivers = 0; - -struct ofmt *ofmt_find(char *name) -{ /* find driver */ - int i; - - for (i = 0; i < ndrivers; i++) - if (!strcmp(name, drivers[i]->shortname)) - return drivers[i]; - - return NULL; -} -struct dfmt *dfmt_find(struct ofmt *ofmt, char *name) -{ /* find driver */ - struct dfmt **dfmt = ofmt->debug_formats; - while (*dfmt) { - if (!strcmp(name, (*dfmt)->shortname)) - return (*dfmt); - dfmt++; - } - return NULL; -} - -void ofmt_list(struct ofmt *deffmt, FILE * fp) -{ - int i; - for (i = 0; i < ndrivers; i++) - fprintf(fp, " %c %-10s%s\n", - drivers[i] == deffmt ? '*' : ' ', - drivers[i]->shortname, drivers[i]->fullname); -} -void dfmt_list(struct ofmt *ofmt, FILE * fp) -{ - struct dfmt **drivers = ofmt->debug_formats; - while (*drivers) { - fprintf(fp, " %c %-10s%s\n", - drivers[0] == ofmt->current_dfmt ? '*' : ' ', - drivers[0]->shortname, drivers[0]->fullname); - drivers++; - } -} -struct ofmt *ofmt_register(efunc error) -{ - for (ndrivers = 0; drivers[ndrivers] != NULL; ndrivers++) ; - - if (ndrivers == 0) { - error(ERR_PANIC | ERR_NOFILE, - "No output drivers given at compile time"); - } - - return (&OF_DEFAULT); -} diff --git a/outform.h b/outform.h deleted file mode 100644 index 585ad4e4..00000000 --- a/outform.h +++ /dev/null @@ -1,304 +0,0 @@ -/* outform.h header file for binding output format drivers to the - * remainder of the code in the Netwide Assembler - * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. - */ - -/* - * This header file allows configuration of which output formats - * get compiled into the NASM binary. You can configure by defining - * various preprocessor symbols beginning with "OF_", either on the - * compiler command line or at the top of this file. - * - * OF_ONLY -- only include specified object formats - * OF_name -- ensure that output format 'name' is included - * OF_NO_name -- remove output format 'name' - * OF_DOS -- ensure that 'obj', 'bin' & 'win32' are included. - * OF_UNIX -- ensure that 'aout', 'aoutb', 'coff', 'elf32' 'elf64' are in. - * OF_OTHERS -- ensure that 'bin', 'as86' & 'rdf' are in. - * OF_ALL -- ensure that all formats are included. - * note that this doesn't include 'dbg', which is - * only really useful if you're doing development - * work on NASM. Define OF_DBG if you want this. - * - * OF_DEFAULT=of_name -- ensure that 'name' is the default format. - * - * eg: -DOF_UNIX -DOF_ELF32 -DOF_DEFAULT=of_elf32 would be a suitable config - * for an average linux system. - * - * Default config = -DOF_ALL -DOF_DEFAULT=of_bin - * - * You probably only want to set these options while compiling 'nasm.c'. */ - -#ifndef NASM_OUTFORM_H -#define NASM_OUTFORM_H - -#include "nasm.h" - -/* -------------- USER MODIFIABLE PART ---------------- */ - -/* - * Insert #defines here in accordance with the configuration - * instructions above. - * - * E.g. - * - * #define OF_ONLY - * #define OF_OBJ - * #define OF_BIN - * - * for a 16-bit DOS assembler with no extraneous formats. - */ - -/* ------------ END USER MODIFIABLE PART -------------- */ - -/* ====configurable info begins here==== */ -/* formats configurable: - * bin,obj,elf32,elf64,aout,aoutb,coff,win32,as86,rdf2,macho32,macho64 */ - -/* process options... */ - -#ifndef OF_ONLY -#ifndef OF_ALL -#define OF_ALL /* default is to have all formats */ -#endif -#endif - -#ifdef OF_ALL /* set all formats on... */ -#ifndef OF_BIN -#define OF_BIN -#endif -#ifndef OF_OBJ -#define OF_OBJ -#endif -#ifndef OF_ELF32 -#define OF_ELF32 -#endif -#ifndef OF_ELF64 -#define OF_ELF64 -#endif -#ifndef OF_COFF -#define OF_COFF -#endif -#ifndef OF_AOUT -#define OF_AOUT -#endif -#ifndef OF_AOUTB -#define OF_AOUTB -#endif -#ifndef OF_WIN32 -#define OF_WIN32 -#endif -#ifndef OF_WIN64 -#define OF_WIN64 -#endif -#ifndef OF_AS86 -#define OF_AS86 -#endif -#ifndef OF_RDF2 -#define OF_RDF2 -#endif -#ifndef OF_IEEE -#define OF_IEEE -#endif -#ifndef OF_MACHO32 -#define OF_MACHO32 -#endif -#ifndef OF_MACHO64 -#define OF_MACHO64 -#endif -#endif /* OF_ALL */ - -/* turn on groups of formats specified.... */ -#ifdef OF_DOS -#ifndef OF_OBJ -#define OF_OBJ -#endif -#ifndef OF_BIN -#define OF_BIN -#endif -#ifndef OF_COFF -#define OF_COFF /* COFF is used by DJGPP */ -#endif -#ifndef OF_WIN32 -#define OF_WIN32 -#endif -#ifndef OF_WIN64 -#define OF_WIN64 -#endif -#endif - -#ifdef OF_UNIX -#ifndef OF_AOUT -#define OF_AOUT -#endif -#ifndef OF_AOUTB -#define OF_AOUTB -#endif -#ifndef OF_COFF -#define OF_COFF -#endif -#ifndef OF_ELF32 -#define OF_ELF32 -#endif -#ifndef OF_ELF64 -#define OF_ELF64 -#endif -#endif - -#ifdef OF_OTHERS -#ifndef OF_BIN -#define OF_BIN -#endif -#ifndef OF_AS86 -#define OF_AS86 -#endif -#ifndef OF_RDF2 -#define OF_RDF2 -#endif -#ifndef OF_IEEE -#define OF_IEEE -#endif -#ifndef OF_MACHO32 -#define OF_MACHO32 -#endif -#ifndef OF_MACHO64 -#define OF_MACHO64 -#endif -#endif - -/* finally... override any format specifically specified to be off */ -#ifdef OF_NO_BIN -#undef OF_BIN -#endif -#ifdef OF_NO_OBJ -#undef OF_OBJ -#endif -#ifdef OF_NO_ELF32 -#undef OF_ELF32 -#endif -#ifdef OF_NO_ELF64 -#undef OF_ELF64 -#endif -#ifdef OF_NO_AOUT -#undef OF_AOUT -#endif -#ifdef OF_NO_AOUTB -#undef OF_AOUTB -#endif -#ifdef OF_NO_COFF -#undef OF_COFF -#endif -#ifdef OF_NO_WIN32 -#undef OF_WIN32 -#endif -#ifdef OF_NO_WIN64 -#undef OF_WIN64 -#endif -#ifdef OF_NO_AS86 -#undef OF_AS86 -#endif -#ifdef OF_NO_RDF2 -#undef OF_RDF -#endif -#ifdef OF_NO_IEEE -#undef OF_IEEE -#endif -#ifdef OF_NO_MACHO32 -#undef OF_MACHO32 -#endif -#ifdef OF_NO_MACHO64 -#undef OF_MACHO64 -#endif - -#ifndef OF_DEFAULT -#define OF_DEFAULT of_bin -#endif - -#ifdef BUILD_DRIVERS_ARRAY /* only if included from outform.c */ - -/* pull in the externs for the different formats, then make the *drivers - * array based on the above defines */ - -extern struct ofmt of_bin; -extern struct ofmt of_aout; -extern struct ofmt of_aoutb; -extern struct ofmt of_coff; -extern struct ofmt of_elf32; -extern struct ofmt of_elf; -extern struct ofmt of_elf64; -extern struct ofmt of_as86; -extern struct ofmt of_obj; -extern struct ofmt of_win32; -extern struct ofmt of_win64; -extern struct ofmt of_rdf2; -extern struct ofmt of_ieee; -extern struct ofmt of_macho32; -extern struct ofmt of_macho; -extern struct ofmt of_macho64; -extern struct ofmt of_dbg; - -struct ofmt *drivers[] = { -#ifdef OF_BIN - &of_bin, -#endif -#ifdef OF_AOUT - &of_aout, -#endif -#ifdef OF_AOUTB - &of_aoutb, -#endif -#ifdef OF_COFF - &of_coff, -#endif -#ifdef OF_ELF32 - &of_elf32, - &of_elf, -#endif -#ifdef OF_ELF64 - &of_elf64, -#endif -#ifdef OF_AS86 - &of_as86, -#endif -#ifdef OF_OBJ - &of_obj, -#endif -#ifdef OF_WIN32 - &of_win32, -#endif -#ifdef OF_WIN64 - &of_win64, -#endif -#ifdef OF_RDF2 - &of_rdf2, -#endif -#ifdef OF_IEEE - &of_ieee, -#endif -#ifdef OF_MACHO32 - &of_macho32, - &of_macho, -#endif -#ifdef OF_MACHO64 - &of_macho64, -#endif -#ifdef OF_DBG - &of_dbg, -#endif - - NULL -}; - -#endif /* BUILD_DRIVERS_ARRAY */ - -struct ofmt *ofmt_find(char *); -struct dfmt *dfmt_find(struct ofmt *, char *); -void ofmt_list(struct ofmt *, FILE *); -void dfmt_list(struct ofmt *ofmt, FILE * fp); -struct ofmt *ofmt_register(efunc error); - -#endif /* NASM_OUTFORM_H */ diff --git a/output/generic.mac b/output/generic.mac deleted file mode 100644 index 0a371ede..00000000 --- a/output/generic.mac +++ /dev/null @@ -1,4 +0,0 @@ -OUT: generic aout aoutb as86 macho macho32 macho64 -%define __SECT__ [section .text] -%macro __NASM_CDecl__ 1 -%endmacro diff --git a/output/outaout.c b/output/outaout.c index 25f1c663..4d38cdfc 100644 --- a/output/outaout.c +++ b/output/outaout.c @@ -1,10 +1,39 @@ -/* outaout.c output routines for the Netwide Assembler to produce - * Linux a.out object files +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * ----------------------------------------------------------------------- */ + +/* + * outaout.c output routines for the Netwide Assembler to produce + * Linux a.out object files */ #include "compiler.h" @@ -20,7 +49,8 @@ #include "saa.h" #include "raa.h" #include "stdscan.h" -#include "outform.h" +#include "output/outform.h" +#include "output/outlib.h" #if defined OF_AOUT || defined OF_AOUTB @@ -603,11 +633,7 @@ static void aout_out(int32_t segto, const void *data, if (!s && type != OUT_RESERVE) { error(ERR_WARNING, "attempt to initialize memory in the" " BSS section: ignored"); - if (type == OUT_REL2ADR) - size = 2; - else if (type == OUT_REL4ADR) - size = 4; - sbss.len += size; + sbss.len += realsize(type, size); return; } @@ -905,7 +931,7 @@ static void aout_filename(char *inname, char *outname, efunc error) standard_extension(inname, outname, ".o", error); } -extern macros_t generic_stdmac[]; +extern macros_t aout_stdmac[]; static int aout_set_info(enum geninfo type, char **val) { @@ -920,10 +946,10 @@ static int aout_set_info(enum geninfo type, char **val) struct ofmt of_aout = { "Linux a.out object files", "aout", - NULL, + 0, null_debug_arr, &null_debug_form, - generic_stdmac, + aout_stdmac, aout_init, aout_set_info, aout_out, @@ -942,10 +968,10 @@ struct ofmt of_aout = { struct ofmt of_aoutb = { "NetBSD/FreeBSD a.out object files", "aoutb", - NULL, + 0, null_debug_arr, &null_debug_form, - generic_stdmac, + aout_stdmac, aoutb_init, aout_set_info, aout_out, diff --git a/output/outas86.c b/output/outas86.c index ba49aa3f..2fa4efca 100644 --- a/output/outas86.c +++ b/output/outas86.c @@ -1,10 +1,39 @@ -/* outas86.c output routines for the Netwide Assembler to produce - * Linux as86 (bin86-0.3) object files +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * ----------------------------------------------------------------------- */ + +/* + * outas86.c output routines for the Netwide Assembler to produce + * Linux as86 (bin86-0.3) object files */ #include "compiler.h" @@ -19,7 +48,8 @@ #include "nasmlib.h" #include "saa.h" #include "raa.h" -#include "outform.h" +#include "output/outform.h" +#include "output/outlib.h" #ifdef OF_AS86 @@ -178,21 +208,31 @@ static int as86_add_string(char *name) static void as86_deflabel(char *name, int32_t segment, int64_t offset, int is_global, char *special) { + bool is_start = false; struct Symbol *sym; if (special) error(ERR_NONFATAL, "as86 format does not support any" " special symbol types"); + if (name[0] == '.' && name[1] == '.' && name[2] != '@') { - error(ERR_NONFATAL, "unrecognised special symbol `%s'", name); - return; + if (strcmp(name, "..start")) { + error(ERR_NONFATAL, "unrecognised special symbol `%s'", name); + return; + } else { + is_start = true; + } } sym = saa_wstruct(syms); sym->strpos = as86_add_string(name); sym->flags = 0; + + if (is_start) + sym->flags = SYM_ENTRY; + if (segment == NO_SEG) sym->flags |= SYM_ABSOLUTE, sym->segment = 0; else if (segment == stext.index) @@ -294,11 +334,7 @@ static void as86_out(int32_t segto, const void *data, if (!s && type != OUT_RESERVE) { error(ERR_WARNING, "attempt to initialize memory in the" " BSS section: ignored"); - if (type == OUT_REL2ADR) - size = 2; - else if (type == OUT_REL4ADR) - size = 4; - bsslen += size; + bsslen += realsize(type, size); return; } @@ -603,7 +639,7 @@ static void as86_filename(char *inname, char *outname, efunc error) standard_extension(inname, outname, ".o", error); } -extern macros_t generic_stdmac[]; +extern macros_t as86_stdmac[]; static int as86_set_info(enum geninfo type, char **val) { @@ -623,10 +659,10 @@ void as86_linenumber(char *name, int32_t segment, int32_t offset, int is_main, struct ofmt of_as86 = { "Linux as86 (bin86 version 0.3) object files", "as86", - NULL, + 0, null_debug_arr, &null_debug_form, - generic_stdmac, + as86_stdmac, as86_init, as86_set_info, as86_out, diff --git a/output/outbin.c b/output/outbin.c index b494a97b..8942acfd 100644 --- a/output/outbin.c +++ b/output/outbin.c @@ -1,10 +1,39 @@ -/* outbin.c output routines for the Netwide Assembler to produce - * flat-form binary files +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * outbin.c output routines for the Netwide Assembler to produce + * flat-form binary files */ /* This is the extended version of NASM's original binary output @@ -58,14 +87,15 @@ #include "stdscan.h" #include "labels.h" #include "eval.h" -#include "outform.h" +#include "output/outform.h" +#include "output/outlib.h" #ifdef OF_BIN -struct ofmt *bin_get_ofmt(); /* Prototype goes here since no header file. */ - static FILE *fp, *rf = NULL; static efunc error; +static struct ofmt *my_ofmt; +static void (*do_output)(void); /* Section flags keep track of which attributes the user has defined. */ #define START_DEFINED 0x001 @@ -246,10 +276,9 @@ static void bin_cleanup(int debuginfo) } /* Do some special pre-processing on nobits sections' attributes. */ if (s->flags & (START_DEFINED | ALIGN_DEFINED | FOLLOWS_DEFINED)) { /* Check for a mixture of real and virtual section attributes. */ - if (s-> - flags & (VSTART_DEFINED | VALIGN_DEFINED | - VFOLLOWS_DEFINED)) - error(ERR_FATAL, + if (s->flags & (VSTART_DEFINED | VALIGN_DEFINED | + VFOLLOWS_DEFINED)) + error(ERR_FATAL|ERR_NOFILE, "cannot mix real and virtual attributes" " in nobits section (%s)", s->name); /* Real and virtual attributes mean the same thing for nobits sections. */ @@ -320,11 +349,11 @@ static void bin_cleanup(int debuginfo) s && strcmp(s->name, g->follows); sp = &s->next, s = s->next) ; if (!s) - error(ERR_FATAL, "section %s follows an invalid or" + error(ERR_FATAL|ERR_NOFILE, "section %s follows an invalid or" " unknown section (%s)", g->name, g->follows); if (s->next && (s->next->flags & FOLLOWS_DEFINED) && !strcmp(s->name, s->next->follows)) - error(ERR_FATAL, "sections %s and %s can't both follow" + error(ERR_FATAL|ERR_NOFILE, "sections %s and %s can't both follow" " section %s", g->name, s->next->name, s->name); /* Find the end of the current follows group (gs). */ for (gsp = &g->next, gs = g->next; @@ -364,21 +393,18 @@ static void bin_cleanup(int debuginfo) /* Step 3: Compute start addresses for all progbits sections. */ /* Make sure we have an origin and a start address for the first section. */ - if (origin_defined) - switch (sections->flags & (START_DEFINED | ALIGN_DEFINED)) { - case START_DEFINED | ALIGN_DEFINED: - case START_DEFINED: + if (origin_defined) { + if (sections->flags & START_DEFINED) { /* Make sure this section doesn't begin before the origin. */ if (sections->start < origin) - error(ERR_FATAL, "section %s begins" + error(ERR_FATAL|ERR_NOFILE, "section %s begins" " before program origin", sections->name); - break; - case ALIGN_DEFINED: + } else if (sections->flags & ALIGN_DEFINED) { sections->start = ((origin + sections->align - 1) & ~(sections->align - 1)); - break; - case 0: + } else { sections->start = origin; + } } else { if (!(sections->flags & START_DEFINED)) sections->start = 0; @@ -427,11 +453,14 @@ static void bin_cleanup(int debuginfo) pend = g->start + g->length; /* Check for section overlap. */ if (s) { - if (g->start > s->start) - error(ERR_FATAL, "sections %s ~ %s and %s overlap!", + if (s->start < origin) + error(ERR_FATAL|ERR_NOFILE, "section %s beings before program origin", + s->name); + if (g->start > s->start) + error(ERR_FATAL|ERR_NOFILE, "sections %s ~ %s and %s overlap!", gs->name, g->name, s->name); if (pend > s->start) - error(ERR_FATAL, "sections %s and %s overlap!", + error(ERR_FATAL|ERR_NOFILE, "sections %s and %s overlap!", g->name, s->name); } /* Remember this section as the latest >0 length section. */ @@ -444,11 +473,13 @@ static void bin_cleanup(int debuginfo) for (s = sections; s->next; s = s->next) ; s->next = nobits; last_progbits = s; - /* Scan for sections that don't have a vstart address. If we find one we'll - * attempt to compute its vstart. If we can't compute the vstart, we leave - * it alone and come back to it in a subsequent scan. We continue scanning - * and re-scanning until we've gone one full cycle without computing any - * vstarts. */ + /* + * Scan for sections that don't have a vstart address. If we find + * one we'll attempt to compute its vstart. If we can't compute + * the vstart, we leave it alone and come back to it in a + * subsequent scan. We continue scanning and re-scanning until + * we've gone one full cycle without computing any vstarts. + */ do { /* Do one full scan of the sections list. */ for (h = 0, g = sections; g; g = g->next) { if (g->flags & VSTART_DEFINED) @@ -458,13 +489,14 @@ static void bin_cleanup(int debuginfo) for (s = sections; s && strcmp(g->vfollows, s->name); s = s->next) ; if (!s) - error(ERR_FATAL, + error(ERR_FATAL|ERR_NOFILE, "section %s vfollows unknown section (%s)", g->name, g->vfollows); } else if (g->ifollows != NULL) for (s = sections; s && (s != g->ifollows); s = s->next) ; - /* The .bss section is the only one with ifollows = NULL. In this case we - * implicitly follow the last progbits section. */ + /* The .bss section is the only one with ifollows = NULL. + In this case we implicitly follow the last progbits + section. */ else s = last_progbits; @@ -475,9 +507,8 @@ static void bin_cleanup(int debuginfo) g->flags |= VALIGN_DEFINED; } /* Compute the vstart address. */ - g->vstart = - (s->vstart + s->length + g->valign - 1) & ~(g->valign - - 1); + g->vstart = (s->vstart + s->length + g->valign - 1) + & ~(g->valign - 1); g->flags |= VSTART_DEFINED; h++; /* Start and vstart mean the same thing for nobits sections. */ @@ -498,7 +529,7 @@ static void bin_cleanup(int debuginfo) } } if (h) - error(ERR_FATAL, "circular vfollows path detected"); + error(ERR_FATAL|ERR_NOFILE, "circular vfollows path detected"); #ifdef DEBUG fprintf(stdout, @@ -561,26 +592,13 @@ static void bin_cleanup(int debuginfo) } /* Step 6: Write the section data to the output file. */ - - /* Write the progbits sections to the output file. */ - for (pend = origin, s = sections; s && (s->flags & TYPE_PROGBITS); s = s->next) { /* Skip zero-length sections. */ - if (s->length == 0) - continue; - /* Pad the space between sections. */ - for (h = s->start - pend; h; h--) - fputc('\0', fp); - /* Write the section to the output file. */ - if (s->length > 0) - saa_fpwrite(s->contents, fp); - pend = s->start + s->length; - } - /* Done writing the file, so close it. */ - fclose(fp); + do_output(); + fclose(fp); /* Done with the output file */ /* Step 7: Generate the map file. */ if (map_control) { - const char *not_defined = { "not defined" }; + static const char not_defined[] = "not defined"; /* Display input and output file names. */ fprintf(rf, "\n- NASM Map file "); @@ -634,22 +652,22 @@ static void bin_cleanup(int debuginfo) if (s->flags & ALIGN_DEFINED) fprintf(rf, "%16"PRIX64"", s->align); else - fprintf(rf, not_defined); + fputs(not_defined, rf); fprintf(rf, "\nfollows: "); if (s->flags & FOLLOWS_DEFINED) fprintf(rf, "%s", s->follows); else - fprintf(rf, not_defined); + fputs(not_defined, rf); fprintf(rf, "\nvstart: %16"PRIX64"\nvalign: ", s->vstart); if (s->flags & VALIGN_DEFINED) fprintf(rf, "%16"PRIX64"", s->valign); else - fprintf(rf, not_defined); + fputs(not_defined, rf); fprintf(rf, "\nvfollows: "); if (s->flags & VFOLLOWS_DEFINED) fprintf(rf, "%s", s->vfollows); else - fprintf(rf, not_defined); + fputs(not_defined, rf); fprintf(rf, "\n\n"); } } @@ -798,20 +816,8 @@ static void bin_out(int32_t segto, const void *data, s->length += size; } else if (type == OUT_REL2ADR || type == OUT_REL4ADR || type == OUT_REL8ADR) { - switch (type) { - case OUT_REL2ADR: - size = 2; - break; - case OUT_REL4ADR: - size = 4; - break; - case OUT_REL8ADR: - size = 8; - break; - default: - size = 0; /* Shut up warning */ - break; - } + int64_t addr = *(int64_t *)data - size; + size = realsize(type, size); if (segment != NO_SEG && !find_section_by_index(segment)) { if (segment % 2) error(ERR_NONFATAL, "binary output format does not support" @@ -824,7 +830,7 @@ static void bin_out(int32_t segto, const void *data, if (s->flags & TYPE_PROGBITS) { add_reloc(s, size, segment, segto); p = mydata; - WRITEADDR(p, *(int64_t *)data - size - s->length, size); + WRITEADDR(p, addr - s->length, size); saa_wbytes(s->contents, mydata, size); } s->length += size; @@ -1203,12 +1209,12 @@ static void bin_define_section_labels(void) /* section.<name>.start */ strcpy(label_name + base_len, ".start"); define_label(label_name, sec->start_index, 0L, - NULL, 0, 0, bin_get_ofmt(), error); + NULL, 0, 0, my_ofmt, error); /* section.<name>.vstart */ strcpy(label_name + base_len, ".vstart"); define_label(label_name, sec->vstart_index, 0L, - NULL, 0, 0, bin_get_ofmt(), error); + NULL, 0, 0, my_ofmt, error); nasm_free(label_name); } @@ -1370,6 +1376,20 @@ static void bin_filename(char *inname, char *outname, efunc error) outfile = outname; } +static void ith_filename(char *inname, char *outname, efunc error) +{ + standard_extension(inname, outname, ".ith", error); + infile = inname; + outfile = outname; +} + +static void srec_filename(char *inname, char *outname, efunc error) +{ + standard_extension(inname, outname, ".srec", error); + infile = inname; + outfile = outname; +} + static int32_t bin_segbase(int32_t segment) { return segment; @@ -1382,7 +1402,34 @@ static int bin_set_info(enum geninfo type, char **val) return 0; } -static void bin_init(FILE * afp, efunc errfunc, ldfunc ldef, evalfunc eval) +static void binfmt_init(FILE *afp, efunc errfunc, ldfunc ldef, evalfunc eval); +struct ofmt of_bin, of_ith, of_srec; +static void do_output_bin(void); +static void do_output_ith(void); +static void do_output_srec(void); + +static void bin_init(FILE *afp, efunc errfunc, ldfunc ldef, evalfunc eval) +{ + my_ofmt = &of_bin; + do_output = do_output_bin; + binfmt_init(afp, errfunc, ldef, eval); +} + +static void ith_init(FILE *afp, efunc errfunc, ldfunc ldef, evalfunc eval) +{ + my_ofmt = &of_ith; + do_output = do_output_ith; + binfmt_init(afp, errfunc, ldef, eval); +} + +static void srec_init(FILE *afp, efunc errfunc, ldfunc ldef, evalfunc eval) +{ + my_ofmt = &of_srec; + do_output = do_output_srec; + binfmt_init(afp, errfunc, ldef, eval); +} + +static void binfmt_init(FILE *afp, efunc errfunc, ldfunc ldef, evalfunc eval) { fp = afp; error = errfunc; @@ -1414,10 +1461,224 @@ static void bin_init(FILE * afp, efunc errfunc, ldfunc ldef, evalfunc eval) last_section->vstart_index = current_section = seg_alloc(); } +/* Generate binary file output */ +static void do_output_bin(void) +{ + struct Section *s; + uint64_t addr = origin; + + /* Write the progbits sections to the output file. */ + for (s = sections; s; s = s->next) { + /* Skip non-progbits sections */ + if (!(s->flags & TYPE_PROGBITS)) + continue; + /* Skip zero-length sections */ + if (s->length == 0) + continue; + + /* Pad the space between sections. */ + nasm_assert(addr <= s->start); + fwritezero(s->start - addr, fp); + + /* Write the section to the output file. */ + saa_fpwrite(s->contents, fp); + + /* Keep track of the current file position */ + addr = s->start + s->length; + } +} + +/* Generate Intel hex file output */ +static int write_ith_record(unsigned int len, uint16_t addr, + uint8_t type, void *data) +{ + char buf[1+2+4+2+255*2+2+2]; + char *p = buf; + uint8_t csum, *dptr = data; + unsigned int i; + + nasm_assert(len <= 255); + + csum = len + addr + (addr >> 8) + type; + for (i = 0; i < len; i++) + csum += dptr[i]; + csum = -csum; + + p += sprintf(p, ":%02X%04X%02X", len, addr, type); + for (i = 0; i < len; i++) + p += sprintf(p, "%02X", dptr[i]); + p += sprintf(p, "%02X\n", csum); + + if (fwrite(buf, 1, p-buf, fp) != (size_t)(p-buf)) + return -1; + + return 0; +} + +static void do_output_ith(void) +{ + uint8_t buf[32]; + struct Section *s; + uint64_t addr, hiaddr, hilba; + uint64_t length; + unsigned int chunk; + + /* Write the progbits sections to the output file. */ + hilba = 0; + for (s = sections; s; s = s->next) { + /* Skip non-progbits sections */ + if (!(s->flags & TYPE_PROGBITS)) + continue; + /* Skip zero-length sections */ + if (s->length == 0) + continue; + + addr = s->start; + length = s->length; + saa_rewind(s->contents); + + while (length) { + hiaddr = addr >> 16; + if (hiaddr != hilba) { + buf[0] = hiaddr >> 8; + buf[1] = hiaddr; + write_ith_record(2, 0, 4, buf); + hilba = hiaddr; + } + + chunk = 32 - (addr & 31); + if (length < chunk) + chunk = length; + + saa_rnbytes(s->contents, buf, chunk); + write_ith_record(chunk, (uint16_t)addr, 0, buf); + + addr += chunk; + length -= chunk; + } + } + + /* Write closing record */ + write_ith_record(0, 0, 1, NULL); +} + +/* Generate Motorola S-records */ +static int write_srecord(unsigned int len, unsigned int alen, + uint32_t addr, uint8_t type, void *data) +{ + char buf[2+2+8+255*2+2+2]; + char *p = buf; + uint8_t csum, *dptr = data; + unsigned int i; + + nasm_assert(len <= 255); + + switch (alen) { + case 2: + addr &= 0xffff; + break; + case 3: + addr &= 0xffffff; + break; + case 4: + break; + default: + nasm_assert(0); + break; + } + + csum = (len+alen+1) + addr + (addr >> 8) + (addr >> 16) + (addr >> 24); + for (i = 0; i < len; i++) + csum += dptr[i]; + csum = 0xff-csum; + + p += sprintf(p, "S%c%02X%0*X", type, len+alen+1, alen*2, addr); + for (i = 0; i < len; i++) + p += sprintf(p, "%02X", dptr[i]); + p += sprintf(p, "%02X\n", csum); + + if (fwrite(buf, 1, p-buf, fp) != (size_t)(p-buf)) + return -1; + + return 0; +} + +static void do_output_srec(void) +{ + uint8_t buf[32]; + struct Section *s; + uint64_t addr, maxaddr; + uint64_t length; + int alen; + unsigned int chunk; + char dtype, etype; + + maxaddr = 0; + for (s = sections; s; s = s->next) { + /* Skip non-progbits sections */ + if (!(s->flags & TYPE_PROGBITS)) + continue; + /* Skip zero-length sections */ + if (s->length == 0) + continue; + + addr = s->start + s->length - 1; + if (addr > maxaddr) + maxaddr = addr; + } + + if (maxaddr <= 0xffff) { + alen = 2; + dtype = '1'; /* S1 = 16-bit data */ + etype = '9'; /* S9 = 16-bit end */ + } else if (maxaddr <= 0xffffff) { + alen = 3; + dtype = '2'; /* S2 = 24-bit data */ + etype = '8'; /* S8 = 24-bit end */ + } else { + alen = 4; + dtype = '3'; /* S3 = 32-bit data */ + etype = '7'; /* S7 = 32-bit end */ + } + + /* Write head record */ + write_srecord(0, 2, 0, '0', NULL); + + /* Write the progbits sections to the output file. */ + for (s = sections; s; s = s->next) { + /* Skip non-progbits sections */ + if (!(s->flags & TYPE_PROGBITS)) + continue; + /* Skip zero-length sections */ + if (s->length == 0) + continue; + + addr = s->start; + length = s->length; + saa_rewind(s->contents); + + while (length) { + chunk = 32 - (addr & 31); + if (length < chunk) + chunk = length; + + saa_rnbytes(s->contents, buf, chunk); + write_srecord(chunk, alen, (uint32_t)addr, dtype, buf); + + addr += chunk; + length -= chunk; + } + } + + /* Write closing record */ + write_srecord(0, alen, 0, etype, NULL); +} + + struct ofmt of_bin = { "flat-form binary files (e.g. DOS .COM, .SYS)", "bin", - NULL, + 0, null_debug_arr, &null_debug_form, bin_stdmac, @@ -1432,10 +1693,40 @@ struct ofmt of_bin = { bin_cleanup }; -/* This is needed for bin_define_section_labels() */ -struct ofmt *bin_get_ofmt(void) -{ - return &of_bin; -} +struct ofmt of_ith = { + "Intel hex", + "ith", + OFMT_TEXT, + null_debug_arr, + &null_debug_form, + bin_stdmac, + ith_init, + bin_set_info, + bin_out, + bin_deflabel, + bin_secname, + bin_segbase, + bin_directive, + ith_filename, + bin_cleanup +}; + +struct ofmt of_srec = { + "Motorola S-records", + "srec", + 0, + null_debug_arr, + &null_debug_form, + bin_stdmac, + srec_init, + bin_set_info, + bin_out, + bin_deflabel, + bin_secname, + bin_segbase, + bin_directive, + srec_filename, + bin_cleanup +}; #endif /* #ifdef OF_BIN */ diff --git a/output/outbin.mac b/output/outbin.mac index d0ae2a3d..be7fefae 100644 --- a/output/outbin.mac +++ b/output/outbin.mac @@ -1,3 +1,36 @@ +;; -------------------------------------------------------------------------- +;; +;; Copyright 1996-2009 The NASM Authors - All Rights Reserved +;; See the file AUTHORS included with the NASM distribution for +;; the specific copyright holders. +;; +;; Redistribution and use in source and binary forms, with or without +;; modification, are permitted provided that the following +;; conditions are met: +;; +;; * Redistributions of source code must retain the above copyright +;; notice, this list of conditions and the following disclaimer. +;; * Redistributions in binary form must reproduce the above +;; copyright notice, this list of conditions and the following +;; disclaimer in the documentation and/or other materials provided +;; with the distribution. +;; +;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +;; CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +;; INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +;; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +;; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;; NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +;; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +;; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +;; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +;; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;; +;; -------------------------------------------------------------------------- + OUT: bin %define __SECT__ [section .text] %imacro org 1+.nolist diff --git a/output/outcoff.c b/output/outcoff.c index 31e5cbef..5a03bec5 100644 --- a/output/outcoff.c +++ b/output/outcoff.c @@ -1,10 +1,39 @@ -/* outcoff.c output routines for the Netwide Assembler to produce - * COFF object files (for DJGPP and Win32) +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * ----------------------------------------------------------------------- */ + +/* + * outcoff.c output routines for the Netwide Assembler to produce + * COFF object files (for DJGPP and Win32) */ #include "compiler.h" @@ -20,7 +49,8 @@ #include "nasmlib.h" #include "saa.h" #include "raa.h" -#include "outform.h" +#include "output/outform.h" +#include "output/outlib.h" #if defined(OF_COFF) || defined(OF_WIN32) || defined(OF_WIN64) @@ -527,11 +557,7 @@ static void coff_out(int32_t segto, const void *data, if (!s->data && type != OUT_RESERVE) { error(ERR_WARNING, "attempt to initialize memory in" " BSS section `%s': ignored", s->name); - if (type == OUT_REL2ADR) - size = 2; - else if (type == OUT_REL4ADR) - size = 4; - s->len += size; + s->len += realsize(type, size); return; } @@ -729,7 +755,9 @@ static int coff_directives(char *directive, char *value, int pass) else sxseg = i; } - if (pass==2) { + /* pass0 == 2 is the only time when the full set of symbols are + guaranteed to be present; it is the final output pass. */ + if (pass0 == 2) { uint32_t n; saa_rewind(syms); for (n = 0; n < nsyms; n++) { @@ -981,7 +1009,7 @@ static int coff_set_info(enum geninfo type, char **val) struct ofmt of_coff = { "COFF (i386) object files (e.g. DJGPP for DOS)", "coff", - NULL, + 0, null_debug_arr, &null_debug_form, coff_stdmac, @@ -1003,7 +1031,7 @@ struct ofmt of_coff = { struct ofmt of_win32 = { "Microsoft Win32 (i386) object files", "win32", - NULL, + 0, null_debug_arr, &null_debug_form, coff_stdmac, @@ -1025,7 +1053,7 @@ struct ofmt of_win32 = { struct ofmt of_win64 = { "Microsoft Win64 (x86-64) object files", "win64", - NULL, + 0, null_debug_arr, &null_debug_form, coff_stdmac, diff --git a/output/outcoff.mac b/output/outcoff.mac index fffb1051..2b8b12ff 100644 --- a/output/outcoff.mac +++ b/output/outcoff.mac @@ -1,3 +1,36 @@ +;; -------------------------------------------------------------------------- +;; +;; Copyright 1996-2009 The NASM Authors - All Rights Reserved +;; See the file AUTHORS included with the NASM distribution for +;; the specific copyright holders. +;; +;; Redistribution and use in source and binary forms, with or without +;; modification, are permitted provided that the following +;; conditions are met: +;; +;; * Redistributions of source code must retain the above copyright +;; notice, this list of conditions and the following disclaimer. +;; * Redistributions in binary form must reproduce the above +;; copyright notice, this list of conditions and the following +;; disclaimer in the documentation and/or other materials provided +;; with the distribution. +;; +;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +;; CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +;; INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +;; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +;; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;; NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +;; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +;; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +;; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +;; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;; +;; -------------------------------------------------------------------------- + OUT: coff win32 win64 %define __SECT__ [section .text] %macro __NASM_CDecl__ 1 diff --git a/output/outdbg.c b/output/outdbg.c index 1646b4b7..1ee16ea2 100644 --- a/output/outdbg.c +++ b/output/outdbg.c @@ -1,10 +1,39 @@ -/* outdbg.c output routines for the Netwide Assembler to produce - * a debugging trace +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * ----------------------------------------------------------------------- */ + +/* + * outdbg.c output routines for the Netwide Assembler to produce + * a debugging trace */ #include "compiler.h" @@ -17,7 +46,7 @@ #include "nasm.h" #include "nasmlib.h" -#include "outform.h" +#include "output/outform.h" #ifdef OF_DBG @@ -40,8 +69,6 @@ static void dbg_init(FILE * fp, efunc errfunc, ldfunc ldef, evalfunc eval) dbgsect = NULL; (void)ldef; fprintf(fp, "NASM Output format debug dump\n"); - of_dbg.current_dfmt->init(&of_dbg, 0, fp, errfunc); - } static void dbg_cleanup(int debuginfo) @@ -93,10 +120,10 @@ static int32_t dbg_section_names(char *name, int pass, int *bits) return seg; } -static void dbg_deflabel(char *name, int32_t segment, int32_t offset, +static void dbg_deflabel(char *name, int32_t segment, int64_t offset, int is_global, char *special) { - fprintf(dbgf, "deflabel %s := %08lx:%08lx %s (%d)%s%s\n", + fprintf(dbgf, "deflabel %s := %08"PRIx32":%016"PRIx64" %s (%d)%s%s\n", name, segment, offset, is_global == 2 ? "common" : is_global ? "global" : "local", is_global, special ? ": " : "", special); @@ -109,7 +136,7 @@ static void dbg_out(int32_t segto, const void *data, int32_t ldata; int id; - fprintf(dbgf, "out to %lx, len = %ld: ", segto, size); + fprintf(dbgf, "out to %"PRIx32", len = %"PRIu64": ", segto, size); switch (type) { case OUT_RESERVE: @@ -126,17 +153,22 @@ static void dbg_out(int32_t segto, const void *data, break; case OUT_ADDRESS: ldata = *(int64_t *)data; - fprintf(dbgf, "addr %08lx (seg %08lx, wrt %08lx)\n", ldata, + fprintf(dbgf, "addr %08"PRIx32" (seg %08"PRIx32", wrt %08"PRIx32")\n", ldata, segment, wrt); break; case OUT_REL2ADR: - fprintf(dbgf, "rel2adr %04x (seg %08lx)\n", (int)*(int16_t *)data, - segment); + fprintf(dbgf, "rel2adr %04"PRIx16" (seg %08"PRIx32")\n", + (uint16_t)*(int64_t *)data, segment); break; case OUT_REL4ADR: - fprintf(dbgf, "rel4adr %08lx (seg %08lx)\n", *(int32_t *)data, + fprintf(dbgf, "rel4adr %08"PRIx32" (seg %08"PRIx32")\n", + (uint32_t)*(int64_t *)data, segment); break; + case OUT_REL8ADR: + fprintf(dbgf, "rel8adr %016"PRIx64" (seg %08"PRIx32")\n", + (uint64_t)*(int64_t *)data, segment); + break; default: fprintf(dbgf, "unknown\n"); break; @@ -184,12 +216,13 @@ static void dbgdbg_cleanup(void) static void dbgdbg_linnum(const char *lnfname, int32_t lineno, int32_t segto) { - fprintf(dbgf, "dbglinenum %s(%ld) := %08lx\n", lnfname, lineno, segto); + fprintf(dbgf, "dbglinenum %s(%"PRId32") := %08"PRIx32"\n", + lnfname, lineno, segto); } static void dbgdbg_deflabel(char *name, int32_t segment, - int32_t offset, int is_global, char *special) + int64_t offset, int is_global, char *special) { - fprintf(dbgf, "dbglabel %s := %08lx:%08lx %s (%d)%s%s\n", + fprintf(dbgf, "dbglabel %s := %08"PRIx32":%016"PRIx64" %s (%d)%s%s\n", name, segment, offset, is_global == 2 ? "common" : is_global ? "global" : "local", @@ -206,7 +239,7 @@ static void dbgdbg_output(int output_type, void *param) } static void dbgdbg_typevalue(int32_t type) { - fprintf(dbgf, "new type: %s(%lX)\n", + fprintf(dbgf, "new type: %s(%"PRIX32")\n", types[TYM_TYPE(type) >> 3], TYM_ELEMENTS(type)); } static struct dfmt debug_debug_form = { @@ -226,12 +259,13 @@ static struct dfmt *debug_debug_arr[3] = { &null_debug_form, NULL }; + struct ofmt of_dbg = { "Trace of all info passed to output stage", "dbg", - NULL, + OFMT_TEXT, debug_debug_arr, - &null_debug_form, + &debug_debug_form, NULL, dbg_init, dbg_set_info, diff --git a/output/outelf.mac b/output/outelf.mac index bd6f82e4..d32520fa 100644 --- a/output/outelf.mac +++ b/output/outelf.mac @@ -1,3 +1,36 @@ +;; -------------------------------------------------------------------------- +;; +;; Copyright 1996-2009 The NASM Authors - All Rights Reserved +;; See the file AUTHORS included with the NASM distribution for +;; the specific copyright holders. +;; +;; Redistribution and use in source and binary forms, with or without +;; modification, are permitted provided that the following +;; conditions are met: +;; +;; * Redistributions of source code must retain the above copyright +;; notice, this list of conditions and the following disclaimer. +;; * Redistributions in binary form must reproduce the above +;; copyright notice, this list of conditions and the following +;; disclaimer in the documentation and/or other materials provided +;; with the distribution. +;; +;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +;; CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +;; INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +;; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +;; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;; NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +;; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +;; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +;; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +;; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;; +;; -------------------------------------------------------------------------- + OUT: elf elf32 elf64 %define __SECT__ [section .text] %macro __NASM_CDecl__ 1 diff --git a/output/outelf32.c b/output/outelf32.c index bff264a3..7159a1f1 100644 --- a/output/outelf32.c +++ b/output/outelf32.c @@ -1,10 +1,39 @@ -/* outelf.c output routines for the Netwide Assembler to produce - * ELF32 (i386 of course) object file format +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * ----------------------------------------------------------------------- */ + +/* + * outelf32.c output routines for the Netwide Assembler to produce + * ELF32 (i386 of course) object file format */ #include "compiler.h" @@ -20,31 +49,19 @@ #include "saa.h" #include "raa.h" #include "stdscan.h" -#include "outform.h" +#include "output/outform.h" +#include "output/outlib.h" +#include "rbtree.h" + +#include "output/elf32.h" +#include "output/dwarf.h" +#include "output/outelf.h" #ifdef OF_ELF32 /* * Relocation types. */ -enum reloc_type { - R_386_32 = 1, /* ordinary absolute relocation */ - R_386_PC32 = 2, /* PC-relative relocation */ - R_386_GOT32 = 3, /* an offset into GOT */ - R_386_PLT32 = 4, /* a PC-relative offset into PLT */ - R_386_COPY = 5, /* ??? */ - R_386_GLOB_DAT = 6, /* ??? */ - R_386_JUMP_SLOT = 7, /* ??? */ - R_386_RELATIVE = 8, /* ??? */ - R_386_GOTOFF = 9, /* an offset from GOT base */ - R_386_GOTPC = 10, /* a PC-relative offset _to_ GOT */ - /* These are GNU extensions, but useful */ - R_386_16 = 20, /* A 16-bit absolute relocation */ - R_386_PC16 = 21, /* A 16-bit PC-relative relocation */ - R_386_8 = 22, /* An 8-bit absolute relocation */ - R_386_PC8 = 23 /* An 8-bit PC-relative relocation */ -}; - struct Reloc { struct Reloc *next; int32_t address; /* relative to _start_ of section */ @@ -53,37 +70,29 @@ struct Reloc { }; struct Symbol { - int32_t strpos; /* string table position of name */ - int32_t section; /* section ID of the symbol */ - int type; /* symbol type */ - int other; /* symbol visibility */ - int32_t value; /* address, or COMMON variable align */ - int32_t size; /* size of symbol */ - int32_t globnum; /* symbol table offset if global */ - struct Symbol *next; /* list of globals in each section */ - struct Symbol *nextfwd; /* list of unresolved-size symbols */ - char *name; /* used temporarily if in above list */ + struct rbtree symv; /* symbol value and symbol rbtree */ + int32_t strpos; /* string table position of name */ + int32_t section; /* section ID of the symbol */ + int type; /* symbol type */ + int other; /* symbol visibility */ + int32_t size; /* size of symbol */ + int32_t globnum; /* symbol table offset if global */ + struct Symbol *nextfwd; /* list of unresolved-size symbols */ + char *name; /* used temporarily if in above list */ }; -#define SHT_PROGBITS 1 -#define SHT_NOBITS 8 - -#define SHF_WRITE 1 -#define SHF_ALLOC 2 -#define SHF_EXECINSTR 4 - struct Section { struct SAA *data; uint32_t len, size, nrelocs; int32_t index; int type; /* SHT_PROGBITS or SHT_NOBITS */ - int align; /* alignment: power of two */ - uint32_t flags; /* section flags */ + uint32_t align; /* alignment: power of two */ + uint32_t flags; /* section flags */ char *name; struct SAA *rel; int32_t rellen; struct Reloc *head, **tail; - struct Symbol *gsyms; /* global symbols in section */ + struct rbtree *gsyms; /* global symbols in section */ }; #define SECT_DELTA 32 @@ -95,7 +104,7 @@ static char *shstrtab; static int shstrtablen, shstrtabsize; static struct SAA *syms; -static uint32_t nlocals, nglobs; +static uint32_t nlocals, nglobs, ndebugs; /* Symbol counts */ static int32_t def_seg; @@ -118,60 +127,8 @@ static uint8_t elf_abiver = 0; /* Current ABI version */ extern struct ofmt of_elf32; extern struct ofmt of_elf; -#define SHN_ABS 0xFFF1 -#define SHN_COMMON 0xFFF2 -#define SHN_UNDEF 0 - -#define SYM_GLOBAL 0x10 - -#define SHT_RELA 4 /* Relocation entries with addends */ - -#define STT_NOTYPE 0 /* Symbol type is unspecified */ -#define STT_OBJECT 1 /* Symbol is a data object */ -#define STT_FUNC 2 /* Symbol is a code object */ -#define STT_SECTION 3 /* Symbol associated with a section */ -#define STT_FILE 4 /* Symbol's name is file name */ -#define STT_COMMON 5 /* Symbol is a common data object */ -#define STT_TLS 6 /* Symbol is thread-local data object*/ -#define STT_NUM 7 /* Number of defined types. */ - -#define STV_DEFAULT 0 -#define STV_INTERNAL 1 -#define STV_HIDDEN 2 -#define STV_PROTECTED 3 - -#define GLOBAL_TEMP_BASE 1048576 /* bigger than any reasonable sym id */ - -#define SEG_ALIGN 16 /* alignment of sections in file */ -#define SEG_ALIGN_1 (SEG_ALIGN-1) - -/* Definitions in lieu of dwarf.h */ -#define DW_TAG_compile_unit 0x11 -#define DW_TAG_subprogram 0x2e -#define DW_AT_name 0x03 -#define DW_AT_stmt_list 0x10 -#define DW_AT_low_pc 0x11 -#define DW_AT_high_pc 0x12 -#define DW_AT_language 0x13 -#define DW_AT_producer 0x25 -#define DW_AT_frame_base 0x40 -#define DW_FORM_addr 0x01 -#define DW_FORM_data2 0x05 -#define DW_FORM_data4 0x06 -#define DW_FORM_string 0x08 -#define DW_LNS_extended_op 0 -#define DW_LNS_advance_pc 2 -#define DW_LNS_advance_line 3 -#define DW_LNS_set_file 4 -#define DW_LNE_end_sequence 1 -#define DW_LNE_set_address 2 -#define DW_LNE_define_file 3 -#define DW_LANG_Mips_Assembler 0x8001 - #define SOC(ln,aa) ln - line_base + (line_range * aa) + opcode_base -static const char align_str[SEG_ALIGN] = ""; /* ANSI will pad this with 0s */ - static struct ELF_SECTDATA { void *data; int32_t len; @@ -190,14 +147,6 @@ static struct SAA *elf_build_symtab(int32_t *, int32_t *); static struct SAA *elf_build_reltab(int32_t *, struct Reloc *); static void add_sectname(char *, char *); -/* this stuff is needed for the stabs debugging format */ -#define N_SO 0x64 /* ID for main source file */ -#define N_SOL 0x84 /* ID for sub-source file */ -#define N_BINCL 0x82 -#define N_EINCL 0xA2 -#define N_SLINE 0x44 -#define TY_STABSSYMLIN 0x40 /* ouch */ - struct stabentry { uint32_t n_strx; uint8_t n_type; @@ -242,7 +191,6 @@ static int debug_immcall = 0; static struct linelist *stabslines = 0; static int numlinestabs = 0; static char *stabs_filename = 0; -static int symtabsection; static uint8_t *stabbuf = 0, *stabstrbuf = 0, *stabrelbuf = 0; static int stablen, stabstrlen, stabrellen; @@ -262,40 +210,36 @@ static struct dfmt df_stabs; static struct Symbol *lastsym; /* common debugging routines */ -void debug32_typevalue(int32_t); -void debug32_init(struct ofmt *, void *, FILE *, efunc); -void debug32_deflabel(char *, int32_t, int64_t, int, char *); -void debug32_directive(const char *, const char *); +static void debug32_typevalue(int32_t); +static void debug32_deflabel(char *, int32_t, int64_t, int, char *); +static void debug32_directive(const char *, const char *); /* stabs debugging routines */ -void stabs32_linenum(const char *filename, int32_t linenumber, int32_t); -void stabs32_output(int, void *); -void stabs32_generate(void); -void stabs32_cleanup(void); +static void stabs32_linenum(const char *filename, int32_t linenumber, int32_t); +static void stabs32_output(int, void *); +static void stabs32_generate(void); +static void stabs32_cleanup(void); /* dwarf debugging routines */ -void dwarf32_linenum(const char *filename, int32_t linenumber, int32_t); -void dwarf32_output(int, void *); -void dwarf32_generate(void); -void dwarf32_cleanup(void); -void dwarf32_findfile(const char *); -void dwarf32_findsect(const int); -void saa_wleb128u(struct SAA *, int); -void saa_wleb128s(struct SAA *, int); +static void dwarf32_init(struct ofmt *, void *, FILE *, efunc); +static void dwarf32_linenum(const char *filename, int32_t linenumber, int32_t); +static void dwarf32_output(int, void *); +static void dwarf32_generate(void); +static void dwarf32_cleanup(void); +static void dwarf32_findfile(const char *); +static void dwarf32_findsect(const int); /* - * Special section numbers which are used to define ELF special - * symbols, which can be used with WRT to provide PIC relocation - * types. + * Special NASM section numbers which are used to define ELF special + * symbols, which can be used with WRT to provide PIC and TLS + * relocation types. */ static int32_t elf_gotpc_sect, elf_gotoff_sect; static int32_t elf_got_sect, elf_plt_sect; -static int32_t elf_sym_sect; +static int32_t elf_sym_sect, elf_tlsie_sect; static void elf_init(FILE * fp, efunc errfunc, ldfunc ldef, evalfunc eval) { - if (of_elf.current_dfmt != &null_debug_form) - of_elf32.current_dfmt = of_elf.current_dfmt; elffp = fp; error = errfunc; evaluate = eval; @@ -303,7 +247,7 @@ static void elf_init(FILE * fp, efunc errfunc, ldfunc ldef, evalfunc eval) sects = NULL; nsects = sectlen = 0; syms = saa_init((int32_t)sizeof(struct Symbol)); - nlocals = nglobs = 0; + nlocals = nglobs = ndebugs = 0; bsym = raa_init(); strs = saa_init(1L); saa_wbytes(strs, "\0", 1L); @@ -330,10 +274,20 @@ static void elf_init(FILE * fp, efunc errfunc, ldfunc ldef, evalfunc eval) elf_sym_sect = seg_alloc(); ldef("..sym", elf_sym_sect + 1, 0L, NULL, false, false, &of_elf32, error); + elf_tlsie_sect = seg_alloc(); + ldef("..tlsie", elf_tlsie_sect + 1, 0L, NULL, false, false, &of_elf32, + error); def_seg = seg_alloc(); } +static void elf_init_hack(FILE * fp, efunc errfunc, ldfunc ldef, + evalfunc eval) +{ + of_elf32.current_dfmt = of_elf.current_dfmt; /* Sync debugging format */ + elf_init(fp, errfunc, ldef, eval); +} + static void elf_cleanup(int debuginfo) { struct Reloc *r; @@ -398,18 +352,19 @@ static int elf_make_section(char *name, int type, int flags, int align) s->gsyms = NULL; if (nsects >= sectlen) - sects = - nasm_realloc(sects, (sectlen += SECT_DELTA) * sizeof(*sects)); + sects = nasm_realloc(sects, (sectlen += SECT_DELTA) * sizeof(*sects)); sects[nsects++] = s; return nsects - 1; } + static int32_t elf_section_names(char *name, int pass, int *bits) { char *p; - unsigned flags_and, flags_or; - int type, align, i; + uint32_t flags, flags_and, flags_or; + uint32_t align; + int type, i; /* * Default is 32 bits. @@ -461,6 +416,9 @@ static int32_t elf_section_names(char *name, int pass, int *bits) } else if (!nasm_stricmp(q, "write")) { flags_and |= SHF_WRITE; flags_or |= SHF_WRITE; + } else if (!nasm_stricmp(q, "tls")) { + flags_and |= SHF_TLS; + flags_or |= SHF_TLS; } else if (!nasm_stricmp(q, "nowrite")) { flags_and |= SHF_WRITE; flags_or &= ~SHF_WRITE; @@ -468,12 +426,15 @@ static int32_t elf_section_names(char *name, int pass, int *bits) type = SHT_PROGBITS; } else if (!nasm_stricmp(q, "nobits")) { type = SHT_NOBITS; - } + } else if (pass == 1) { + error(ERR_WARNING, "Unknown section attribute '%s' ignored on" + " declaration of section `%s'", q, name); + } } - if (!strcmp(name, ".comment") || - !strcmp(name, ".shstrtab") || - !strcmp(name, ".symtab") || !strcmp(name, ".strtab")) { + if (!strcmp(name, ".shstrtab") || + !strcmp(name, ".symtab") || + !strcmp(name, ".strtab")) { error(ERR_NONFATAL, "attempt to redefine reserved section" "name `%s'", name); return NO_SEG; @@ -483,28 +444,22 @@ static int32_t elf_section_names(char *name, int pass, int *bits) if (!strcmp(name, sects[i]->name)) break; if (i == nsects) { - if (!strcmp(name, ".text")) - i = elf_make_section(name, SHT_PROGBITS, - SHF_ALLOC | SHF_EXECINSTR, 16); - else if (!strcmp(name, ".rodata")) - i = elf_make_section(name, SHT_PROGBITS, SHF_ALLOC, 4); - else if (!strcmp(name, ".data")) - i = elf_make_section(name, SHT_PROGBITS, - SHF_ALLOC | SHF_WRITE, 4); - else if (!strcmp(name, ".bss")) - i = elf_make_section(name, SHT_NOBITS, - SHF_ALLOC | SHF_WRITE, 4); - else - i = elf_make_section(name, SHT_PROGBITS, SHF_ALLOC, 1); - if (type) - sects[i]->type = type; - if (align) - sects[i]->align = align; - sects[i]->flags &= ~flags_and; - sects[i]->flags |= flags_or; + const struct elf_known_section *ks = elf_known_sections; + + while (ks->name) { + if (!strcmp(name, ks->name)) + break; + ks++; + } + + type = type ? type : ks->type; + align = align ? align : ks->align; + flags = (ks->flags & ~flags_and) | flags_or; + + i = elf_make_section(name, type, flags, align); } else if (pass == 1) { if ((type && sects[i]->type != type) - || (align && sects[i]->align != align) + || (align && sects[i]->align != align) || (flags_and && ((sects[i]->flags & flags_and) != flags_or))) error(ERR_WARNING, "section attributes ignored on" " redeclaration of section `%s'", name); @@ -533,7 +488,7 @@ static void elf_deflabel(char *name, int32_t segment, int64_t offset, */ if (strcmp(name, "..gotpc") && strcmp(name, "..gotoff") && strcmp(name, "..got") && strcmp(name, "..plt") && - strcmp(name, "..sym")) + strcmp(name, "..sym") && strcmp(name, "..tlsie")) error(ERR_NONFATAL, "unrecognised special symbol `%s'", name); return; } @@ -581,6 +536,8 @@ static void elf_deflabel(char *name, int32_t segment, int64_t offset, lastsym = sym = saa_wstruct(syms); + memset(&sym->symv, 0, sizeof(struct rbtree)); + sym->strpos = pos; sym->type = is_global ? SYM_GLOBAL : 0; sym->other = STV_DEFAULT; @@ -607,7 +564,7 @@ static void elf_deflabel(char *name, int32_t segment, int64_t offset, if (is_global == 2) { sym->size = offset; - sym->value = 0; + sym->symv.key = 0; sym->section = SHN_COMMON; /* * We have a common variable. Check the special text to see @@ -616,17 +573,18 @@ static void elf_deflabel(char *name, int32_t segment, int64_t offset, */ if (special) { bool err; - sym->value = readnum(special, &err); + sym->symv.key = readnum(special, &err); if (err) error(ERR_NONFATAL, "alignment constraint `%s' is not a" " valid number", special); - else if ((sym->value | (sym->value - 1)) != 2 * sym->value - 1) + else if ((sym->symv.key | (sym->symv.key - 1)) + != 2 * sym->symv.key - 1) error(ERR_NONFATAL, "alignment constraint `%s' is not a" " power of two", special); } special_used = true; } else - sym->value = (sym->section == SHN_UNDEF ? 0 : offset); + sym->symv.key = (sym->section == SHN_UNDEF ? 0 : offset); if (sym->type == SYM_GLOBAL) { /* @@ -643,16 +601,14 @@ static void elf_deflabel(char *name, int32_t segment, int64_t offset, bsym = raa_write(bsym, segment, nglobs); } else if (sym->section != SHN_ABS) { /* - * This is a global symbol; so we must add it to the linked - * list of global symbols in its section. We'll push it on - * the beginning of the list, because it doesn't matter - * much which end we put it on and it's easier like this. + * This is a global symbol; so we must add it to the rbtree + * of global symbols in its section. * * In addition, we check the special text for symbol * type and size information. */ - sym->next = sects[sym->section - 1]->gsyms; - sects[sym->section - 1]->gsyms = sym; + sects[sym->section-1]->gsyms = + rb_insert(sects[sym->section-1]->gsyms, &sym->symv); if (special) { int n = strcspn(special, " \t"); @@ -718,6 +674,13 @@ static void elf_deflabel(char *name, int32_t segment, int64_t offset, } special_used = true; } + /* + * If TLS segment, mark symbol accordingly. + */ + if (sects[sym->section - 1]->flags & SHF_TLS) { + sym->type &= 0xf0; + sym->type |= STT_TLS; + } } sym->globnum = nglobs; nglobs++; @@ -776,12 +739,13 @@ static void elf_add_reloc(struct Section *sect, int32_t segment, int type) * isn't even necessarily sorted. */ static int32_t elf_add_gsym_reloc(struct Section *sect, - int32_t segment, int32_t offset, + int32_t segment, uint32_t offset, int type, bool exact) { struct Reloc *r; struct Section *s; - struct Symbol *sym, *sm; + struct Symbol *sym; + struct rbtree *srb; int i; /* @@ -806,27 +770,13 @@ static int32_t elf_add_gsym_reloc(struct Section *sect, return offset; } - if (exact) { - /* - * Find a symbol pointing _exactly_ at this one. - */ - for (sym = s->gsyms; sym; sym = sym->next) - if (sym->value == offset) - break; - } else { - /* - * Find the nearest symbol below this one. - */ - sym = NULL; - for (sm = s->gsyms; sm; sm = sm->next) - if (sm->value <= offset && (!sym || sm->value > sym->value)) - sym = sm; - } - if (!sym && exact) { - error(ERR_NONFATAL, "unable to find a suitable global symbol" - " for this reference"); - return 0; + srb = rb_search(s->gsyms, offset); + if (!srb || (exact && srb->key != offset)) { + error(ERR_NONFATAL, "unable to find a suitable global symbol" + " for this reference"); + return 0; } + sym = container_of(srb, struct Symbol, symv); r = *sect->tail = nasm_malloc(sizeof(struct Reloc)); sect->tail = &r->next; @@ -838,7 +788,7 @@ static int32_t elf_add_gsym_reloc(struct Section *sect, sect->nrelocs++; - return offset - sym->value; + return offset - sym->symv.key; } static void elf_out(int32_t segto, const void *data, @@ -889,11 +839,7 @@ static void elf_out(int32_t segto, const void *data, if (s->type == SHT_NOBITS && type != OUT_RESERVE) { error(ERR_WARNING, "attempt to initialize memory in" " BSS section `%s': ignored", s->name); - if (type == OUT_REL2ADR) - size = 2; - else if (type == OUT_REL4ADR) - size = 4; - s->len += size; + s->len += realsize(type, size); return; } @@ -933,6 +879,9 @@ static void elf_out(int32_t segto, const void *data, elf_add_reloc(s, segment, R_386_GOTPC); } else if (wrt == elf_gotoff_sect + 1) { elf_add_reloc(s, segment, R_386_GOTOFF); + } else if (wrt == elf_tlsie_sect + 1) { + addr = elf_add_gsym_reloc(s, segment, addr, + R_386_TLS_IE, true); } else if (wrt == elf_got_sect + 1) { addr = elf_add_gsym_reloc(s, segment, addr, R_386_GOT32, true); @@ -1018,10 +967,7 @@ static void elf_out(int32_t segto, const void *data, static void elf_write(void) { int align; - int scount; char *p; - int commlen; - char comment[64]; int i; struct SAA *symtab; @@ -1029,18 +975,16 @@ static void elf_write(void) /* * Work out how many sections we will have. We have SHN_UNDEF, - * then the flexible user sections, then the four fixed - * sections `.comment', `.shstrtab', `.symtab' and `.strtab', - * then optionally relocation sections for the user sections. + * then the flexible user sections, then the fixed sections + * `.shstrtab', `.symtab' and `.strtab', then optionally + * relocation sections for the user sections. */ + nsections = sec_numspecial + 1; if (of_elf32.current_dfmt == &df_stabs) - nsections = 8; + nsections += 3; else if (of_elf32.current_dfmt == &df_dwarf) - nsections = 15; - else - nsections = 5; /* SHN_UNDEF and the fixed ones */ + nsections += 10; - add_sectname("", ".comment"); add_sectname("", ".shstrtab"); add_sectname("", ".symtab"); add_sectname("", ".strtab"); @@ -1057,16 +1001,10 @@ static void elf_write(void) add_sectname("", ".stab"); add_sectname("", ".stabstr"); add_sectname(".rel", ".stab"); - } - - else if (of_elf32.current_dfmt == &df_dwarf) { + } else if (of_elf32.current_dfmt == &df_dwarf) { /* the dwarf debug standard specifies the following ten sections, not all of which are currently implemented, although all of them are defined. */ - #define debug_aranges (int32_t) (nsections-10) - #define debug_info (int32_t) (nsections-7) - #define debug_abbrev (int32_t) (nsections-5) - #define debug_line (int32_t) (nsections-4) add_sectname("", ".debug_aranges"); add_sectname(".rela", ".debug_aranges"); add_sectname("", ".debug_pubnames"); @@ -1080,34 +1018,27 @@ static void elf_write(void) } /* - * Do the comment. - */ - *comment = '\0'; - commlen = - 2 + sprintf(comment + 1, "The Netwide Assembler %s", NASM_VER); - - /* * Output the ELF header. */ fwrite("\177ELF\1\1\1", 7, 1, elffp); fputc(elf_osabi, elffp); fputc(elf_abiver, elffp); - fwrite("\0\0\0\0\0\0\0", 7, 1, elffp); + fwritezero(7, elffp); fwriteint16_t(1, elffp); /* ET_REL relocatable file */ fwriteint16_t(3, elffp); /* EM_386 processor ID */ fwriteint32_t(1L, elffp); /* EV_CURRENT file format version */ fwriteint32_t(0L, elffp); /* no entry point */ fwriteint32_t(0L, elffp); /* no program header table */ fwriteint32_t(0x40L, elffp); /* section headers straight after - * ELF header plus alignment */ + * ELF header plus alignment */ fwriteint32_t(0L, elffp); /* 386 defines no special flags */ fwriteint16_t(0x34, elffp); /* size of ELF header */ fwriteint16_t(0, elffp); /* no program header table, again */ fwriteint16_t(0, elffp); /* still no program header table */ fwriteint16_t(0x28, elffp); /* size of section header */ fwriteint16_t(nsections, elffp); /* number of sections */ - fwriteint16_t(nsects + 2, elffp); /* string table section index for - * section header table */ + fwriteint16_t(sec_shstrtab, elffp); /* string table section index for + * section header table */ fwriteint32_t(0L, elffp); /* align to 0x40 bytes */ fwriteint32_t(0L, elffp); fwriteint32_t(0L, elffp); @@ -1131,33 +1062,43 @@ static void elf_write(void) elf_nsect = 0; elf_sects = nasm_malloc(sizeof(*elf_sects) * nsections); - elf_section_header(0, 0, 0, NULL, false, 0L, 0, 0, 0, 0); /* SHN_UNDEF */ - scount = 1; /* needed for the stabs debugging to track the symtable section */ + /* SHN_UNDEF */ + elf_section_header(0, SHT_NULL, 0, NULL, false, 0, SHN_UNDEF, 0, 0, 0); p = shstrtab + 1; + + /* The normal sections */ for (i = 0; i < nsects; i++) { elf_section_header(p - shstrtab, sects[i]->type, sects[i]->flags, (sects[i]->type == SHT_PROGBITS ? sects[i]->data : NULL), true, sects[i]->len, 0, 0, sects[i]->align, 0); p += strlen(p) + 1; - scount++; /* dito */ } - elf_section_header(p - shstrtab, 1, 0, comment, false, (int32_t)commlen, 0, 0, 1, 0); /* .comment */ - scount++; /* dito */ + + /* .shstrtab */ + elf_section_header(p - shstrtab, SHT_STRTAB, 0, shstrtab, false, + shstrtablen, 0, 0, 1, 0); p += strlen(p) + 1; - elf_section_header(p - shstrtab, 3, 0, shstrtab, false, (int32_t)shstrtablen, 0, 0, 1, 0); /* .shstrtab */ - scount++; /* dito */ + + /* .symtab */ + elf_section_header(p - shstrtab, SHT_SYMTAB, 0, symtab, true, + symtablen, sec_strtab, symtablocal, 4, 16); p += strlen(p) + 1; - elf_section_header(p - shstrtab, 2, 0, symtab, true, symtablen, nsects + 4, symtablocal, 4, 16); /* .symtab */ - symtabsection = scount; /* now we got the symtab section index in the ELF file */ + + /* .strtab */ + elf_section_header(p - shstrtab, SHT_STRTAB, 0, strs, true, + strslen, 0, 0, 1, 0); p += strlen(p) + 1; - elf_section_header(p - shstrtab, 3, 0, strs, true, strslen, 0, 0, 1, 0); /* .strtab */ + + /* The relocation sections */ for (i = 0; i < nsects; i++) if (sects[i]->head) { + elf_section_header(p - shstrtab, SHT_REL, 0, sects[i]->rel, true, + sects[i]->rellen, sec_symtab, i + 1, 4, 8); p += strlen(p) + 1; - elf_section_header(p - shstrtab, 9, 0, sects[i]->rel, true, - sects[i]->rellen, nsects + 3, i + 1, 4, 8); + } + if (of_elf32.current_dfmt == &df_stabs) { /* for debugging information, create the last three sections which are the .stab , .stabstr and .rel.stab sections respectively */ @@ -1165,61 +1106,69 @@ static void elf_write(void) /* this function call creates the stab sections in memory */ stabs32_generate(); - if ((stabbuf) && (stabstrbuf) && (stabrelbuf)) { + if (stabbuf && stabstrbuf && stabrelbuf) { + elf_section_header(p - shstrtab, SHT_PROGBITS, 0, stabbuf, false, + stablen, sec_stabstr, 0, 4, 12); p += strlen(p) + 1; - elf_section_header(p - shstrtab, 1, 0, stabbuf, false, stablen, - nsections - 2, 0, 4, 12); - p += strlen(p) + 1; - elf_section_header(p - shstrtab, 3, 0, stabstrbuf, false, + elf_section_header(p - shstrtab, SHT_STRTAB, 0, stabstrbuf, false, stabstrlen, 0, 0, 4, 0); - p += strlen(p) + 1; + /* link -> symtable info -> section to refer to */ - elf_section_header(p - shstrtab, 9, 0, stabrelbuf, false, - stabrellen, symtabsection, nsections - 3, 4, - 8); + elf_section_header(p - shstrtab, SHT_REL, 0, stabrelbuf, false, + stabrellen, sec_symtab, sec_stab, 4, 8); + p += strlen(p) + 1; } - } - else if (of_elf32.current_dfmt == &df_dwarf) { + } else if (of_elf32.current_dfmt == &df_dwarf) { /* for dwarf debugging information, create the ten dwarf sections */ /* this function call creates the dwarf sections in memory */ - if (dwarf_fsect) dwarf32_generate(); + if (dwarf_fsect) + dwarf32_generate(); - p += strlen(p) + 1; elf_section_header(p - shstrtab, SHT_PROGBITS, 0, arangesbuf, false, arangeslen, 0, 0, 1, 0); p += strlen(p) + 1; + elf_section_header(p - shstrtab, SHT_RELA, 0, arangesrelbuf, false, - arangesrellen, symtabsection, debug_aranges, 1, 12); + arangesrellen, sec_symtab, sec_debug_aranges, + 1, 12); p += strlen(p) + 1; - elf_section_header(p - shstrtab, SHT_PROGBITS, 0, pubnamesbuf, false, - pubnameslen, 0, 0, 1, 0); + + elf_section_header(p - shstrtab, SHT_PROGBITS, 0, pubnamesbuf, + false, pubnameslen, 0, 0, 1, 0); p += strlen(p) + 1; + elf_section_header(p - shstrtab, SHT_PROGBITS, 0, infobuf, false, infolen, 0, 0, 1, 0); p += strlen(p) + 1; + elf_section_header(p - shstrtab, SHT_RELA, 0, inforelbuf, false, - inforellen, symtabsection, debug_info, 1, 12); + inforellen, sec_symtab, sec_debug_info, 1, 12); p += strlen(p) + 1; + elf_section_header(p - shstrtab, SHT_PROGBITS, 0, abbrevbuf, false, abbrevlen, 0, 0, 1, 0); p += strlen(p) + 1; + elf_section_header(p - shstrtab, SHT_PROGBITS, 0, linebuf, false, linelen, 0, 0, 1, 0); p += strlen(p) + 1; + elf_section_header(p - shstrtab, SHT_RELA, 0, linerelbuf, false, - linerellen, symtabsection, debug_line, 1, 12); + linerellen, sec_symtab, sec_debug_line, 1, 12); p += strlen(p) + 1; + elf_section_header(p - shstrtab, SHT_PROGBITS, 0, framebuf, false, framelen, 0, 0, 8, 0); p += strlen(p) + 1; + elf_section_header(p - shstrtab, SHT_PROGBITS, 0, locbuf, false, loclen, 0, 0, 1, 0); - + p += strlen(p) + 1; } - fwrite(align_str, align, 1, elffp); + fwritezero(align, elffp); /* * Now output the sections. @@ -1284,7 +1233,7 @@ static struct SAA *elf_build_symtab(int32_t *len, int32_t *local) continue; p = entry; WRITELONG(p, sym->strpos); - WRITELONG(p, sym->value); + WRITELONG(p, sym->symv.key); WRITELONG(p, sym->size); WRITECHAR(p, sym->type); /* type and binding */ WRITECHAR(p, sym->other); /* visibility */ @@ -1305,7 +1254,7 @@ static struct SAA *elf_build_symtab(int32_t *len, int32_t *local) WRITELONG(p, (uint32_t) 0); /* offset zero */ WRITELONG(p, (uint32_t) 0); /* size zero */ WRITESHORT(p, STT_SECTION); /* type, binding, and visibility */ - WRITESHORT(p, debug_info); /* section id */ + WRITESHORT(p, sec_debug_info); /* section id */ saa_wbytes(s, entry, 16L); *len += 16; (*local)++; @@ -1315,7 +1264,7 @@ static struct SAA *elf_build_symtab(int32_t *len, int32_t *local) WRITELONG(p, (uint32_t) 0); /* offset zero */ WRITELONG(p, (uint32_t) 0); /* size zero */ WRITESHORT(p, STT_SECTION); /* type, binding, and visibility */ - WRITESHORT(p, debug_abbrev); /* section id */ + WRITESHORT(p, sec_debug_abbrev); /* section id */ saa_wbytes(s, entry, 16L); *len += 16; (*local)++; @@ -1325,7 +1274,7 @@ static struct SAA *elf_build_symtab(int32_t *len, int32_t *local) WRITELONG(p, (uint32_t) 0); /* offset zero */ WRITELONG(p, (uint32_t) 0); /* size zero */ WRITESHORT(p, STT_SECTION); /* type, binding, and visibility */ - WRITESHORT(p, debug_line); /* section id */ + WRITESHORT(p, sec_debug_line); /* section id */ saa_wbytes(s, entry, 16L); *len += 16; (*local)++; @@ -1340,7 +1289,7 @@ static struct SAA *elf_build_symtab(int32_t *len, int32_t *local) continue; p = entry; WRITELONG(p, sym->strpos); - WRITELONG(p, sym->value); + WRITELONG(p, sym->symv.key); WRITELONG(p, sym->size); WRITECHAR(p, sym->type); /* type and binding */ WRITECHAR(p, sym->other); /* visibility */ @@ -1356,6 +1305,7 @@ static struct SAA *elf_build_reltab(int32_t *len, struct Reloc *r) { struct SAA *s; uint8_t *p, entry[8]; + int32_t global_offset; if (!r) return NULL; @@ -1363,15 +1313,22 @@ static struct SAA *elf_build_reltab(int32_t *len, struct Reloc *r) s = saa_init(1L); *len = 0; + /* + * How to onvert from a global placeholder to a real symbol index; + * the +2 refers to the two special entries, the null entry and + * the filename entry. + */ + global_offset = -GLOBAL_TEMP_BASE + nsects + nlocals + ndebugs + 2; + while (r) { int32_t sym = r->symbol; + /* + * Create a real symbol index; the +2 refers to the two special + * entries, the null entry and the filename entry. + */ if (sym >= GLOBAL_TEMP_BASE) - { - if (of_elf32.current_dfmt == &df_dwarf) - sym += -GLOBAL_TEMP_BASE + (nsects + 5) + nlocals; - else sym += -GLOBAL_TEMP_BASE + (nsects + 2) + nlocals; - } + sym += global_offset; p = entry; WRITELONG(p, r->address); @@ -1420,7 +1377,7 @@ static void elf_write_sections(void) saa_fpwrite(elf_sects[i].data, elffp); else fwrite(elf_sects[i].data, len, 1, elffp); - fwrite(align_str, align, 1, elffp); + fwritezero(align, elffp); } } @@ -1489,9 +1446,9 @@ static int elf_set_info(enum geninfo type, char **val) return 0; } static struct dfmt df_dwarf = { - "ELF32 (i386) dwarf debug format for Linux", + "ELF32 (i386) dwarf debug format for Linux/Unix", "dwarf", - debug32_init, + dwarf32_init, dwarf32_linenum, debug32_deflabel, debug32_directive, @@ -1500,9 +1457,9 @@ static struct dfmt df_dwarf = { dwarf32_cleanup }; static struct dfmt df_stabs = { - "ELF32 (i386) stabs debug format for Linux", + "ELF32 (i386) stabs debug format for Linux/Unix", "stabs", - debug32_init, + null_debug_init, stabs32_linenum, debug32_deflabel, debug32_directive, @@ -1511,14 +1468,14 @@ static struct dfmt df_stabs = { stabs32_cleanup }; -struct dfmt *elf32_debugs_arr[3] = { &df_stabs, &df_dwarf, NULL }; +struct dfmt *elf32_debugs_arr[3] = { &df_dwarf, &df_stabs, NULL }; struct ofmt of_elf32 = { "ELF32 (i386) object files (e.g. Linux)", "elf32", - NULL, + 0, elf32_debugs_arr, - &null_debug_form, + &df_stabs, elf_stdmac, elf_init, elf_set_info, @@ -1534,11 +1491,11 @@ struct ofmt of_elf32 = { struct ofmt of_elf = { "ELF (short name for ELF32) ", "elf", - NULL, + 0, elf32_debugs_arr, - &null_debug_form, + &df_stabs, elf_stdmac, - elf_init, + elf_init_hack, elf_set_info, elf_out, elf_deflabel, @@ -1550,15 +1507,8 @@ struct ofmt of_elf = { }; /* again, the stabs debugging stuff (code) */ -void debug32_init(struct ofmt *of, void *id, FILE * fp, efunc error) -{ - (void)of; - (void)id; - (void)fp; - (void)error; -} - -void stabs32_linenum(const char *filename, int32_t linenumber, int32_t segto) +static void stabs32_linenum(const char *filename, int32_t linenumber, + int32_t segto) { (void)segto; @@ -1581,7 +1531,7 @@ void stabs32_linenum(const char *filename, int32_t linenumber, int32_t segto) currentline = linenumber; } -void debug32_deflabel(char *name, int32_t segment, int64_t offset, int is_global, +static void debug32_deflabel(char *name, int32_t segment, int64_t offset, int is_global, char *special) { (void)name; @@ -1591,13 +1541,13 @@ void debug32_deflabel(char *name, int32_t segment, int64_t offset, int is_global (void)special; } -void debug32_directive(const char *directive, const char *params) +static void debug32_directive(const char *directive, const char *params) { (void)directive; (void)params; } -void debug32_typevalue(int32_t type) +static void debug32_typevalue(int32_t type) { int32_t stype, ssize; switch (TYM_TYPE(type)) { @@ -1660,7 +1610,7 @@ void debug32_typevalue(int32_t type) } } -void stabs32_output(int type, void *param) +static void stabs32_output(int type, void *param) { struct symlininfo *s; struct linelist *el; @@ -1700,7 +1650,7 @@ void stabs32_output(int type, void *param) /* for creating the .stab , .stabstr and .rel.stab sections in memory */ -void stabs32_generate(void) +static void stabs32_generate(void) { int i, numfiles, strsize, numstabs = 0, currfile, mainfileindex; uint8_t *sbuf, *ssbuf, *rbuf, *sptr, *rptr; @@ -1831,7 +1781,7 @@ void stabs32_generate(void) stabstrbuf = ssbuf; } -void stabs32_cleanup(void) +static void stabs32_cleanup(void) { struct linelist *ptr, *del; if (!stabslines) @@ -1849,10 +1799,21 @@ void stabs32_cleanup(void) if (stabstrbuf) nasm_free(stabstrbuf); } + /* dwarf routines */ +static void dwarf32_init(struct ofmt *of, void *id, FILE * fp, efunc error) +{ + (void)of; + (void)id; + (void)fp; + (void)error; + + ndebugs = 3; /* 3 debug symbols */ +} -void dwarf32_linenum(const char *filename, int32_t linenumber, int32_t segto) +static void dwarf32_linenum(const char *filename, int32_t linenumber, + int32_t segto) { (void)segto; dwarf32_findfile(filename); @@ -1861,7 +1822,7 @@ void dwarf32_linenum(const char *filename, int32_t linenumber, int32_t segto) } /* called from elf_out with type == TY_DEBUGSYMLIN */ -void dwarf32_output(int type, void *param) +static void dwarf32_output(int type, void *param) { int ln, aa, inx, maxln, soc; struct symlininfo *s; @@ -1924,9 +1885,8 @@ void dwarf32_output(int type, void *param) } -void dwarf32_generate(void) +static void dwarf32_generate(void) { - static const char nasm_signature[] = "NASM " NASM_VER; uint8_t *pbuf; int indx; struct linelist *ftentry; @@ -2161,7 +2121,7 @@ void dwarf32_generate(void) WRITELONG(pbuf,0); /* null ending offset */ } -void dwarf32_cleanup(void) +static void dwarf32_cleanup(void) { if (arangesbuf) nasm_free(arangesbuf); @@ -2184,7 +2144,7 @@ void dwarf32_cleanup(void) if (locbuf) nasm_free(locbuf); } -void dwarf32_findfile(const char * fname) +static void dwarf32_findfile(const char * fname) { int finx; struct linelist *match; @@ -2229,7 +2189,7 @@ void dwarf32_findfile(const char * fname) } } /* */ -void dwarf32_findsect(const int index) +static void dwarf32_findsect(const int index) { int sinx; struct sectlist *match; diff --git a/output/outelf64.c b/output/outelf64.c index f483393c..d0498947 100644 --- a/output/outelf64.c +++ b/output/outelf64.c @@ -1,11 +1,41 @@ -/* outelf64.c output routines for the Netwide Assembler to produce - * ELF64 (x86_64 of course) object file format +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * outelf64.c output routines for the Netwide Assembler to produce + * ELF64 (x86_64 of course) object file format */ + #include "compiler.h" #include <stdio.h> @@ -19,120 +49,51 @@ #include "saa.h" #include "raa.h" #include "stdscan.h" -#include "outform.h" - -/* Definitions in lieu of elf.h */ -#define SHT_NULL 0 /* Inactive section header */ -#define SHT_PROGBITS 1 /* Program defined content */ -#define SHT_RELA 4 /* Relocation entries with addends */ -#define SHT_NOBITS 8 /* Section requires no space in file */ -#define SHF_WRITE (1 << 0) /* Writable */ -#define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ -#define SHF_EXECINSTR (1 << 2) /* Executable */ -#define SHN_ABS 0xfff1 /* Associated symbol is absolute */ -#define SHN_COMMON 0xfff2 /* Associated symbol is common */ -#define R_X86_64_NONE 0 /* No reloc */ -#define R_X86_64_64 1 /* Direct 64 bit address */ -#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ -#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ -#define R_X86_64_PLT32 4 /* 32 bit PLT address */ -#define R_X86_64_GOTPCREL 9 /* 32 bit signed PC relative */ -#define R_X86_64_32 10 /* Direct 32 bit zero extended */ -#define R_X86_64_16 12 /* Direct 16 bit zero extended */ -#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ -#define R_X86_64_GOTTPOFF 22 /* 32 bit signed PC relative offset */ -#define ET_REL 1 /* Relocatable file */ -#define EM_X86_64 62 /* AMD x86-64 architecture */ -#define STT_NOTYPE 0 /* Symbol type is unspecified */ -#define STT_OBJECT 1 /* Symbol is a data object */ -#define STT_FUNC 2 /* Symbol is a code object */ -#define STT_SECTION 3 /* Symbol associated with a section */ -#define STT_FILE 4 /* Symbol's name is file name */ -#define STT_COMMON 5 /* Symbol is a common data object */ -#define STT_TLS 6 /* Symbol is thread-local data object*/ -#define STT_NUM 7 /* Number of defined types. */ - -/* Definitions in lieu of dwarf.h */ -#define DW_TAG_compile_unit 0x11 -#define DW_TAG_subprogram 0x2e -#define DW_AT_name 0x03 -#define DW_AT_stmt_list 0x10 -#define DW_AT_low_pc 0x11 -#define DW_AT_high_pc 0x12 -#define DW_AT_language 0x13 -#define DW_AT_producer 0x25 -#define DW_AT_frame_base 0x40 -#define DW_FORM_addr 0x01 -#define DW_FORM_data2 0x05 -#define DW_FORM_data4 0x06 -#define DW_FORM_string 0x08 -#define DW_LNS_extended_op 0 -#define DW_LNS_advance_pc 2 -#define DW_LNS_advance_line 3 -#define DW_LNS_set_file 4 -#define DW_LNE_end_sequence 1 -#define DW_LNE_set_address 2 -#define DW_LNE_define_file 3 -#define DW_LANG_Mips_Assembler 0x8001 - -#define SOC(ln,aa) ln - line_base + (line_range * aa) + opcode_base - -typedef uint32_t Elf64_Word; -typedef uint64_t Elf64_Xword; -typedef uint64_t Elf64_Addr; -typedef uint64_t Elf64_Off; -typedef struct -{ - Elf64_Word sh_name; /* Section name (string tbl index) */ - Elf64_Word sh_type; /* Section type */ - Elf64_Xword sh_flags; /* Section flags */ - Elf64_Addr sh_addr; /* Section virtual addr at execution */ - Elf64_Off sh_offset; /* Section file offset */ - Elf64_Xword sh_size; /* Section size in bytes */ - Elf64_Word sh_link; /* Link to another section */ - Elf64_Word sh_info; /* Additional section information */ - Elf64_Xword sh_addralign; /* Section alignment */ - Elf64_Xword sh_entsize; /* Entry size if section holds table */ -} Elf64_Shdr; +#include "output/outform.h" +#include "output/outlib.h" +#include "rbtree.h" +#include "output/elf64.h" +#include "output/dwarf.h" +#include "output/outelf.h" #ifdef OF_ELF64 +#define SOC(ln,aa) ln - line_base + (line_range * aa) + opcode_base struct Reloc { struct Reloc *next; - int64_t address; /* relative to _start_ of section */ - int64_t symbol; /* symbol index */ - int type; /* type of relocation */ + int64_t address; /* relative to _start_ of section */ + int64_t symbol; /* symbol index */ + int64_t offset; /* symbol addend */ + int type; /* type of relocation */ }; struct Symbol { - int32_t strpos; /* string table position of name */ - int32_t section; /* section ID of the symbol */ - int type; /* symbol type */ - int other; /* symbol visibility */ - int64_t value; /* address, or COMMON variable align */ - int32_t size; /* size of symbol */ - int32_t globnum; /* symbol table offset if global */ - struct Symbol *next; /* list of globals in each section */ + struct rbtree symv; /* symbol value and rbtree of globals */ + int32_t strpos; /* string table position of name */ + int32_t section; /* section ID of the symbol */ + int type; /* symbol type */ + int other; /* symbol visibility */ + int32_t size; /* size of symbol */ + int32_t globnum; /* symbol table offset if global */ struct Symbol *nextfwd; /* list of unresolved-size symbols */ - char *name; /* used temporarily if in above list */ + char *name; /* used temporarily if in above list */ }; - struct Section { struct SAA *data; uint64_t len, size; uint32_t nrelocs; - int32_t index; /* index into sects array */ - uint32_t type; /* SHT_PROGBITS or SHT_NOBITS */ - uint64_t align; /* alignment: power of two */ - uint64_t flags; /* section flags */ + int32_t index; /* index into sects array */ + int type; /* SHT_PROGBITS or SHT_NOBITS */ + uint64_t align; /* alignment: power of two */ + uint64_t flags; /* section flags */ char *name; struct SAA *rel; uint64_t rellen; struct Reloc *head, **tail; - struct Symbol *gsyms; /* global symbols in section */ + struct rbtree *gsyms; /* global symbols in section */ }; #define SECT_DELTA 32 @@ -144,7 +105,7 @@ static char *shstrtab; static int shstrtablen, shstrtabsize; static struct SAA *syms; -static uint32_t nlocals, nglobs; +static uint32_t nlocals, nglobs, ndebugs; static int32_t def_seg; @@ -166,24 +127,6 @@ static uint8_t elf_abiver = 0; /* Current ABI version */ extern struct ofmt of_elf64; -#define SHN_UNDEF 0 - -#define SYM_GLOBAL 0x10 - -#define STV_DEFAULT 0 -#define STV_INTERNAL 1 -#define STV_HIDDEN 2 -#define STV_PROTECTED 3 - -#define GLOBAL_TEMP_BASE 1048576 /* bigger than any reasonable sym id */ - -#define SEG_ALIGN 16 /* alignment of sections in file */ -#define SEG_ALIGN_1 (SEG_ALIGN-1) - -#define TY_DEBUGSYMLIN 0x40 /* internal call to debug_out */ - -static const char align_str[SEG_ALIGN] = ""; /* ANSI will pad this with 0s */ - static struct ELF_SECTDATA { void *data; int64_t len; @@ -193,8 +136,8 @@ static int elf_nsect, nsections; static int64_t elf_foffs; static void elf_write(void); -static void elf_sect_write(struct Section *, const uint8_t *, - uint64_t); +static void elf_sect_write(struct Section *, const void *, size_t); +static void elf_sect_writeaddr(struct Section *, int64_t, size_t); static void elf_section_header(int, int, uint64_t, void *, bool, uint64_t, int, int, int, int); static void elf_write_sections(void); @@ -275,24 +218,24 @@ static struct dfmt df_stabs; static struct Symbol *lastsym; /* common debugging routines */ -void debug64_typevalue(int32_t); -void debug64_init(struct ofmt *, void *, FILE *, efunc); -void debug64_deflabel(char *, int32_t, int64_t, int, char *); -void debug64_directive(const char *, const char *); +static void debug64_typevalue(int32_t); +static void debug64_deflabel(char *, int32_t, int64_t, int, char *); +static void debug64_directive(const char *, const char *); /* stabs debugging routines */ -void stabs64_linenum(const char *filename, int32_t linenumber, int32_t); -void stabs64_output(int, void *); -void stabs64_generate(void); -void stabs64_cleanup(void); +static void stabs64_linenum(const char *filename, int32_t linenumber, int32_t); +static void stabs64_output(int, void *); +static void stabs64_generate(void); +static void stabs64_cleanup(void); /* dwarf debugging routines */ -void dwarf64_linenum(const char *filename, int32_t linenumber, int32_t); -void dwarf64_output(int, void *); -void dwarf64_generate(void); -void dwarf64_cleanup(void); -void dwarf64_findfile(const char *); -void dwarf64_findsect(const int); +static void dwarf64_init(struct ofmt *, void *, FILE *, efunc); +static void dwarf64_linenum(const char *filename, int32_t linenumber, int32_t); +static void dwarf64_output(int, void *); +static void dwarf64_generate(void); +static void dwarf64_cleanup(void); +static void dwarf64_findfile(const char *); +static void dwarf64_findsect(const int); /* * Special section numbers which are used to define ELF special @@ -302,6 +245,7 @@ void dwarf64_findsect(const int); static int32_t elf_gotpc_sect, elf_gotoff_sect; static int32_t elf_got_sect, elf_plt_sect; static int32_t elf_sym_sect; +static int32_t elf_gottpoff_sect; static void elf_init(FILE * fp, efunc errfunc, ldfunc ldef, evalfunc eval) { @@ -313,7 +257,7 @@ static void elf_init(FILE * fp, efunc errfunc, ldfunc ldef, evalfunc eval) sects = NULL; nsects = sectlen = 0; syms = saa_init((int32_t)sizeof(struct Symbol)); - nlocals = nglobs = 0; + nlocals = nglobs = ndebugs = 0; bsym = raa_init(); strs = saa_init(1L); saa_wbytes(strs, "\0", 1L); @@ -340,6 +284,9 @@ static void elf_init(FILE * fp, efunc errfunc, ldfunc ldef, evalfunc eval) elf_sym_sect = seg_alloc(); ldef("..sym", elf_sym_sect + 1, 0L, NULL, false, false, &of_elf64, error); + elf_gottpoff_sect = seg_alloc(); + ldef("..gottpoff", elf_gottpoff_sect + 1, 0L, NULL, false, false, &of_elf64, + error); def_seg = seg_alloc(); @@ -409,8 +356,7 @@ static int elf_make_section(char *name, int type, int flags, int align) s->gsyms = NULL; if (nsects >= sectlen) - sects = - nasm_realloc(sects, (sectlen += SECT_DELTA) * sizeof(*sects)); + sects = nasm_realloc(sects, (sectlen += SECT_DELTA) * sizeof(*sects)); sects[nsects++] = s; return nsects - 1; @@ -419,9 +365,9 @@ static int elf_make_section(char *name, int type, int flags, int align) static int32_t elf_section_names(char *name, int pass, int *bits) { char *p; - unsigned flags_and, flags_or; - uint64_t type, align; - int i; + uint32_t flags, flags_and, flags_or; + uint64_t align; + int type, i; /* * Default is 64 bits. @@ -473,6 +419,9 @@ static int32_t elf_section_names(char *name, int pass, int *bits) } else if (!nasm_stricmp(q, "write")) { flags_and |= SHF_WRITE; flags_or |= SHF_WRITE; + } else if (!nasm_stricmp(q, "tls")) { + flags_and |= SHF_TLS; + flags_or |= SHF_TLS; } else if (!nasm_stricmp(q, "nowrite")) { flags_and |= SHF_WRITE; flags_or &= ~SHF_WRITE; @@ -480,12 +429,15 @@ static int32_t elf_section_names(char *name, int pass, int *bits) type = SHT_PROGBITS; } else if (!nasm_stricmp(q, "nobits")) { type = SHT_NOBITS; - } + } else if (pass == 1) { + error(ERR_WARNING, "Unknown section attribute '%s' ignored on" + " declaration of section `%s'", q, name); + } } - if (!strcmp(name, ".comment") || - !strcmp(name, ".shstrtab") || - !strcmp(name, ".symtab") || !strcmp(name, ".strtab")) { + if (!strcmp(name, ".shstrtab") || + !strcmp(name, ".symtab") || + !strcmp(name, ".strtab")) { error(ERR_NONFATAL, "attempt to redefine reserved section" "name `%s'", name); return NO_SEG; @@ -495,25 +447,19 @@ static int32_t elf_section_names(char *name, int pass, int *bits) if (!strcmp(name, sects[i]->name)) break; if (i == nsects) { - if (!strcmp(name, ".text")) - i = elf_make_section(name, SHT_PROGBITS, - SHF_ALLOC | SHF_EXECINSTR, 16); - else if (!strcmp(name, ".rodata")) - i = elf_make_section(name, SHT_PROGBITS, SHF_ALLOC, 4); - else if (!strcmp(name, ".data")) - i = elf_make_section(name, SHT_PROGBITS, - SHF_ALLOC | SHF_WRITE, 4); - else if (!strcmp(name, ".bss")) - i = elf_make_section(name, SHT_NOBITS, - SHF_ALLOC | SHF_WRITE, 4); - else - i = elf_make_section(name, SHT_PROGBITS, SHF_ALLOC, 1); - if (type) - sects[i]->type = type; - if (align) - sects[i]->align = align; - sects[i]->flags &= ~flags_and; - sects[i]->flags |= flags_or; + const struct elf_known_section *ks = elf_known_sections; + + while (ks->name) { + if (!strcmp(name, ks->name)) + break; + ks++; + } + + type = type ? type : ks->type; + align = align ? align : ks->align; + flags = (ks->flags & ~flags_and) | flags_or; + + i = elf_make_section(name, type, flags, align); } else if (pass == 1) { if ((type && sects[i]->type != type) || (align && sects[i]->align != align) @@ -545,7 +491,7 @@ static void elf_deflabel(char *name, int32_t segment, int64_t offset, */ if (strcmp(name, "..gotpc") && strcmp(name, "..gotoff") && strcmp(name, "..got") && strcmp(name, "..plt") && - strcmp(name, "..sym")) + strcmp(name, "..sym") && strcmp(name, "..gottpoff")) error(ERR_NONFATAL, "unrecognised special symbol `%s'", name); return; } @@ -593,6 +539,8 @@ static void elf_deflabel(char *name, int32_t segment, int64_t offset, lastsym = sym = saa_wstruct(syms); + memset(&sym->symv, 0, sizeof(struct rbtree)); + sym->strpos = pos; sym->type = is_global ? SYM_GLOBAL : 0; sym->other = STV_DEFAULT; @@ -619,7 +567,7 @@ static void elf_deflabel(char *name, int32_t segment, int64_t offset, if (is_global == 2) { sym->size = offset; - sym->value = 0; + sym->symv.key = 0; sym->section = SHN_COMMON; /* * We have a common variable. Check the special text to see @@ -628,17 +576,18 @@ static void elf_deflabel(char *name, int32_t segment, int64_t offset, */ if (special) { bool err; - sym->value = readnum(special, &err); + sym->symv.key = readnum(special, &err); if (err) error(ERR_NONFATAL, "alignment constraint `%s' is not a" " valid number", special); - else if ((sym->value | (sym->value - 1)) != 2 * sym->value - 1) + else if ((sym->symv.key | (sym->symv.key - 1)) + != 2 * sym->symv.key - 1) error(ERR_NONFATAL, "alignment constraint `%s' is not a" " power of two", special); } special_used = true; } else - sym->value = (sym->section == SHN_UNDEF ? 0 : offset); + sym->symv.key = (sym->section == SHN_UNDEF ? 0 : offset); if (sym->type == SYM_GLOBAL) { /* @@ -655,16 +604,14 @@ static void elf_deflabel(char *name, int32_t segment, int64_t offset, bsym = raa_write(bsym, segment, nglobs); } else if (sym->section != SHN_ABS) { /* - * This is a global symbol; so we must add it to the linked - * list of global symbols in its section. We'll push it on - * the beginning of the list, because it doesn't matter - * much which end we put it on and it's easier like this. + * This is a global symbol; so we must add it to the rbtree + * of global symbols in its section. * * In addition, we check the special text for symbol * type and size information. */ - sym->next = sects[sym->section - 1]->gsyms; - sects[sym->section - 1]->gsyms = sym; + sects[sym->section-1]->gsyms = + rb_insert(sects[sym->section-1]->gsyms, &sym->symv); if (special) { int n = strcspn(special, " \t"); @@ -730,6 +677,13 @@ static void elf_deflabel(char *name, int32_t segment, int64_t offset, } special_used = true; } + /* + * If TLS segment, mark symbol accordingly. + */ + if (sects[sym->section - 1]->flags & SHF_TLS) { + sym->type &= 0xf0; + sym->type |= STT_TLS; + } } sym->globnum = nglobs; nglobs++; @@ -740,7 +694,8 @@ static void elf_deflabel(char *name, int32_t segment, int64_t offset, error(ERR_NONFATAL, "no special symbol features supported here"); } -static void elf_add_reloc(struct Section *sect, int32_t segment, int type) +static void elf_add_reloc(struct Section *sect, int32_t segment, + int64_t offset, int type) { struct Reloc *r; r = *sect->tail = nasm_malloc(sizeof(struct Reloc)); @@ -748,6 +703,7 @@ static void elf_add_reloc(struct Section *sect, int32_t segment, int type) r->next = NULL; r->address = sect->len; + r->offset = offset; if (segment == NO_SEG) r->symbol = 0; else { @@ -786,13 +742,14 @@ static void elf_add_reloc(struct Section *sect, int32_t segment, int type) * Inefficiency: we search, currently, using a linked list which * isn't even necessarily sorted. */ -static int32_t elf_add_gsym_reloc(struct Section *sect, - int32_t segment, int64_t offset, - int type, bool exact) +static void elf_add_gsym_reloc(struct Section *sect, + int32_t segment, uint64_t offset, int64_t pcrel, + int type, bool exact) { struct Reloc *r; struct Section *s; - struct Symbol *sym, *sm; + struct Symbol *sym; + struct rbtree *srb; int i; /* @@ -808,48 +765,33 @@ static int32_t elf_add_gsym_reloc(struct Section *sect, s = sects[i]; break; } + if (!s) { - if (exact && offset != 0) - error(ERR_NONFATAL, "unable to find a suitable global symbol" - " for this reference"); - else - elf_add_reloc(sect, segment, type); - return offset; + if (exact && offset) + error(ERR_NONFATAL, "invalid access to an external symbol"); + else + elf_add_reloc(sect, segment, offset - pcrel, type); + return; } - if (exact) { - /* - * Find a symbol pointing _exactly_ at this one. - */ - for (sym = s->gsyms; sym; sym = sym->next) - if (sym->value == offset) - break; - } else { - /* - * Find the nearest symbol below this one. - */ - sym = NULL; - for (sm = s->gsyms; sm; sm = sm->next) - if (sm->value <= offset && (!sym || sm->value > sym->value)) - sym = sm; - } - if (!sym && exact) { - error(ERR_NONFATAL, "unable to find a suitable global symbol" - " for this reference"); - return 0; + srb = rb_search(s->gsyms, offset); + if (!srb || (exact && srb->key != offset)) { + error(ERR_NONFATAL, "unable to find a suitable global symbol" + " for this reference"); + return; } + sym = container_of(srb, struct Symbol, symv); r = *sect->tail = nasm_malloc(sizeof(struct Reloc)); sect->tail = &r->next; r->next = NULL; r->address = sect->len; + r->offset = offset - pcrel - sym->symv.key; r->symbol = GLOBAL_TEMP_BASE + sym->globnum; r->type = type; sect->nrelocs++; - - return offset - sym->value; } static void elf_out(int32_t segto, const void *data, @@ -857,11 +799,12 @@ static void elf_out(int32_t segto, const void *data, int32_t segment, int32_t wrt) { struct Section *s; - int64_t addr; - uint8_t mydata[16], *p; + int64_t addr, zero; int i; static struct symlininfo sinfo; + zero = 0; + #if defined(DEBUG) && DEBUG>2 if (data) fprintf(stderr, " elf_out line: %d type: %x seg: %d segto: %d bytes: %x data: %"PRIx64"\n", @@ -909,11 +852,7 @@ static void elf_out(int32_t segto, const void *data, if (s->type == SHT_NOBITS && type != OUT_RESERVE) { error(ERR_WARNING, "attempt to initialize memory in" " BSS section `%s': ignored", s->name); - if (type == OUT_REL2ADR) - size = 2; - else if (type == OUT_REL4ADR) - size = 4; - s->len += size; + s->len += realsize(type, size); return; } @@ -929,134 +868,193 @@ static void elf_out(int32_t segto, const void *data, error(ERR_PANIC, "OUT_RAWDATA with other than NO_SEG"); elf_sect_write(s, data, size); } else if (type == OUT_ADDRESS) { - bool gnu16 = false; addr = *(int64_t *)data; - if (segment != NO_SEG) { - if (segment % 2) { - error(ERR_NONFATAL, "ELF format does not support" - " segment base references"); - } else { - if (wrt == NO_SEG) { - switch ((int)size) { - case 2: - elf_add_reloc(s, segment, R_X86_64_16); - break; - case 4: - elf_add_reloc(s, segment, R_X86_64_32); - break; - case 8: - elf_add_reloc(s, segment, R_X86_64_64); - break; - default: - error(ERR_PANIC, "internal error elf64-hpa-871"); - break; - } - } else if (wrt == elf_gotpc_sect + 1) { - /* - * The user will supply GOT relative to $$. ELF - * will let us have GOT relative to $. So we - * need to fix up the data item by $-$$. - */ - addr += s->len; - elf_add_reloc(s, segment, R_X86_64_GOTPCREL); - } else if (wrt == elf_gotoff_sect + 1) { - elf_add_reloc(s, segment, R_X86_64_GOTTPOFF); - } else if (wrt == elf_got_sect + 1) { - addr = elf_add_gsym_reloc(s, segment, addr, - R_X86_64_GOT32, true); - } else if (wrt == elf_sym_sect + 1) { - switch ((int)size) { - case 2: - gnu16 = true; - addr = elf_add_gsym_reloc(s, segment, addr, - R_X86_64_16, false); - break; - case 4: - addr = elf_add_gsym_reloc(s, segment, addr, - R_X86_64_32, false); - break; - case 8: - addr = elf_add_gsym_reloc(s, segment, addr, - R_X86_64_64, false); - break; - default: - error(ERR_PANIC, "internal error elf64-hpa-903"); - break; - } - } else if (wrt == elf_plt_sect + 1) { - error(ERR_NONFATAL, "ELF format cannot produce non-PC-" - "relative PLT references"); - } else { - error(ERR_NONFATAL, "ELF format does not support this" - " use of WRT"); - wrt = NO_SEG; /* we can at least _try_ to continue */ - } - } - } - p = mydata; - if (gnu16) { - WRITESHORT(p, addr); - } else { - if (size != 8 && size != 4 && segment != NO_SEG) { - error(ERR_NONFATAL, - "Unsupported non-64-bit ELF relocation"); - } - if (size == 4) WRITELONG(p, addr); - else WRITEDLONG(p, (int64_t)addr); - } - elf_sect_write(s, mydata, size); + if (segment == NO_SEG) { + /* Do nothing */ + } else if (segment % 2) { + error(ERR_NONFATAL, "ELF format does not support" + " segment base references"); + } else { + if (wrt == NO_SEG) { + switch ((int)size) { + case 1: + elf_add_reloc(s, segment, addr, R_X86_64_8); + break; + case 2: + elf_add_reloc(s, segment, addr, R_X86_64_16); + break; + case 4: + elf_add_reloc(s, segment, addr, R_X86_64_32); + break; + case 8: + elf_add_reloc(s, segment, addr, R_X86_64_64); + break; + default: + error(ERR_PANIC, "internal error elf64-hpa-871"); + break; + } + addr = 0; + } else if (wrt == elf_gotpc_sect + 1) { + /* + * The user will supply GOT relative to $$. ELF + * will let us have GOT relative to $. So we + * need to fix up the data item by $-$$. + */ + addr += s->len; + elf_add_reloc(s, segment, addr, R_X86_64_GOTPC32); + addr = 0; + } else if (wrt == elf_gotoff_sect + 1) { + if (size != 8) { + error(ERR_NONFATAL, "ELF64 requires ..gotoff " + "references to be qword"); + } else { + elf_add_reloc(s, segment, addr, R_X86_64_GOTOFF64); + addr = 0; + } + } else if (wrt == elf_got_sect + 1) { + switch ((int)size) { + case 4: + elf_add_gsym_reloc(s, segment, addr, 0, + R_X86_64_GOT32, true); + addr = 0; + break; + case 8: + elf_add_gsym_reloc(s, segment, addr, 0, + R_X86_64_GOT64, true); + addr = 0; + break; + default: + error(ERR_NONFATAL, "invalid ..got reference"); + break; + } + } else if (wrt == elf_sym_sect + 1) { + switch ((int)size) { + case 1: + elf_add_gsym_reloc(s, segment, addr, 0, + R_X86_64_8, false); + addr = 0; + break; + case 2: + elf_add_gsym_reloc(s, segment, addr, 0, + R_X86_64_16, false); + addr = 0; + break; + case 4: + elf_add_gsym_reloc(s, segment, addr, 0, + R_X86_64_32, false); + addr = 0; + break; + case 8: + elf_add_gsym_reloc(s, segment, addr, 0, + R_X86_64_64, false); + addr = 0; + break; + default: + error(ERR_PANIC, "internal error elf64-hpa-903"); + break; + } + } else if (wrt == elf_plt_sect + 1) { + error(ERR_NONFATAL, "ELF format cannot produce non-PC-" + "relative PLT references"); + } else { + error(ERR_NONFATAL, "ELF format does not support this" + " use of WRT"); + } + } + elf_sect_writeaddr(s, addr, size); } else if (type == OUT_REL2ADR) { + addr = *(int64_t *)data - size; if (segment == segto) error(ERR_PANIC, "intra-segment OUT_REL2ADR"); - if (segment != NO_SEG && segment % 2) { + if (segment == NO_SEG) { + /* Do nothing */ + } else if (segment % 2) { error(ERR_NONFATAL, "ELF format does not support" " segment base references"); } else { if (wrt == NO_SEG) { - elf_add_reloc(s, segment, R_X86_64_PC16); + elf_add_reloc(s, segment, addr, R_X86_64_PC16); + addr = 0; } else { error(ERR_NONFATAL, "Unsupported non-32-bit ELF relocation [2]"); } } - p = mydata; - WRITESHORT(p, *(int64_t *)data - size); - elf_sect_write(s, mydata, 2L); + elf_sect_writeaddr(s, addr, 2); } else if (type == OUT_REL4ADR) { + addr = *(int64_t *)data - size; if (segment == segto) error(ERR_PANIC, "intra-segment OUT_REL4ADR"); - if (segment != NO_SEG && segment % 2) { - error(ERR_NONFATAL, "ELF format does not support" + if (segment == NO_SEG) { + /* Do nothing */ + } else if (segment % 2) { + error(ERR_NONFATAL, "ELF64 format does not support" " segment base references"); } else { if (wrt == NO_SEG) { - elf_add_reloc(s, segment, R_X86_64_PC32); + elf_add_reloc(s, segment, addr, R_X86_64_PC32); + addr = 0; } else if (wrt == elf_plt_sect + 1) { - elf_add_reloc(s, segment, R_X86_64_PLT32); + elf_add_gsym_reloc(s, segment, addr+size, size, + R_X86_64_PLT32, true); + addr = 0; } else if (wrt == elf_gotpc_sect + 1 || - wrt == elf_gotoff_sect + 1 || - wrt == elf_got_sect + 1) { - error(ERR_NONFATAL, "ELF format cannot produce PC-" - "relative GOT references"); + wrt == elf_got_sect + 1) { + elf_add_gsym_reloc(s, segment, addr+size, size, + R_X86_64_GOTPCREL, true); + addr = 0; + } else if (wrt == elf_gotoff_sect + 1 || + wrt == elf_got_sect + 1) { + error(ERR_NONFATAL, "ELF64 requires ..gotoff references to be " + "qword absolute"); + } else if (wrt == elf_gottpoff_sect + 1) { + elf_add_gsym_reloc(s, segment, addr+size, size, + R_X86_64_GOTTPOFF, true); + addr = 0; } else { - error(ERR_NONFATAL, "ELF format does not support this" + error(ERR_NONFATAL, "ELF64 format does not support this" " use of WRT"); - wrt = NO_SEG; /* we can at least _try_ to continue */ } } - p = mydata; - WRITELONG(p, *(int64_t *)data - size); - elf_sect_write(s, mydata, 4L); + elf_sect_writeaddr(s, addr, 4); + } else if (type == OUT_REL8ADR) { + addr = *(int64_t *)data - size; + if (segment == segto) + error(ERR_PANIC, "intra-segment OUT_REL8ADR"); + if (segment == NO_SEG) { + /* Do nothing */ + } else if (segment % 2) { + error(ERR_NONFATAL, "ELF64 format does not support" + " segment base references"); + } else { + if (wrt == NO_SEG) { + elf_add_reloc(s, segment, addr, R_X86_64_PC64); + addr = 0; + } else if (wrt == elf_gotpc_sect + 1 || + wrt == elf_got_sect + 1) { + elf_add_gsym_reloc(s, segment, addr+size, size, + R_X86_64_GOTPCREL64, true); + addr = 0; + } else if (wrt == elf_gotoff_sect + 1 || + wrt == elf_got_sect + 1) { + error(ERR_NONFATAL, "ELF64 requires ..gotoff references to be " + "absolute"); + } else if (wrt == elf_gottpoff_sect + 1) { + error(ERR_NONFATAL, "ELF64 requires ..gottpoff references to be " + "dword"); + } else { + error(ERR_NONFATAL, "ELF64 format does not support this" + " use of WRT"); + } + } + elf_sect_writeaddr(s, addr, 8); } } static void elf_write(void) { int align; - int scount; char *p; - int commlen; - char comment[64]; int i; struct SAA *symtab; @@ -1064,18 +1062,16 @@ static void elf_write(void) /* * Work out how many sections we will have. We have SHN_UNDEF, - * then the flexible user sections, then the four fixed - * sections `.comment', `.shstrtab', `.symtab' and `.strtab', - * then optionally relocation sections for the user sections. + * then the flexible user sections, then the fixed sections + * `.shstrtab', `.symtab' and `.strtab', then optionally + * relocation sections for the user sections. */ + nsections = sec_numspecial + 1; if (of_elf64.current_dfmt == &df_stabs) - nsections = 8; + nsections += 3; else if (of_elf64.current_dfmt == &df_dwarf) - nsections = 15; - else - nsections = 5; /* SHN_UNDEF and the fixed ones */ + nsections += 10; - add_sectname("", ".comment"); add_sectname("", ".shstrtab"); add_sectname("", ".symtab"); add_sectname("", ".strtab"); @@ -1115,19 +1111,12 @@ static void elf_write(void) } /* - * Do the comment. - */ - *comment = '\0'; - commlen = - 2 + sprintf(comment + 1, "The Netwide Assembler %s", NASM_VER); - - /* * Output the ELF header. */ fwrite("\177ELF\2\1\1", 7, 1, elffp); fputc(elf_osabi, elffp); fputc(elf_abiver, elffp); - fwrite("\0\0\0\0\0\0\0", 7, 1, elffp); + fwritezero(7, elffp); fwriteint16_t(ET_REL, elffp); /* relocatable file */ fwriteint16_t(EM_X86_64, elffp); /* processor ID */ fwriteint32_t(1L, elffp); /* EV_CURRENT file format version */ @@ -1141,8 +1130,8 @@ static void elf_write(void) fwriteint16_t(0, elffp); /* still no program header table */ fwriteint16_t(sizeof(Elf64_Shdr), elffp); /* size of section header */ fwriteint16_t(nsections, elffp); /* number of sections */ - fwriteint16_t(nsects + 2, elffp); /* string table section index for - * section header table */ + fwriteint16_t(sec_shstrtab, elffp); /* string table section index for + * section header table */ /* * Build the symbol table and relocation tables. @@ -1162,33 +1151,43 @@ static void elf_write(void) elf_foffs += align; elf_nsect = 0; elf_sects = nasm_malloc(sizeof(*elf_sects) * nsections); - elf_section_header(0, 0, 0, NULL, false, 0L, 0, 0, 0, 0); /* SHN_UNDEF */ - scount = 1; /* needed for the stabs debugging to track the symtable section */ + + /* SHN_UNDEF */ + elf_section_header(0, SHT_NULL, 0, NULL, false, 0, SHN_UNDEF, 0, 0, 0); p = shstrtab + 1; + + /* The normal sections */ for (i = 0; i < nsects; i++) { elf_section_header(p - shstrtab, sects[i]->type, sects[i]->flags, (sects[i]->type == SHT_PROGBITS ? sects[i]->data : NULL), true, sects[i]->len, 0, 0, sects[i]->align, 0); p += strlen(p) + 1; - scount++; /* ditto */ } - elf_section_header(p - shstrtab, 1, 0, comment, false, (int32_t)commlen, 0, 0, 1, 0); /* .comment */ - scount++; /* ditto */ + + /* .shstrtab */ + elf_section_header(p - shstrtab, SHT_STRTAB, 0, shstrtab, false, + shstrtablen, 0, 0, 1, 0); p += strlen(p) + 1; - elf_section_header(p - shstrtab, 3, 0, shstrtab, false, (int32_t)shstrtablen, 0, 0, 1, 0); /* .shstrtab */ - scount++; /* ditto */ + + /* .symtab */ + elf_section_header(p - shstrtab, SHT_SYMTAB, 0, symtab, true, + symtablen, sec_strtab, symtablocal, 4, 24); p += strlen(p) + 1; - elf_section_header(p - shstrtab, 2, 0, symtab, true, symtablen, nsects + 4, symtablocal, 4, 24); /* .symtab */ - symtabsection = scount; /* now we got the symtab section index in the ELF file */ + + /* .strtab */ + elf_section_header(p - shstrtab, SHT_STRTAB, 0, strs, true, + strslen, 0, 0, 1, 0); p += strlen(p) + 1; - elf_section_header(p - shstrtab, 3, 0, strs, true, strslen, 0, 0, 1, 0); /* .strtab */ + + /* The relocation sections */ for (i = 0; i < nsects; i++) if (sects[i]->head) { + elf_section_header(p - shstrtab, SHT_RELA, 0, sects[i]->rel, true, + sects[i]->rellen, sec_symtab, i + 1, 4, 24); p += strlen(p) + 1; - elf_section_header(p - shstrtab,SHT_RELA, 0, sects[i]->rel, true, - sects[i]->rellen, nsects + 3, i + 1, 4, 24); } + if (of_elf64.current_dfmt == &df_stabs) { /* for debugging information, create the last three sections which are the .stab , .stabstr and .rel.stab sections respectively */ @@ -1196,61 +1195,69 @@ static void elf_write(void) /* this function call creates the stab sections in memory */ stabs64_generate(); - if ((stabbuf) && (stabstrbuf) && (stabrelbuf)) { + if (stabbuf && stabstrbuf && stabrelbuf) { + elf_section_header(p - shstrtab, SHT_PROGBITS, 0, stabbuf, false, + stablen, sec_stabstr, 0, 4, 12); p += strlen(p) + 1; - elf_section_header(p - shstrtab, 1, 0, stabbuf, false, stablen, - nsections - 2, 0, 4, 12); - p += strlen(p) + 1; - elf_section_header(p - shstrtab, 3, 0, stabstrbuf, false, + elf_section_header(p - shstrtab, SHT_STRTAB, 0, stabstrbuf, false, stabstrlen, 0, 0, 4, 0); - p += strlen(p) + 1; + /* link -> symtable info -> section to refer to */ - elf_section_header(p - shstrtab, 9, 0, stabrelbuf, false, - stabrellen, symtabsection, nsections - 3, 4, - 16); + elf_section_header(p - shstrtab, SHT_REL, 0, stabrelbuf, false, + stabrellen, symtabsection, sec_stab, 4, 16); + p += strlen(p) + 1; } } else if (of_elf64.current_dfmt == &df_dwarf) { /* for dwarf debugging information, create the ten dwarf sections */ /* this function call creates the dwarf sections in memory */ - if (dwarf_fsect) dwarf64_generate(); + if (dwarf_fsect) + dwarf64_generate(); - p += strlen(p) + 1; elf_section_header(p - shstrtab, SHT_PROGBITS, 0, arangesbuf, false, arangeslen, 0, 0, 1, 0); p += strlen(p) + 1; + elf_section_header(p - shstrtab, SHT_RELA, 0, arangesrelbuf, false, arangesrellen, symtabsection, debug_aranges, 1, 24); p += strlen(p) + 1; + elf_section_header(p - shstrtab, SHT_PROGBITS, 0, pubnamesbuf, false, pubnameslen, 0, 0, 1, 0); p += strlen(p) + 1; + elf_section_header(p - shstrtab, SHT_PROGBITS, 0, infobuf, false, infolen, 0, 0, 1, 0); p += strlen(p) + 1; + elf_section_header(p - shstrtab, SHT_RELA, 0, inforelbuf, false, inforellen, symtabsection, debug_info, 1, 24); p += strlen(p) + 1; + elf_section_header(p - shstrtab, SHT_PROGBITS, 0, abbrevbuf, false, abbrevlen, 0, 0, 1, 0); p += strlen(p) + 1; + elf_section_header(p - shstrtab, SHT_PROGBITS, 0, linebuf, false, linelen, 0, 0, 1, 0); p += strlen(p) + 1; + elf_section_header(p - shstrtab, SHT_RELA, 0, linerelbuf, false, linerellen, symtabsection, debug_line, 1, 24); p += strlen(p) + 1; + elf_section_header(p - shstrtab, SHT_PROGBITS, 0, framebuf, false, framelen, 0, 0, 8, 0); p += strlen(p) + 1; + elf_section_header(p - shstrtab, SHT_PROGBITS, 0, locbuf, false, loclen, 0, 0, 1, 0); - + p += strlen(p) + 1; } - fwrite(align_str, align, 1, elffp); + fwritezero(align, elffp); /* * Now output the sections. @@ -1319,7 +1326,7 @@ static struct SAA *elf_build_symtab(int32_t *len, int32_t *local) WRITECHAR(p, sym->type); /* type and binding */ WRITECHAR(p, sym->other); /* visibility */ WRITESHORT(p, sym->section); /* index into section header table */ - WRITEDLONG(p, (int64_t)sym->value); /* value of symbol */ + WRITEDLONG(p, (int64_t)sym->symv.key); /* value of symbol */ WRITEDLONG(p, (int64_t)sym->size); /* size of symbol */ saa_wbytes(s, entry, 24L); *len += 24; @@ -1374,7 +1381,7 @@ static struct SAA *elf_build_symtab(int32_t *len, int32_t *local) WRITECHAR(p, sym->type); /* type and binding */ WRITECHAR(p, sym->other); /* visibility */ WRITESHORT(p, sym->section); - WRITEDLONG(p, (int64_t)sym->value); + WRITEDLONG(p, (int64_t)sym->symv.key); WRITEDLONG(p, (int64_t)sym->size); saa_wbytes(s, entry, 24L); *len += 24; @@ -1387,6 +1394,7 @@ static struct SAA *elf_build_reltab(uint64_t *len, struct Reloc *r) { struct SAA *s; uint8_t *p, entry[24]; + int32_t global_offset; if (!r) return NULL; @@ -1394,19 +1402,24 @@ static struct SAA *elf_build_reltab(uint64_t *len, struct Reloc *r) s = saa_init(1L); *len = 0; + /* + * How to onvert from a global placeholder to a real symbol index; + * the +2 refers to the two special entries, the null entry and + * the filename entry. + */ + global_offset = -GLOBAL_TEMP_BASE + nsects + nlocals + ndebugs + 2; + while (r) { - int64_t sym = r->symbol; + int32_t sym = r->symbol; if (sym >= GLOBAL_TEMP_BASE) - { - if (of_elf64.current_dfmt == &df_dwarf) - sym += -GLOBAL_TEMP_BASE + (nsects + 5) + nlocals; - else sym += -GLOBAL_TEMP_BASE + (nsects + 2) + nlocals; - } + sym += global_offset; + p = entry; WRITEDLONG(p, r->address); - WRITEDLONG(p, (sym << 32) + r->type); - WRITEDLONG(p, (uint64_t) 0); + WRITELONG(p, r->type); + WRITELONG(p, sym); + WRITEDLONG(p, r->offset); saa_wbytes(s, entry, 24L); *len += 24; @@ -1451,16 +1464,20 @@ static void elf_write_sections(void) saa_fpwrite(elf_sects[i].data, elffp); else fwrite(elf_sects[i].data, len, 1, elffp); - fwrite(align_str, align, 1, elffp); + fwritezero(align, elffp); } } -static void elf_sect_write(struct Section *sect, - const uint8_t *data, uint64_t len) +static void elf_sect_write(struct Section *sect, const void *data, size_t len) { saa_wbytes(sect->data, data, len); sect->len += len; } +static void elf_sect_writeaddr(struct Section *sect, int64_t data, size_t len) +{ + saa_writeaddr(sect->data, data, len); + sect->len += len; +} static int32_t elf_segbase(int32_t segment) { @@ -1520,9 +1537,9 @@ static int elf_set_info(enum geninfo type, char **val) return 0; } static struct dfmt df_dwarf = { - "ELF64 (X86_64) dwarf debug format for Linux", + "ELF64 (x86-64) dwarf debug format for Linux/Unix", "dwarf", - debug64_init, + dwarf64_init, dwarf64_linenum, debug64_deflabel, debug64_directive, @@ -1531,9 +1548,9 @@ static struct dfmt df_dwarf = { dwarf64_cleanup }; static struct dfmt df_stabs = { - "ELF64 (X86_64) stabs debug format for Linux", + "ELF64 (x86-64) stabs debug format for Linux/Unix", "stabs", - debug64_init, + null_debug_init, stabs64_linenum, debug64_deflabel, debug64_directive, @@ -1542,14 +1559,14 @@ static struct dfmt df_stabs = { stabs64_cleanup }; -struct dfmt *elf64_debugs_arr[3] = { &df_stabs, &df_dwarf, NULL }; +struct dfmt *elf64_debugs_arr[3] = { &df_dwarf, &df_stabs, NULL }; struct ofmt of_elf64 = { "ELF64 (x86_64) object files (e.g. Linux)", "elf64", - NULL, + 0, elf64_debugs_arr, - &null_debug_form, + &df_stabs, elf_stdmac, elf_init, elf_set_info, @@ -1563,15 +1580,8 @@ struct ofmt of_elf64 = { }; /* common debugging routines */ -void debug64_init(struct ofmt *of, void *id, FILE * fp, efunc error) -{ - (void)of; - (void)id; - (void)fp; - (void)error; -} -void debug64_deflabel(char *name, int32_t segment, int64_t offset, int is_global, - char *special) +static void debug64_deflabel(char *name, int32_t segment, int64_t offset, + int is_global, char *special) { (void)name; (void)segment; @@ -1580,13 +1590,13 @@ void debug64_deflabel(char *name, int32_t segment, int64_t offset, int is_global (void)special; } -void debug64_directive(const char *directive, const char *params) +static void debug64_directive(const char *directive, const char *params) { (void)directive; (void)params; } -void debug64_typevalue(int32_t type) +static void debug64_typevalue(int32_t type) { int32_t stype, ssize; switch (TYM_TYPE(type)) { @@ -1651,8 +1661,7 @@ void debug64_typevalue(int32_t type) /* stabs debugging routines */ - -void stabs64_linenum(const char *filename, int32_t linenumber, int32_t segto) +static void stabs64_linenum(const char *filename, int32_t linenumber, int32_t segto) { (void)segto; if (!stabs_filename) { @@ -1675,7 +1684,7 @@ void stabs64_linenum(const char *filename, int32_t linenumber, int32_t segto) } -void stabs64_output(int type, void *param) +static void stabs64_output(int type, void *param) { struct symlininfo *s; struct linelist *el; @@ -1715,7 +1724,7 @@ void stabs64_output(int type, void *param) /* for creating the .stab , .stabstr and .rel.stab sections in memory */ -void stabs64_generate(void) +static void stabs64_generate(void) { int i, numfiles, strsize, numstabs = 0, currfile, mainfileindex; uint8_t *sbuf, *ssbuf, *rbuf, *sptr, *rptr; @@ -1850,7 +1859,7 @@ void stabs64_generate(void) stabstrbuf = ssbuf; } -void stabs64_cleanup(void) +static void stabs64_cleanup(void) { struct linelist *ptr, *del; if (!stabslines) @@ -1869,9 +1878,18 @@ void stabs64_cleanup(void) nasm_free(stabstrbuf); } /* dwarf routines */ +static void dwarf64_init(struct ofmt *of, void *id, FILE * fp, efunc error) +{ + (void)of; + (void)id; + (void)fp; + (void)error; + ndebugs = 3; /* 3 debug symbols */ +} -void dwarf64_linenum(const char *filename, int32_t linenumber, int32_t segto) +static void dwarf64_linenum(const char *filename, int32_t linenumber, + int32_t segto) { (void)segto; dwarf64_findfile(filename); @@ -1880,7 +1898,7 @@ void dwarf64_linenum(const char *filename, int32_t linenumber, int32_t segto) } /* called from elf_out with type == TY_DEBUGSYMLIN */ -void dwarf64_output(int type, void *param) +static void dwarf64_output(int type, void *param) { int ln, aa, inx, maxln, soc; struct symlininfo *s; @@ -1943,9 +1961,8 @@ void dwarf64_output(int type, void *param) } -void dwarf64_generate(void) +static void dwarf64_generate(void) { - static const char nasm_signature[] = "NASM " NASM_VER; uint8_t *pbuf; int indx; struct linelist *ftentry; @@ -2180,7 +2197,7 @@ void dwarf64_generate(void) WRITEDLONG(pbuf,0); /* null ending offset */ } -void dwarf64_cleanup(void) +static void dwarf64_cleanup(void) { if (arangesbuf) nasm_free(arangesbuf); @@ -2203,7 +2220,7 @@ void dwarf64_cleanup(void) if (locbuf) nasm_free(locbuf); } -void dwarf64_findfile(const char * fname) +static void dwarf64_findfile(const char * fname) { int finx; struct linelist *match; @@ -2248,7 +2265,7 @@ void dwarf64_findfile(const char * fname) } } /* */ -void dwarf64_findsect(const int index) +static void dwarf64_findsect(const int index) { int sinx; struct sectlist *match; diff --git a/output/outieee.c b/output/outieee.c index b70d3b2d..d587d4ce 100644 --- a/output/outieee.c +++ b/output/outieee.c @@ -1,10 +1,39 @@ -/* outieee.c output routines for the Netwide Assembler to produce - * IEEE-std object files +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * ----------------------------------------------------------------------- */ + +/* + * outieee.c output routines for the Netwide Assembler to produce + * IEEE-std object files */ /* notes: I have tried to make this correspond to the IEEE version @@ -48,7 +77,8 @@ #include "nasm.h" #include "nasmlib.h" -#include "outform.h" +#include "output/outform.h" +#include "output/outlib.h" #ifdef OF_IEEE @@ -196,8 +226,8 @@ static void ieee_init(FILE * fp, efunc errfunc, ldfunc ldef, evalfunc eval) ieee_entry_seg = NO_SEG; ieee_uppercase = false; checksum = 0; - of_ieee.current_dfmt->init(&of_ieee, NULL, fp, errfunc); } + static int ieee_set_info(enum geninfo type, char **val) { (void)type; @@ -861,30 +891,29 @@ static void ieee_write_file(int debuginfo) struct ieeeObjData *data; struct ieeeFixupp *fix; struct Array *arr; - static char boast[] = "The Netwide Assembler " NASM_VER; int i; /* * Write the module header */ - ieee_putascii("MBFNASM,%02X%s.\r\n", strlen(ieee_infile), ieee_infile); + ieee_putascii("MBFNASM,%02X%s.\n", strlen(ieee_infile), ieee_infile); /* * Write the NASM boast comment. */ - ieee_putascii("CO0,%02X%s.\r\n", strlen(boast), boast); + ieee_putascii("CO0,%02X%s.\n", strlen(nasm_comment), nasm_comment); /* * write processor-specific information */ - ieee_putascii("AD8,4,L.\r\n"); + ieee_putascii("AD8,4,L.\n"); /* * date and time */ time(&reltime); thetime = localtime(&reltime); - ieee_putascii("DT%04d%02d%02d%02d%02d%02d.\r\n", + ieee_putascii("DT%04d%02d%02d%02d%02d%02d.\n", 1900 + thetime->tm_year, thetime->tm_mon + 1, thetime->tm_mday, thetime->tm_hour, thetime->tm_min, thetime->tm_sec); @@ -892,10 +921,10 @@ static void ieee_write_file(int debuginfo) * if debugging, dump file names */ for (fn = fnhead; fn && debuginfo; fn = fn->next) { - ieee_putascii("C0105,%02X%s.\r\n", strlen(fn->name), fn->name); + ieee_putascii("C0105,%02X%s.\n", strlen(fn->name), fn->name); } - ieee_putascii("CO101,07ENDHEAD.\r\n"); + ieee_putascii("CO101,07ENDHEAD.\n"); /* * the standard doesn't specify when to put checksums, * we'll just do it periodically. @@ -925,15 +954,15 @@ static void ieee_write_file(int debuginfo) } ieee_unqualified_name(buf, seg->name); if (seg->align >= SEG_ABS) { - ieee_putascii("ST%X,A,%02X%s.\r\n", seg->ieee_index, + ieee_putascii("ST%X,A,%02X%s.\n", seg->ieee_index, strlen(buf), buf); - ieee_putascii("ASL%X,%lX.\r\n", seg->ieee_index, + ieee_putascii("ASL%X,%lX.\n", seg->ieee_index, (seg->align - SEG_ABS) * 16); } else { - ieee_putascii("ST%X,%c,%02X%s.\r\n", seg->ieee_index, attrib, + ieee_putascii("ST%X,%c,%02X%s.\n", seg->ieee_index, attrib, strlen(buf), buf); - ieee_putascii("SA%X,%lX.\r\n", seg->ieee_index, seg->align); - ieee_putascii("ASS%X,%X.\r\n", seg->ieee_index, + ieee_putascii("SA%X,%lX.\n", seg->ieee_index, seg->align); + ieee_putascii("ASS%X,%X.\n", seg->ieee_index, seg->currentpos); } seg = seg->next; @@ -948,7 +977,7 @@ static void ieee_write_file(int debuginfo) if (!seg) error(ERR_PANIC, "Start address records are incorrect"); else - ieee_putascii("ASG,R%X,%lX,+.\r\n", seg->ieee_index, + ieee_putascii("ASG,R%X,%lX,+.\n", seg->ieee_index, ieee_entry_ofs); } @@ -961,18 +990,18 @@ static void ieee_write_file(int debuginfo) for (pub = seg->pubhead; pub; pub = pub->next) { char buf[256]; ieee_unqualified_name(buf, pub->name); - ieee_putascii("NI%X,%02X%s.\r\n", i, strlen(buf), buf); + ieee_putascii("NI%X,%02X%s.\n", i, strlen(buf), buf); if (pub->segment == -1) - ieee_putascii("ASI%X,R%X,%lX,+.\r\n", i, pub->index, + ieee_putascii("ASI%X,R%X,%lX,+.\n", i, pub->index, pub->offset); else - ieee_putascii("ASI%X,%lX,%lX,+.\r\n", i, pub->segment * 16, + ieee_putascii("ASI%X,%lX,%lX,+.\n", i, pub->segment * 16, pub->offset); if (debuginfo) { if (pub->type >= 0x100) - ieee_putascii("ATI%X,T%X.\r\n", i, pub->type - 0x100); + ieee_putascii("ATI%X,T%X.\n", i, pub->type - 0x100); else - ieee_putascii("ATI%X,%X.\r\n", i, pub->type); + ieee_putascii("ATI%X,%X.\n", i, pub->type); } i++; } @@ -982,18 +1011,18 @@ static void ieee_write_file(int debuginfo) while (pub) { char buf[256]; ieee_unqualified_name(buf, pub->name); - ieee_putascii("NI%X,%02X%s.\r\n", i, strlen(buf), buf); + ieee_putascii("NI%X,%02X%s.\n", i, strlen(buf), buf); if (pub->segment == -1) - ieee_putascii("ASI%X,R%X,%lX,+.\r\n", i, pub->index, + ieee_putascii("ASI%X,R%X,%lX,+.\n", i, pub->index, pub->offset); else - ieee_putascii("ASI%X,%lX,%lX,+.\r\n", i, pub->segment * 16, + ieee_putascii("ASI%X,%lX,%lX,+.\n", i, pub->segment * 16, pub->offset); if (debuginfo) { if (pub->type >= 0x100) - ieee_putascii("ATI%X,T%X.\r\n", i, pub->type - 0x100); + ieee_putascii("ATI%X,T%X.\n", i, pub->type - 0x100); else - ieee_putascii("ATI%X,%X.\r\n", i, pub->type); + ieee_putascii("ATI%X,%X.\n", i, pub->type); } i++; pub = pub->next; @@ -1006,7 +1035,7 @@ static void ieee_write_file(int debuginfo) while (ext) { char buf[256]; ieee_unqualified_name(buf, ext->name); - ieee_putascii("NX%X,%02X%s.\r\n", i++, strlen(buf), buf); + ieee_putascii("NX%X,%02X%s.\n", i++, strlen(buf), buf); ext = ext->next; } ieee_putcs(false); @@ -1015,14 +1044,14 @@ static void ieee_write_file(int debuginfo) * IEEE doesn't have a standard pass break record * so use the ladsoft variant */ - ieee_putascii("CO100,06ENDSYM.\r\n"); + ieee_putascii("CO100,06ENDSYM.\n"); /* * now put types */ i = ARRAY_BOT; for (arr = arrhead; arr && debuginfo; arr = arr->next) { - ieee_putascii("TY%X,20,%X,%lX.\r\n", i++, arr->basetype, + ieee_putascii("TY%X,20,%X,%lX.\n", i++, arr->basetype, arr->size); } /* @@ -1033,18 +1062,18 @@ static void ieee_write_file(int debuginfo) for (loc = seg->lochead; loc; loc = loc->next) { char buf[256]; ieee_unqualified_name(buf, loc->name); - ieee_putascii("NN%X,%02X%s.\r\n", i, strlen(buf), buf); + ieee_putascii("NN%X,%02X%s.\n", i, strlen(buf), buf); if (loc->segment == -1) - ieee_putascii("ASN%X,R%X,%lX,+.\r\n", i, loc->index, + ieee_putascii("ASN%X,R%X,%lX,+.\n", i, loc->index, loc->offset); else - ieee_putascii("ASN%X,%lX,%lX,+.\r\n", i, loc->segment * 16, + ieee_putascii("ASN%X,%lX,%lX,+.\n", i, loc->segment * 16, loc->offset); if (debuginfo) { if (loc->type >= 0x100) - ieee_putascii("ATN%X,T%X.\r\n", i, loc->type - 0x100); + ieee_putascii("ATN%X,T%X.\n", i, loc->type - 0x100); else - ieee_putascii("ATN%X,%X.\r\n", i, loc->type); + ieee_putascii("ATN%X,%X.\n", i, loc->type); } i++; } @@ -1060,7 +1089,7 @@ static void ieee_write_file(int debuginfo) if (seg->currentpos) { int32_t size, org = 0; data = seg->data; - ieee_putascii("SB%X.\r\n", seg->ieee_index); + ieee_putascii("SB%X.\n", seg->ieee_index); fix = seg->fptr; while (fix) { size = HUNKSIZE - (org % HUNKSIZE); @@ -1091,7 +1120,7 @@ static void ieee_write_file(int debuginfo) /* * module end record */ - ieee_putascii("ME.\r\n"); + ieee_putascii("ME.\n"); } static void ieee_write_byte(struct ieeeSection *seg, int data) @@ -1125,7 +1154,7 @@ static void ieee_putascii(char *format, ...) vsnprintf(buffer, sizeof(buffer), format, ap); l = strlen(buffer); for (i = 0; i < l; i++) - if ((buffer[i] & 0xff) > 31) + if ((uint8_t)buffer[i] > 31) checksum += buffer[i]; va_end(ap); fprintf(ofp, buffer); @@ -1136,11 +1165,11 @@ static void ieee_putascii(char *format, ...) static void ieee_putcs(int toclear) { if (toclear) { - ieee_putascii("CS.\r\n"); + ieee_putascii("CS.\n"); } else { checksum += 'C'; checksum += 'S'; - ieee_putascii("CS%02X.\r\n", checksum & 127); + ieee_putascii("CS%02X.\n", checksum & 127); } checksum = 0; } @@ -1159,7 +1188,7 @@ static int32_t ieee_putld(int32_t start, int32_t end, uint8_t *buf) ieee_putascii("%02X", buf[val++]); start++; } - ieee_putascii(".\r\n"); + ieee_putascii(".\n"); } /* if no partial lines */ if (start == end) @@ -1170,7 +1199,7 @@ static int32_t ieee_putld(int32_t start, int32_t end, uint8_t *buf) ieee_putascii("%02X", buf[val++]); start++; } - ieee_putascii(".\r\n"); + ieee_putascii(".\n"); return (start); } static int32_t ieee_putlr(struct ieeeFixupp *p) @@ -1235,7 +1264,7 @@ static int32_t ieee_putlr(struct ieeeFixupp *p) sprintf(buf, "X%"PRIX32",Y%"PRIX32",+,L%"PRIX32",-", p->id2, p->id2, p->id1); break; } - ieee_putascii("LR(%s,%"PRIX32").\r\n", buf, size); + ieee_putascii("LR(%s,%"PRIX32").\n", buf, size); return (size); } @@ -1472,9 +1501,9 @@ static struct dfmt *ladsoft_debug_arr[3] = { struct ofmt of_ieee = { "IEEE-695 (LADsoft variant) object file format", "ieee", - NULL, + OFMT_TEXT, ladsoft_debug_arr, - &null_debug_form, + &ladsoft_debug_form, NULL, ieee_init, ieee_set_info, diff --git a/output/outmacho32.c b/output/outmacho32.c deleted file mode 100644 index 6b6cfaba..00000000 --- a/output/outmacho32.c +++ /dev/null @@ -1,1353 +0,0 @@ -/* outmacho32.c output routines for the Netwide Assembler to produce - * NeXTstep/OpenStep/Rhapsody/Darwin/MacOS X (i386) object files - * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. - */ - -/* Most of this file is, like Mach-O itself, based on a.out. For more - * guidelines see outaout.c. */ - -#include "compiler.h" - -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <ctype.h> -#include <inttypes.h> - -#include "nasm.h" -#include "nasmlib.h" -#include "saa.h" -#include "raa.h" -#include "outform.h" -#include "compiler.h" - -#if defined(OF_MACHO32) - -/* Mach-O in-file header structure sizes */ -#define MACHO_HEADER_SIZE (28) -#define MACHO_SEGCMD_SIZE (56) -#define MACHO_SECTCMD_SIZE (68) -#define MACHO_SYMCMD_SIZE (24) -#define MACHO_NLIST_SIZE (12) -#define MACHO_RELINFO_SIZE (8) - -/* Mach-O file header values */ -#define MH_MAGIC (0xfeedface) -#define CPU_TYPE_I386 (7) /* x86 platform */ -#define CPU_SUBTYPE_I386_ALL (3) /* all-x86 compatible */ -#define MH_OBJECT (0x1) /* object file */ - -#define LC_SEGMENT (0x1) /* segment load command */ -#define LC_SYMTAB (0x2) /* symbol table load command */ - -#define VM_PROT_NONE (0x00) -#define VM_PROT_READ (0x01) -#define VM_PROT_WRITE (0x02) -#define VM_PROT_EXECUTE (0x04) - -#define VM_PROT_DEFAULT (VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE) -#define VM_PROT_ALL (VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE) - -struct section { - /* nasm internal data */ - struct section *next; - struct SAA *data; - int32_t index; - struct reloc *relocs; - int align; - - /* data that goes into the file */ - char sectname[16]; /* what this section is called */ - char segname[16]; /* segment this section will be in */ - uint32_t size; /* in-memory and -file size */ - uint32_t nreloc; /* relocation entry count */ - uint32_t flags; /* type and attributes (masked) */ -}; - -#define SECTION_TYPE 0x000000ff /* section type mask */ - -#define S_REGULAR (0x0) /* standard section */ -#define S_ZEROFILL (0x1) /* zerofill, in-memory only */ - -#define SECTION_ATTRIBUTES_SYS 0x00ffff00 /* system setable attributes */ -#define S_ATTR_SOME_INSTRUCTIONS 0x00000400 /* section contains some - machine instructions */ -#define S_ATTR_EXT_RELOC 0x00000200 /* section has external - relocation entries */ -#define S_ATTR_LOC_RELOC 0x00000100 /* section has local - relocation entries */ - - -static struct sectmap { - const char *nasmsect; - const char *segname; - const char *sectname; - const int32_t flags; -} sectmap[] = { - {".text", "__TEXT", "__text", S_REGULAR|S_ATTR_SOME_INSTRUCTIONS}, - {".data", "__DATA", "__data", S_REGULAR}, - {".rodata", "__DATA", "__const", S_REGULAR}, - {".bss", "__DATA", "__bss", S_ZEROFILL}, - {NULL, NULL, NULL, 0} -}; - -struct reloc { - /* nasm internal data */ - struct reloc *next; - - /* data that goes into the file */ - int32_t addr; /* op's offset in section */ - unsigned int snum:24, /* contains symbol index if - ** ext otherwise in-file - ** section number */ - pcrel:1, /* relative relocation */ - length:2, /* 0=byte, 1=word, 2=int32_t */ - ext:1, /* external symbol referenced */ - type:4; /* reloc type, 0 for us */ -}; - -#define R_ABS 0 /* absolute relocation */ -#define R_SCATTERED 0x80000000 /* reloc entry is scattered if - ** highest bit == 1 */ - -struct symbol { - /* nasm internal data */ - struct symbol *next; /* next symbol in the list */ - char *name; /* name of this symbol */ - int32_t initial_snum; /* symbol number used above in - reloc */ - int32_t snum; /* true snum for reloc */ - - /* data that goes into the file */ - int32_t strx; /* string table index */ - uint8_t type; /* symbol type */ - uint8_t sect; /* NO_SECT or section number */ - int16_t desc; /* for stab debugging, 0 for us */ - uint32_t value; /* offset of symbol in section */ -}; - -/* symbol type bits */ -#define N_EXT 0x01 /* global or external symbol */ - -#define N_UNDF 0x0 /* undefined symbol | n_sect == */ -#define N_ABS 0x2 /* absolute symbol | NO_SECT */ -#define N_SECT 0xe /* defined symbol, n_sect holds - ** section number */ - -#define N_TYPE 0x0e /* type bit mask */ - -#define DEFAULT_SECTION_ALIGNMENT 0 /* byte (i.e. no) alignment */ - -/* special section number values */ -#define NO_SECT 0 /* no section, invalid */ -#define MAX_SECT 255 /* maximum number of sections */ - -static struct section *sects, **sectstail; -static struct symbol *syms, **symstail; -static uint32_t nsyms; - -/* These variables are set by macho_layout_symbols() to organize - the symbol table and string table in order the dynamic linker - expects. They are then used in macho_write() to put out the - symbols and strings in that order. - - The order of the symbol table is: - local symbols - defined external symbols (sorted by name) - undefined external symbols (sorted by name) - - The order of the string table is: - strings for external symbols - strings for local symbols - */ -static uint32_t ilocalsym = 0; -static uint32_t iextdefsym = 0; -static uint32_t iundefsym = 0; -static uint32_t nlocalsym; -static uint32_t nextdefsym; -static uint32_t nundefsym; -static struct symbol **extdefsyms = NULL; -static struct symbol **undefsyms = NULL; - -static struct RAA *extsyms; -static struct SAA *strs; -static uint32_t strslen; - -static FILE *machofp; -static efunc error; -static evalfunc evaluate; - -extern struct ofmt of_macho; - -/* Global file information. This should be cleaned up into either - a structure or as function arguments. */ -uint32_t head_ncmds = 0; -uint32_t head_sizeofcmds = 0; -uint32_t seg_filesize = 0; -uint32_t seg_vmsize = 0; -uint32_t seg_nsects = 0; -uint32_t rel_padcnt = 0; - - -#define xstrncpy(xdst, xsrc) \ - memset(xdst, '\0', sizeof(xdst)); /* zero out whole buffer */ \ - strncpy(xdst, xsrc, sizeof(xdst)); /* copy over string */ \ - xdst[sizeof(xdst) - 1] = '\0'; /* proper null-termination */ - -#define align(x, y) \ - (((x) + (y) - 1) & ~((y) - 1)) /* align x to multiple of y */ - -#define alignint32_t(x) \ - align(x, sizeof(int32_t)) /* align x to int32_t boundary */ - -static void debug_reloc (struct reloc *); -static void debug_section_relocs (struct section *) _unused; - -static int exact_log2 (uint32_t align) -{ - if (align == 0) { - return 0; - } else if (align & (align-1)) { - return -1; /* Not a power of 2 */ - } else { -#ifdef HAVE_GNUC_4 - return __builtin_ctzl (align); -#else - uint32_t result = 0; - - /* We know exactly one bit is set at this point. */ - if (align & 0xffff0000) - result |= 16; - if (align & 0xff00ff00) - result |= 8; - if (align & 0xf0f0f0f0) - result |= 4; - if (align & 0xcccccccc) - result |= 2; - if (align & 0xaaaaaaaa) - result |= 1; - - return result; -#endif - } -} - -static struct section *get_section_by_name(const char *segname, - const char *sectname) -{ - struct section *s; - - for (s = sects; s != NULL; s = s->next) - if (!strcmp(s->segname, segname) && !strcmp(s->sectname, sectname)) - break; - - return s; -} - -static struct section *get_section_by_index(const int32_t index) -{ - struct section *s; - - for (s = sects; s != NULL; s = s->next) - if (index == s->index) - break; - - return s; -} - -static int32_t get_section_index_by_name(const char *segname, - const char *sectname) -{ - struct section *s; - - for (s = sects; s != NULL; s = s->next) - if (!strcmp(s->segname, segname) && !strcmp(s->sectname, sectname)) - return s->index; - - return -1; -} - -static char *get_section_name_by_index(const int32_t index) -{ - struct section *s; - - for (s = sects; s != NULL; s = s->next) - if (index == s->index) - return s->sectname; - - return NULL; -} - -static uint8_t get_section_fileindex_by_index(const int32_t index) -{ - struct section *s; - uint8_t i = 1; - - for (s = sects; s != NULL && i < MAX_SECT; s = s->next, ++i) - if (index == s->index) - return i; - - if (i == MAX_SECT) - error(ERR_WARNING, - "too many sections (>255) - clipped by fileindex"); - - return NO_SECT; -} - -static void macho_init(FILE * fp, efunc errfunc, ldfunc ldef, - evalfunc eval) -{ - char zero = 0; - - machofp = fp; - error = errfunc; - evaluate = eval; - - (void)ldef; /* placate optimisers */ - - sects = NULL; - sectstail = §s; - - syms = NULL; - symstail = &syms; - nsyms = 0; - nlocalsym = 0; - nextdefsym = 0; - nundefsym = 0; - - extsyms = raa_init(); - strs = saa_init(1L); - - /* string table starts with a zero byte - don't ask why */ - saa_wbytes(strs, &zero, sizeof(char)); - strslen = 1; -} - -static int macho_setinfo(enum geninfo type, char **val) -{ - (void)type; - (void)val; - return 0; -} - -static void sect_write(struct section *sect, - const uint8_t *data, uint32_t len) -{ - saa_wbytes(sect->data, data, len); - sect->size += len; -} - -static void add_reloc(struct section *sect, int32_t section, - int pcrel, int bytes) -{ - struct reloc *r; - int32_t fi; - - /* NeXT as puts relocs in reversed order (address-wise) into the - ** files, so we do the same, doesn't seem to make much of a - ** difference either way */ - r = nasm_malloc(sizeof(struct reloc)); - r->next = sect->relocs; - sect->relocs = r; - - /* the current end of the section will be the symbol's address for - ** now, might have to be fixed by macho_fixup_relocs() later on. make - ** sure we don't make the symbol scattered by setting the highest - ** bit by accident */ - r->addr = sect->size & ~R_SCATTERED; - r->ext = 0; - r->pcrel = pcrel; - - /* match byte count 1, 2, 4 to length codes 0, 1, 2 respectively */ - r->length = bytes >> 1; - - /* vanilla relocation (GENERIC_RELOC_VANILLA) */ - r->type = 0; - - if (section == NO_SEG) { - /* absolute local symbol if no section index given */ - r->snum = R_ABS; - } else { - fi = get_section_fileindex_by_index(section); - - if (fi == NO_SECT) { - /* external symbol if no section with that index known, - ** symbol number was saved in macho_symdef() */ - r->snum = raa_read(extsyms, section); - r->ext = 1; - } else { - /* local symbol in section fi */ - r->snum = fi; - } - } - - ++sect->nreloc; -} - -static void macho_output(int32_t secto, const void *data, - enum out_type type, uint64_t size, - int32_t section, int32_t wrt) -{ - struct section *s, *sbss; - int32_t addr; - uint8_t mydata[4], *p; - - if (wrt != NO_SEG) { - wrt = NO_SEG; - error(ERR_NONFATAL, "WRT not supported by Mach-O output format"); - /* continue to do _something_ */ - } - - if (secto == NO_SEG) { - if (type != OUT_RESERVE) - error(ERR_NONFATAL, "attempt to assemble code in " - "[ABSOLUTE] space"); - - return; - } - - s = get_section_by_index(secto); - - if (s == NULL) { - error(ERR_WARNING, "attempt to assemble code in" - " section %d: defaulting to `.text'", secto); - s = get_section_by_name("__TEXT", "__text"); - - /* should never happen */ - if (s == NULL) - error(ERR_PANIC, "text section not found"); - } - - sbss = get_section_by_name("__DATA", "__bss"); - - if (s == sbss && type != OUT_RESERVE) { - error(ERR_WARNING, "attempt to initialize memory in the" - " BSS section: ignored"); - - switch (type) { - case OUT_REL2ADR: - size = 2; - break; - - case OUT_REL4ADR: - size = 4; - break; - - default: - break; - } - - s->size += size; - return; - } - - switch (type) { - case OUT_RESERVE: - if (s != sbss) { - error(ERR_WARNING, "uninitialized space declared in" - " %s section: zeroing", - get_section_name_by_index(secto)); - - sect_write(s, NULL, size); - } else - s->size += size; - - break; - - case OUT_RAWDATA: - if (section != NO_SEG) - error(ERR_PANIC, "OUT_RAWDATA with other than NO_SEG"); - - sect_write(s, data, size); - break; - - case OUT_ADDRESS: - addr = *(int64_t *)data; - - if (section != NO_SEG) { - if (section % 2) { - error(ERR_NONFATAL, "Mach-O format does not support" - " section base references"); - } else - add_reloc(s, section, 0, size); - } - - p = mydata; - WRITEADDR(p, addr, size); - sect_write(s, mydata, size); - break; - - case OUT_REL2ADR: - if (section == secto) - error(ERR_PANIC, "intra-section OUT_REL2ADR"); - - if (section != NO_SEG && section % 2) { - error(ERR_NONFATAL, "Mach-O format does not support" - " section base references"); - } else - add_reloc(s, section, 1, 2); - - p = mydata; - WRITESHORT(p, *(int32_t *)data - (size + s->size)); - sect_write(s, mydata, 2L); - break; - - case OUT_REL4ADR: - if (section == secto) - error(ERR_PANIC, "intra-section OUT_REL4ADR"); - - if (section != NO_SEG && section % 2) { - error(ERR_NONFATAL, "Mach-O format does not support" - " section base references"); - } else - add_reloc(s, section, 1, 4); - - p = mydata; - WRITELONG(p, *(int32_t *)data - (size + s->size)); - sect_write(s, mydata, 4L); - break; - - default: - error(ERR_PANIC, "unknown output type?"); - break; - } -} - -static int32_t macho_section(char *name, int pass, int *bits) -{ - int32_t index, originalIndex; - char *sectionAttributes; - struct sectmap *sm; - struct section *s; - - (void)pass; - - /* Default to 32 bits. */ - if (!name) { - *bits = 32; - name = ".text"; - sectionAttributes = NULL; - } else { - sectionAttributes = name; - name = nasm_strsep(§ionAttributes, " \t"); - } - - for (sm = sectmap; sm->nasmsect != NULL; ++sm) { - /* make lookup into section name translation table */ - if (!strcmp(name, sm->nasmsect)) { - char *currentAttribute; - - /* try to find section with that name */ - originalIndex = index = get_section_index_by_name(sm->segname, - sm->sectname); - - /* create it if it doesn't exist yet */ - if (index == -1) { - s = *sectstail = nasm_malloc(sizeof(struct section)); - s->next = NULL; - sectstail = &s->next; - - s->data = saa_init(1L); - s->index = seg_alloc(); - s->relocs = NULL; - s->align = -1; - - xstrncpy(s->segname, sm->segname); - xstrncpy(s->sectname, sm->sectname); - s->size = 0; - s->nreloc = 0; - s->flags = sm->flags; - - index = s->index; - } else { - s = get_section_by_index(index); - } - - while ((NULL != sectionAttributes) - && (currentAttribute = nasm_strsep(§ionAttributes, " \t"))) { - if (0 != *currentAttribute) { - if (!nasm_strnicmp("align=", currentAttribute, 6)) { - char *end; - int newAlignment, value; - - value = strtoul(currentAttribute + 6, (char**)&end, 0); - newAlignment = exact_log2(value); - - if (0 != *end) { - error(ERR_PANIC, - "unknown or missing alignment value \"%s\" " - "specified for section \"%s\"", - currentAttribute + 6, - name); - return NO_SEG; - } else if (0 > newAlignment) { - error(ERR_PANIC, - "alignment of %d (for section \"%s\") is not " - "a power of two", - value, - name); - return NO_SEG; - } - - if ((-1 != originalIndex) - && (s->align != newAlignment) - && (s->align != -1)) { - error(ERR_PANIC, - "section \"%s\" has already been specified " - "with alignment %d, conflicts with new " - "alignment of %d", - name, - (1 << s->align), - value); - return NO_SEG; - } - - s->align = newAlignment; - } else if (!nasm_stricmp("data", currentAttribute)) { - /* Do nothing; 'data' is implicit */ - } else { - error(ERR_PANIC, - "unknown section attribute %s for section %s", - currentAttribute, - name); - return NO_SEG; - } - } - } - - return index; - } - } - - error(ERR_PANIC, "invalid section name %s", name); - return NO_SEG; -} - -static void macho_symdef(char *name, int32_t section, int64_t offset, - int is_global, char *special) -{ - struct symbol *sym; - - if (special) { - error(ERR_NONFATAL, "The Mach-O output format does " - "not support any special symbol types"); - return; - } - - if (is_global == 3) { - error(ERR_NONFATAL, "The Mach-O format does not " - "(yet) support forward reference fixups."); - return; - } - - sym = *symstail = nasm_malloc(sizeof(struct symbol)); - sym->next = NULL; - symstail = &sym->next; - - sym->name = name; - sym->strx = strslen; - sym->type = 0; - sym->desc = 0; - sym->value = offset; - sym->initial_snum = -1; - - /* external and common symbols get N_EXT */ - if (is_global != 0) - sym->type |= N_EXT; - - if (section == NO_SEG) { - /* symbols in no section get absolute */ - sym->type |= N_ABS; - sym->sect = NO_SECT; - } else { - sym->type |= N_SECT; - - /* get the in-file index of the section the symbol was defined in */ - sym->sect = get_section_fileindex_by_index(section); - - if (sym->sect == NO_SECT) { - /* remember symbol number of references to external - ** symbols, this works because every external symbol gets - ** its own section number allocated internally by nasm and - ** can so be used as a key */ - extsyms = raa_write(extsyms, section, nsyms); - sym->initial_snum = nsyms; - - switch (is_global) { - case 1: - case 2: - /* there isn't actually a difference between global - ** and common symbols, both even have their size in - ** sym->value */ - sym->type = N_EXT; - break; - - default: - /* give an error on unfound section if it's not an - ** external or common symbol (assemble_file() does a - ** seg_alloc() on every call for them) */ - error(ERR_PANIC, "in-file index for section %d not found", - section); - } - } - } - - ++nsyms; -} - -static int32_t macho_segbase(int32_t section) -{ - return section; -} - -static int macho_directive(char *directive, char *value, int pass) -{ - (void)directive; - (void)value; - (void)pass; - return 0; -} - -static void macho_filename(char *inname, char *outname, efunc error) -{ - standard_extension(inname, outname, ".o", error); -} - -extern macros_t generic_stdmac[]; - -/* Comparison function for qsort symbol layout. */ -static int layout_compare (const struct symbol **s1, - const struct symbol **s2) -{ - return (strcmp ((*s1)->name, (*s2)->name)); -} - -/* The native assembler does a few things in a similar function - - * Remove temporary labels - * Sort symbols according to local, external, undefined (by name) - * Order the string table - - We do not remove temporary labels right now. - - numsyms is the total number of symbols we have. strtabsize is the - number entries in the string table. */ - -static void macho_layout_symbols (uint32_t *numsyms, - uint32_t *strtabsize) -{ - struct symbol *sym, **symp; - uint32_t i,j; - - *numsyms = 0; - *strtabsize = sizeof (char); - - symp = &syms; - - while ((sym = *symp)) { - /* Undefined symbols are now external. */ - if (sym->type == N_UNDF) - sym->type |= N_EXT; - - if ((sym->type & N_EXT) == 0) { - sym->snum = *numsyms; - *numsyms = *numsyms + 1; - nlocalsym++; - } - else { - if ((sym->type & N_TYPE) != N_UNDF) - nextdefsym++; - else - nundefsym++; - - /* If we handle debug info we'll want - to check for it here instead of just - adding the symbol to the string table. */ - sym->strx = *strtabsize; - saa_wbytes (strs, sym->name, (int32_t)(strlen(sym->name) + 1)); - *strtabsize += strlen(sym->name) + 1; - } - symp = &(sym->next); - } - - /* Next, sort the symbols. Most of this code is a direct translation from - the Apple cctools symbol layout. We need to keep compatibility with that. */ - /* Set the indexes for symbol groups into the symbol table */ - ilocalsym = 0; - iextdefsym = nlocalsym; - iundefsym = nlocalsym + nextdefsym; - - /* allocate arrays for sorting externals by name */ - extdefsyms = nasm_malloc(nextdefsym * sizeof(struct symbol *)); - undefsyms = nasm_malloc(nundefsym * sizeof(struct symbol *)); - - i = 0; - j = 0; - - symp = &syms; - - while ((sym = *symp)) { - - if((sym->type & N_EXT) == 0) { - sym->strx = *strtabsize; - saa_wbytes (strs, sym->name, (int32_t)(strlen (sym->name) + 1)); - *strtabsize += strlen(sym->name) + 1; - } - else { - if((sym->type & N_TYPE) != N_UNDF) - extdefsyms[i++] = sym; - else - undefsyms[j++] = sym; - } - symp = &(sym->next); - } - - qsort(extdefsyms, nextdefsym, sizeof(struct symbol *), - (int (*)(const void *, const void *))layout_compare); - qsort(undefsyms, nundefsym, sizeof(struct symbol *), - (int (*)(const void *, const void *))layout_compare); - - for(i = 0; i < nextdefsym; i++) { - extdefsyms[i]->snum = *numsyms; - *numsyms += 1; - } - for(j = 0; j < nundefsym; j++) { - undefsyms[j]->snum = *numsyms; - *numsyms += 1; - } -} - -/* Calculate some values we'll need for writing later. */ - -static void macho_calculate_sizes (void) -{ - struct section *s; - - /* count sections and calculate in-memory and in-file offsets */ - for (s = sects; s != NULL; s = s->next) { - /* zerofill sections aren't actually written to the file */ - if ((s->flags & SECTION_TYPE) != S_ZEROFILL) - seg_filesize += s->size; - - seg_vmsize += s->size; - ++seg_nsects; - } - - /* calculate size of all headers, load commands and sections to - ** get a pointer to the start of all the raw data */ - if (seg_nsects > 0) { - ++head_ncmds; - head_sizeofcmds += - MACHO_SEGCMD_SIZE + seg_nsects * MACHO_SECTCMD_SIZE; - } - - if (nsyms > 0) { - ++head_ncmds; - head_sizeofcmds += MACHO_SYMCMD_SIZE; - } -} - -/* Write out the header information for the file. */ - -static void macho_write_header (void) -{ - fwriteint32_t(MH_MAGIC, machofp); /* magic */ - fwriteint32_t(CPU_TYPE_I386, machofp); /* CPU type */ - fwriteint32_t(CPU_SUBTYPE_I386_ALL, machofp); /* CPU subtype */ - fwriteint32_t(MH_OBJECT, machofp); /* Mach-O file type */ - fwriteint32_t(head_ncmds, machofp); /* number of load commands */ - fwriteint32_t(head_sizeofcmds, machofp); /* size of load commands */ - fwriteint32_t(0, machofp); /* no flags */ -} - -/* Write out the segment load command at offset. */ - -static uint32_t macho_write_segment (uint32_t offset) -{ - uint32_t s_addr = 0; - uint32_t rel_base = alignint32_t (offset + seg_filesize); - uint32_t s_reloff = 0; - struct section *s; - - fwriteint32_t(LC_SEGMENT, machofp); /* cmd == LC_SEGMENT */ - - /* size of load command including section load commands */ - fwriteint32_t(MACHO_SEGCMD_SIZE + seg_nsects * - MACHO_SECTCMD_SIZE, machofp); - - /* in an MH_OBJECT file all sections are in one unnamed (name - ** all zeros) segment */ - fwrite("\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0", 16, 1, machofp); - fwriteint32_t(0, machofp); /* in-memory offset */ - fwriteint32_t(seg_vmsize, machofp); /* in-memory size */ - fwriteint32_t(offset, machofp); /* in-file offset to data */ - fwriteint32_t(seg_filesize, machofp); /* in-file size */ - fwriteint32_t(VM_PROT_DEFAULT, machofp); /* maximum vm protection */ - fwriteint32_t(VM_PROT_DEFAULT, machofp); /* initial vm protection */ - fwriteint32_t(seg_nsects, machofp); /* number of sections */ - fwriteint32_t(0, machofp); /* no flags */ - - /* emit section headers */ - for (s = sects; s != NULL; s = s->next) { - fwrite(s->sectname, sizeof(s->sectname), 1, machofp); - fwrite(s->segname, sizeof(s->segname), 1, machofp); - fwriteint32_t(s_addr, machofp); - fwriteint32_t(s->size, machofp); - - /* dummy data for zerofill sections or proper values */ - if ((s->flags & SECTION_TYPE) != S_ZEROFILL) { - fwriteint32_t(offset, machofp); - /* Write out section alignment, as a power of two. - e.g. 32-bit word alignment would be 2 (2^^2 = 4). */ - if (s->align == -1) - s->align = DEFAULT_SECTION_ALIGNMENT; - fwriteint32_t(s->align, machofp); - /* To be compatible with cctools as we emit - a zero reloff if we have no relocations. */ - fwriteint32_t(s->nreloc ? rel_base + s_reloff : 0, machofp); - fwriteint32_t(s->nreloc, machofp); - - offset += s->size; - s_reloff += s->nreloc * MACHO_RELINFO_SIZE; - } else { - fwriteint32_t(0, machofp); - fwriteint32_t(0, machofp); - fwriteint32_t(0, machofp); - fwriteint32_t(0, machofp); - } - - fwriteint32_t(s->flags, machofp); /* flags */ - fwriteint32_t(0, machofp); /* reserved */ - fwriteint32_t(0, machofp); /* reserved */ - - s_addr += s->size; - } - - rel_padcnt = rel_base - offset; - offset = rel_base + s_reloff; - - return offset; -} - -/* For a given chain of relocs r, write out the entire relocation - chain to the object file. */ - -static void macho_write_relocs (struct reloc *r) -{ - while (r) { - uint32_t word2; - - fwriteint32_t(r->addr, machofp); /* reloc offset */ - - word2 = r->snum; - word2 |= r->pcrel << 24; - word2 |= r->length << 25; - word2 |= r->ext << 27; - word2 |= r->type << 28; - fwriteint32_t(word2, machofp); /* reloc data */ - - r = r->next; - } -} - -/* Write out the section data. */ -static void macho_write_section (void) -{ - struct section *s, *s2; - struct reloc *r; - char *rel_paddata = "\0\0\0"; - uint8_t fi, *p, *q, blk[4]; - int32_t l; - - for (s = sects; s != NULL; s = s->next) { - if ((s->flags & SECTION_TYPE) == S_ZEROFILL) - continue; - - /* no padding needs to be done to the sections */ - - /* Like a.out Mach-O references things in the data or bss - * sections by addresses which are actually relative to the - * start of the _text_ section, in the _file_. See outaout.c - * for more information. */ - saa_rewind(s->data); - for (r = s->relocs; r != NULL; r = r->next) { - saa_fread(s->data, r->addr, blk, (int32_t)r->length << 1); - p = q = blk; - l = *p++; - - /* get offset based on relocation type */ - if (r->length > 0) { - l += ((int32_t)*p++) << 8; - - if (r->length == 2) { - l += ((int32_t)*p++) << 16; - l += ((int32_t)*p++) << 24; - } - } - - /* If the relocation is internal add to the current section - offset. Otherwise the only value we need is the symbol - offset which we already have. The linker takes care - of the rest of the address. */ - if (!r->ext) { - /* add sizes of previous sections to current offset */ - for (s2 = sects, fi = 1; - s2 != NULL && fi < r->snum; s2 = s2->next, fi++) - l += s2->size; - } - - /* write new offset back */ - if (r->length == 2) - WRITELONG(q, l); - else if (r->length == 1) - WRITESHORT(q, l); - else - *q++ = l & 0xFF; - - saa_fwrite(s->data, r->addr, blk, (int32_t)r->length << 1); - } - - /* dump the section data to file */ - saa_fpwrite(s->data, machofp); - } - - /* pad last section up to reloc entries on int32_t boundary */ - fwrite(rel_paddata, rel_padcnt, 1, machofp); - - /* emit relocation entries */ - for (s = sects; s != NULL; s = s->next) - macho_write_relocs (s->relocs); -} - -/* Write out the symbol table. We should already have sorted this - before now. */ -static void macho_write_symtab (void) -{ - struct symbol *sym; - struct section *s; - int32_t fi; - uint32_t i; - - /* we don't need to pad here since MACHO_RELINFO_SIZE == 8 */ - - for (sym = syms; sym != NULL; sym = sym->next) { - if ((sym->type & N_EXT) == 0) { - fwriteint32_t(sym->strx, machofp); /* string table entry number */ - fwrite(&sym->type, 1, 1, machofp); /* symbol type */ - fwrite(&sym->sect, 1, 1, machofp); /* section */ - fwriteint16_t(sym->desc, machofp); /* description */ - - /* Fix up the symbol value now that we know the final section - sizes. */ - if (((sym->type & N_TYPE) == N_SECT) && (sym->sect != NO_SECT)) { - for (s = sects, fi = 1; - s != NULL && fi < sym->sect; s = s->next, ++fi) - sym->value += s->size; - } - - fwriteint32_t(sym->value, machofp); /* value (i.e. offset) */ - } - } - - for (i = 0; i < nextdefsym; i++) { - sym = extdefsyms[i]; - fwriteint32_t(sym->strx, machofp); - fwrite(&sym->type, 1, 1, machofp); /* symbol type */ - fwrite(&sym->sect, 1, 1, machofp); /* section */ - fwriteint16_t(sym->desc, machofp); /* description */ - - /* Fix up the symbol value now that we know the final section - sizes. */ - if (((sym->type & N_TYPE) == N_SECT) && (sym->sect != NO_SECT)) { - for (s = sects, fi = 1; - s != NULL && fi < sym->sect; s = s->next, ++fi) - sym->value += s->size; - } - - fwriteint32_t(sym->value, machofp); /* value (i.e. offset) */ - } - - for (i = 0; i < nundefsym; i++) { - sym = undefsyms[i]; - fwriteint32_t(sym->strx, machofp); - fwrite(&sym->type, 1, 1, machofp); /* symbol type */ - fwrite(&sym->sect, 1, 1, machofp); /* section */ - fwriteint16_t(sym->desc, machofp); /* description */ - - /* Fix up the symbol value now that we know the final section - sizes. */ - if (((sym->type & N_TYPE) == N_SECT) && (sym->sect != NO_SECT)) { - for (s = sects, fi = 1; - s != NULL && fi < sym->sect; s = s->next, ++fi) - sym->value += s->size; - } - - fwriteint32_t(sym->value, machofp); /* value (i.e. offset) */ - } -} - -/* Fixup the snum in the relocation entries, we should be - doing this only for externally undefined symbols. */ -static void macho_fixup_relocs (struct reloc *r) -{ - struct symbol *sym; - uint32_t i; - - while (r != NULL) { - if (r->ext) { - for (i = 0; i < nundefsym; i++) { - sym = undefsyms[i]; - if (sym->initial_snum == r->snum) { - r->snum = sym->snum; - break; - } - } - } - r = r->next; - } -} - -/* Write out the object file. */ - -static void macho_write (void) -{ - uint32_t offset = 0; - - /* mach-o object file structure: - ** - ** mach header - ** uint32_t magic - ** int cpu type - ** int cpu subtype - ** uint32_t mach file type - ** uint32_t number of load commands - ** uint32_t size of all load commands - ** (includes section struct size of segment command) - ** uint32_t flags - ** - ** segment command - ** uint32_t command type == LC_SEGMENT - ** uint32_t size of load command - ** (including section load commands) - ** char[16] segment name - ** uint32_t in-memory offset - ** uint32_t in-memory size - ** uint32_t in-file offset to data area - ** uint32_t in-file size - ** (in-memory size excluding zerofill sections) - ** int maximum vm protection - ** int initial vm protection - ** uint32_t number of sections - ** uint32_t flags - ** - ** section commands - ** char[16] section name - ** char[16] segment name - ** uint32_t in-memory offset - ** uint32_t in-memory size - ** uint32_t in-file offset - ** uint32_t alignment - ** (irrelevant in MH_OBJECT) - ** uint32_t in-file offset of relocation entires - ** uint32_t number of relocations - ** uint32_t flags - ** uint32_t reserved - ** uint32_t reserved - ** - ** symbol table command - ** uint32_t command type == LC_SYMTAB - ** uint32_t size of load command - ** uint32_t symbol table offset - ** uint32_t number of symbol table entries - ** uint32_t string table offset - ** uint32_t string table size - ** - ** raw section data - ** - ** padding to int32_t boundary - ** - ** relocation data (struct reloc) - ** int32_t offset - ** uint data (symbolnum, pcrel, length, extern, type) - ** - ** symbol table data (struct nlist) - ** int32_t string table entry number - ** uint8_t type - ** (extern, absolute, defined in section) - ** uint8_t section - ** (0 for global symbols, section number of definition (>= 1, <= - ** 254) for local symbols, size of variable for common symbols - ** [type == extern]) - ** int16_t description - ** (for stab debugging format) - ** uint32_t value (i.e. file offset) of symbol or stab offset - ** - ** string table data - ** list of null-terminated strings - */ - - /* Emit the Mach-O header. */ - macho_write_header(); - - offset = MACHO_HEADER_SIZE + head_sizeofcmds; - - /* emit the segment load command */ - if (seg_nsects > 0) - offset = macho_write_segment (offset); - else - error(ERR_WARNING, "no sections?"); - - if (nsyms > 0) { - /* write out symbol command */ - fwriteint32_t(LC_SYMTAB, machofp); /* cmd == LC_SYMTAB */ - fwriteint32_t(MACHO_SYMCMD_SIZE, machofp); /* size of load command */ - fwriteint32_t(offset, machofp); /* symbol table offset */ - fwriteint32_t(nsyms, machofp); /* number of symbol - ** table entries */ - - offset += nsyms * MACHO_NLIST_SIZE; - fwriteint32_t(offset, machofp); /* string table offset */ - fwriteint32_t(strslen, machofp); /* string table size */ - } - - /* emit section data */ - if (seg_nsects > 0) - macho_write_section (); - - /* emit symbol table if we have symbols */ - if (nsyms > 0) - macho_write_symtab (); - - /* we don't need to pad here since MACHO_NLIST_SIZE == 12 */ - - /* emit string table */ - saa_fpwrite(strs, machofp); -} -/* We do quite a bit here, starting with finalizing all of the data - for the object file, writing, and then freeing all of the data from - the file. */ - -static void macho_cleanup(int debuginfo) -{ - struct section *s; - struct reloc *r; - struct symbol *sym; - - (void)debuginfo; - - /* Sort all symbols. */ - macho_layout_symbols (&nsyms, &strslen); - - /* Fixup relocation entries */ - for (s = sects; s != NULL; s = s->next) { - macho_fixup_relocs (s->relocs); - } - - /* First calculate and finalize needed values. */ - macho_calculate_sizes(); - macho_write(); - - /* done - yay! */ - fclose(machofp); - - /* free up everything */ - while (sects->next) { - s = sects; - sects = sects->next; - - saa_free(s->data); - while (s->relocs != NULL) { - r = s->relocs; - s->relocs = s->relocs->next; - nasm_free(r); - } - - nasm_free(s); - } - - saa_free(strs); - raa_free(extsyms); - - if (syms) { - while (syms->next) { - sym = syms; - syms = syms->next; - - nasm_free (sym); - } -} -} - -/* Debugging routines. */ -static void debug_reloc (struct reloc *r) -{ - fprintf (stdout, "reloc:\n"); - fprintf (stdout, "\taddr: %"PRId32"\n", r->addr); - fprintf (stdout, "\tsnum: %d\n", r->snum); - fprintf (stdout, "\tpcrel: %d\n", r->pcrel); - fprintf (stdout, "\tlength: %d\n", r->length); - fprintf (stdout, "\text: %d\n", r->ext); - fprintf (stdout, "\ttype: %d\n", r->type); -} - -static void debug_section_relocs (struct section *s) -{ - struct reloc *r = s->relocs; - - fprintf (stdout, "relocs for section %s:\n\n", s->sectname); - - while (r != NULL) { - debug_reloc (r); - r = r->next; - } -} - -struct ofmt of_macho32 = { - "NeXTstep/OpenStep/Rhapsody/Darwin/MacOS X (i386) object files", - "macho32", - NULL, - null_debug_arr, - &null_debug_form, - generic_stdmac, - macho_init, - macho_setinfo, - macho_output, - macho_symdef, - macho_section, - macho_segbase, - macho_directive, - macho_filename, - macho_cleanup -}; - -struct ofmt of_macho = { - "MACHO (short name for MACHO32)", - "macho", - NULL, - null_debug_arr, - &null_debug_form, - generic_stdmac, - macho_init, - macho_setinfo, - macho_output, - macho_symdef, - macho_section, - macho_segbase, - macho_directive, - macho_filename, - macho_cleanup -}; - -#endif - -/* - * Local Variables: - * mode:c - * c-basic-offset:4 - * End: - * - * end of file */ diff --git a/output/outmacho64.c b/output/outmacho64.c deleted file mode 100644 index d61d3b88..00000000 --- a/output/outmacho64.c +++ /dev/null @@ -1,1536 +0,0 @@ -/* ----------------------------------------------------------------------- * - * - * Copyright 1996-2009 The NASM Authors - All Rights Reserved - * See the file AUTHORS included with the NASM distribution for - * the specific copyright holders. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as - * published by the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston MA 02110-1301, USA; version 2.1, - * or, at your option, any later version, incorporated herein by - * reference. - * - * Patches submitted to this file are required to be dual licensed - * under the LGPL 2.1+ and the 2-clause BSD license: - * - * Copyright 1996-2009 the NASM Authors - All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following - * conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * ----------------------------------------------------------------------- */ - -/* - * outmacho64.c output routines for the Netwide Assembler to produce - * NeXTstep/OpenStep/Rhapsody/Darwin/MacOS X (x86_64) object files - */ - -/* Most of this file is, like Mach-O itself, based on a.out. For more - * guidelines see outaout.c. */ - -#include "compiler.h" - -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <ctype.h> -#include <inttypes.h> - -#include "nasm.h" -#include "nasmlib.h" -#include "saa.h" -#include "raa.h" -#include "output/outform.h" -#include "output/outlib.h" - -#if defined(OF_MACHO64) - -/* Mach-O in-file header structure sizes */ -#define MACHO_HEADER64_SIZE (32) -#define MACHO_SEGCMD64_SIZE (72) -#define MACHO_SECTCMD64_SIZE (80) -#define MACHO_SYMCMD_SIZE (24) -#define MACHO_NLIST64_SIZE (16) -#define MACHO_RELINFO64_SIZE (8) - -/* Mach-O file header values */ -#define MH_MAGIC_64 (0xfeedfacf) -#define CPU_TYPE_X86_64 (0x01000007) /* x86-64 platform */ -#define CPU_SUBTYPE_I386_ALL (3) /* all-x86 compatible */ -#define MH_OBJECT (0x1) /* object file */ - -#define LC_SEGMENT_64 (0x19) /* segment load command */ -#define LC_SYMTAB (0x2) /* symbol table load command */ - -#define VM_PROT_NONE (0x00) -#define VM_PROT_READ (0x01) -#define VM_PROT_WRITE (0x02) -#define VM_PROT_EXECUTE (0x04) - -#define VM_PROT_DEFAULT (VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE) -#define VM_PROT_ALL (VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE) - -struct section { - /* nasm internal data */ - struct section *next; - struct SAA *data; - int32_t index; - struct reloc *relocs; - int align; - - /* data that goes into the file */ - char sectname[16]; /* what this section is called */ - char segname[16]; /* segment this section will be in */ - uint64_t addr; /* in-memory address (subject to alignment) */ - uint64_t size; /* in-memory and -file size */ - uint32_t nreloc; /* relocation entry count */ - uint32_t flags; /* type and attributes (masked) */ - uint32_t extreloc; /* external relocations */ -}; - -#define SECTION_TYPE 0x000000ff /* section type mask */ - -#define S_REGULAR (0x0) /* standard section */ -#define S_ZEROFILL (0x1) /* zerofill, in-memory only */ - -#define SECTION_ATTRIBUTES_SYS 0x00ffff00 /* system setable attributes */ -#define S_ATTR_SOME_INSTRUCTIONS 0x00000400 /* section contains some - machine instructions */ -#define S_ATTR_EXT_RELOC 0x00000200 /* section has external - relocation entries */ -#define S_ATTR_LOC_RELOC 0x00000100 /* section has local - relocation entries */ -#define S_ATTR_PURE_INSTRUCTIONS 0x80000000 /* section uses pure - machine instructions */ - -static struct sectmap { - const char *nasmsect; - const char *segname; - const char *sectname; - const int32_t flags; -} sectmap[] = { - {".text", "__TEXT", "__text", S_REGULAR|S_ATTR_SOME_INSTRUCTIONS|S_ATTR_PURE_INSTRUCTIONS}, - {".data", "__DATA", "__data", S_REGULAR}, - {".rodata", "__DATA", "__const", S_REGULAR}, - {".bss", "__DATA", "__bss", S_ZEROFILL}, - {NULL, NULL, NULL, 0} -}; - -struct reloc { - /* nasm internal data */ - struct reloc *next; - - /* data that goes into the file */ - int32_t addr; /* op's offset in section */ - uint32_t snum:24, /* contains symbol index if - ** ext otherwise in-file - ** section number */ - pcrel:1, /* relative relocation */ - length:2, /* 0=byte, 1=word, 2=int32_t, 3=int64_t */ - ext:1, /* external symbol referenced */ - type:4; /* reloc type */ -}; - -#define R_ABS 0 /* absolute relocation */ -#define R_SCATTERED 0x80000000 /* reloc entry is scattered if - ** highest bit == 1 */ - -struct symbol { - /* nasm internal data */ - struct symbol *next; /* next symbol in the list */ - char *name; /* name of this symbol */ - int32_t initial_snum; /* symbol number used above in - reloc */ - int32_t snum; /* true snum for reloc */ - - /* data that goes into the file */ - uint32_t strx; /* string table index */ - uint8_t type; /* symbol type */ - uint8_t sect; /* NO_SECT or section number */ - uint16_t desc; /* for stab debugging, 0 for us */ - uint64_t value; /* offset of symbol in section */ -}; - -/* symbol type bits */ -#define N_EXT 0x01 /* global or external symbol */ - -#define N_UNDF 0x0 /* undefined symbol | n_sect == */ -#define N_ABS 0x2 /* absolute symbol | NO_SECT */ -#define N_SECT 0xe /* defined symbol, n_sect holds - ** section number */ - -#define N_TYPE 0x0e /* type bit mask */ - -#define DEFAULT_SECTION_ALIGNMENT 0 /* byte (i.e. no) alignment */ - -/* special section number values */ -#define NO_SECT 0 /* no section, invalid */ -#define MAX_SECT 255 /* maximum number of sections */ - -static struct section *sects, **sectstail; -static struct symbol *syms, **symstail; -static uint32_t nsyms; - -/* These variables are set by macho_layout_symbols() to organize - the symbol table and string table in order the dynamic linker - expects. They are then used in macho_write() to put out the - symbols and strings in that order. - - The order of the symbol table is: - local symbols - defined external symbols (sorted by name) - undefined external symbols (sorted by name) - - The order of the string table is: - strings for external symbols - strings for local symbols - */ -static uint32_t ilocalsym = 0; -static uint32_t iextdefsym = 0; -static uint32_t iundefsym = 0; -static uint32_t nlocalsym; -static uint32_t nextdefsym; -static uint32_t nundefsym; -static struct symbol **extdefsyms = NULL; -static struct symbol **undefsyms = NULL; - -static struct RAA *extsyms; -static struct SAA *strs; -static uint32_t strslen; - -static FILE *machofp; -static efunc error; -static evalfunc evaluate; - -extern struct ofmt of_macho64; - -/* Global file information. This should be cleaned up into either - a structure or as function arguments. */ -uint32_t head_ncmds64 = 0; -uint32_t head_sizeofcmds64 = 0; -uint64_t seg_filesize64 = 0; -uint64_t seg_vmsize64 = 0; -uint32_t seg_nsects64 = 0; -uint64_t rel_padcnt64 = 0; - - -#define xstrncpy(xdst, xsrc) \ - memset(xdst, '\0', sizeof(xdst)); /* zero out whole buffer */ \ - strncpy(xdst, xsrc, sizeof(xdst)); /* copy over string */ \ - xdst[sizeof(xdst) - 1] = '\0'; /* proper null-termination */ - -#define align(x, y) \ - (((x) + (y) - 1) & ~((y) - 1)) /* align x to multiple of y */ - -#define alignint32_t(x) \ - align(x, sizeof(int32_t)) /* align x to int32_t boundary */ - -#define alignint64_t(x) \ - align(x, sizeof(int64_t)) /* align x to int64_t boundary */ - -static void debug_reloc (struct reloc *); -static void debug_section_relocs (struct section *) _unused; - -static int exact_log2 (uint32_t align) -{ - if (align == 0) { - return 0; - } else if (align & (align-1)) { - return -1; /* Not a power of 2 */ - } else { -#ifdef HAVE_GNUC_4 - return __builtin_ctzl (align); -#else - uint32_t result = 0; - - /* We know exactly one bit is set at this point. */ - if (align & 0xffff0000) - result |= 16; - if (align & 0xff00ff00) - result |= 8; - if (align & 0xf0f0f0f0) - result |= 4; - if (align & 0xcccccccc) - result |= 2; - if (align & 0xaaaaaaaa) - result |= 1; - - return result; -#endif - } -} - -static struct section *get_section_by_name(const char *segname, - const char *sectname) -{ - struct section *s; - - for (s = sects; s != NULL; s = s->next) - if (!strcmp(s->segname, segname) && !strcmp(s->sectname, sectname)) - break; - - return s; -} - -static struct section *get_section_by_index(const int32_t index) -{ - struct section *s; - - for (s = sects; s != NULL; s = s->next) - if (index == s->index) - break; - - return s; -} - -static int32_t get_section_index_by_name(const char *segname, - const char *sectname) -{ - struct section *s; - - for (s = sects; s != NULL; s = s->next) - if (!strcmp(s->segname, segname) && !strcmp(s->sectname, sectname)) - return s->index; - - return -1; -} - -static char *get_section_name_by_index(const int32_t index) -{ - struct section *s; - - for (s = sects; s != NULL; s = s->next) - if (index == s->index) - return s->sectname; - - return NULL; -} - -static uint8_t get_section_fileindex_by_index(const int32_t index) -{ - struct section *s; - uint8_t i = 1; - - for (s = sects; s != NULL && i < MAX_SECT; s = s->next, ++i) - if (index == s->index) - return i; - - if (i == MAX_SECT) - error(ERR_WARNING, - "too many sections (>255) - clipped by fileindex"); - - return NO_SECT; -} - -static struct symbol *get_closest_section_symbol_by_offset(uint8_t fileindex, int64_t offset) -{ - struct symbol *sym; - - for (sym = syms; sym != NULL; sym = sym->next) { - if ((sym->sect != NO_SECT) && - (sym->sect == fileindex) && - ((int64_t)sym->value >= offset)) - return sym; - } - - return NULL; -} - - -/* - * Special section numbers which are used to define Mach-O special - * symbols, which can be used with WRT to provide PIC relocation - * types. - */ -static int32_t macho_gotpcrel_sect; - -static void macho_init(FILE * fp, efunc errfunc, ldfunc ldef, - evalfunc eval) -{ - char zero = 0; - - maxbits = 64; - machofp = fp; - error = errfunc; - evaluate = eval; - - (void)ldef; /* placate optimizers */ - - sects = NULL; - sectstail = §s; - - syms = NULL; - symstail = &syms; - nsyms = 0; - nlocalsym = 0; - nextdefsym = 0; - nundefsym = 0; - - extsyms = raa_init(); - strs = saa_init(1L); - - /* string table starts with a zero byte - don't ask why */ - saa_wbytes(strs, &zero, sizeof(char)); - strslen = 1; - - /* add special symbol for ..gotpcrel */ - macho_gotpcrel_sect = seg_alloc(); - macho_gotpcrel_sect ++; -// ldef("..gotpcrel", macho_gotpcrel_sect, 0L, NULL, false, false, &of_macho64, error); -} - -static int macho_setinfo(enum geninfo type, char **val) -{ - (void)type; - (void)val; - return 0; -} - -static void sect_write(struct section *sect, - const uint8_t *data, uint32_t len) -{ - saa_wbytes(sect->data, data, len); - sect->size += len; -} - -static int32_t add_reloc(struct section *sect, int32_t section, - int pcrel, int bytes, int64_t reloff) -{ - struct reloc *r; - struct symbol *sym; - int32_t fi; - int32_t adjustment = 0; - - /* NeXT as puts relocs in reversed order (address-wise) into the - ** files, so we do the same, doesn't seem to make much of a - ** difference either way */ - r = nasm_malloc(sizeof(struct reloc)); - r->next = sect->relocs; - sect->relocs = r; - - /* the current end of the section will be the symbol's address for - ** now, might have to be fixed by macho_fixup_relocs() later on. make - ** sure we don't make the symbol scattered by setting the highest - ** bit by accident */ - r->addr = sect->size & ~R_SCATTERED; - r->ext = 1; - r->pcrel = (pcrel ? 1 : 0); - - /* match byte count 1, 2, 4, 8 to length codes 0, 1, 2, 3 respectively */ - switch(bytes){ - case 1: - r->length = 0; - break; - case 2: - r->length = 1; - break; - case 4: - r->length = 2; - break; - case 8: - r->length = 3; - break; - default: - break; - } - - /* set default relocation values */ - r->type = 0; // X86_64_RELOC_UNSIGNED - r->snum = R_ABS; // Absolute Symbol (indicates no relocation) - - /* absolute relocation */ - if (pcrel == 0) { - - /* intra-section */ - if (section == NO_SEG) { - // r->snum = R_ABS; // Set above - - /* inter-section */ - } else { - fi = get_section_fileindex_by_index(section); - - /* external */ - if (fi == NO_SECT) { - r->snum = raa_read(extsyms, section); - - /* local */ - } else { - sym = get_closest_section_symbol_by_offset(fi, reloff); - r->snum = sym->initial_snum; - adjustment = sym->value; - } - } - - /* relative relocation */ - } else if (pcrel == 1) { - - /* intra-section */ - if (section == NO_SEG) { - r->type = 1; // X86_64_RELOC_SIGNED - - /* inter-section */ - } else { - r->type = 2; // X86_64_RELOC_BRANCH - fi = get_section_fileindex_by_index(section); - - /* external */ - if (fi == NO_SECT) { - sect->extreloc = 1; - r->snum = raa_read(extsyms, section); - - /* local */ - } else { - sym = get_closest_section_symbol_by_offset(fi, reloff); - r->snum = sym->initial_snum; - adjustment = sym->value; - } - } - - /* subtractor */ - } else if (pcrel == 2) { - r->pcrel = 0; - r->type = 5; // X86_64_RELOC_SUBTRACTOR -// r->snum = macho_gotpcrel_sect; - - /* gotpcrel */ - } else if (pcrel == 3) { - r->type = 4; // X86_64_RELOC_GOT - } else if (pcrel == 4) { - r->type = 3; // X86_64_RELOC_GOT_LOAD - } - - ++sect->nreloc; - - return adjustment; -} - -static void macho_output(int32_t secto, const void *data, - enum out_type type, uint64_t size, - int32_t section, int32_t wrt) -{ - struct section *s, *sbss; - int64_t addr; - uint8_t mydata[16], *p; - - if (secto == NO_SEG) { - if (type != OUT_RESERVE) - error(ERR_NONFATAL, "attempt to assemble code in " - "[ABSOLUTE] space"); - - return; - } - - s = get_section_by_index(secto); - - if (s == NULL) { - error(ERR_WARNING, "attempt to assemble code in" - " section %d: defaulting to `.text'", secto); - s = get_section_by_name("__TEXT", "__text"); - - /* should never happen */ - if (s == NULL) - error(ERR_PANIC, "text section not found"); - } - - sbss = get_section_by_name("__DATA", "__bss"); - - if (s == sbss && type != OUT_RESERVE) { - error(ERR_WARNING, "attempt to initialize memory in the" - " BSS section: ignored"); - s->size += realsize(type, size); - return; - } - - switch (type) { - case OUT_RESERVE: - if (s != sbss) { - error(ERR_WARNING, "uninitialized space declared in" - " %s section: zeroing", - get_section_name_by_index(secto)); - - sect_write(s, NULL, size); - } else - s->size += size; - - break; - - case OUT_RAWDATA: - if (section != NO_SEG) - error(ERR_PANIC, "OUT_RAWDATA with other than NO_SEG"); - - sect_write(s, data, size); - break; - - case OUT_ADDRESS: - addr = *(int64_t *)data; - if (section != NO_SEG) { - if (section % 2) { - error(ERR_NONFATAL, "Mach-O format does not support" - " section base references"); - } else { - if (wrt == NO_SEG) { - if (size < 8) { - error(ERR_NONFATAL, "Mach-O 64-bit format does not support" - " 32-bit absolute addresses"); - /* - Seemingly, Mach-O's X86_64_RELOC_SUBTRACTOR would require - pre-determined knowledge of where the image base would be, - making it impractical for use in intermediate object files - */ - } else { - addr -= add_reloc(s, section, 0, size, addr); - } - } else if (wrt == macho_gotpcrel_sect) { - addr += s->size; - add_reloc(s, section, 3, size, addr); // X86_64_RELOC_GOT - } else { - error(ERR_NONFATAL, "Mach-O format does not support" - " this use of WRT"); - } - } - } - - p = mydata; - WRITEADDR(p, addr, size); - sect_write(s, mydata, size); - break; - - case OUT_REL2ADR: - p = mydata; - WRITESHORT(p, *(int64_t *)data); - - if (section == secto) - error(ERR_PANIC, "intra-section OUT_REL2ADR"); - - if (section != NO_SEG && section % 2) { - error(ERR_NONFATAL, "Mach-O format does not support" - " section base references"); - } else { - if (wrt == NO_SEG) { - *mydata -= add_reloc(s, section, 2, 2, (int64_t)*mydata); - *mydata -= add_reloc(s, section, 0, 2, (int64_t)*mydata); - } else { - error(ERR_NONFATAL, "Unsupported non-32-bit" - " Macho-O relocation [2]"); - } - } - - sect_write(s, mydata, 2L); - break; - - case OUT_REL4ADR: - p = mydata; - WRITELONG(p, *(int64_t *)data); - - if (section == secto) - error(ERR_PANIC, "intra-section OUT_REL4ADR"); - - if (section != NO_SEG && section % 2) { - error(ERR_NONFATAL, "Mach-O format does not support" - " section base references"); - } else { - if (wrt == NO_SEG) { - *mydata -= add_reloc(s, section, 1, 4, (int64_t)*mydata); // X86_64_RELOC_UNSIGNED/SIGNED/BRANCH - } else if (wrt == macho_gotpcrel_sect) { - error(ERR_NONFATAL, "Mach-O format cannot produce PC-" - "relative GOT references"); - } else { - error(ERR_NONFATAL, "Mach-O format does not support" - " this use of WRT"); - wrt = NO_SEG; /* we can at least _try_ to continue */ - } - } - - sect_write(s, mydata, 4L); - break; - - default: - error(ERR_PANIC, "unknown output type?"); - break; - } -} - -static int32_t macho_section(char *name, int pass, int *bits) -{ - int32_t index, originalIndex; - char *sectionAttributes; - struct sectmap *sm; - struct section *s; - - (void)pass; - - /* Default to 64 bits. */ - if (!name) { - *bits = 64; - name = ".text"; - sectionAttributes = NULL; - } else { - sectionAttributes = name; - name = nasm_strsep(§ionAttributes, " \t"); - } - - for (sm = sectmap; sm->nasmsect != NULL; ++sm) { - /* make lookup into section name translation table */ - if (!strcmp(name, sm->nasmsect)) { - char *currentAttribute; - - /* try to find section with that name */ - originalIndex = index = get_section_index_by_name(sm->segname, - sm->sectname); - - /* create it if it doesn't exist yet */ - if (index == -1) { - s = *sectstail = nasm_malloc(sizeof(struct section)); - s->next = NULL; - sectstail = &s->next; - - s->data = saa_init(1L); - s->index = seg_alloc(); - s->relocs = NULL; - s->align = -1; - - xstrncpy(s->segname, sm->segname); - xstrncpy(s->sectname, sm->sectname); - s->size = 0; - s->nreloc = 0; - s->flags = sm->flags; - - index = s->index; - } else { - s = get_section_by_index(index); - } - - while ((NULL != sectionAttributes) - && (currentAttribute = nasm_strsep(§ionAttributes, " \t"))) { - if (0 != *currentAttribute) { - if (!nasm_strnicmp("align=", currentAttribute, 6)) { - char *end; - int newAlignment, value; - - value = strtoul(currentAttribute + 6, (char**)&end, 0); - newAlignment = exact_log2(value); - - if (0 != *end) { - error(ERR_PANIC, - "unknown or missing alignment value \"%s\" " - "specified for section \"%s\"", - currentAttribute + 6, - name); - return NO_SEG; - } else if (0 > newAlignment) { - error(ERR_PANIC, - "alignment of %d (for section \"%s\") is not " - "a power of two", - value, - name); - return NO_SEG; - } - - if ((-1 != originalIndex) - && (s->align != newAlignment) - && (s->align != -1)) { - error(ERR_PANIC, - "section \"%s\" has already been specified " - "with alignment %d, conflicts with new " - "alignment of %d", - name, - (1 << s->align), - value); - return NO_SEG; - } - - s->align = newAlignment; - } else if (!nasm_stricmp("data", currentAttribute)) { - /* Do nothing; 'data' is implicit */ - } else { - error(ERR_PANIC, - "unknown section attribute %s for section %s", - currentAttribute, - name); - return NO_SEG; - } - } - } - - return index; - } - } - - error(ERR_PANIC, "invalid section name %s", name); - return NO_SEG; -} - -static void macho_symdef(char *name, int32_t section, int64_t offset, - int is_global, char *special) -{ - struct symbol *sym; - - if (special) { - error(ERR_NONFATAL, "The Mach-O output format does " - "not support any special symbol types"); - return; - } - - if (is_global == 3) { - error(ERR_NONFATAL, "The Mach-O format does not " - "(yet) support forward reference fixups."); - return; - } - - sym = *symstail = nasm_malloc(sizeof(struct symbol)); - sym->next = NULL; - symstail = &sym->next; - - sym->name = name; - sym->strx = strslen; - sym->type = 0; - sym->desc = 0; - sym->value = offset; - sym->initial_snum = -1; - - if (name[0] == '.' && name[1] == '.' && name[2] != '@') { - /* - * This is a NASM special symbol. We never allow it into - * the Macho-O symbol table, even if it's a valid one. If it - * _isn't_ a valid one, we should barf immediately. - */ - if (strcmp(name, "..gotpcrel")) - error(ERR_NONFATAL, "unrecognized special symbol `%s'", name); - return; - } - - /* external and common symbols get N_EXT */ - if (is_global != 0) { - sym->type |= N_EXT; - } - - if (section == NO_SEG) { - /* symbols in no section get absolute */ - sym->type |= N_ABS; - sym->sect = NO_SECT; - } else { - sym->type |= N_SECT; - - /* get the in-file index of the section the symbol was defined in */ - sym->sect = get_section_fileindex_by_index(section); - - /* track the initially allocated symbol number for use in future fix-ups */ - sym->initial_snum = nsyms; - - if (sym->sect == NO_SECT) { - - /* remember symbol number of references to external - ** symbols, this works because every external symbol gets - ** its own section number allocated internally by nasm and - ** can so be used as a key */ - extsyms = raa_write(extsyms, section, nsyms); - - switch (is_global) { - case 1: - case 2: - /* there isn't actually a difference between global - ** and common symbols, both even have their size in - ** sym->value */ - sym->type = N_EXT; - break; - - default: - /* give an error on unfound section if it's not an - ** external or common symbol (assemble_file() does a - ** seg_alloc() on every call for them) */ - error(ERR_PANIC, "in-file index for section %d not found", - section); - } - } - } - ++nsyms; -} - -static int32_t macho_segbase(int32_t section) -{ - return section; -} - -static int macho_directive(char *directive, char *value, int pass) -{ - (void)directive; - (void)value; - (void)pass; - return 0; -} - -static void macho_filename(char *inname, char *outname, efunc error) -{ - standard_extension(inname, outname, ".o", error); -} - -extern macros_t macho_stdmac[]; - -/* Comparison function for qsort symbol layout. */ -static int layout_compare (const struct symbol **s1, - const struct symbol **s2) -{ - return (strcmp ((*s1)->name, (*s2)->name)); -} - -/* The native assembler does a few things in a similar function - - * Remove temporary labels - * Sort symbols according to local, external, undefined (by name) - * Order the string table - - We do not remove temporary labels right now. - - numsyms is the total number of symbols we have. strtabsize is the - number entries in the string table. */ - -static void macho_layout_symbols (uint32_t *numsyms, - uint32_t *strtabsize) -{ - struct symbol *sym, **symp; - uint32_t i,j; - - *numsyms = 0; - *strtabsize = sizeof (char); - - symp = &syms; - - while ((sym = *symp)) { - /* Undefined symbols are now external. */ - if (sym->type == N_UNDF) - sym->type |= N_EXT; - - if ((sym->type & N_EXT) == 0) { - sym->snum = *numsyms; - *numsyms = *numsyms + 1; - nlocalsym++; - } - else { - if ((sym->type & N_TYPE) != N_UNDF) { - nextdefsym++; - } else { - nundefsym++; - } - - /* If we handle debug info we'll want - to check for it here instead of just - adding the symbol to the string table. */ - sym->strx = *strtabsize; - saa_wbytes (strs, sym->name, (int32_t)(strlen(sym->name) + 1)); - *strtabsize += strlen(sym->name) + 1; - } - symp = &(sym->next); - } - - /* Next, sort the symbols. Most of this code is a direct translation from - the Apple cctools symbol layout. We need to keep compatibility with that. */ - /* Set the indexes for symbol groups into the symbol table */ - ilocalsym = 0; - iextdefsym = nlocalsym; - iundefsym = nlocalsym + nextdefsym; - - /* allocate arrays for sorting externals by name */ - extdefsyms = nasm_malloc(nextdefsym * sizeof(struct symbol *)); - undefsyms = nasm_malloc(nundefsym * sizeof(struct symbol *)); - - i = 0; - j = 0; - - symp = &syms; - - while ((sym = *symp)) { - - if((sym->type & N_EXT) == 0) { - sym->strx = *strtabsize; - saa_wbytes (strs, sym->name, (int32_t)(strlen (sym->name) + 1)); - *strtabsize += strlen(sym->name) + 1; - } - else { - if((sym->type & N_TYPE) != N_UNDF) { - extdefsyms[i++] = sym; - } else { - undefsyms[j++] = sym; - } - } - symp = &(sym->next); - } - - qsort(extdefsyms, nextdefsym, sizeof(struct symbol *), - (int (*)(const void *, const void *))layout_compare); - qsort(undefsyms, nundefsym, sizeof(struct symbol *), - (int (*)(const void *, const void *))layout_compare); - - for(i = 0; i < nextdefsym; i++) { - extdefsyms[i]->snum = *numsyms; - *numsyms += 1; - } - for(j = 0; j < nundefsym; j++) { - undefsyms[j]->snum = *numsyms; - *numsyms += 1; - } -} - -/* Calculate some values we'll need for writing later. */ - -static void macho_calculate_sizes (void) -{ - struct section *s; - - /* count sections and calculate in-memory and in-file offsets */ - for (s = sects; s != NULL; s = s->next) { - uint64_t pad = 0; - - /* zerofill sections aren't actually written to the file */ - if ((s->flags & SECTION_TYPE) != S_ZEROFILL) - seg_filesize64 += s->size; - - /* recalculate segment address based on alignment and vm size */ - s->addr = seg_vmsize64; - /* we need section alignment to calculate final section address */ - if (s->align == -1) - s->align = DEFAULT_SECTION_ALIGNMENT; - if(s->align) { - uint64_t newaddr = align(s->addr, 1 << s->align); - pad = newaddr - s->addr; - s->addr = newaddr; - } - - seg_vmsize64 += s->size + pad; - ++seg_nsects64; - } - - /* calculate size of all headers, load commands and sections to - ** get a pointer to the start of all the raw data */ - if (seg_nsects64 > 0) { - ++head_ncmds64; - head_sizeofcmds64 += - MACHO_SEGCMD64_SIZE + seg_nsects64 * MACHO_SECTCMD64_SIZE; - } - - if (nsyms > 0) { - ++head_ncmds64; - head_sizeofcmds64 += MACHO_SYMCMD_SIZE; - } -} - -/* Write out the header information for the file. */ - -static void macho_write_header (void) -{ - fwriteint32_t(MH_MAGIC_64, machofp); /* magic */ - fwriteint32_t(CPU_TYPE_X86_64, machofp); /* CPU type */ - fwriteint32_t(CPU_SUBTYPE_I386_ALL, machofp); /* CPU subtype */ - fwriteint32_t(MH_OBJECT, machofp); /* Mach-O file type */ - fwriteint32_t(head_ncmds64, machofp); /* number of load commands */ - fwriteint32_t(head_sizeofcmds64, machofp); /* size of load commands */ - fwriteint32_t(0, machofp); /* no flags */ - fwriteint32_t(0, machofp); /* reserved for future use */ -} - -/* Write out the segment load command at offset. */ - -static uint32_t macho_write_segment (uint64_t offset) -{ - uint64_t rel_base = alignint64_t (offset + seg_filesize64); - uint32_t s_reloff = 0; - struct section *s; - - fwriteint32_t(LC_SEGMENT_64, machofp); /* cmd == LC_SEGMENT_64 */ - - /* size of load command including section load commands */ - fwriteint32_t(MACHO_SEGCMD64_SIZE + seg_nsects64 * - MACHO_SECTCMD64_SIZE, machofp); - - /* in an MH_OBJECT file all sections are in one unnamed (name - ** all zeros) segment */ - fwritezero(16, machofp); - fwriteint64_t(0, machofp); /* in-memory offset */ - fwriteint64_t(seg_vmsize64, machofp); /* in-memory size */ - fwriteint64_t(offset, machofp); /* in-file offset to data */ - fwriteint64_t(seg_filesize64, machofp); /* in-file size */ - fwriteint32_t(VM_PROT_DEFAULT, machofp); /* maximum vm protection */ - fwriteint32_t(VM_PROT_DEFAULT, machofp); /* initial vm protection */ - fwriteint32_t(seg_nsects64, machofp); /* number of sections */ - fwriteint32_t(0, machofp); /* no flags */ - - /* emit section headers */ - for (s = sects; s != NULL; s = s->next) { - fwrite(s->sectname, sizeof(s->sectname), 1, machofp); - fwrite(s->segname, sizeof(s->segname), 1, machofp); - fwriteint64_t(s->addr, machofp); - fwriteint64_t(s->size, machofp); - - /* dummy data for zerofill sections or proper values */ - if ((s->flags & SECTION_TYPE) != S_ZEROFILL) { - fwriteint32_t(offset, machofp); - /* Write out section alignment, as a power of two. - e.g. 32-bit word alignment would be 2 (2^2 = 4). */ - if (s->align == -1) - s->align = DEFAULT_SECTION_ALIGNMENT; - fwriteint32_t(s->align, machofp); - /* To be compatible with cctools as we emit - a zero reloff if we have no relocations. */ - fwriteint32_t(s->nreloc ? rel_base + s_reloff : 0, machofp); - fwriteint32_t(s->nreloc, machofp); - - offset += s->size; - s_reloff += s->nreloc * MACHO_RELINFO64_SIZE; - } else { - fwriteint32_t(0, machofp); - fwriteint32_t(0, machofp); - fwriteint32_t(0, machofp); - fwriteint32_t(0, machofp); - } - - if (s->nreloc) { - s->flags |= S_ATTR_LOC_RELOC; - if (s->extreloc) - s->flags |= S_ATTR_EXT_RELOC; - } - - fwriteint32_t(s->flags, machofp); /* flags */ - fwriteint32_t(0, machofp); /* reserved */ - fwriteint32_t(0, machofp); /* reserved */ - - fwriteint32_t(0, machofp); /* align */ - } - - rel_padcnt64 = rel_base - offset; - offset = rel_base + s_reloff; - - return offset; -} - -/* For a given chain of relocs r, write out the entire relocation - chain to the object file. */ - -static void macho_write_relocs (struct reloc *r) -{ - while (r) { - uint32_t word2; - - fwriteint32_t(r->addr, machofp); /* reloc offset */ - - word2 = r->snum; - word2 |= r->pcrel << 24; - word2 |= r->length << 25; - word2 |= r->ext << 27; - word2 |= r->type << 28; - fwriteint32_t(word2, machofp); /* reloc data */ - r = r->next; - } -} - -/* Write out the section data. */ -static void macho_write_section (void) -{ - struct section *s, *s2; - struct reloc *r; - uint8_t fi, *p, *q, blk[8]; - int32_t len; - int64_t l; - - for (s = sects; s != NULL; s = s->next) { - if ((s->flags & SECTION_TYPE) == S_ZEROFILL) - continue; - - /* no padding needs to be done to the sections */ - - /* Like a.out Mach-O references things in the data or bss - * sections by addresses which are actually relative to the - * start of the _text_ section, in the _file_. See outaout.c - * for more information. */ - saa_rewind(s->data); - for (r = s->relocs; r != NULL; r = r->next) { - len = (int32_t)r->length << 1; - if(len > 4) len = 8; - saa_fread(s->data, r->addr, blk, len); - p = q = blk; - l = *p++; - - /* get offset based on relocation type */ - if (r->length > 0) { - l += ((int64_t)*p++) << 8; - - if (r->length > 1) { - l += ((int64_t)*p++) << 16; - l += ((int64_t)*p++) << 24; - } - - if (r->length > 2) { - l += ((int64_t)*p++) << 32; - l += ((int64_t)*p++) << 40; - l += ((int64_t)*p++) << 48; - l += ((int64_t)*p++) << 56; - } - - - } - - /* If the relocation is internal add to the current section - offset. Otherwise the only value we need is the symbol - offset which we already have. The linker takes care - of the rest of the address. */ - if (!r->ext) { - /* generate final address by section address and offset */ - for (s2 = sects, fi = 1; - s2 != NULL && fi < r->snum; s2 = s2->next, fi++) - l += s2->size; - } - - /* write new offset back */ - if (r->length == 3) - WRITEDLONG(q, l); - else if (r->length == 2) - WRITELONG(q, l); - else if (r->length == 1) - WRITESHORT(q, l); - else - *q++ = l & 0xFF; - - saa_fwrite(s->data, r->addr, blk, len); - } - - /* dump the section data to file */ - saa_fpwrite(s->data, machofp); - } - - /* pad last section up to reloc entries on int64_t boundary */ - fwritezero(rel_padcnt64, machofp); - - /* emit relocation entries */ - for (s = sects; s != NULL; s = s->next) - macho_write_relocs (s->relocs); -} - -/* Write out the symbol table. We should already have sorted this - before now. */ -static void macho_write_symtab (void) -{ - struct symbol *sym; - struct section *s; - int64_t fi; - uint64_t i; - - /* we don't need to pad here since MACHO_RELINFO_SIZE == 8 */ - - for (sym = syms; sym != NULL; sym = sym->next) { - if ((sym->type & N_EXT) == 0) { - fwriteint32_t(sym->strx, machofp); /* string table entry number */ - fwrite(&sym->type, 1, 1, machofp); /* symbol type */ - fwrite(&sym->sect, 1, 1, machofp); /* section */ - fwriteint16_t(sym->desc, machofp); /* description */ - - /* Fix up the symbol value now that we know the final section - sizes. */ - if (((sym->type & N_TYPE) == N_SECT) && (sym->sect != NO_SECT)) { - for (s = sects, fi = 1; - s != NULL && fi < sym->sect; s = s->next, ++fi) - sym->value += s->size; - } - - fwriteint64_t(sym->value, machofp); /* value (i.e. offset) */ - } - } - - for (i = 0; i < nextdefsym; i++) { - sym = extdefsyms[i]; - fwriteint32_t(sym->strx, machofp); - fwrite(&sym->type, 1, 1, machofp); /* symbol type */ - fwrite(&sym->sect, 1, 1, machofp); /* section */ - fwriteint16_t(sym->desc, machofp); /* description */ - - /* Fix up the symbol value now that we know the final section - sizes. */ - if (((sym->type & N_TYPE) == N_SECT) && (sym->sect != NO_SECT)) { - for (s = sects, fi = 1; - s != NULL && fi < sym->sect; s = s->next, ++fi) - sym->value += s->size; - } - - fwriteint64_t(sym->value, machofp); /* value (i.e. offset) */ - } - - for (i = 0; i < nundefsym; i++) { - sym = undefsyms[i]; - fwriteint32_t(sym->strx, machofp); - fwrite(&sym->type, 1, 1, machofp); /* symbol type */ - fwrite(&sym->sect, 1, 1, machofp); /* section */ - fwriteint16_t(sym->desc, machofp); /* description */ - - // Fix up the symbol value now that we know the final section sizes. - if (((sym->type & N_TYPE) == N_SECT) && (sym->sect != NO_SECT)) { - for (s = sects, fi = 1; - s != NULL && fi < sym->sect; s = s->next, ++fi) - sym->value += s->size; - } - - fwriteint64_t(sym->value, machofp); // value (i.e. offset) - } - -} - -/* Fixup the snum in the relocation entries, we should be - doing this only for externally referenced symbols. */ -static void macho_fixup_relocs (struct reloc *r) -{ - struct symbol *sym; - - while (r != NULL) { - if (r->ext) { - for (sym = syms; sym != NULL; sym = sym->next) { - if (sym->initial_snum == r->snum) { - r->snum = sym->snum; - break; - } - } - } - r = r->next; - } -} - -/* Write out the object file. */ - -static void macho_write (void) -{ - uint64_t offset = 0; - - /* mach-o object file structure: - ** - ** mach header - ** uint32_t magic - ** int cpu type - ** int cpu subtype - ** uint32_t mach file type - ** uint32_t number of load commands - ** uint32_t size of all load commands - ** (includes section struct size of segment command) - ** uint32_t flags - ** - ** segment command - ** uint32_t command type == LC_SEGMENT_64 - ** uint32_t size of load command - ** (including section load commands) - ** char[16] segment name - ** uint64_t in-memory offset - ** uint64_t in-memory size - ** uint64_t in-file offset to data area - ** uint64_t in-file size - ** (in-memory size excluding zerofill sections) - ** int maximum vm protection - ** int initial vm protection - ** uint32_t number of sections - ** uint32_t flags - ** - ** section commands - ** char[16] section name - ** char[16] segment name - ** uint64_t in-memory offset - ** uint64_t in-memory size - ** uint32_t in-file offset - ** uint32_t alignment - ** (irrelevant in MH_OBJECT) - ** uint32_t in-file offset of relocation entires - ** uint32_t number of relocations - ** uint32_t flags - ** uint32_t reserved - ** uint32_t reserved - ** - ** symbol table command - ** uint32_t command type == LC_SYMTAB - ** uint32_t size of load command - ** uint32_t symbol table offset - ** uint32_t number of symbol table entries - ** uint32_t string table offset - ** uint32_t string table size - ** - ** raw section data - ** - ** padding to int64_t boundary - ** - ** relocation data (struct reloc) - ** int32_t offset - ** uint data (symbolnum, pcrel, length, extern, type) - ** - ** symbol table data (struct nlist) - ** int32_t string table entry number - ** uint8_t type - ** (extern, absolute, defined in section) - ** uint8_t section - ** (0 for global symbols, section number of definition (>= 1, <= - ** 254) for local symbols, size of variable for common symbols - ** [type == extern]) - ** int16_t description - ** (for stab debugging format) - ** uint64_t value (i.e. file offset) of symbol or stab offset - ** - ** string table data - ** list of null-terminated strings - */ - - /* Emit the Mach-O header. */ - macho_write_header(); - - offset = MACHO_HEADER64_SIZE + head_sizeofcmds64; - - /* emit the segment load command */ - if (seg_nsects64 > 0) - offset = macho_write_segment (offset); - else - error(ERR_WARNING, "no sections?"); - - if (nsyms > 0) { - /* write out symbol command */ - fwriteint32_t(LC_SYMTAB, machofp); /* cmd == LC_SYMTAB */ - fwriteint32_t(MACHO_SYMCMD_SIZE, machofp); /* size of load command */ - fwriteint32_t(offset, machofp); /* symbol table offset */ - fwriteint32_t(nsyms, machofp); /* number of symbol - ** table entries */ - - offset += nsyms * MACHO_NLIST64_SIZE; - fwriteint32_t(offset, machofp); /* string table offset */ - fwriteint32_t(strslen, machofp); /* string table size */ - } - - /* emit section data */ - if (seg_nsects64 > 0) - macho_write_section (); - - /* emit symbol table if we have symbols */ - if (nsyms > 0) - macho_write_symtab (); - - /* we don't need to pad here since MACHO_NLIST64_SIZE == 16 */ - - /* emit string table */ - saa_fpwrite(strs, machofp); -} -/* We do quite a bit here, starting with finalizing all of the data - for the object file, writing, and then freeing all of the data from - the file. */ - -static void macho_cleanup(int debuginfo) -{ - struct section *s; - struct reloc *r; - struct symbol *sym; - - (void)debuginfo; - - /* Sort all symbols. */ - macho_layout_symbols (&nsyms, &strslen); - - /* Fixup relocation entries */ - for (s = sects; s != NULL; s = s->next) { - macho_fixup_relocs (s->relocs); - } - - /* First calculate and finalize needed values. */ - macho_calculate_sizes(); - macho_write(); - - /* done - yay! */ - fclose(machofp); - - /* free up everything */ - while (sects->next) { - s = sects; - sects = sects->next; - - saa_free(s->data); - while (s->relocs != NULL) { - r = s->relocs; - s->relocs = s->relocs->next; - nasm_free(r); - } - - nasm_free(s); - } - - saa_free(strs); - raa_free(extsyms); - - if (syms) { - while (syms->next) { - sym = syms; - syms = syms->next; - - nasm_free (sym); - } -} -} - -/* Debugging routines. */ -static void debug_reloc (struct reloc *r) -{ - fprintf (stdout, "reloc:\n"); - fprintf (stdout, "\taddr: %"PRId32"\n", r->addr); - fprintf (stdout, "\tsnum: %d\n", r->snum); - fprintf (stdout, "\tpcrel: %d\n", r->pcrel); - fprintf (stdout, "\tlength: %d\n", r->length); - fprintf (stdout, "\text: %d\n", r->ext); - fprintf (stdout, "\ttype: %d\n", r->type); -} - -static void debug_section_relocs (struct section *s) -{ - struct reloc *r = s->relocs; - - fprintf (stdout, "relocs for section %s:\n\n", s->sectname); - - while (r != NULL) { - debug_reloc (r); - r = r->next; - } -} - -struct ofmt of_macho64 = { - "NeXTstep/OpenStep/Rhapsody/Darwin/MacOS X (x86_64) object files", - "macho64", - NULL, - null_debug_arr, - &null_debug_form, - macho_stdmac, - macho_init, - macho_setinfo, - macho_output, - macho_symdef, - macho_section, - macho_segbase, - macho_directive, - macho_filename, - macho_cleanup -}; - -#endif - -/* - * Local Variables: - * mode:c - * c-basic-offset:4 - * End: - * - * end of file */ diff --git a/output/outobj.c b/output/outobj.c index e248ac31..73bec3cc 100644 --- a/output/outobj.c +++ b/output/outobj.c @@ -1,10 +1,39 @@ -/* outobj.c output routines for the Netwide Assembler to produce - * .OBJ object files +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * ----------------------------------------------------------------------- */ + +/* + * outobj.c output routines for the Netwide Assembler to produce + * .OBJ object files */ #include "compiler.h" @@ -18,7 +47,8 @@ #include "nasm.h" #include "nasmlib.h" #include "stdscan.h" -#include "outform.h" +#include "output/outform.h" +#include "output/outlib.h" #ifdef OF_OBJ @@ -385,7 +415,7 @@ static ObjRecord *obj_value(ObjRecord * orp, uint32_t val) /* * Writes a counted string */ -static ObjRecord *obj_name(ObjRecord * orp, char *name) +static ObjRecord *obj_name(ObjRecord * orp, const char *name) { int len = strlen(name); uint8_t *ptr; @@ -634,8 +664,6 @@ static void obj_init(FILE * fp, efunc errfunc, ldfunc ldef, evalfunc eval) obj_use32 = false; passtwo = 0; current_seg = NULL; - - of_obj.current_dfmt->init(&of_obj, NULL, fp, errfunc); } static int obj_set_info(enum geninfo type, char **val) @@ -1068,8 +1096,7 @@ static void obj_out(int32_t segto, const void *data, if (type == OUT_REL2ADR) { ldata += (size - 2); size = 2; - } - if (type == OUT_REL4ADR) { + } else if (type == OUT_REL4ADR) { ldata += (size - 4); size = 4; } @@ -1781,14 +1808,22 @@ static int32_t obj_segbase(int32_t segment) } if (eb) { e = eb->exts[i]; - if (e->defwrt_type == DEFWRT_NONE) + if (!e) { + nasm_assert(pass0 == 0); + /* Not available - can happen during optimization */ + return NO_SEG; + } + + switch (e->defwrt_type) { + case DEFWRT_NONE: return segment; /* fine */ - else if (e->defwrt_type == DEFWRT_SEGMENT) + case DEFWRT_SEGMENT: return e->defwrt_ptr.seg->index + 1; - else if (e->defwrt_type == DEFWRT_GROUP) + case DEFWRT_GROUP: return e->defwrt_ptr.grp->index + 1; - else + default: return NO_SEG; /* can't tell what it is */ + } } return segment; /* not one of ours - leave it alone */ @@ -1818,7 +1853,6 @@ static void obj_write_file(int debuginfo) struct External *ext; struct ImpDef *imp; struct ExpDef *export; - static char boast[] = "The Netwide Assembler " NASM_VER; int lname_idx; ObjRecord *orp; @@ -1835,7 +1869,7 @@ static void obj_write_file(int debuginfo) */ orp->type = COMENT; obj_rword(orp, 0); /* comment type zero */ - obj_name(orp, boast); + obj_name(orp, nasm_comment); obj_emit2(orp); orp->type = COMENT; @@ -2524,9 +2558,9 @@ static struct dfmt *borland_debug_arr[3] = { struct ofmt of_obj = { "MS-DOS 16-bit/32-bit OMF object files", "obj", - NULL, + 0, borland_debug_arr, - &null_debug_form, + &borland_debug_form, obj_stdmac, obj_init, obj_set_info, diff --git a/output/outobj.mac b/output/outobj.mac index ef60638a..a5da833e 100644 --- a/output/outobj.mac +++ b/output/outobj.mac @@ -1,3 +1,36 @@ +;; -------------------------------------------------------------------------- +;; +;; Copyright 1996-2009 The NASM Authors - All Rights Reserved +;; See the file AUTHORS included with the NASM distribution for +;; the specific copyright holders. +;; +;; Redistribution and use in source and binary forms, with or without +;; modification, are permitted provided that the following +;; conditions are met: +;; +;; * Redistributions of source code must retain the above copyright +;; notice, this list of conditions and the following disclaimer. +;; * Redistributions in binary form must reproduce the above +;; copyright notice, this list of conditions and the following +;; disclaimer in the documentation and/or other materials provided +;; with the distribution. +;; +;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +;; CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +;; INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +;; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +;; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;; NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +;; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +;; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +;; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +;; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;; +;; -------------------------------------------------------------------------- + OUT: obj %define __SECT__ [section .text] %imacro group 1+.nolist diff --git a/output/outrdf.c b/output/outrdf.c index 8c5b2396..fef18fbf 100644 --- a/output/outrdf.c +++ b/output/outrdf.c @@ -1,15 +1,44 @@ -/* outrdf.c output routines for the Netwide Assembler to produce +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * outrdf.c output routines for the Netwide Assembler to produce * RDOFF format object files (which are intended mainly * for use in proprietary projects, as the code to load and * execute them is very simple). They will also be used * for device drivers and possibly some executable files * in the MOSCOW operating system. See Rdoff.txt for * details. - * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. */ #include "compiler.h" @@ -22,7 +51,7 @@ #include "nasm.h" #include "nasmlib.h" -#include "outform.h" +#include "output/outform.h" /* VERBOSE_WARNINGS: define this to add some extra warnings... */ #define VERBOSE_WARNINGS @@ -523,7 +552,7 @@ struct ofmt of_rdf = { #else "rdf", #endif - NULL, + 0, null_debug_arr, &null_debug_form, rdf_stdmac, diff --git a/output/outrdf.mac b/output/outrdf.mac index f0c41557..64a7ac14 100644 --- a/output/outrdf.mac +++ b/output/outrdf.mac @@ -1,3 +1,36 @@ +;; -------------------------------------------------------------------------- +;; +;; Copyright 1996-2009 The NASM Authors - All Rights Reserved +;; See the file AUTHORS included with the NASM distribution for +;; the specific copyright holders. +;; +;; Redistribution and use in source and binary forms, with or without +;; modification, are permitted provided that the following +;; conditions are met: +;; +;; * Redistributions of source code must retain the above copyright +;; notice, this list of conditions and the following disclaimer. +;; * Redistributions in binary form must reproduce the above +;; copyright notice, this list of conditions and the following +;; disclaimer in the documentation and/or other materials provided +;; with the distribution. +;; +;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +;; CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +;; INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +;; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +;; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;; NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +;; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +;; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +;; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +;; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;; +;; -------------------------------------------------------------------------- + OUT: rdf %define __SECT__ [section .text] %imacro library 1+.nolist diff --git a/output/outrdf2.c b/output/outrdf2.c index b502715b..578c9237 100644 --- a/output/outrdf2.c +++ b/output/outrdf2.c @@ -1,12 +1,40 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + /* * outrdf2.c output routines for the Netwide Assembler to produce * RDOFF version 2 format object files, which Julian originally * planned to use it in his MOSCOW operating system. - * - * The Netwide Assembler is copyright (C) 1996-1998 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. */ #include "compiler.h" @@ -21,7 +49,8 @@ #include "nasm.h" #include "nasmlib.h" #include "saa.h" -#include "outform.h" +#include "output/outform.h" +#include "output/outlib.h" /* VERBOSE_WARNINGS: define this to add some extra warnings... */ #define VERBOSE_WARNINGS @@ -758,7 +787,7 @@ static int rdf2_set_info(enum geninfo type, char **val) struct ofmt of_rdf2 = { "Relocatable Dynamic Object File Format v2.0", "rdf", - NULL, + 0, null_debug_arr, &null_debug_form, rdf2_stdmac, diff --git a/output/outrdf2.mac b/output/outrdf2.mac index a48cbfb6..4875c50c 100644 --- a/output/outrdf2.mac +++ b/output/outrdf2.mac @@ -1,3 +1,36 @@ +;; -------------------------------------------------------------------------- +;; +;; Copyright 1996-2009 The NASM Authors - All Rights Reserved +;; See the file AUTHORS included with the NASM distribution for +;; the specific copyright holders. +;; +;; Redistribution and use in source and binary forms, with or without +;; modification, are permitted provided that the following +;; conditions are met: +;; +;; * Redistributions of source code must retain the above copyright +;; notice, this list of conditions and the following disclaimer. +;; * Redistributions in binary form must reproduce the above +;; copyright notice, this list of conditions and the following +;; disclaimer in the documentation and/or other materials provided +;; with the distribution. +;; +;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +;; CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +;; INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +;; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +;; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;; NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +;; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +;; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +;; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +;; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;; +;; -------------------------------------------------------------------------- + OUT: rdf2 %define __SECT__ [section .text] %imacro library 1+.nolist @@ -1,11 +1,38 @@ -/* parser.c source line parser for the Netwide Assembler +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: * - * initial version 27/iii/95 by Simon Tatham + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * parser.c source line parser for the Netwide Assembler */ #include "compiler.h" @@ -46,6 +73,8 @@ void parser_global_info(struct ofmt *output, struct location * locp) static int prefix_slot(enum prefixes prefix) { switch (prefix) { + case P_WAIT: + return PPS_WAIT; case R_CS: case R_DS: case R_SS: @@ -172,6 +201,7 @@ insn *parse_line(int pass, char *buffer, insn * result, int j; bool first; bool insn_is_label = false; + bool recover; restart_parse: first = true; @@ -256,7 +286,7 @@ restart_parse: result->times = 1L; } else { result->times = value->value; - if (value->value < 0) { + if (value->value < 0 && pass0 == 2) { error(ERR_NONFATAL, "TIMES value %d is negative", value->value); result->times = 0; @@ -308,21 +338,13 @@ restart_parse: result->condition = tokval.t_inttwo; /* - * RESB, RESW and RESD cannot be satisfied with incorrectly + * INCBIN cannot be satisfied with incorrectly * evaluated operands, since the correct values _must_ be known * on the first pass. Hence, even in pass one, we set the * `critical' flag on calling evaluate(), so that it will bomb - * out on undefined symbols. Nasty, but there's nothing we can - * do about it. - * - * For the moment, EQU has the same difficulty, so we'll - * include that. + * out on undefined symbols. */ - if (result->opcode == I_RESB || result->opcode == I_RESW || - result->opcode == I_RESD || result->opcode == I_RESQ || - result->opcode == I_REST || result->opcode == I_RESO || - result->opcode == I_RESY || - result->opcode == I_INCBIN) { + if (result->opcode == I_INCBIN) { critical = (pass0 < 2 ? 1 : 2); } else @@ -684,24 +706,32 @@ restart_parse: return result; /* ignore this instruction */ } } + + recover = false; if (mref && bracket) { /* find ] at the end */ if (i != ']') { error(ERR_NONFATAL, "parser: expecting ]"); - do { /* error recovery again */ - i = stdscan(NULL, &tokval); - } while (i != 0 && i != ','); - } else /* we got the required ] */ + recover = true; + } else { /* we got the required ] */ i = stdscan(NULL, &tokval); + if (i != 0 && i != ',') { + error(ERR_NONFATAL, "comma or end of line expected"); + recover = true; + } + } } else { /* immediate operand */ if (i != 0 && i != ',' && i != ':') { - error(ERR_NONFATAL, "comma or end of line expected"); - do { /* error recovery */ - i = stdscan(NULL, &tokval); - } while (i != 0 && i != ','); + error(ERR_NONFATAL, "comma, colon or end of line expected"); + recover = true; } else if (i == ':') { result->oprs[operand].type |= COLON; } } + if (recover) { + do { /* error recovery */ + i = stdscan(NULL, &tokval); + } while (i != 0 && i != ','); + } /* now convert the exprs returned from evaluate() into operand * descriptions... */ @@ -743,6 +773,7 @@ restart_parse: return result; } else { if (e->type == EXPR_UNKNOWN) { + result->oprs[operand].opflags |= OPFLAG_UNKNOWN; o = 0; /* doesn't matter what */ result->oprs[operand].wrt = NO_SEG; /* nor this */ result->oprs[operand].segment = NO_SEG; /* or this */ @@ -821,12 +852,18 @@ restart_parse: result->oprs[operand].scale = s; result->oprs[operand].offset = o; } else { /* it's not a memory reference */ - if (is_just_unknown(value)) { /* it's immediate but unknown */ result->oprs[operand].type |= IMMEDIATE; + result->oprs[operand].opflags |= OPFLAG_UNKNOWN; result->oprs[operand].offset = 0; /* don't care */ result->oprs[operand].segment = NO_SEG; /* don't care again */ result->oprs[operand].wrt = NO_SEG; /* still don't care */ + + if(optimizing >= 0 && !(result->oprs[operand].type & STRICT)) + { + /* Be optimistic */ + result->oprs[operand].type |= SBYTE16 | SBYTE32 | SBYTE64; + } } else if (is_reloc(value)) { /* it's immediate */ result->oprs[operand].type |= IMMEDIATE; result->oprs[operand].offset = reloc_value(value); @@ -1,10 +1,39 @@ -/* parser.h header file for the parser module of the Netwide - * Assembler +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * ----------------------------------------------------------------------- */ + +/* + * parser.h header file for the parser module of the Netwide + * Assembler */ #ifndef NASM_PARSER_H @@ -1,4 +1,35 @@ #!/usr/bin/perl +## -------------------------------------------------------------------------- +## +## Copyright 1996-2009 the NASM Authors - All rights reserved. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following +## conditions are met: +## +## * Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above +## copyright notice, this list of conditions and the following +## disclaimer in the documentation and/or other materials provided +## with the distribution. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## -------------------------------------------------------------------------- + # # Perfect Minimal Hash Generator written in Perl, which produces # C output. @@ -1,3 +1,36 @@ +## -------------------------------------------------------------------------- +## +## Copyright 1996-2009 The NASM Authors - All Rights Reserved +## See the file AUTHORS included with the NASM distribution for +## the specific copyright holders. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following +## conditions are met: +## +## * Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above +## copyright notice, this list of conditions and the following +## disclaimer in the documentation and/or other materials provided +## with the distribution. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## -------------------------------------------------------------------------- + # # A * at the end indicates a condition; the list of conditions are # on lines starting with *; the negatives are auto-generated @@ -27,6 +60,7 @@ %endrep %error %exitrep +%fatal %iassign %idefine %idefstr @@ -1,4 +1,37 @@ #!/usr/bin/perl +## -------------------------------------------------------------------------- +## +## Copyright 1996-2009 The NASM Authors - All Rights Reserved +## See the file AUTHORS included with the NASM distribution for +## the specific copyright holders. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following +## conditions are met: +## +## * Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above +## copyright notice, this list of conditions and the following +## disclaimer in the documentation and/or other materials provided +## with the distribution. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## -------------------------------------------------------------------------- + # # Produce pptok.c, pptok.h and pptok.ph from pptok.dat # @@ -1,11 +1,38 @@ -/* preproc.c macro preprocessor for the Netwide Assembler +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: * - * initial version 18/iii/97 by Simon Tatham + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * preproc.c macro preprocessor for the Netwide Assembler */ /* Typical flow of text through preproc @@ -159,6 +186,8 @@ enum pp_token_type { TOK_NUMBER, TOK_FLOAT, TOK_SMAC_END, TOK_OTHER, TOK_INTERNAL_STRING, TOK_PREPROC_Q, TOK_PREPROC_QQ, + TOK_PASTE, /* %+ */ + TOK_INDIRECT, /* %[...] */ TOK_SMAC_PARAM, /* MUST BE LAST IN THE LIST!!! */ TOK_MAX = INT_MAX /* Keep compiler from reducing the range */ }; @@ -253,14 +282,15 @@ enum { */ COND_ELSE_TRUE, COND_ELSE_FALSE, /* - * This state means that we're not emitting now, and also that - * nothing until %endif will be emitted at all. It's for use in - * two circumstances: (i) when we've had our moment of emission - * and have now started seeing %elifs, and (ii) when the - * condition construct in question is contained within a - * non-emitting branch of a larger condition construct. + * These states mean that we're not emitting now, and also that + * nothing until %endif will be emitted at all. COND_DONE is + * used when we've had our moment of emission + * and have now started seeing %elifs. COND_NEVER is used when + * the condition construct in question is contained within a + * non-emitting branch of a larger condition construct, + * or if there is an error. */ - COND_NEVER + COND_DONE, COND_NEVER }; #define emitting(x) ( (x) == COND_IF_TRUE || (x) == COND_ELSE_TRUE ) @@ -395,9 +425,11 @@ static Blocks blocks = { NULL, NULL }; static Token *expand_mmac_params(Token * tline); static Token *expand_smacro(Token * tline); static Token *expand_id(Token * tline); -static Context *get_ctx(const char *name, bool all_contexts); +static Context *get_ctx(const char *name, const char **namep, + bool all_contexts); static void make_tok_num(Token * tok, int64_t val); static void error(int severity, const char *fmt, ...); +static void error_precond(int severity, const char *fmt, ...); static void *new_Block(size_t size); static void delete_Blocks(void); static Token *new_Token(Token * next, enum pp_token_type type, @@ -448,12 +480,13 @@ static char *check_tasm_directive(char *line) line = nasm_malloc(len + 2); line[0] = '%'; if (k == TM_IFDIFI) { - /* NASM does not recognise IFDIFI, so we convert it to - * %ifdef BOGUS. This is not used in NASM comaptible - * code, but does need to parse for the TASM macro - * package. + /* + * NASM does not recognise IFDIFI, so we convert + * it to %if 0. This is not used in NASM + * compatible code, but does need to parse for the + * TASM macro package. */ - strcpy(line + 1, "ifdef BOGUS"); + strcpy(line + 1, "if 0"); } else { memcpy(line + 1, p, len + 1); } @@ -775,7 +808,7 @@ static char *read_line(void) */ static Token *tokenize(char *line) { - char *p = line; + char c, *p = line; enum pp_token_type type; Token *list = NULL; Token *t, **tail = &list; @@ -784,9 +817,11 @@ static Token *tokenize(char *line) p = line; if (*p == '%') { p++; - if (nasm_isdigit(*p) || - ((*p == '-' || *p == '+') && nasm_isdigit(p[1])) || - ((*p == '+') && (nasm_isspace(p[1]) || !p[1]))) { + if (*p == '+' && !nasm_isdigit(p[1])) { + p++; + type = TOK_PASTE; + } else if (nasm_isdigit(*p) || + ((*p == '-' || *p == '+') && nasm_isdigit(p[1]))) { do { p++; } @@ -802,6 +837,34 @@ static Token *tokenize(char *line) if (*p) p++; type = TOK_PREPROC_ID; + } else if (*p == '[') { + int lvl = 1; + line += 2; /* Skip the leading %[ */ + p++; + while (lvl && (c = *p++)) { + switch (c) { + case ']': + lvl--; + break; + case '%': + if (*p == '[') + lvl++; + break; + case '\'': + case '\"': + case '`': + p = nasm_skip_string(p)+1; + break; + default: + break; + } + } + p--; + if (*p) + *p++ = '\0'; + if (lvl) + error(ERR_NONFATAL, "unterminated %[ construct"); + type = TOK_INDIRECT; } else if (*p == '?') { type = TOK_PREPROC_Q; /* %? */ p++; @@ -837,10 +900,13 @@ static Token *tokenize(char *line) if (*p) { p++; } else { - error(ERR_WARNING, "unterminated string"); + error(ERR_WARNING|ERR_PASS1, "unterminated string"); /* Handling unterminated strings by UNV */ /* type = -1; */ } + } else if (p[0] == '$' && p[1] == '$') { + type = TOK_OTHER; /* TOKEN_BASE */ + p += 2; } else if (isnumstart(*p)) { bool is_hex = false; bool is_float = false; @@ -900,12 +966,16 @@ static Token *tokenize(char *line) } p--; /* Point to first character beyond number */ - if (has_e && !is_hex) { - /* 1e13 is floating-point, but 1e13h is not */ - is_float = true; - } + if (p == line+1 && *line == '$') { + type = TOK_OTHER; /* TOKEN_HERE */ + } else { + if (has_e && !is_hex) { + /* 1e13 is floating-point, but 1e13h is not */ + is_float = true; + } - type = is_float ? TOK_FLOAT : TOK_NUMBER; + type = is_float ? TOK_FLOAT : TOK_NUMBER; + } } else if (nasm_isspace(*p)) { type = TOK_WHITESPACE; p++; @@ -1080,12 +1150,11 @@ static char *detoken(Token * tlist, bool expand_locals) if (expand_locals && t->type == TOK_PREPROC_ID && t->text && t->text[0] == '%' && t->text[1] == '$') { - Context *ctx = get_ctx(t->text, false); + const char *q; + char *p; + Context *ctx = get_ctx(t->text, &q, false); if (ctx) { char buffer[40]; - char *p, *q = t->text + 2; - - q += strspn(q, "$"); snprintf(buffer, sizeof(buffer), "..@%"PRIu32".", ctx->number); p = nasm_strcat(buffer, q); nasm_free(t->text); @@ -1251,13 +1320,20 @@ static int mmemcmp(const char *p, const char *q, size_t l, bool casesense) * also scanned for such smacro, until it is found; if not - * only the context that directly results from the number of $'s * in variable's name. + * + * If "namep" is non-NULL, set it to the pointer to the macro name + * tail, i.e. the part beyond %$... */ -static Context *get_ctx(const char *name, bool all_contexts) +static Context *get_ctx(const char *name, const char **namep, + bool all_contexts) { Context *ctx; SMacro *m; int i; + if (namep) + *namep = name; + if (!name || name[0] != '%' || name[1] != '$') return NULL; @@ -1266,15 +1342,23 @@ static Context *get_ctx(const char *name, bool all_contexts) return NULL; } - for (i = strspn(name + 2, "$"), ctx = cstk; (i > 0) && ctx; i--) { - ctx = ctx->next; -/* i--; Lino - 02/25/02 */ + name += 2; + ctx = cstk; + i = 0; + while (ctx && *name == '$') { + name++; + i++; + ctx = ctx->next; } if (!ctx) { error(ERR_NONFATAL, "`%s': context stack is only" - " %d level%s deep", name, i - 1, (i == 2 ? "" : "s")); + " %d level%s deep", name, i, (i == 1 ? "" : "s")); return NULL; } + + if (namep) + *namep = name; + if (!all_contexts) return ctx; @@ -1395,7 +1479,7 @@ smacro_defined(Context * ctx, const char *name, int nparam, SMacro ** defn, smtbl = &ctx->localmac; } else if (name[0] == '%' && name[1] == '$') { if (cstk) - ctx = get_ctx(name, false); + ctx = get_ctx(name, &name, false); if (!ctx) return false; /* got to return _something_ */ smtbl = &ctx->localmac; @@ -1582,7 +1666,6 @@ static bool if_condition(Token * tline, enum preproc_token ct) bool found = false; MMacro searching, *mmac; - tline = tline->next; skip_white_(tline); tline = expand_id(tline); if (!tok_type_(tline, TOK_ID)) { @@ -1649,7 +1732,8 @@ static bool if_condition(Token * tline, enum preproc_token ct) mmac = mmac->next; } if(tline && tline->next) - error(ERR_WARNING, "trailing garbage after %%ifmacro ignored"); + error(ERR_WARNING|ERR_PASS1, + "trailing garbage after %%ifmacro ignored"); nasm_free(searching.name); j = found; break; @@ -1709,7 +1793,7 @@ static bool if_condition(Token * tline, enum preproc_token ct) if (!evalresult) return -1; if (tokval.t_type) - error(ERR_WARNING, + error(ERR_WARNING|ERR_PASS1, "trailing garbage after expression ignored"); if (!is_simple(evalresult)) { error(ERR_NONFATAL, @@ -1737,7 +1821,7 @@ fail: /* * Common code for defining an smacro */ -static bool define_smacro(Context *ctx, char *mname, bool casesense, +static bool define_smacro(Context *ctx, const char *mname, bool casesense, int nparam, Token *expansion) { SMacro *smac, **smhead; @@ -1745,7 +1829,7 @@ static bool define_smacro(Context *ctx, char *mname, bool casesense, if (smacro_defined(ctx, mname, nparam, &smac, casesense)) { if (!smac) { - error(ERR_WARNING, + error(ERR_WARNING|ERR_PASS1, "single-line macro `%s' defined both with and" " without parameters", mname); @@ -1884,7 +1968,8 @@ static bool parse_mmacro_spec(Token *tline, MMacro *def, const char *directive) if(def->defaults && def->ndefs > def->nparam_max - def->nparam_min && !def->plus) - error(ERR_WARNING | ERR_WARN_MDP, "too many default macro parameters"); + error(ERR_WARNING|ERR_PASS1|ERR_WARN_MDP, + "too many default macro parameters"); return true; } @@ -1924,7 +2009,8 @@ static int do_directive(Token * tline) bool casesense; int k, m; int offset; - char *p, *pp, *mname; + char *p, *pp; + const char *mname; Include *inc; Context *ctx; Cond *cond; @@ -1936,6 +2022,7 @@ static int do_directive(Token * tline) MMacro *tmp_defining; /* Used when manipulating rep_nest */ int64_t count; size_t len; + int severity; origline = tline; @@ -2203,7 +2290,8 @@ static int do_directive(Token * tline) case PP_CLEAR: if (tline->next) - error(ERR_WARNING, "trailing garbage after `%%clear' ignored"); + error(ERR_WARNING|ERR_PASS1, + "trailing garbage after `%%clear' ignored"); free_macros(); init_macros(); free_tlist(origline); @@ -2219,7 +2307,7 @@ static int do_directive(Token * tline) return DIRECTIVE_FOUND; /* but we did _something_ */ } if (t->next) - error(ERR_WARNING, + error(ERR_WARNING|ERR_PASS1, "trailing garbage after `%%depend' ignored"); p = t->text; if (t->type != TOK_INTERNAL_STRING) @@ -2245,7 +2333,7 @@ static int do_directive(Token * tline) return DIRECTIVE_FOUND; /* but we did _something_ */ } if (t->next) - error(ERR_WARNING, + error(ERR_WARNING|ERR_PASS1, "trailing garbage after `%%include' ignored"); p = t->text; if (t->type != TOK_INTERNAL_STRING) @@ -2274,24 +2362,25 @@ static int do_directive(Token * tline) static macros_t *use_pkg; const char *pkg_macro; - t = tline->next = expand_smacro(tline->next); - skip_white_(t); + tline = tline->next; + skip_white_(tline); + tline = expand_id(tline); - if (!t || (t->type != TOK_STRING && - t->type != TOK_INTERNAL_STRING && - t->type != TOK_ID)) { + if (!tline || (tline->type != TOK_STRING && + tline->type != TOK_INTERNAL_STRING && + tline->type != TOK_ID)) { error(ERR_NONFATAL, "`%%use' expects a package name"); free_tlist(origline); return DIRECTIVE_FOUND; /* but we did _something_ */ } - if (t->next) - error(ERR_WARNING, + if (tline->next) + error(ERR_WARNING|ERR_PASS1, "trailing garbage after `%%use' ignored"); - if (t->type == TOK_STRING) - nasm_unquote(t->text, NULL); - use_pkg = nasm_stdmac_find_package(t->text); + if (tline->type == TOK_STRING) + nasm_unquote(tline->text, NULL); + use_pkg = nasm_stdmac_find_package(tline->text); if (!use_pkg) - error(ERR_NONFATAL, "unknown `%%use' package: %s", t->text); + error(ERR_NONFATAL, "unknown `%%use' package: %s", tline->text); /* The first string will be <%define>__USE_*__ */ pkg_macro = (char *)use_pkg + 1; if (!smacro_defined(NULL, pkg_macro, 0, NULL, true)) { @@ -2302,71 +2391,71 @@ static int do_directive(Token * tline) return DIRECTIVE_FOUND; } case PP_PUSH: + case PP_REPL: + case PP_POP: tline = tline->next; skip_white_(tline); tline = expand_id(tline); if (tline) { if (!tok_type_(tline, TOK_ID)) { - error(ERR_NONFATAL, "`%%push' expects a context identifier"); + error(ERR_NONFATAL, "`%s' expects a context identifier", + pp_directives[i]); free_tlist(origline); return DIRECTIVE_FOUND; /* but we did _something_ */ } if (tline->next) - error(ERR_WARNING, "trailing garbage after `%%push' ignored"); + error(ERR_WARNING|ERR_PASS1, + "trailing garbage after `%s' ignored", + pp_directives[i]); p = nasm_strdup(tline->text); } else { - p = NULL; /* Anonymous context */ + p = NULL; /* Anonymous */ } - ctx = nasm_malloc(sizeof(Context)); - ctx->next = cstk; - hash_init(&ctx->localmac, HASH_SMALL); - ctx->name = p; - ctx->number = unique++; - cstk = ctx; - free_tlist(origline); - return DIRECTIVE_FOUND; - case PP_REPL: - tline = tline->next; - skip_white_(tline); - tline = expand_id(tline); - if (tline) { - if (!tok_type_(tline, TOK_ID)) { - error(ERR_NONFATAL, "`%%repl' expects a context identifier"); - free_tlist(origline); - return DIRECTIVE_FOUND; /* but we did _something_ */ - } - if (tline->next) - error(ERR_WARNING, "trailing garbage after `%%repl' ignored"); - p = nasm_strdup(tline->text); + if (i == PP_PUSH) { + ctx = nasm_malloc(sizeof(Context)); + ctx->next = cstk; + hash_init(&ctx->localmac, HASH_SMALL); + ctx->name = p; + ctx->number = unique++; + cstk = ctx; } else { - p = NULL; + /* %pop or %repl */ + if (!cstk) { + error(ERR_NONFATAL, "`%s': context stack is empty", + pp_directives[i]); + } else if (i == PP_POP) { + if (p && (!cstk->name || nasm_stricmp(p, cstk->name))) + error(ERR_NONFATAL, "`%%pop' in wrong context: %s, " + "expected %s", + cstk->name ? cstk->name : "anonymous", p); + else + ctx_pop(); + } else { + /* i == PP_REPL */ + nasm_free(cstk->name); + cstk->name = p; + p = NULL; + } + nasm_free(p); } - if (!cstk) - error(ERR_NONFATAL, "`%%repl': context stack is empty"); - else { - nasm_free(cstk->name); - cstk->name = p; - } free_tlist(origline); return DIRECTIVE_FOUND; - - case PP_POP: - if (tline->next) - error(ERR_WARNING, "trailing garbage after `%%pop' ignored"); - if (!cstk) - error(ERR_NONFATAL, "`%%pop': context stack is already empty"); - else - ctx_pop(); - free_tlist(origline); - return DIRECTIVE_FOUND; - + case PP_FATAL: + severity = ERR_FATAL; + goto issue_error; case PP_ERROR: + severity = ERR_NONFATAL; + goto issue_error; case PP_WARNING: + severity = ERR_WARNING|ERR_WARN_USER; + goto issue_error; + + issue_error: { - int severity = (i == PP_ERROR) - ? ERR_NONFATAL|ERR_NO_SEVERITY - : ERR_WARNING|ERR_NO_SEVERITY; + /* Only error out if this is the final pass */ + if (pass != 2 && i != PP_FATAL) + return DIRECTIVE_FOUND; tline->next = expand_smacro(tline->next); tline = tline->next; @@ -2377,11 +2466,11 @@ static int do_directive(Token * tline) /* The line contains only a quoted string */ p = tline->text; nasm_unquote(p, NULL); - error(severity, "%s: %s", pp_directives[i], p); + error(severity, "%s", p); } else { /* Not a quoted string, or more than a quoted string */ p = detoken(tline, false); - error(severity, "%s: %s", pp_directives[i], p); + error(severity, "%s", p); nasm_free(p); } free_tlist(origline); @@ -2406,42 +2495,73 @@ static int do_directive(Token * tline) CASE_PP_ELIF: if (!istk->conds) error(ERR_FATAL, "`%s': no matching `%%if'", pp_directives[i]); - if (emitting(istk->conds->state) - || istk->conds->state == COND_NEVER) - istk->conds->state = COND_NEVER; - else { - /* - * IMPORTANT: In the case of %if, we will already have - * called expand_mmac_params(); however, if we're - * processing an %elif we must have been in a - * non-emitting mode, which would have inhibited - * the normal invocation of expand_mmac_params(). Therefore, - * we have to do it explicitly here. - */ - j = if_condition(expand_mmac_params(tline->next), i); - tline->next = NULL; /* it got freed */ - istk->conds->state = - j < 0 ? COND_NEVER : j ? COND_IF_TRUE : COND_IF_FALSE; + switch(istk->conds->state) { + case COND_IF_TRUE: + istk->conds->state = COND_DONE; + break; + + case COND_DONE: + case COND_NEVER: + break; + + case COND_ELSE_TRUE: + case COND_ELSE_FALSE: + error_precond(ERR_WARNING|ERR_PASS1, + "`%%elif' after `%%else' ignored"); + istk->conds->state = COND_NEVER; + break; + + case COND_IF_FALSE: + /* + * IMPORTANT: In the case of %if, we will already have + * called expand_mmac_params(); however, if we're + * processing an %elif we must have been in a + * non-emitting mode, which would have inhibited + * the normal invocation of expand_mmac_params(). + * Therefore, we have to do it explicitly here. + */ + j = if_condition(expand_mmac_params(tline->next), i); + tline->next = NULL; /* it got freed */ + istk->conds->state = + j < 0 ? COND_NEVER : j ? COND_IF_TRUE : COND_IF_FALSE; + break; } free_tlist(origline); return DIRECTIVE_FOUND; case PP_ELSE: if (tline->next) - error(ERR_WARNING, "trailing garbage after `%%else' ignored"); + error_precond(ERR_WARNING|ERR_PASS1, + "trailing garbage after `%%else' ignored"); if (!istk->conds) error(ERR_FATAL, "`%%else': no matching `%%if'"); - if (emitting(istk->conds->state) - || istk->conds->state == COND_NEVER) - istk->conds->state = COND_ELSE_FALSE; - else - istk->conds->state = COND_ELSE_TRUE; + switch(istk->conds->state) { + case COND_IF_TRUE: + case COND_DONE: + istk->conds->state = COND_ELSE_FALSE; + break; + + case COND_NEVER: + break; + + case COND_IF_FALSE: + istk->conds->state = COND_ELSE_TRUE; + break; + + case COND_ELSE_TRUE: + case COND_ELSE_FALSE: + error_precond(ERR_WARNING|ERR_PASS1, + "`%%else' after `%%else' ignored."); + istk->conds->state = COND_NEVER; + break; + } free_tlist(origline); return DIRECTIVE_FOUND; case PP_ENDIF: if (tline->next) - error(ERR_WARNING, "trailing garbage after `%%endif' ignored"); + error_precond(ERR_WARNING|ERR_PASS1, + "trailing garbage after `%%endif' ignored"); if (!istk->conds) error(ERR_FATAL, "`%%endif': no matching `%%if'"); cond = istk->conds; @@ -2473,7 +2593,7 @@ static int do_directive(Token * tline) || defining->plus) && (defining->nparam_min <= mmac->nparam_max || mmac->plus)) { - error(ERR_WARNING, + error(ERR_WARNING|ERR_PASS1, "redefining multi-line macro `%s'", defining->name); return DIRECTIVE_FOUND; } @@ -2544,7 +2664,7 @@ static int do_directive(Token * tline) if (!evalresult) return DIRECTIVE_FOUND; if (tokval.t_type) - error(ERR_WARNING, + error(ERR_WARNING|ERR_PASS1, "trailing garbage after expression ignored"); if (!is_simple(evalresult)) { error(ERR_NONFATAL, "non-constant value given to `%%rotate'"); @@ -2594,7 +2714,7 @@ static int do_directive(Token * tline) return DIRECTIVE_FOUND; } if (tokval.t_type) - error(ERR_WARNING, + error(ERR_WARNING|ERR_PASS1, "trailing garbage after expression ignored"); if (!is_simple(evalresult)) { error(ERR_NONFATAL, "non-constant value given to `%%rep'"); @@ -2688,9 +2808,7 @@ static int do_directive(Token * tline) return DIRECTIVE_FOUND; } - ctx = get_ctx(tline->text, false); - - mname = tline->text; + ctx = get_ctx(tline->text, &mname, false); last = tline; param_start = tline = tline->next; nparam = 0; @@ -2778,13 +2896,13 @@ static int do_directive(Token * tline) return DIRECTIVE_FOUND; } if (tline->next) { - error(ERR_WARNING, + error(ERR_WARNING|ERR_PASS1, "trailing garbage after macro name ignored"); } /* Find the context that symbol belongs to */ - ctx = get_ctx(tline->text, false); - undef_smacro(ctx, tline->text); + ctx = get_ctx(tline->text, &mname, false); + undef_smacro(ctx, mname); free_tlist(origline); return DIRECTIVE_FOUND; @@ -2804,9 +2922,7 @@ static int do_directive(Token * tline) return DIRECTIVE_FOUND; } - ctx = get_ctx(tline->text, false); - - mname = tline->text; + ctx = get_ctx(tline->text, &mname, false); last = tline; tline = expand_smacro(tline->next); last->next = NULL; @@ -2850,9 +2966,7 @@ static int do_directive(Token * tline) free_tlist(origline); return DIRECTIVE_FOUND; } - ctx = get_ctx(tline->text, false); - - mname = tline->text; + ctx = get_ctx(tline->text, &mname, false); last = tline; tline = expand_smacro(tline->next); last->next = NULL; @@ -2869,7 +2983,7 @@ static int do_directive(Token * tline) return DIRECTIVE_FOUND; /* but we did _something_ */ } if (t->next) - error(ERR_WARNING, + error(ERR_WARNING|ERR_PASS1, "trailing garbage after `%%pathsearch' ignored"); p = t->text; if (t->type != TOK_INTERNAL_STRING) @@ -2913,9 +3027,7 @@ static int do_directive(Token * tline) free_tlist(origline); return DIRECTIVE_FOUND; } - ctx = get_ctx(tline->text, false); - - mname = tline->text; + ctx = get_ctx(tline->text, &mname, false); last = tline; tline = expand_smacro(tline->next); last->next = NULL; @@ -2961,9 +3073,7 @@ static int do_directive(Token * tline) free_tlist(origline); return DIRECTIVE_FOUND; } - ctx = get_ctx(tline->text, false); - - mname = tline->text; + ctx = get_ctx(tline->text, &mname, false); last = tline; tline = expand_smacro(tline->next); last->next = NULL; @@ -3029,9 +3139,7 @@ static int do_directive(Token * tline) free_tlist(origline); return DIRECTIVE_FOUND; } - ctx = get_ctx(tline->text, false); - - mname = tline->text; + ctx = get_ctx(tline->text, &mname, false); last = tline; tline = expand_smacro(tline->next); last->next = NULL; @@ -3126,9 +3234,7 @@ static int do_directive(Token * tline) free_tlist(origline); return DIRECTIVE_FOUND; } - ctx = get_ctx(tline->text, false); - - mname = tline->text; + ctx = get_ctx(tline->text, &mname, false); last = tline; tline = expand_smacro(tline->next); last->next = NULL; @@ -3145,7 +3251,7 @@ static int do_directive(Token * tline) } if (tokval.t_type) - error(ERR_WARNING, + error(ERR_WARNING|ERR_PASS1, "trailing garbage after expression ignored"); if (!is_simple(evalresult)) { @@ -3251,13 +3357,118 @@ static int find_cc(Token * t) return i; } +static bool paste_tokens(Token **head, bool handle_paste_tokens) +{ + Token **tail, *t, *tt; + Token **paste_head; + bool did_paste = false; + char *tmp; + + /* Now handle token pasting... */ + paste_head = NULL; + tail = head; + while ((t = *tail) && (tt = t->next)) { + switch (t->type) { + case TOK_WHITESPACE: + if (tt->type == TOK_WHITESPACE) { + /* Zap adjacent whitespace tokens */ + t->next = delete_Token(tt); + } else { + /* Do not advance paste_head here */ + tail = &t->next; + } + break; + case TOK_ID: + case TOK_PREPROC_ID: + case TOK_NUMBER: + case TOK_FLOAT: + { + size_t len = 0; + char *tmp, *p; + + while (tt && (tt->type == TOK_ID || tt->type == TOK_PREPROC_ID || + tt->type == TOK_NUMBER || tt->type == TOK_FLOAT || + tt->type == TOK_OTHER)) { + len += strlen(tt->text); + tt = tt->next; + } + + /* Now tt points to the first token after the potential + paste area... */ + if (tt != t->next) { + /* We have at least two tokens... */ + len += strlen(t->text); + p = tmp = nasm_malloc(len+1); + + while (t != tt) { + strcpy(p, t->text); + p = strchr(p, '\0'); + t = delete_Token(t); + } + + t = *tail = tokenize(tmp); + nasm_free(tmp); + + while (t->next) { + tail = &t->next; + t = t->next; + } + t->next = tt; /* Attach the remaining token chain */ + + did_paste = true; + } + paste_head = tail; + tail = &t->next; + break; + } + case TOK_PASTE: /* %+ */ + if (handle_paste_tokens) { + /* Zap %+ and whitespace tokens to the right */ + while (t && (t->type == TOK_WHITESPACE || + t->type == TOK_PASTE)) + t = *tail = delete_Token(t); + if (!paste_head || !t) + break; /* Nothing to paste with */ + tail = paste_head; + t = *tail; + tt = t->next; + while (tok_type_(tt, TOK_WHITESPACE)) + tt = t->next = delete_Token(tt); + + if (tt) { + tmp = nasm_strcat(t->text, tt->text); + delete_Token(t); + tt = delete_Token(tt); + t = *tail = tokenize(tmp); + nasm_free(tmp); + while (t->next) { + tail = &t->next; + t = t->next; + } + t->next = tt; /* Attach the remaining token chain */ + did_paste = true; + } + paste_head = tail; + tail = &t->next; + break; + } + /* else fall through */ + default: + tail = paste_head = &t->next; + break; + } + } + return did_paste; +} /* * Expand MMacro-local things: parameter references (%0, %n, %+n, - * %-n) and MMacro-local identifiers (%%foo). + * %-n) and MMacro-local identifiers (%%foo) as well as + * macro indirection (%[...]). */ static Token *expand_mmac_params(Token * tline) { Token *t, *tt, **tail, *thead; + bool changed = false; tail = &thead; thead = NULL; @@ -3322,8 +3533,7 @@ static Token *expand_mmac_params(Token * tline) conditions[cc]); text = NULL; } else - text = - nasm_strdup(conditions[inverse_ccs[cc]]); + text = nasm_strdup(conditions[inverse_ccs[cc]]); } break; case '+': @@ -3375,7 +3585,22 @@ static Token *expand_mmac_params(Token * tline) t->text = text; t->a.mac = NULL; } + changed = true; continue; + } else if (tline->type == TOK_INDIRECT) { + t = tline; + tline = tline->next; + tt = tokenize(t->text); + tt = expand_mmac_params(tt); + tt = expand_smacro(tt); + *tail = tt; + while (tt) { + tt->a.mac = NULL; /* Necessary? */ + tail = &tt->next; + tt = tt->next; + } + delete_Token(t); + changed = true; } else { t = *tail = tline; tline = tline->next; @@ -3384,33 +3609,9 @@ static Token *expand_mmac_params(Token * tline) } } *tail = NULL; - t = thead; - for (; t && (tt = t->next) != NULL; t = t->next) - switch (t->type) { - case TOK_WHITESPACE: - if (tt->type == TOK_WHITESPACE) { - t->next = delete_Token(tt); - } - break; - case TOK_ID: - if (tt->type == TOK_ID || tt->type == TOK_NUMBER) { - char *tmp = nasm_strcat(t->text, tt->text); - nasm_free(t->text); - t->text = tmp; - t->next = delete_Token(tt); - } - break; - case TOK_NUMBER: - if (tt->type == TOK_NUMBER) { - char *tmp = nasm_strcat(t->text, tt->text); - nasm_free(t->text); - t->text = tmp; - t->next = delete_Token(tt); - } - break; - default: - break; - } + + if (changed) + paste_tokens(&thead, false); return thead; } @@ -3432,11 +3633,12 @@ static Token *expand_smacro(Token * tline) Token **params; int *paramsize; unsigned int nparam, sparam; - int brackets, rescan; + int brackets; Token *org_tline = tline; Context *ctx; - char *mname; + const char *mname; int deadman = DEADMAN_LIMIT; + bool expanded; /* * Trick: we should avoid changing the start token pointer since it can @@ -3453,6 +3655,8 @@ static Token *expand_smacro(Token * tline) org_tline->text = NULL; } + expanded = true; /* Always expand %+ at least once */ + again: tail = &thead; thead = NULL; @@ -3465,13 +3669,11 @@ again: if ((mname = tline->text)) { /* if this token is a local macro, look in local context */ - ctx = NULL; - smtbl = &smacros; - if (tline->type == TOK_ID || tline->type == TOK_PREPROC_ID) { - ctx = get_ctx(mname, true); - if (ctx) - smtbl = &ctx->localmac; - } + if (tline->type == TOK_ID || tline->type == TOK_PREPROC_ID) + ctx = get_ctx(mname, &mname, true); + else + ctx = NULL; + smtbl = ctx ? &ctx->localmac : &smacros; head = (SMacro *) hash_findix(smtbl, mname); /* @@ -3633,7 +3835,7 @@ again: m->casesense))) m = m->next; if (!m) - error(ERR_WARNING | ERR_WARN_MNP, + error(ERR_WARNING|ERR_PASS1|ERR_WARN_MNP, "macro `%s' exists, " "but not taking %d parameters", mstart->text, nparam); @@ -3702,6 +3904,7 @@ again: nasm_free(params); nasm_free(paramsize); free_tlist(mstart); + expanded = true; continue; /* main token loop */ } } @@ -3726,38 +3929,13 @@ again: * Also we look for %+ tokens and concatenate the tokens before and after * them (without white spaces in between). */ - t = thead; - rescan = 0; - while (t) { - while (t && t->type != TOK_ID && t->type != TOK_PREPROC_ID) - t = t->next; - if (!t || !t->next) - break; - if (t->next->type == TOK_ID || - t->next->type == TOK_PREPROC_ID || - t->next->type == TOK_NUMBER) { - char *p = nasm_strcat(t->text, t->next->text); - nasm_free(t->text); - t->next = delete_Token(t->next); - t->text = p; - rescan = 1; - } else if (t->next->type == TOK_WHITESPACE && t->next->next && - t->next->next->type == TOK_PREPROC_ID && - strcmp(t->next->next->text, "%+") == 0) { - /* free the next whitespace, the %+ token and next whitespace */ - int i; - for (i = 1; i <= 3; i++) { - if (!t->next - || (i != 2 && t->next->type != TOK_WHITESPACE)) - break; - t->next = delete_Token(t->next); - } /* endfor */ - } else - t = t->next; - } - /* If we concatenaded something, re-scan the line for macros */ - if (rescan) { + if (expanded && paste_tokens(&thead, true)) { + /* + * If we concatenated something, *and* we had previously expanded + * an actual macro, scan the lines again for macros... + */ tline = thead; + expanded = false; goto again; } @@ -3935,7 +4113,7 @@ static MMacro *is_mmacro(Token * tline, Token *** params_array) * After all that, we didn't find one with the right number of * parameters. Issue a warning, and fail to expand the macro. */ - error(ERR_WARNING | ERR_WARN_MNP, + error(ERR_WARNING|ERR_PASS1|ERR_WARN_MNP, "macro `%s' exists, but not taking %d parameters", tline->text, nparam); nasm_free(params); @@ -4115,36 +4293,62 @@ static int expand_mmacro(Token * tline) return 1; } +/* The function that actually does the error reporting */ +static void verror(int severity, const char *fmt, va_list arg) +{ + char buff[1024]; + + vsnprintf(buff, sizeof(buff), fmt, arg); + + if (istk && istk->mstk && istk->mstk->name) + _error(severity, "(%s:%d) %s", istk->mstk->name, + istk->mstk->lineno, buff); + else + _error(severity, "%s", buff); +} + /* * Since preprocessor always operate only on the line that didn't - * arrived yet, we should always use ERR_OFFBY1. Also since user - * won't want to see same error twice (preprocessing is done once - * per pass) we will want to show errors only during pass one. + * arrived yet, we should always use ERR_OFFBY1. */ static void error(int severity, const char *fmt, ...) { va_list arg; - char buff[1024]; /* If we're in a dead branch of IF or something like it, ignore the error */ if (istk && istk->conds && !emitting(istk->conds->state)) return; va_start(arg, fmt); - vsnprintf(buff, sizeof(buff), fmt, arg); + verror(severity, fmt, arg); va_end(arg); +} - if (istk && istk->mstk && istk->mstk->name) - _error(severity | ERR_PASS1, "(%s:%d) %s", istk->mstk->name, - istk->mstk->lineno, buff); - else - _error(severity | ERR_PASS1, "%s", buff); +/* + * Because %else etc are evaluated in the state context + * of the previous branch, errors might get lost with error(): + * %if 0 ... %else trailing garbage ... %endif + * So %else etc should report errors with this function. + */ +static void error_precond(int severity, const char *fmt, ...) +{ + va_list arg; + + /* Only ignore the error if it's really in a dead branch */ + if (istk && istk->conds && istk->conds->state == COND_NEVER) + return; + + va_start(arg, fmt); + verror(severity, fmt, arg); + va_end(arg); } static void pp_reset(char *file, int apass, efunc errfunc, evalfunc eval, ListGen * listgen, StrList **deplist) { + Token *t; + _error = errfunc; cstk = NULL; istk = nasm_malloc(sizeof(Include)); @@ -4158,7 +4362,7 @@ pp_reset(char *file, int apass, efunc errfunc, evalfunc eval, src_set_linnum(0); istk->lineinc = 1; if (!istk->fp) - error(ERR_FATAL | ERR_NOFILE, "unable to open input file `%s'", + error(ERR_FATAL|ERR_NOFILE, "unable to open input file `%s'", file); defining = NULL; nested_mac_count = 0; @@ -4174,7 +4378,14 @@ pp_reset(char *file, int apass, efunc errfunc, evalfunc eval, do_predef = true; list = listgen; evaluate = eval; - pass = apass; + + /* + * 0 for dependencies, 1 for preparatory passes, 2 for final pass. + * The caller, however, will also pass in 3 for preprocess-only so + * we can set __PASS__ accordingly. + */ + pass = apass > 2 ? 2 : apass; + dephead = deptail = deplist; if (deplist) { StrList *sl = nasm_malloc(strlen(file)+1+sizeof sl->next); @@ -4183,6 +4394,17 @@ pp_reset(char *file, int apass, efunc errfunc, evalfunc eval, *deptail = sl; deptail = &sl->next; } + + /* + * Define the __PASS__ macro. This is defined here unlike + * all the other builtins, because it is special -- it varies between + * passes. + */ + t = nasm_malloc(sizeof(*t)); + t->next = NULL; + make_tok_num(t, apass); + t->a.mac = NULL; + define_smacro(NULL, "__PASS__", true, 0, t); } static char *pp_getline(void) @@ -4319,6 +4541,8 @@ static char *pp_getline(void) nasm_free(i); if (!istk) return NULL; + if (istk->expansion && istk->expansion->finishes) + break; } } @@ -4333,8 +4557,9 @@ static char *pp_getline(void) * anything. */ if (!defining && !(istk->conds && !emitting(istk->conds->state)) - && !(istk->mstk && !istk->mstk->in_progress)) + && !(istk->mstk && !istk->mstk->in_progress)) { tline = expand_mmac_params(tline); + } /* * Check the line to see if it's a preprocessor directive. @@ -1,9 +1,38 @@ -/* preproc.h header file for preproc.c +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * preproc.h header file for preproc.c */ #ifndef NASM_PREPROC_H @@ -1,9 +1,38 @@ -/* quote.c library routines for the Netwide Assembler +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * quote.c */ #include "compiler.h" @@ -1,3 +1,36 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + #ifndef NASM_QUOTE_H #define NASM_QUOTE_H @@ -1,3 +1,36 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + #include "nasmlib.h" #include "raa.h" @@ -1,3 +1,36 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + #ifndef NASM_RAA_H #define NASM_RAA_H 1 diff --git a/rdoff/Makefile.in b/rdoff/Makefile.in index 2ceb9548..93f2e2af 100644 --- a/rdoff/Makefile.in +++ b/rdoff/Makefile.in @@ -37,7 +37,7 @@ O = @OBJEXT@ X = @EXEEXT@ PROGRAMS = rdfdump$(X) ldrdf$(X) rdx$(X) rdflib$(X) \ - rdf2bin$(X) rdf2com$(X) rdf2ihx$(X) + rdf2bin$(X) rdf2com$(X) rdf2ith$(X) rdf2ihx$(X) rdf2srec$(X) .SUFFIXES: .c .i .s .$(O) .1 .man @@ -58,8 +58,12 @@ rdf2bin$(X): rdf2bin.$(O) $(RDXLIBS) nasmlib.$(O) $(CC) $(LDFLAGS) -o rdf2bin$(X) rdf2bin.$(O) $(RDXLIBS) nasmlib.$(O) rdf2com$(X): rm -f rdf2com$(X) && $(LN_S) rdf2bin$(X) rdf2com$(X) -rdf2ihx$(X): rdf2ihx.$(O) $(RDXLIBS) nasmlib.$(O) - $(CC) $(LDFLAGS) -o rdf2ihx$(X) rdf2ihx.$(O) $(RDXLIBS) nasmlib.$(O) +rdf2ith$(X): + rm -f rdf2ith$(X) && $(LN_S) rdf2bin$(X) rdf2ith$(X) +rdf2ihx$(X): + rm -f rdf2ihx$(X) && $(LN_S) rdf2bin$(X) rdf2ihx$(X) +rdf2srec$(X): + rm -f rdf2srec$(X) && $(LN_S) rdf2bin$(X) rdf2srec$(X) rdf2ihx.$(O): rdf2ihx.c rdf2bin.$(O): rdf2bin.c @@ -93,7 +97,9 @@ install: all $(INSTALL_PROGRAM) rdx$(X) $(INSTALLROOT)$(bindir)/rdx$(X) $(INSTALL_PROGRAM) rdflib$(X) $(INSTALLROOT)$(bindir)/rdflib$(X) $(INSTALL_PROGRAM) rdf2bin$(X) $(INSTALLROOT)$(bindir)/rdf2bin$(X) - $(INSTALL_PROGRAM) rdf2ihx$(X) $(INSTALLROOT)$(bindir)/rdf2ihx$(X) cd $(INSTALLROOT)$(bindir) && rm -f rdf2com$(X) && $(LN_S) rdf2bin$(X) rdf2com$(X) + cd $(INSTALLROOT)$(bindir) && rm -f rdf2ith$(X) && $(LN_S) rdf2bin$(X) rdf2ith$(X) + cd $(INSTALLROOT)$(bindir) && rm -f rdf2ihx$(X) && $(LN_S) rdf2bin$(X) rdf2ihx$(X) + cd $(INSTALLROOT)$(bindir) && rm -f rdf2srec$(X) && $(LN_S) rdf2bin$(X) rdf2srec$(X) $(MKDIR) -p $(INSTALLROOT)$(mandir)/man1 $(INSTALL_DATA) $(srcdir)/*.1 $(INSTALLROOT)$(mandir)/man1/ diff --git a/rdoff/hash.c b/rdoff/hash.c index ebf13598..ad2b568e 100644 --- a/rdoff/hash.c +++ b/rdoff/hash.c @@ -1,11 +1,40 @@ -/* hash.h Routines to calculate a CRC32 hash value +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * These routines donated to the NASM effort by Graeme Defty. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * ----------------------------------------------------------------------- */ + +/* + * hash.h Routines to calculate a CRC32 hash value + * + * These routines donated to the NASM effort by Graeme Defty. */ #include "compiler.h" diff --git a/rdoff/ldrdf.c b/rdoff/ldrdf.c index 046139b3..2ddada33 100644 --- a/rdoff/ldrdf.c +++ b/rdoff/ldrdf.c @@ -1,12 +1,38 @@ -/* - * ldrdf.c - RDOFF Object File linker/loader main program. +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: * - * Copyright (c) 1996,99 Julian Hall. All rights reserved. - * Improvements and fixes (c) 1999-2004 RET & COM Research. + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * This file is distributed under the terms and conditions of the - * GNU Lesser Public License (LGPL), version 2.1. - * See http://www.gnu.org/copyleft/lgpl.html for details. + * ----------------------------------------------------------------------- */ + +/* + * ldrdf.c - RDOFF Object File linker/loader main program. */ /* @@ -37,6 +63,7 @@ #include "collectn.h" #include "rdlib.h" #include "segtab.h" +#include "nasmlib.h" #define LDRDF_VERSION "1.07" @@ -1119,7 +1146,7 @@ void write_output(const char *filename) fwrite(outputseg[i].data, outputseg[i].length, 1, f); } - fwrite("\0\0\0\0\0\0\0\0\0\0", 10, 1, f); + fwritezero(10, f); } /* ========================================================================= diff --git a/rdoff/rdf2bin.1 b/rdoff/rdf2bin.1 index 85d6b930..d274d580 100644 --- a/rdoff/rdf2bin.1 +++ b/rdoff/rdf2bin.1 @@ -3,29 +3,63 @@ rdf2bin, rdf2com \- convert an RDOFF object file to flat binary .SH SYNOPSIS .B rdf2bin -.RI "[-o " relocation-origin ] -.RI "[-p " segment-alignment ] +.RI "[\-o " relocation-origin ] +.RI "[\-p " segment-alignment ] +.RI "[\-f " format ] .I input-file .I output-file .br .B rdf2com -.RI "[-p " segment-alignment ] +.RI "[\-p " segment-alignment ] +.I input-file +.I output-file +.br +.B rdf2ith +.RI "[\-o " relocation-origin ] +.RI "[\-p " segment-alignment ] +.I input-file +.I output-file +.br +.B rdf2srec +.RI "[\-o " relocation-origin ] +.RI "[\-p " segment-alignment ] .I input-file .I output-file .SH OPTIONS .TP -.RI "-o " relocation-origin +.RI "\-o " relocation-origin Relocate at origin .IR relocation-origin . If invoked as .BR rdf2com , the default relocation origin will be 0x100. Else, the default origin is 0. .TP -.RI "-p " segment-alignment +.RI "\-p " segment-alignment Pad segments until their size is a multiple of .IR segment-alignment . By default, 16 is used. +.TP +.RI "\-f " format +Specify the output format. The currently supported formats are binary +.RI ( bin ), +DOS COM (binary with origin 0x100) +.RI ( com ) +Intel hex +.RI ( ith +or +.IR ihx ), +and +Motorola S-Records +.RI ( srec ). +If not specified, the format is set by the command name. .SH AUTHORS -Julian Hall <jules@earthcorp.com>. +Julian Hall <jules@earthcorp.com>, H. Peter Anvin <hpa@zytor.com>. .PP This manual page was written by Matej Vela <vela@debian.org>. +.SH BUGS +This utility currently only supports the classic segments +.IR .text , +.I .data +and +.IR .bss . + diff --git a/rdoff/rdf2bin.c b/rdoff/rdf2bin.c index c23b18c4..72e5104b 100644 --- a/rdoff/rdf2bin.c +++ b/rdoff/rdf2bin.c @@ -1,3 +1,36 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + /* * rdf2bin.c - convert an RDOFF object file to flat binary */ @@ -7,24 +40,251 @@ #include <stdlib.h> #include <stdio.h> #include <string.h> +#include <ctype.h> +#include <errno.h> #include "rdfload.h" #include "nasmlib.h" -int32_t origin = 0; -int align = 16; +const char *progname; + +static uint32_t origin = 0; +static bool origin_def = false; +static uint32_t align = 16; +static bool align_def = false; + +struct output_format { + const char *name; + const char *mode; + int (*init)(FILE *f); + int (*output)(FILE *f, void *data, uint32_t bytes, uint32_t where); + int (*fini)(FILE *f); +}; + +static int null_init_fini(FILE *f) +{ + (void)f; + return 0; +} + +static int com_init(FILE *f) +{ + (void)f; + if (!origin_def) + origin = 0x100; + return 0; +} + +static int output_bin(FILE *f, void *data, uint32_t bytes, uint32_t where) +{ + static uint32_t offset = 0; /* Current file offset, if applicable */ + size_t pad; + + if (where-origin < offset) { + fprintf(stderr, "%s: internal error: backwards movement\n", progname); + exit(1); + } + + pad = (where-origin) - offset; + if (fwritezero(pad, f) != pad) + return -1; + offset += pad; + + if (fwrite(data, 1, bytes, f) != bytes) + return -1; + offset += bytes; + + return 0; +} + +static int write_ith_record(FILE *f, unsigned int len, uint16_t addr, + uint8_t type, void *data) +{ + char buf[1+2+4+2+255*2+2+2]; + char *p = buf; + uint8_t csum, *dptr = data; + unsigned int i; + + if (len > 255) { + fprintf(stderr, "%s: internal error: invalid ith record size\n", + progname); + exit(1); + } + + csum = len + addr + (addr >> 8) + type; + for (i = 0; i < len; i++) + csum += dptr[i]; + csum = -csum; + + p += sprintf(p, ":%02X%04X%02X", len, addr, type); + for (i = 0; i < len; i++) + p += sprintf(p, "%02X", dptr[i]); + p += sprintf(p, "%02X\n", csum); + + if (fwrite(buf, 1, p-buf, f) != (size_t)(p-buf)) + return -1; + + return 0; +} + +static int output_ith(FILE *f, void *data, uint32_t bytes, uint32_t where) +{ + static uint32_t last = 0; /* Last address written */ + uint8_t abuf[2]; + uint8_t *dbuf = data; + uint32_t chunk; + + while (bytes) { + if ((where ^ last) & ~0xffff) { + abuf[0] = where >> 24; + abuf[1] = where >> 16; + if (write_ith_record(f, 2, 0, 4, abuf)) + return -1; + } + + /* Output up to 32 bytes, but always end on an aligned boundary */ + chunk = 32 - (where & 31); + if (bytes < chunk) + chunk = bytes; + + if (write_ith_record(f, chunk, (uint16_t)where, 0, dbuf)) + return -1; + + dbuf += chunk; + last = where + chunk - 1; + where += chunk; + bytes -= chunk; + } + return 0; +} + +static int fini_ith(FILE *f) +{ + /* XXX: entry point? */ + return write_ith_record(f, 0, 0, 1, NULL); +} + +static int write_srecord(FILE *f, unsigned int len, unsigned int alen, + uint32_t addr, uint8_t type, void *data) +{ + char buf[2+2+8+255*2+2+2]; + char *p = buf; + uint8_t csum, *dptr = data; + unsigned int i; + + if (len > 255) { + fprintf(stderr, "%s: internal error: invalid srec record size\n", + progname); + exit(1); + } + + switch (alen) { + case 2: + addr &= 0xffff; + break; + case 3: + addr &= 0xffffff; + break; + case 4: + break; + default: + fprintf(stderr, "%s: internal error: invalid srec address length\n", + progname); + exit(1); + } + + csum = (len+alen+1) + addr + (addr >> 8) + (addr >> 16) + (addr >> 24); + for (i = 0; i < len; i++) + csum += dptr[i]; + csum = 0xff-csum; + + p += sprintf(p, "S%c%02X%0*X", type, len+alen+1, alen*2, addr); + for (i = 0; i < len; i++) + p += sprintf(p, "%02X", dptr[i]); + p += sprintf(p, "%02X\n", csum); + + if (fwrite(buf, 1, p-buf, f) != (size_t)(p-buf)) + return -1; -char *getfilename(char *pathname) + return 0; +} + +static int init_srec(FILE *f) { - char *lastslash = pathname - 1; - char *i = pathname; + return write_srecord(f, 0, 2, 0, '0', NULL); +} - while (*i) { - if (*i == '/') - lastslash = i; - i++; +static int fini_srec(FILE *f) +{ + /* XXX: entry point? */ + return write_srecord(f, 0, 4, 0, '7', NULL); +} + +static int output_srec(FILE *f, void *data, uint32_t bytes, uint32_t where) +{ + uint8_t *dbuf = data; + unsigned int chunk; + + while (bytes) { + /* Output up to 32 bytes, but always end on an aligned boundary */ + chunk = 32 - (where & 31); + if (bytes < chunk) + chunk = bytes; + + if (write_srecord(f, chunk, 4, where, '3', dbuf)) + return -1; + + dbuf += chunk; + where += chunk; + bytes -= chunk; } - return lastslash + 1; + return 0; +} + +static struct output_format output_formats[] = { + { "bin", "wb", null_init_fini, output_bin, null_init_fini }, + { "com", "wb", com_init, output_bin, null_init_fini }, + { "ith", "wt", null_init_fini, output_ith, fini_ith }, + { "ihx", "wt", null_init_fini, output_ith, fini_ith }, + { "srec", "wt", init_srec, output_srec, fini_srec }, + { NULL, NULL, NULL, NULL, NULL } +}; + +static const char *getformat(const char *pathname) +{ + const char *p; + static char fmt_buf[16]; + + /* + * Search backwards for the string "rdf2" followed by a string + * of alphanumeric characters. This should handle path prefixes, + * as well as extensions (e.g. C:\FOO\RDF2SREC.EXE). + */ + for (p = strchr(pathname, '\0')-1 ; p >= pathname ; p--) { + if (!nasm_stricmp(p, "rdf2")) { + const char *q = p+4; + char *r = fmt_buf; + while (isalnum(*q) && r < fmt_buf+sizeof fmt_buf-1) + *r++ = *q++; + *r = '\0'; + if (fmt_buf[0]) + return fmt_buf; + } + } + return NULL; +} + +static void usage(void) +{ + fprintf(stderr, + "Usage: %s [options] input-file output-file\n" + "Options:\n" + " -o origin Specify the relocation origin\n" + " -p alignment Specify minimum segment alignment\n" + " -f format Select format (bin, com, ith, srec)\n" + " -q Run quiet\n" + " -v Run verbose\n", + progname); } int main(int argc, char **argv) @@ -32,58 +292,99 @@ int main(int argc, char **argv) rdfmodule *m; bool err; FILE *of; - char *padding; - int codepad, datapad, bsspad = 0; + int codepad, datapad; + const char *format = NULL; + const struct output_format *fmt; + bool quiet = false; + + progname = argv[0]; if (argc < 2) { - puts("Usage: rdf2bin [-o relocation-origin] [-p segment-alignment] " "input-file output-file"); - puts(" rdf2com [-p segment-alignment] input-file output-file"); + usage(); return 1; } - if (!nasm_stricmp(getfilename(*argv), "rdf2com")) { - origin = 0x100; - } argv++, argc--; while (argc > 2) { - if (!strcmp(*argv, "-o")) { - argv++, argc--; - origin = readnum(*argv, &err); - if (err) { - fprintf(stderr, "rdf2bin: invalid parameter: %s\n", *argv); - return 1; - } - } else if (!strcmp(*argv, "-p")) { - argv++, argc--; - align = readnum(*argv, &err); - if (err) { - fprintf(stderr, "rdf2bin: invalid parameter: %s\n", *argv); - return 1; - } - } else if (!strcmp(*argv, "-b")) { - argv++, argc--; - bsspad = readnum(*argv, &err); - if (err) { - fprintf(stderr, "rdf2bin: invalid parameter: %s\n", *argv); - return 1; - } - } else - break; - + if (argv[0][0] == '-' && argv[0][1] && !argv[0][2]) { + switch (argv[0][1]) { + case 'o': + argv++, argc--; + origin = readnum(*argv, &err); + if (err) { + fprintf(stderr, "%s: invalid parameter: %s\n", + progname, *argv); + return 1; + } + origin_def = true; + break; + case 'p': + argv++, argc--; + align = readnum(*argv, &err); + if (err) { + fprintf(stderr, "%s: invalid parameter: %s\n", + progname, *argv); + return 1; + } + align_def = true; + break; + case 'f': + argv++, argc--; + format = *argv; + break; + case 'q': + quiet = true; + break; + case 'v': + quiet = false; + break; + case 'h': + usage(); + return 0; + default: + fprintf(stderr, "%s: unknown option: %s\n", + progname, *argv); + return 1; + } + } argv++, argc--; } + if (argc < 2) { - puts("rdf2bin: required parameter missing"); - return -1; + usage(); + return 1; + } + + if (!format) + format = getformat(progname); + + if (!format) { + fprintf(stderr, "%s: unable to determine desired output format\n", + progname); + return 1; } + + for (fmt = output_formats; fmt->name; fmt++) { + if (!nasm_stricmp(format, fmt->name)) + break; + } + + if (!fmt->name) { + fprintf(stderr, "%s: unknown output format: %s\n", progname, format); + return 1; + } + m = rdfload(*argv); if (!m) { - rdfperror("rdf2bin", *argv); + rdfperror(progname, *argv); return 1; } - printf("relocating %s: origin=%"PRIx32", align=%d\n", *argv, origin, align); + + if (!quiet) + printf("relocating %s: origin=%"PRIx32", align=%d\n", + *argv, origin, align); m->textrel = origin; m->datarel = origin + m->f.seg[0].length; @@ -100,37 +401,30 @@ int main(int argc, char **argv) } else datapad = 0; - printf("code: %08"PRIx32"\ndata: %08"PRIx32"\nbss: %08"PRIx32"\n", - m->textrel, m->datarel, m->bssrel); + if (!quiet) + printf("code: %08"PRIx32"\ndata: %08"PRIx32"\nbss: %08"PRIx32"\n", + m->textrel, m->datarel, m->bssrel); rdf_relocate(m); argv++; - of = fopen(*argv, "wb"); + of = fopen(*argv, fmt->mode); if (!of) { - fprintf(stderr, "rdf2bin: could not open output file %s\n", *argv); + fprintf(stderr, "%s: could not open output file %s: %s\n", + progname, *argv, strerror(errno)); return 1; } - padding = malloc(align); - if (!padding) { - fprintf(stderr, "rdf2bin: out of memory\n"); + if (fmt->init(of) || + fmt->output(of, m->t, m->f.seg[0].length, m->textrel) || + fmt->output(of, m->d, m->f.seg[1].length, m->datarel) || + fmt->fini(of)) { + fprintf(stderr, "%s: error writing to %s: %s\n", + progname, *argv, strerror(errno)); return 1; } - if (fwrite(m->t, 1, m->f.seg[0].length, of) != (size_t)m->f.seg[0].length || - fwrite(padding, 1, codepad, of) != (size_t)codepad || - fwrite(m->d, 1, m->f.seg[1].length, of) != (size_t)m->f.seg[1].length) { - fprintf(stderr, "rdf2bin: error writing to %s\n", *argv); - return 1; - } - - if (bsspad) { - void *p = calloc(bsspad -= (m->bssrel - origin), 1); - fwrite(p, 1, bsspad, of); - } - fclose(of); return 0; } diff --git a/rdoff/rdf2ihx.c b/rdoff/rdf2ihx.c deleted file mode 100644 index 5e9fba0b..00000000 --- a/rdoff/rdf2ihx.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * rdf2ihx.c - convert an RDOFF object file to Intel Hex format. - * This is based on rdf2bin. - * Note that this program only writes 16-bit HEX. - */ - -#include "compiler.h" - -#include <stdlib.h> -#include <stdio.h> -#include <string.h> - -#include "rdfload.h" -#include "nasmlib.h" -#include "symtab.h" - -int32_t origin = 0; -int align = 16; - -/* This function writes a single n-byte data record to of. Maximum value - for n is 255. */ -static int write_data_record(FILE * of, int ofs, int nbytes, - uint8_t *data) -{ - int i, iofs; - unsigned int checksum; - - iofs = ofs; - fprintf(of, ":%02X%04X00", nbytes, ofs); - checksum = 0; - for (i = 0; i < nbytes; i++) { - fprintf(of, "%02X", data[i]); - ofs++; - checksum += data[i]; - } - checksum = checksum + /* current checksum */ - nbytes + /* RECLEN (one byte) */ - ((iofs >> 8) & 0xff) + /* high byte of load offset */ - (iofs & 0xff); /* low byte of load offset */ - checksum = ~checksum + 1; - fprintf(of, "%02X\n", checksum & 0xff); - return (ofs); -} - -int main(int argc, char **argv) -{ - rdfmodule *m; - bool err; - FILE *of; - char *padding; - uint8_t *segbin[2]; - int pad[2], segn, ofs, i; - int32_t segaddr; - unsigned int checksum; - symtabEnt *s; - - if (argc < 2) { - puts("Usage: rdf2ihx [-o relocation-origin] [-p segment-alignment] " "input-file output-file"); - return (1); - } - - argv++, argc--; - - while (argc > 2) { - if (strcmp(*argv, "-o") == 0) { - argv++, argc--; - origin = readnum(*argv, &err); - if (err) { - fprintf(stderr, "rdf2ihx: invalid parameter: %s\n", *argv); - return 1; - } - } else if (strcmp(*argv, "-p") == 0) { - argv++, argc--; - align = readnum(*argv, &err); - if (err) { - fprintf(stderr, "rdf2ihx: invalid parameter: %s\n", *argv); - return 1; - } - } else - break; - argv++, argc--; - } - if (argc < 2) { - puts("rdf2ihx: required parameter missing"); - return -1; - } - m = rdfload(*argv); - - if (!m) { - rdfperror("rdf2ihx", *argv); - return 1; - } - printf("relocating %s: origin=%"PRIx32", align=%d\n", *argv, origin, align); - - m->textrel = origin; - m->datarel = origin + m->f.seg[0].length; - if (m->datarel % align != 0) { - pad[0] = align - (m->datarel % align); - m->datarel += pad[0]; - } else { - pad[0] = 0; - } - - m->bssrel = m->datarel + m->f.seg[1].length; - if (m->bssrel % align != 0) { - pad[1] = align - (m->bssrel % align); - m->bssrel += pad[1]; - } else { - pad[1] = 0; - } - - printf("code: %08"PRIx32"\ndata: %08"PRIx32"\nbss: %08"PRIx32"\n", - m->textrel, m->datarel, m->bssrel); - - rdf_relocate(m); - - argv++; - - of = fopen(*argv, "w"); - if (!of) { - fprintf(stderr, "rdf2ihx: could not open output file %s\n", *argv); - return (1); - } - - padding = malloc(align); - if (!padding) { - fprintf(stderr, "rdf2ihx: out of memory\n"); - return (1); - } - - /* write extended segment address record */ - fprintf(of, ":02000002"); /* Record mark, reclen, load offset & rectyp - fields for ext. seg. address record */ - segaddr = ((origin >> 16) & 0xffff); /* segment address */ - fprintf(of, "%04X", (unsigned int)(segaddr & 0xffff)); - checksum = 0x02 + /* reclen */ - 0x0000 + /* Load Offset */ - 0x02 + /* Rectyp */ - (segaddr & 0xff) + /* USBA low */ - ((segaddr >> 8) & 0xff); /* USBA high */ - checksum = ~checksum + 1; /* two's-complement the checksum */ - fprintf(of, "%02X\n", checksum & 0xff); - - /* See if there's a '_main' symbol in the symbol table */ - if ((s = symtabFind(m->symtab, "_main")) == NULL) { - printf - ("No _main symbol found, no start segment address record added\n"); - } else { - printf("_main symbol found at %04x:%04x\n", s->segment, - (unsigned int)(s->offset & 0xffff)); - /* Create a start segment address record for the _main symbol. */ - segaddr = ((s->segment & 0xffff) << 16) + ((s->offset) & 0xffff); - fprintf(of, ":04000003"); /* Record mark, reclen, load offset & rectyp - fields for start seg. addr. record */ - fprintf(of, "%08"PRIX32"", segaddr); /* CS/IP field */ - checksum = 0x04 + /* reclen */ - 0x0000 + /* load offset */ - 0x03 + /* Rectyp */ - (segaddr & 0xff) + /* low-low byte of segaddr */ - ((segaddr >> 8) & 0xff) + /* low-high byte of segaddr */ - ((segaddr >> 16) & 0xff) + /* high-low byte of segaddr */ - ((segaddr >> 24) & 0xff); /* high-high byte of segaddr */ - checksum = ~checksum + 1; /* two's complement */ - fprintf(of, "%02X\n", checksum & 0xff); - } - - /* Now it's time to write data records from the code and data segments in. - This current version doesn't check for segment overflow; proper behavior - should be to output a segment address record for the code and data - segments. Something to do. */ - ofs = 0; - segbin[0] = m->t; - segbin[1] = m->d; - for (segn = 0; segn < 2; segn++) { - int mod, adr; - - if (m->f.seg[segn].length == 0) - continue; - for (i = 0; i + 15 < m->f.seg[segn].length; i += 16) { - ofs = write_data_record(of, ofs, 16, &segbin[segn][i]); - } - if ((mod = m->f.seg[segn].length & 0x000f) != 0) { - adr = m->f.seg[segn].length & 0xfff0; - ofs = write_data_record(of, ofs, mod, &segbin[segn][adr]); - } - } - /* output an end of file record */ - fprintf(of, ":00000001FF\n"); - - fclose(of); - return 0; -} diff --git a/rdoff/rdfdump.c b/rdoff/rdfdump.c index 83305570..0e55c67f 100644 --- a/rdoff/rdfdump.c +++ b/rdoff/rdfdump.c @@ -1,3 +1,36 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + /* * rdfdump.c - dump RDOFF file header. */ diff --git a/rdoff/rdflib.c b/rdoff/rdflib.c index 852920ed..e12c6c6b 100644 --- a/rdoff/rdflib.c +++ b/rdoff/rdflib.c @@ -1,3 +1,36 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + /* rdflib - manipulate RDOFF library files (.rdl) */ /* diff --git a/rdoff/rdfload.c b/rdoff/rdfload.c index ac46de78..4fd3dbd0 100644 --- a/rdoff/rdfload.c +++ b/rdoff/rdfload.c @@ -1,13 +1,38 @@ -/* rdfload.c RDOFF Object File loader library +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: * - * Permission to use this file in your own projects is granted, as int32_t - * as acknowledgement is given in an appropriate manner to its authors, - * with instructions of how to obtain a copy via ftp. + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * rdfload.c RDOFF Object File loader library */ /* diff --git a/rdoff/rdfload.h b/rdoff/rdfload.h index 8f66694d..87d7ecc5 100644 --- a/rdoff/rdfload.h +++ b/rdoff/rdfload.h @@ -19,9 +19,9 @@ typedef struct RDFModuleStruct { rdffile f; /* file structure */ uint8_t *t, *d, *b; /* text, data, and bss segments */ - int32_t textrel; - int32_t datarel; - int32_t bssrel; + uint32_t textrel; + uint32_t datarel; + uint32_t bssrel; void *symtab; } rdfmodule; diff --git a/rdoff/rdlar.c b/rdoff/rdlar.c index 4728b57b..98b0f8f6 100644 --- a/rdoff/rdlar.c +++ b/rdoff/rdlar.c @@ -1,6 +1,38 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + /* * rdlar.c - new librarian/archiver for RDOFF2. - * Copyright (c) 2002 RET & COM Research. */ #include "compiler.h" @@ -61,10 +93,7 @@ static void int32_ttolocal(int32_t *l) */ void show_version(void) { - puts("New RDOFF2 librarian/archiver, version " PROGRAM_VERSION "\n" - "Copyright (c) 2002 RET & COM Research.\n" - "This program is free software and distributed under GPL (version 2 or later);\n" - "see http://www.gnu.org/copyleft/gpl.html for details."); + puts("New RDOFF2 librarian/archiver, version " PROGRAM_VERSION); } /* diff --git a/rdoff/rdlib.c b/rdoff/rdlib.c index 885752d4..31dbdb4b 100644 --- a/rdoff/rdlib.c +++ b/rdoff/rdlib.c @@ -1,3 +1,36 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + /* * rdlib.c - routines for manipulating RDOFF libraries (.rdl) */ diff --git a/rdoff/rdlib.h b/rdoff/rdlib.h index 17978d41..e1b3c5a1 100644 --- a/rdoff/rdlib.h +++ b/rdoff/rdlib.h @@ -1,3 +1,36 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + /* * rdlib.h Functions for manipulating libraries of RDOFF object files. */ diff --git a/rdoff/rdoff.c b/rdoff/rdoff.c index a77e6e11..3c7b3360 100644 --- a/rdoff/rdoff.c +++ b/rdoff/rdoff.c @@ -1,13 +1,38 @@ -/* rdoff.c library of routines for manipulating rdoff files +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: * - * Permission to use this file in your own projects is granted, as int32_t - * as acknowledgement is given in an appropriate manner to its authors, - * with instructions of how to obtain a copy via ftp. + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * rdoff.c library of routines for manipulating rdoff files */ /* TODO: The functions in this module assume they are running diff --git a/rdoff/rdoff.h b/rdoff/rdoff.h index d2047201..a1617336 100644 --- a/rdoff/rdoff.h +++ b/rdoff/rdoff.h @@ -1,14 +1,38 @@ -/* - * rdoff.h RDOFF Object File manipulation routines header file +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Permission to use this file in your own projects is granted, as int32_t - * as acknowledgement is given in an appropriate manner to its authors, - * with instructions of how to obtain a copy via ftp. + * ----------------------------------------------------------------------- */ + +/* + * rdoff.h RDOFF Object File manipulation routines header file */ #ifndef RDOFF_RDOFF_H diff --git a/rdoff/rdx.c b/rdoff/rdx.c index 8e70b1ad..240ab592 100644 --- a/rdoff/rdx.c +++ b/rdoff/rdx.c @@ -1,9 +1,38 @@ -/* rdx.c RDOFF Object File loader program +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * rdx.c RDOFF Object File loader program */ /* note: most of the actual work of this program is done by the modules diff --git a/rdoff/segtab.c b/rdoff/segtab.c index 693094e4..4a4c5b80 100644 --- a/rdoff/segtab.c +++ b/rdoff/segtab.c @@ -1,3 +1,36 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + #include "compiler.h" #include <stdio.h> diff --git a/rdoff/segtab.h b/rdoff/segtab.h index 1679d3f9..87ef0171 100644 --- a/rdoff/segtab.h +++ b/rdoff/segtab.h @@ -1,3 +1,36 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + #ifndef RDOFF_SEGTAB_H #define RDOFF_SEGTAB_H 1 diff --git a/rdoff/symtab.c b/rdoff/symtab.c index f6b1fe5d..1dfee1ae 100644 --- a/rdoff/symtab.c +++ b/rdoff/symtab.c @@ -1,11 +1,40 @@ -/* symtab.c Routines to maintain and manipulate a symbol table +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * These routines donated to the NASM effort by Graeme Defty. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * ----------------------------------------------------------------------- */ + +/* + * symtab.c Routines to maintain and manipulate a symbol table + * + * These routines donated to the NASM effort by Graeme Defty. */ #include "compiler.h" diff --git a/rdoff/symtab.h b/rdoff/symtab.h index e0924958..0dc8c7b1 100644 --- a/rdoff/symtab.h +++ b/rdoff/symtab.h @@ -1,9 +1,38 @@ -/* symtab.h Header file for symbol table manipulation routines +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * symtab.h Header file for symbol table manipulation routines */ #ifndef RDOFF_SYMTAB_H diff --git a/rdoff/test/Makefile b/rdoff/test/Makefile index 8e9f42e2..658a6d4e 100644 --- a/rdoff/test/Makefile +++ b/rdoff/test/Makefile @@ -1,2 +1,10 @@ +RDT = $(patsubst %.asm,%.rdf,$(wildcard *.asm)) +NASM = ../../nasm + +all: $(RDT) + +%.rdf: %.asm + $(NASM) -f rdf -o $@ -l $*.lst $< + clean: - rm -f *.rdf *.rdx + rm -f *.rdf *.rdx *.lst @@ -1,3 +1,36 @@ +## -------------------------------------------------------------------------- +## +## Copyright 1996-2009 The NASM Authors - All Rights Reserved +## See the file AUTHORS included with the NASM distribution for +## the specific copyright holders. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following +## conditions are met: +## +## * Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above +## copyright notice, this list of conditions and the following +## disclaimer in the documentation and/or other materials provided +## with the distribution. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## -------------------------------------------------------------------------- + # # List of registers and their classes; classes are defined in nasm.h # @@ -1,4 +1,37 @@ #!/usr/bin/perl +## -------------------------------------------------------------------------- +## +## Copyright 1996-2009 The NASM Authors - All Rights Reserved +## See the file AUTHORS included with the NASM distribution for +## the specific copyright holders. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following +## conditions are met: +## +## * Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above +## copyright notice, this list of conditions and the following +## disclaimer in the documentation and/or other materials provided +## with the distribution. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## -------------------------------------------------------------------------- + # # Read regs.dat and output regs.h and regs.c (included in names.c) # @@ -1,3 +1,36 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + #include "compiler.h" #include "nasmlib.h" #include "saa.h" @@ -287,6 +320,11 @@ void saa_write64(struct SAA *s, uint64_t v) saa_wbytes(s, &v, 8); } +void saa_writeaddr(struct SAA *s, uint64_t v, size_t len) +{ + saa_wbytes(s, &v, len); +} + #else /* not WORDS_LITTLEENDIAN */ void saa_write16(struct SAA *s, uint16_t v) @@ -324,6 +362,22 @@ void saa_write64(struct SAA *s, uint64_t v) saa_wbytes(s, b, 8); } +void saa_writeaddr(struct SAA *s, uint64_t v, size_t len) +{ + uint8_t b[8]; + + b[0] = v; + b[1] = v >> 8; + b[2] = v >> 16; + b[3] = v >> 24; + b[4] = v >> 32; + b[5] = v >> 40; + b[6] = v >> 48; + b[7] = v >> 56; + + saa_wbytes(s, &v, len); +} + #endif /* WORDS_LITTLEENDIAN */ /* write unsigned LEB128 value to SAA */ @@ -1,3 +1,36 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + #ifndef NASM_SAA_H #define NASM_SAA_H @@ -55,5 +88,6 @@ void saa_write32(struct SAA *s, uint32_t v); void saa_write64(struct SAA *s, uint64_t v); void saa_wleb128u(struct SAA *, int); /* write unsigned LEB128 value */ void saa_wleb128s(struct SAA *, int); /* write signed LEB128 value */ +void saa_writeaddr(struct SAA *, uint64_t, size_t); #endif /* NASM_SAA_H */ diff --git a/standard.mac b/standard.mac index 4e356d96..a3e8eea3 100644 --- a/standard.mac +++ b/standard.mac @@ -1,3 +1,36 @@ +;; -------------------------------------------------------------------------- +;; +;; Copyright 1996-2009 The NASM Authors - All Rights Reserved +;; See the file AUTHORS included with the NASM distribution for +;; the specific copyright holders. +;; +;; Redistribution and use in source and binary forms, with or without +;; modification, are permitted provided that the following +;; conditions are met: +;; +;; * Redistributions of source code must retain the above copyright +;; notice, this list of conditions and the following disclaimer. +;; * Redistributions in binary form must reproduce the above +;; copyright notice, this list of conditions and the following +;; disclaimer in the documentation and/or other materials provided +;; with the distribution. +;; +;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +;; CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +;; INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +;; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +;; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;; NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +;; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +;; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +;; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +;; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;; +;; -------------------------------------------------------------------------- + ; Standard macro set for NASM -*- nasm -*- ; Macros to make NASM ignore some TASM directives before the first include @@ -39,14 +72,14 @@ __SECT__ %endmacro -%imacro struc 1.nolist +%imacro struc 1-2.nolist 0 %push %define %$strucname %1 -[absolute 0] +[absolute %2] %$strucname: ; allow definition of `.member' to work sanely -%endmacro +%endmacro %imacro endstruc 0.nolist -%{$strucname}_size: +%{$strucname}_size equ ($-%$strucname) %pop __SECT__ %endmacro @@ -57,7 +90,7 @@ __SECT__ %$strucstart: %endmacro %imacro at 1-2+.nolist - times %1-($-%$strucstart) db 0 + times (%1-%$strucname)-($-%$strucstart) db 0 %2 %endmacro %imacro iend 0.nolist @@ -66,13 +99,13 @@ __SECT__ %endmacro %imacro align 1-2+.nolist nop - times ($$-$) % (%1) %2 + times (((%1) - (($-$$) % (%1))) % (%1)) %2 %endmacro %imacro alignb 1-2+.nolist %ifempty %2 - resb ($$-$) % (%1) + resb (((%1) - (($-$$) % (%1))) % (%1)) %else - times ($$-$) % (%1) %2 + times (((%1) - (($-$$) % (%1))) % (%1)) %2 %endif %endmacro @@ -1,3 +1,36 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + #include "compiler.h" #include <stdio.h> @@ -1,9 +1,38 @@ -/* stdscan.h header file for stdscan.c +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * stdscan.h header file for stdscan.c */ #ifndef NASM_STDSCAN_H @@ -1,3 +1,36 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + /* * strfunc.c * @@ -1,9 +1,38 @@ -/* sync.c the Netwide Disassembler synchronisation processing module +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * sync.c the Netwide Disassembler synchronisation processing module */ #include "compiler.h" @@ -1,9 +1,38 @@ -/* sync.h header file for sync.c +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. * - * The Netwide Assembler is copyright (C) 1996 Simon Tatham and - * Julian Hall. All rights reserved. The software is - * redistributable under the license given in the file "LICENSE" - * distributed in the NASM archive. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + +/* + * sync.h header file for sync.c */ #ifndef NASM_SYNC_H diff --git a/syncfiles.pl b/syncfiles.pl index 95969231..4da87f9c 100755 --- a/syncfiles.pl +++ b/syncfiles.pl @@ -1,4 +1,37 @@ #!/usr/bin/perl +## -------------------------------------------------------------------------- +## +## Copyright 1996-2009 The NASM Authors - All Rights Reserved +## See the file AUTHORS included with the NASM distribution for +## the specific copyright holders. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following +## conditions are met: +## +## * Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above +## copyright notice, this list of conditions and the following +## disclaimer in the documentation and/or other materials provided +## with the distribution. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## -------------------------------------------------------------------------- + # # Sync the output file list between Makefiles # Use the mkdep.pl parameters to get the filename syntax @@ -1,3 +1,36 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * See the file AUTHORS included with the NASM distribution for + * the specific copyright holders. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following + * conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------- */ + /* * tables.h * diff --git a/test/Makefile b/test/Makefile index cc11f0e4..0b81fc79 100644 --- a/test/Makefile +++ b/test/Makefile @@ -1,12 +1,19 @@ .SUFFIXES: .bin .o .o64 .obj .obj64 .exe .asm .lst .pl -NASM = ../nasm +NASM = ../nasm NASMOPT = -Ox -I../misc -PERL = perl +PERL = perl +TESTS = $(wildcard *.asm) %.bin: %.asm $(NASM) $(NASM) $(NASMOPT) -f bin -o $@ -l $*.lst $< +%.ith: %.asm $(NASM) + $(NASM) $(NASMOPT) -f ith -o $@ -l $*.lst $< + +%.srec: %.asm $(NASM) + $(NASM) $(NASMOPT) -f srec -o $@ -l $*.lst $< + %.o: %.asm $(NASM) $(NASM) $(NASMOPT) -f elf32 -o $@ -l $*.lst $< @@ -19,10 +26,53 @@ PERL = perl %.obj64: %.asm $(NASM) $(NASM) $(NASMOPT) -f win64 -o $@ -l $*.lst $< +%.dbg: %.asm $(NASM) + $(NASM) $(NASMOPT) -f dbg -o $@ -l $*.lst $< + %.asm: %.pl $(PERL) $< > $@ all: +golden: performtest.pl $(TESTS) + $(PERL) performtest.pl --golden --nasm='$(NASM)' $(TESTS) + +test: performtest.pl $(NASM) $(TESTS) + $(PERL) performtest.pl --nasm='$(NASM)' $(TESTS) + +diff: performtest.pl $(NASM) $(TESTS) + $(PERL) performtest.pl --diff --nasm='$(NASM)' $(TESTS) + clean: rm -f *.com *.o *.o64 *.obj *.obj64 *.exe *.lst *.bin + rm -rf testresults + rm -f elftest elftest64 + +spotless: clean + rm -rf golden + +# +# Test for ELF32 shared libraries; assumes an x86 Linux system +# +elfso.o: elfso.asm $(NASM) + $(NASM) $(NASMOPT) -f elf32 -F stabs -o $@ -l $*.lst $< + +elfso.so: elfso.o + $(LD) -m elf_i386 -shared -o $@ $< + +elftest: elftest.c elfso.so + $(CC) -g -m32 -o $@ $^ + -env LD_LIBRARY_PATH=.:$$LD_LIBRARY_PATH ./elftest + +# +# Test for ELF64 shared libraries; assumes an x86-64 Linux system +# +elf64so.o: elf64so.asm $(NASM) + $(NASM) $(NASMOPT) -f elf64 -F dwarf -o $@ -l $*.lst $< + +elf64so.so: elf64so.o + $(LD) -shared -o $@ $< + +elftest64: elftest64.c elf64so.so + $(CC) -g -o $@ $^ + -env LD_LIBRARY_PATH=.:$$LD_LIBRARY_PATH ./elftest64 diff --git a/test/_file_.asm b/test/_file_.asm index 1ec7187b..f633febd 100644 --- a/test/_file_.asm +++ b/test/_file_.asm @@ -1,4 +1,4 @@ -;Testname=bin; Arguments=-fbin -o_file_.bin; Files=.stdout .stderr _file_.bin +;Testname=bin; Arguments=-fbin -o_file_.bin; Files=stdout stderr _file_.bin db __FILE__, `\r\n` db __FILE__, `\r\n` dw __LINE__ diff --git a/test/_version.asm b/test/_version.asm index 4c89a859..d20a74d1 100755..100644 --- a/test/_version.asm +++ b/test/_version.asm @@ -1,2 +1,2 @@ -;Testname=version; Arguments=-v; Files=.stdout +;Testname=version; Arguments=-v; Files=stdout ;Dummy test to record version numbers diff --git a/test/a32offs.asm b/test/a32offs.asm index e34aa64f..4d17e0e4 100644 --- a/test/a32offs.asm +++ b/test/a32offs.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-O0 -fbin -oa32offs.bin; Files=a32offs.bin .stdout .stderr -;Testname=optimized; Arguments=-Ox -fbin -oa32offs.bin; Files=a32offs.bin .stdout .stderr +;Testname=unoptimized; Arguments=-O0 -fbin -oa32offs.bin; Files=a32offs.bin stdout stderr +;Testname=optimized; Arguments=-Ox -fbin -oa32offs.bin; Files=a32offs.bin stdout stderr bits 16 foo: a32 loop foo bar: loop bar, ecx diff --git a/test/absolute.asm b/test/absolute.asm index ee5bb638..31c8178c 100644 --- a/test/absolute.asm +++ b/test/absolute.asm @@ -1,4 +1,4 @@ -;Testname=bin; Arguments=-fbin -oabsolute.bin; Files=.stdout .stderr absolute.bin +;Testname=bin; Arguments=-fbin -oabsolute.bin; Files=stdout stderr absolute.bin org 7c00h init_foo: jmp init_bar diff --git a/test/addr64x.asm b/test/addr64x.asm index bf52d920..5aa63879 100644 --- a/test/addr64x.asm +++ b/test/addr64x.asm @@ -1,10 +1,10 @@ -;Testname=O0; Arguments=-O0 -fbin -oaddr64.bin; Files=.stdout .stderr addr64.bin -;Testname=O1; Arguments=-O1 -fbin -oaddr64.bin; Files=.stdout .stderr addr64.bin -;Testname=O2; Arguments=-O2 -fbin -oaddr64.bin; Files=.stdout .stderr addr64.bin -;Testname=O3; Arguments=-O3 -fbin -oaddr64.bin; Files=.stdout .stderr addr64.bin -;Testname=O4; Arguments=-O4 -fbin -oaddr64.bin; Files=.stdout .stderr addr64.bin -;Testname=O5; Arguments=-O5 -fbin -oaddr64.bin; Files=.stdout .stderr addr64.bin -;Testname=Ox; Arguments=-Ox -fbin -oaddr64.bin; Files=.stdout .stderr addr64.bin +;Testname=O0; Arguments=-O0 -fbin -oaddr64.bin; Files=stdout stderr addr64.bin +;Testname=O1; Arguments=-O1 -fbin -oaddr64.bin; Files=stdout stderr addr64.bin +;Testname=O2; Arguments=-O2 -fbin -oaddr64.bin; Files=stdout stderr addr64.bin +;Testname=O3; Arguments=-O3 -fbin -oaddr64.bin; Files=stdout stderr addr64.bin +;Testname=O4; Arguments=-O4 -fbin -oaddr64.bin; Files=stdout stderr addr64.bin +;Testname=O5; Arguments=-O5 -fbin -oaddr64.bin; Files=stdout stderr addr64.bin +;Testname=Ox; Arguments=-Ox -fbin -oaddr64.bin; Files=stdout stderr addr64.bin bits 64 mov rdx,[rax] mov eax,[byte rsp+0x01] diff --git a/test/aoutso.asm b/test/aoutso.asm index eeab2e3f..aab35a56 100644 --- a/test/aoutso.asm +++ b/test/aoutso.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-O0 -faoutb -oaoutso.o; Files=.stdout .stderr aoutso.o -;Testname=optimized; Arguments=-Ox -faoutb -oaoutso.o; Files=.stdout .stderr aoutso.o +;Testname=unoptimized; Arguments=-O0 -faoutb -oaoutso.o; Files=stdout stderr aoutso.o +;Testname=optimized; Arguments=-Ox -faoutb -oaoutso.o; Files=stdout stderr aoutso.o ; test source file for assembling to NetBSD/FreeBSD a.out shared library ; build with: diff --git a/test/aouttest.asm b/test/aouttest.asm index 207a5452..10d0e10a 100644 --- a/test/aouttest.asm +++ b/test/aouttest.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-O0 -faout -oaouttest.o; Files=.stdout .stderr aouttest.o -;Testname=optimized; Arguments=-Ox -faout -oaouttest.o; Files=.stdout .stderr aouttest.o +;Testname=unoptimized; Arguments=-O0 -faout -oaouttest.o; Files=stdout stderr aouttest.o +;Testname=optimized; Arguments=-Ox -faout -oaouttest.o; Files=stdout stderr aouttest.o ; test source file for assembling to a.out ; build with: diff --git a/test/avx.asm b/test/avx.asm index a63c6400..9e5e15bf 100644 --- a/test/avx.asm +++ b/test/avx.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-O0 -fbin -oavx.bin; Files=.stdout .stderr avx.bin -;Testname=optimized; Arguments=-Ox -fbin -oavx.bin; Files=.stdout .stderr avx.bin +;Testname=unoptimized; Arguments=-O0 -fbin -oavx.bin; Files=stdout stderr avx.bin +;Testname=optimized; Arguments=-Ox -fbin -oavx.bin; Files=stdout stderr avx.bin bits 64 blendvpd xmm2,xmm1,xmm0 diff --git a/test/binexe.asm b/test/binexe.asm index bc85eb41..2a9eb6e8 100644 --- a/test/binexe.asm +++ b/test/binexe.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-O0 -fbin -obinexe.exe -i../misc/; Files=.stdout .stderr binexe.exe -;Testname=optimized; Arguments=-Ox -fbin -obinexe.exe -i../misc/; Files=.stdout .stderr binexe.exe +;Testname=unoptimized; Arguments=-O0 -fbin -obinexe.exe -i../misc/; Files=stdout stderr binexe.exe +;Testname=optimized; Arguments=-Ox -fbin -obinexe.exe -i../misc/; Files=stdout stderr binexe.exe ; Demonstration of how to write an entire .EXE format program by using ; the `exebin.mac' macro package. diff --git a/test/bintest.asm b/test/bintest.asm index 7246a452..57a3b2df 100644 --- a/test/bintest.asm +++ b/test/bintest.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-O0 -fbin -obintest.bin; Files=.stdout .stderr bintest.bin -;Testname=optimized; Arguments=-Ox -fbin -obintest.bin; Files=.stdout .stderr bintest.bin +;Testname=unoptimized; Arguments=-O0 -fbin -obintest.bin; Files=stdout stderr bintest.bin +;Testname=optimized; Arguments=-Ox -fbin -obintest.bin; Files=stdout stderr bintest.bin ; test source file for assembling to binary files ; build with: diff --git a/test/br1879590.asm b/test/br1879590.asm index d51a16c1..23e38728 100644 --- a/test/br1879590.asm +++ b/test/br1879590.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-O0 -fbin -obr1879590.bin; Files=.stdout .stderr br1879590.bin -;Testname=optimized; Arguments=-Ox -fbin -obr1879590.bin; Files=.stdout .stderr br1879590.bin +;Testname=unoptimized; Arguments=-O0 -fbin -obr1879590.bin; Files=stdout stderr br1879590.bin +;Testname=optimized; Arguments=-Ox -fbin -obr1879590.bin; Files=stdout stderr br1879590.bin bits 32 diff --git a/test/br560575.asm b/test/br560575.asm index bb6feb83..a252db63 100644 --- a/test/br560575.asm +++ b/test/br560575.asm @@ -1,14 +1,14 @@ -;Testname=aout; Arguments=-faout -obr560575.o; Files=.stderr .stdout br560575.o -;Testname=aoutb; Arguments=-faoutb -obr560575.o; Files=.stderr .stdout br560575.o -;Testname=coff; Arguments=-fcoff -obr560575.o; Files=.stderr .stdout br560575.o -;Testname=elf32; Arguments=-felf32 -obr560575.o; Files=.stderr .stdout br560575.o -;Testname=elf64; Arguments=-felf64 -obr560575.o; Files=.stderr .stdout br560575.o -;Testname=as86; Arguments=-fas86 -obr560575.o; Files=.stderr .stdout br560575.o -;Testname=win32; Arguments=-fwin32 -obr560575.o; Files=.stderr .stdout br560575.o -;Testname=win64; Arguments=-fwin64 -obr560575.o; Files=.stderr .stdout br560575.o -;Testname=rdf; Arguments=-frdf -obr560575.o; Files=.stderr .stdout br560575.o -;Testname=ieee; Arguments=-fieee -obr560575.o; Files=.stderr .stdout br560575.o -;Testname=macho; Arguments=-fmacho -obr560575.o; Files=.stderr .stdout br560575.o +;Testname=aout; Arguments=-faout -obr560575.o; Files=stderr stdout br560575.o +;Testname=aoutb; Arguments=-faoutb -obr560575.o; Files=stderr stdout br560575.o +;Testname=coff; Arguments=-fcoff -obr560575.o; Files=stderr stdout br560575.o +;Testname=elf32; Arguments=-felf32 -obr560575.o; Files=stderr stdout br560575.o +;Testname=elf64; Arguments=-felf64 -obr560575.o; Files=stderr stdout br560575.o +;Testname=as86; Arguments=-fas86 -obr560575.o; Files=stderr stdout br560575.o +;Testname=win32; Arguments=-fwin32 -obr560575.o; Files=stderr stdout br560575.o +;Testname=win64; Arguments=-fwin64 -obr560575.o; Files=stderr stdout br560575.o +;Testname=rdf; Arguments=-frdf -obr560575.o; Files=stderr stdout br560575.o +;Testname=ieee; Arguments=-fieee -obr560575.o; Files=stderr stdout br560575.o +;Testname=macho; Arguments=-fmacho -obr560575.o; Files=stderr stdout br560575.o ;Test for bug report 560575 - Using SEG with non-relocatable values doesn't work ; diff --git a/test/br560873.asm b/test/br560873.asm index 724507b4..21334926 100644 --- a/test/br560873.asm +++ b/test/br560873.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-O0 -frdf -obr560873.rdf; Files=.stdout .stderr br560873.rdf -;Testname=optimized; Arguments=-Ox -frdf -obr560873.rdf; Files=.stdout .stderr br560873.rdf +;Testname=unoptimized; Arguments=-O0 -frdf -obr560873.rdf; Files=stdout stderr br560873.rdf +;Testname=optimized; Arguments=-Ox -frdf -obr560873.rdf; Files=stdout stderr br560873.rdf label: bits 16 diff --git a/test/elfso.asm b/test/elfso.asm index 78df8bac..e72497ba 100644 --- a/test/elfso.asm +++ b/test/elfso.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-O0 -felf -oelfso.o; Files=.stdout .stderr elfso.o -;Testname=optimized; Arguments=-Ox -felf -oelfso.o; Files=.stdout .stderr elfso.o +;Testname=unoptimized; Arguments=-O0 -felf -oelfso.o; Files=stdout stderr elfso.o +;Testname=optimized; Arguments=-Ox -felf -oelfso.o; Files=stdout stderr elfso.o ; test source file for assembling to ELF shared library ; build with: diff --git a/test/elftest.c b/test/elftest.c index 8dd57a2c..42b3f7e9 100644 --- a/test/elftest.c +++ b/test/elftest.c @@ -33,4 +33,6 @@ int main(void) printf("These pointers should be equal: %p and %p\n", &greet, textptr); printf("So should these: %p and %p\n", selfptr, &selfptr); + + return 0; } diff --git a/test/elif.asm b/test/elif.asm index 57c9ac24..49e66688 100644 --- a/test/elif.asm +++ b/test/elif.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-O0 -fobj -oelif.obj; Files=.stdout .stderr elif.obj -;Testname=optimized; Arguments=-Ox -fobj -oelif.obj; Files=.stdout .stderr elif.obj +;Testname=unoptimized; Arguments=-O0 -fobj -oelif.obj; Files=stdout stderr elif.obj +;Testname=optimized; Arguments=-Ox -fobj -oelif.obj; Files=stdout stderr elif.obj %macro DosPrintMsg 1+ %ifnid %1 diff --git a/test/expimp.asm b/test/expimp.asm index 2a0c1def..77839770 100644 --- a/test/expimp.asm +++ b/test/expimp.asm @@ -1,12 +1,12 @@ -;Testname=O0; Arguments=-O0 -fbin -oexpimp.bin; Files=.stdout .stderr expimp.bin -;Testname=O1; Arguments=-O1 -fbin -oexpimp.bin; Files=.stdout .stderr expimp.bin -;Testname=O2; Arguments=-O2 -fbin -oexpimp.bin; Files=.stdout .stderr expimp.bin -;Testname=O3; Arguments=-O3 -fbin -oexpimp.bin; Files=.stdout .stderr expimp.bin -;Testname=O4; Arguments=-O4 -fbin -oexpimp.bin; Files=.stdout .stderr expimp.bin -;Testname=O5; Arguments=-O5 -fbin -oexpimp.bin; Files=.stdout .stderr expimp.bin -;Testname=Ox; Arguments=-Ox -fbin -oexpimp.bin; Files=.stdout .stderr expimp.bin -;Testname=error-O0; Arguments=-O0 -fbin -oexpimp.bin -DERROR; Files=.stdout .stderr expimp.bin -;Testname=error-Ox; Arguments=-Ox -fbin -oexpimp.bin -DERROR; Files=.stdout .stderr expimp.bin +;Testname=O0; Arguments=-O0 -fbin -oexpimp.bin; Files=stdout stderr expimp.bin +;Testname=O1; Arguments=-O1 -fbin -oexpimp.bin; Files=stdout stderr expimp.bin +;Testname=O2; Arguments=-O2 -fbin -oexpimp.bin; Files=stdout stderr expimp.bin +;Testname=O3; Arguments=-O3 -fbin -oexpimp.bin; Files=stdout stderr expimp.bin +;Testname=O4; Arguments=-O4 -fbin -oexpimp.bin; Files=stdout stderr expimp.bin +;Testname=O5; Arguments=-O5 -fbin -oexpimp.bin; Files=stdout stderr expimp.bin +;Testname=Ox; Arguments=-Ox -fbin -oexpimp.bin; Files=stdout stderr expimp.bin +;Testname=error-O0; Arguments=-O0 -fbin -oexpimp.bin -DERROR; Files=stdout stderr expimp.bin +;Testname=error-Ox; Arguments=-Ox -fbin -oexpimp.bin -DERROR; Files=stdout stderr expimp.bin ; ; Test of explicitly and implicitly sized operands diff --git a/test/far64.asm b/test/far64.asm index b7a5108e..e18bca42 100644 --- a/test/far64.asm +++ b/test/far64.asm @@ -1,4 +1,4 @@ -;Testname=test; Arguments=-fbin -ofar64.bin; Files=.stdout .stderr far64.bin +;Testname=test; Arguments=-fbin -ofar64.bin; Files=stdout stderr far64.bin ; BR 2039212 bits 64 diff --git a/test/float.asm b/test/float.asm index 567d2009..88519b2e 100644 --- a/test/float.asm +++ b/test/float.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-O0 -fbin -ofloat.bin; Files=.stdout .stderr float.bin -;Testname=optimized; Arguments=-Ox -fbin -ofloat.bin; Files=.stdout .stderr float.bin +;Testname=unoptimized; Arguments=-O0 -fbin -ofloat.bin; Files=stdout stderr float.bin +;Testname=optimized; Arguments=-Ox -fbin -ofloat.bin; Files=stdout stderr float.bin ; ; Test of floating-point formats diff --git a/test/float8.asm b/test/float8.asm index 5520060a..d59abecc 100644 --- a/test/float8.asm +++ b/test/float8.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-O0 -fbin -ofloat8.bin; Files=.stdout .stderr float8.bin -;Testname=optimized; Arguments=-Ox -fbin -ofloat8.bin; Files=.stdout .stderr float8.bin +;Testname=unoptimized; Arguments=-O0 -fbin -ofloat8.bin; Files=stdout stderr float8.bin +;Testname=optimized; Arguments=-Ox -fbin -ofloat8.bin; Files=stdout stderr float8.bin ; Test of 8-bit floating-point constants diff --git a/test/floatb.asm b/test/floatb.asm index 75ca788c..dc0422e0 100644 --- a/test/floatb.asm +++ b/test/floatb.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-O0 -fbin -ofloatb.bin; Files=.stdout .stderr floatb.bin -;Testname=optimized; Arguments=-Ox -fbin -ofloatb.bin; Files=.stdout .stderr floatb.bin +;Testname=unoptimized; Arguments=-O0 -fbin -ofloatb.bin; Files=stdout stderr floatb.bin +;Testname=optimized; Arguments=-Ox -fbin -ofloatb.bin; Files=stdout stderr floatb.bin ;; Known problematic floating-point numbers and their proper ;; encoding... diff --git a/test/floatexp.asm b/test/floatexp.asm index 5ef185fb..2bc359eb 100644 --- a/test/floatexp.asm +++ b/test/floatexp.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-O0 -fbin -ofloatexp.bin; Files=.stdout .stderr floatexp.bin -;Testname=optimized; Arguments=-Ox -fbin -ofloatexp.bin; Files=.stdout .stderr floatexp.bin +;Testname=unoptimized; Arguments=-O0 -fbin -ofloatexp.bin; Files=stdout stderr floatexp.bin +;Testname=optimized; Arguments=-Ox -fbin -ofloatexp.bin; Files=stdout stderr floatexp.bin bits 64 ; diff --git a/test/floatize.asm b/test/floatize.asm index 714b44d9..cc0bbe92 100644 --- a/test/floatize.asm +++ b/test/floatize.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-O0 -fbin -ofloatize.bin; Files=.stdout .stderr floatize.bin -;Testname=optimized; Arguments=-Ox -fbin -ofloatize.bin; Files=.stdout .stderr floatize.bin +;Testname=unoptimized; Arguments=-O0 -fbin -ofloatize.bin; Files=stdout stderr floatize.bin +;Testname=optimized; Arguments=-Ox -fbin -ofloatize.bin; Files=stdout stderr floatize.bin %assign x13 13+26 %assign f16 __float16__(1.6e-7) diff --git a/test/floattest.asm b/test/floattest.asm index a8db5acb..3c7ba8b0 100644 --- a/test/floattest.asm +++ b/test/floattest.asm @@ -1,4 +1,4 @@ -;Testname=optimized; Arguments=-Ox -felf -ofloattest.o; Files=.stdout .stderr floattest.o +;Testname=optimized; Arguments=-Ox -felf -ofloattest.o; Files=stdout stderr floattest.o ; nasm -O99 -f elf32 floattest.asm ; ld -m elf_i386 -o floattest floattest.o -I/lib/ld-linux.so.2 -lc diff --git a/test/fmsub.asm b/test/fmsub.asm index ca599d54..b58273fd 100644 --- a/test/fmsub.asm +++ b/test/fmsub.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-O0 -fbin -ofmsub.bin; Files=.stdout .stderr fmsub.bin -;Testname=optimized; Arguments=-Ox -fbin -ofmsub.bin; Files=.stdout .stderr fmsub.bin +;Testname=unoptimized; Arguments=-O0 -fbin -ofmsub.bin; Files=stdout stderr fmsub.bin +;Testname=optimized; Arguments=-Ox -fbin -ofmsub.bin; Files=stdout stderr fmsub.bin bits 64 diff --git a/test/fpu.asm b/test/fpu.asm index 04680f7e..4051fddd 100644 --- a/test/fpu.asm +++ b/test/fpu.asm @@ -1,4 +1,4 @@ -;Testname=test; Arguments=-fbin -ofpu.bin; Files=.stdout .stderr fpu.bin +;Testname=test; Arguments=-fbin -ofpu.bin; Files=stdout stderr fpu.bin ; relaxed encodings for FPU instructions, which NASM should support ; ----------------------------------------------------------------- diff --git a/test/ifmacro.asm b/test/ifmacro.asm index abfa6a24..53f3d291 100644 --- a/test/ifmacro.asm +++ b/test/ifmacro.asm @@ -1,4 +1,4 @@ -;Testname=test; Arguments=-fbin -oifmacro.txt; Files=.stdout .stderr ifmacro.txt +;Testname=test; Arguments=-fbin -oifmacro.txt; Files=stdout stderr ifmacro.txt ; ; ifmacro.asm diff --git a/test/iftoken.asm b/test/iftoken.asm index 92cf4034..7a0fec49 100644 --- a/test/iftoken.asm +++ b/test/iftoken.asm @@ -1,4 +1,4 @@ -;Testname=test; Arguments=-fbin -oiftoken.txt; Files=.stdout .stderr iftoken.txt +;Testname=test; Arguments=-fbin -oiftoken.txt; Files=stdout stderr iftoken.txt %define ZMACRO %define NMACRO 1 diff --git a/test/iftoken.pl b/test/iftoken.pl index 8f063668..925dd40c 100755 --- a/test/iftoken.pl +++ b/test/iftoken.pl @@ -4,7 +4,7 @@ 'foo', 'foo bar', '%', '+foo', '<<'); @tests = ('token', 'empty'); -print ";Testname=test; Arguments=-fbin -oiftoken.txt; Files=.stdout .stderr iftoken.txt" +print ";Testname=test; Arguments=-fbin -oiftoken.txt; Files=stdout stderr iftoken.txt" print "%define ZMACRO\n"; print "%define NMACRO 1\n"; print "%define TMACRO 1 2\n"; diff --git a/test/imacro.asm b/test/imacro.asm index 0db9e628..bc397cc3 100644 --- a/test/imacro.asm +++ b/test/imacro.asm @@ -1,4 +1,4 @@ -;Testname=test; Arguments=-fbin -oimacro.bin; Files=.stdout .stderr imacro.bin +;Testname=test; Arguments=-fbin -oimacro.bin; Files=stdout stderr imacro.bin %imacro Zero 1 xor %1,%1 diff --git a/test/inctest.asm b/test/inctest.asm index edc084f1..35f29107 100644 --- a/test/inctest.asm +++ b/test/inctest.asm @@ -1,4 +1,4 @@ -;Testname=test; Arguments=-fbin -oinctest.com; Files=.stdout .stderr inctest.com +;Testname=test; Arguments=-fbin -oinctest.com; Files=stdout stderr inctest.com ; This file, plus inc1.asm and inc2.asm, test NASM's file inclusion ; mechanism. diff --git a/test/insnlbl.asm b/test/insnlbl.asm index 648bb47f..e4563723 100644 --- a/test/insnlbl.asm +++ b/test/insnlbl.asm @@ -1,4 +1,4 @@ -;Testname=test; Arguments=-fbin -oinsnlbl.bin; Files=.stdout .stderr insnlbl.bin +;Testname=test; Arguments=-fbin -oinsnlbl.bin; Files=stdout stderr insnlbl.bin ; ; Test "instruction as label" -- make opcodes legal as labels if diff --git a/test/invlpga.asm b/test/invlpga.asm index 43759ec1..21ab4b42 100644 --- a/test/invlpga.asm +++ b/test/invlpga.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-fbin -oinvlpga.bin; Files=.stdout .stderr invlpga.bin -;Testname=optimized; Arguments=-fbin -oinvlpga.bin -Ox; Files=.stdout .stderr invlpga.bin +;Testname=unoptimized; Arguments=-fbin -oinvlpga.bin; Files=stdout stderr invlpga.bin +;Testname=optimized; Arguments=-fbin -oinvlpga.bin -Ox; Files=stdout stderr invlpga.bin bits 32 invlpga diff --git a/test/jmp64.asm b/test/jmp64.asm index 440551f7..f007b9ed 100644 --- a/test/jmp64.asm +++ b/test/jmp64.asm @@ -1,4 +1,15 @@ +;Testname=test; Arguments=-fbin -ojmp64.bin; Files=stdout stderr jmp64.bin + bits 64 jmp rcx + jmp [rax] + jmp qword [rax] + jmp far [rax] + jmp far dword [rax] + jmp far qword [rax] + call rcx call [rax] - call qword [rdx] + call qword [rax] + call far [rax] + call far dword [rax] + call far qword [rax] diff --git a/test/lar_lsl.asm b/test/lar_lsl.asm index 7c7b82ca..a0a9c0eb 100644 --- a/test/lar_lsl.asm +++ b/test/lar_lsl.asm @@ -1,4 +1,4 @@ -;Testname=test; Arguments=-fbin -olar_lsl.bin; Files=.stdout .stderr lar_lsl.bin +;Testname=test; Arguments=-fbin -olar_lsl.bin; Files=stdout stderr lar_lsl.bin ; LAR/LSL ;--------- diff --git a/test/larlsl.asm b/test/larlsl.asm index fb1c42e4..cddaac79 100644 --- a/test/larlsl.asm +++ b/test/larlsl.asm @@ -1,4 +1,4 @@ -;Testname=test; Arguments=-fbin -olarlsl.bin; Files=.stdout .stderr larlsl.bin +;Testname=test; Arguments=-fbin -olarlsl.bin; Files=stdout stderr larlsl.bin bits 64 diff --git a/test/lnxhello.asm b/test/lnxhello.asm index d48ab5b3..1aa5a5f8 100644 --- a/test/lnxhello.asm +++ b/test/lnxhello.asm @@ -1,7 +1,7 @@ -;Testname=aout; Arguments=-faout -olnxhello.o -Ox; Files=.stdout .stderr lnxhello.o -;Testname=aoutb; Arguments=-faoutb -olnxhello.o -Ox; Files=.stdout .stderr lnxhello.o -;Testname=as86; Arguments=-fas86 -olnxhello.o -Ox; Files=.stdout .stderr lnxhello.o -;Testname=elf32; Arguments=-felf32 -olnxhello.o -Ox; Files=.stdout .stderr lnxhello.o +;Testname=aout; Arguments=-faout -olnxhello.o -Ox; Files=stdout stderr lnxhello.o +;Testname=aoutb; Arguments=-faoutb -olnxhello.o -Ox; Files=stdout stderr lnxhello.o +;Testname=as86; Arguments=-fas86 -olnxhello.o -Ox; Files=stdout stderr lnxhello.o +;Testname=elf32; Arguments=-felf32 -olnxhello.o -Ox; Files=stdout stderr lnxhello.o ; ; Assembly "Hello, World!" for Linux diff --git a/test/local.asm b/test/local.asm index a5ce7070..8a42bb86 100644 --- a/test/local.asm +++ b/test/local.asm @@ -1,4 +1,4 @@ -;Testname=test; Arguments=-fbin -olocal.bin; Files=.stdout .stderr local.bin +;Testname=test; Arguments=-fbin -olocal.bin; Files=stdout stderr local.bin bits 32 %push bluttan diff --git a/test/loopoffs.asm b/test/loopoffs.asm index f035e4a8..54ef4ac6 100644 --- a/test/loopoffs.asm +++ b/test/loopoffs.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-fbin -oloopoffs.bin -O0; Files=.stdout .stderr loopoffs.bin -;Testname=optimized; Arguments=-fbin -oloopoffs.bin -Ox; Files=.stdout .stderr loopoffs.bin +;Testname=unoptimized; Arguments=-fbin -oloopoffs.bin -O0; Files=stdout stderr loopoffs.bin +;Testname=optimized; Arguments=-fbin -oloopoffs.bin -Ox; Files=stdout stderr loopoffs.bin bits 16 delay: loop delay loop $ diff --git a/test/macro-defaults.asm b/test/macro-defaults.asm index 17b1624b..047f2053 100755..100644 --- a/test/macro-defaults.asm +++ b/test/macro-defaults.asm @@ -1,5 +1,5 @@ -;Testname=warning; Arguments=-fbin -omacdef.bin -w+macro-defaults; Files=.stdout .stderr macdef.bin -;Testname=nonwarning; Arguments=-fbin -omacdef.bin -w-macro-defaults; Files=.stdout .stderr macdef.bin +;Testname=warning; Arguments=-fbin -omacdef.bin -w+macro-defaults; Files=stdout stderr macdef.bin +;Testname=nonwarning; Arguments=-fbin -omacdef.bin -w-macro-defaults; Files=stdout stderr macdef.bin %MACRO mmac_fix 1 a ; While defined to take one parameter, any invocation will diff --git a/test/mmxsize.asm b/test/mmxsize.asm index 260f9947..0a478391 100644 --- a/test/mmxsize.asm +++ b/test/mmxsize.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-fbin -ommxsize.bin -O0; Files=.stdout .stderr mmxsize.bin -;Testname=optimized; Arguments=-fbin -ommxsize.bin -Ox; Files=.stdout .stderr mmxsize.bin +;Testname=unoptimized; Arguments=-fbin -ommxsize.bin -O0; Files=stdout stderr mmxsize.bin +;Testname=optimized; Arguments=-fbin -ommxsize.bin -Ox; Files=stdout stderr mmxsize.bin bits 32 movd mm0,eax movd mm0,[foo] diff --git a/test/movimm.asm b/test/movimm.asm index d6450a61..c34c1669 100644 --- a/test/movimm.asm +++ b/test/movimm.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-fbin -omovimm.bin -O0; Files=.stdout .stderr movimm.bin -;Testname=optimized; Arguments=-fbin -omovimm.bin -Ox; Files=.stdout .stderr movimm.bin +;Testname=unoptimized; Arguments=-fbin -omovimm.bin -O0; Files=stdout stderr movimm.bin +;Testname=optimized; Arguments=-fbin -omovimm.bin -Ox; Files=stdout stderr movimm.bin bits 64 mov rax,1234567890abcdefh diff --git a/test/movnti.asm b/test/movnti.asm index d20d3c13..920f3279 100644 --- a/test/movnti.asm +++ b/test/movnti.asm @@ -1,4 +1,4 @@ -;Testname=test; Arguments=-fbin -omovnti.bin; Files=.stdout .stderr movnti.bin +;Testname=test; Arguments=-fbin -omovnti.bin; Files=stdout stderr movnti.bin ; BR 2028995 bits 16 diff --git a/test/multisection.asm b/test/multisection.asm index 997ae6db..34e7f7d8 100644 --- a/test/multisection.asm +++ b/test/multisection.asm @@ -1,12 +1,12 @@ -;Testname=aout; Arguments=-faout -olnxhello.o -Ox; Files=.stdout .stderr lnxhello.o -;Testname=aoutb; Arguments=-faoutb -olnxhello.o -Ox; Files=.stdout .stderr lnxhello.o -;Testname=as86; Arguments=-fas86 -olnxhello.o -Ox; Files=.stdout .stderr lnxhello.o -;Testname=elf32; Arguments=-felf32 -olnxhello.o -Ox; Files=.stdout .stderr lnxhello.o -;Testname=elf64; Arguments=-felf64 -olnxhello.o -Ox; Files=.stdout .stderr lnxhello.o -;Testname=obj; Arguments=-fobj -olnxhello.o -Ox; Files=.stdout .stderr lnxhello.o -;Testname=rdf; Arguments=-frdf -olnxhello.o -Ox; Files=.stdout .stderr lnxhello.o -;Testname=win32; Arguments=-fwin32 -olnxhello.o -Ox; Files=.stdout .stderr lnxhello.o -;Testname=win64; Arguments=-fwin64 -olnxhello.o -Ox; Files=.stdout .stderr lnxhello.o +;Testname=aout; Arguments=-faout -olnxhello.o -Ox; Files=stdout stderr lnxhello.o +;Testname=aoutb; Arguments=-faoutb -olnxhello.o -Ox; Files=stdout stderr lnxhello.o +;Testname=as86; Arguments=-fas86 -olnxhello.o -Ox; Files=stdout stderr lnxhello.o +;Testname=elf32; Arguments=-felf32 -olnxhello.o -Ox; Files=stdout stderr lnxhello.o +;Testname=elf64; Arguments=-felf64 -olnxhello.o -Ox; Files=stdout stderr lnxhello.o +;Testname=obj; Arguments=-fobj -olnxhello.o -Ox; Files=stdout stderr lnxhello.o +;Testname=rdf; Arguments=-frdf -olnxhello.o -Ox; Files=stdout stderr lnxhello.o +;Testname=win32; Arguments=-fwin32 -olnxhello.o -Ox; Files=stdout stderr lnxhello.o +;Testname=win64; Arguments=-fwin64 -olnxhello.o -Ox; Files=stdout stderr lnxhello.o ; To test where code that is placed before any explicit SECTION ; gets placed, and what happens if a .text section has an ORG diff --git a/test/nasmformat.asm b/test/nasmformat.asm index 0c3f0a7b..ea19b923 100644 --- a/test/nasmformat.asm +++ b/test/nasmformat.asm @@ -1,6 +1,6 @@ -;Testname=obj; Arguments=-fobj -onasmfomat.o; Files=.stdout .stderr nasmfomat.o -;Testname=bin; Arguments=-fbin -onasmfomat.o; Files=.stdout .stderr nasmfomat.o -;Testname=rdf; Arguments=-frdf -onasmfomat.o; Files=.stdout .stderr nasmfomat.o +;Testname=obj; Arguments=-fobj -onasmfomat.o; Files=stdout stderr nasmfomat.o +;Testname=bin; Arguments=-fbin -onasmfomat.o; Files=stdout stderr nasmfomat.o +;Testname=rdf; Arguments=-frdf -onasmfomat.o; Files=stdout stderr nasmfomat.o %if __OUTPUT_FORMAT__ == 'bin' @@ -5,5 +5,5 @@ for f; do echo "$0: $f already exists" 1>&2 exit 1 fi - echo ";Testname=test; Arguments=-fbin -o$f.bin; Files=.stdout .stderr $f.bin" > "$f".asm + echo ";Testname=test; Arguments=-fbin -o$f.bin; Files=stdout stderr $f.bin" > "$f".asm done diff --git a/test/nop.asm b/test/nop.asm index 49c1de09..71b7f7b2 100644 --- a/test/nop.asm +++ b/test/nop.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-fbin -onop.bin; Files=.stdout .stderr nop.bin -;Testname=optimized; Arguments=-fbin -onop.bin -Ox; Files=.stdout .stderr nop.bin +;Testname=unoptimized; Arguments=-fbin -onop.bin; Files=stdout stderr nop.bin +;Testname=optimized; Arguments=-fbin -onop.bin -Ox; Files=stdout stderr nop.bin bits 64 diff --git a/test/nullfile.asm b/test/nullfile.asm index f837e798..83e306e0 100644 --- a/test/nullfile.asm +++ b/test/nullfile.asm @@ -1,4 +1,4 @@ -;Testname=test; Arguments=-fbin -onull.bin; Files=.stdout .stderr null.bin +;Testname=test; Arguments=-fbin -onull.bin; Files=stdout stderr null.bin ; ; A file that produces no output has been known to occationally crash NASM. ; diff --git a/test/objtest.asm b/test/objtest.asm index ba94c23d..03b7f9e2 100644 --- a/test/objtest.asm +++ b/test/objtest.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-O0 -fobj -oobj.o; Files=.stdout .stderr obj.o -;Testname=optimized; Arguments=-Ox -fobj -oobj.o; Files=.stdout .stderr obj.o +;Testname=unoptimized; Arguments=-O0 -fobj -oobj.o; Files=stdout stderr obj.o +;Testname=optimized; Arguments=-Ox -fobj -oobj.o; Files=stdout stderr obj.o ; test source file for assembling to Microsoft 16-bit .OBJ ; build with (16-bit Microsoft C): diff --git a/test/org.asm b/test/org.asm index a958242c..792c39a5 100644 --- a/test/org.asm +++ b/test/org.asm @@ -1,5 +1,5 @@ -;Testname=elf64; Arguments=-Ox -felf64 -oorg.o; Files=.stdout .stderr org.o -;Testname=win64; Arguments=-Ox -fwin64 -oorg.o; Files=.stdout .stderr org.o +;Testname=elf64; Arguments=-Ox -felf64 -oorg.o; Files=stdout stderr org.o +;Testname=win64; Arguments=-Ox -fwin64 -oorg.o; Files=stdout stderr org.o ; ; Simple test of a 64-bit org directive diff --git a/test/performtest.pl b/test/performtest.pl index 5574fc6c..f9b7bb2c 100755 --- a/test/performtest.pl +++ b/test/performtest.pl @@ -18,7 +18,7 @@ use File::Path qw(mkpath rmtree); #Process one testfile sub perform { my ($clean, $diff, $golden, $nasm, $quiet, $testpath) = @_; - my ($stdoutfile, $stderrfile) = (".stdout", ".stderr"); + my ($stdoutfile, $stderrfile) = ("stdout", "stderr"); my ($testname, $ignoredpath, $ignoredsuffix) = fileparse($testpath, ".asm"); debugprint $testname; @@ -100,7 +100,7 @@ sub perform { if($diff) { for(@failedfiles) { if($_ eq $stdoutfile or $_ eq $stderrfile) { - system "diff golden/$testname/$subname/$_ $outputdir/$testname/$subname/$_"; + system "diff -u golden/$testname/$subname/$_ $outputdir/$testname/$subname/$_"; print "\n"; } } @@ -156,7 +156,7 @@ with "golden" output files. Options: --clean Clean up test results (or golden files with --golden) - --diff Execute diff when .stdout or .stderr don't match + --diff Execute diff when stdout or stderr don't match --golden Create golden files --help Get this help --nasm=file Specify the file name for the NASM executable, e.g. ../nasm @@ -178,7 +178,7 @@ with "golden" output files. an output file specifier (-o) etc. The output files should be a space seperated list of files that will be checked for regressions. This should often be the output file - and the special files .stdout and .stderr. + and the special files stdout and stderr. Any mismatch could be a regression, but it doesn't have to be. COFF files have a timestamp which diff --git a/test/r13.asm b/test/r13.asm index 5d153dec..88079e1b 100644 --- a/test/r13.asm +++ b/test/r13.asm @@ -1,4 +1,4 @@ -;Testname=test; Arguments=-fbin -or13.bin; Files=.stdout .stderr r13.bin +;Testname=test; Arguments=-fbin -or13.bin; Files=stdout stderr r13.bin bits 64 mov rax,[rbx] diff --git a/test/radix.asm b/test/radix.asm index a22c2dc8..1c564572 100644 --- a/test/radix.asm +++ b/test/radix.asm @@ -1,4 +1,4 @@ -;Testname=test; Arguments=-fbin -oradix.bin; Files=.stdout .stderr radix.bin +;Testname=test; Arguments=-fbin -oradix.bin; Files=stdout stderr radix.bin ;; Integer constants... diff --git a/test/riprel.asm b/test/riprel.asm index 937694b2..757a8dd1 100644 --- a/test/riprel.asm +++ b/test/riprel.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-fbin -oriprel.bin -O0; Files=.stdout .stderr riprel.bin -;Testname=optimized; Arguments=-fbin -oriprel.bin -Ox; Files=.stdout .stderr riprel.bin +;Testname=unoptimized; Arguments=-fbin -oriprel.bin -O0; Files=stdout stderr riprel.bin +;Testname=optimized; Arguments=-fbin -oriprel.bin -Ox; Files=stdout stderr riprel.bin bits 64 default abs diff --git a/test/riprel.pl b/test/riprel.pl index d4b3ad5a..61af7239 100755 --- a/test/riprel.pl +++ b/test/riprel.pl @@ -1,7 +1,7 @@ #!/usr/bin/perl -print ";Testname=unoptimized; Arguments=-fbin -oriprel.bin -O0; Files=.stdout .stderr riprel.bin\n"; -print ";Testname=optimized; Arguments=-fbin -oriprel.bin -Ox; Files=.stdout .stderr riprel.bin\n"; +print ";Testname=unoptimized; Arguments=-fbin -oriprel.bin -O0; Files=stdout stderr riprel.bin\n"; +print ";Testname=optimized; Arguments=-fbin -oriprel.bin -Ox; Files=stdout stderr riprel.bin\n"; print "\tbits 64\n"; diff --git a/test/smartalign.asm b/test/smartalign.asm deleted file mode 100644 index 1b8bdaeb..00000000 --- a/test/smartalign.asm +++ /dev/null @@ -1,34 +0,0 @@ -%use smartalign - - bits 32 - - alignmode nop - add ax,ax - align 16 - - alignmode generic - add ax,ax - align 16 - - alignmode k7 - add ax,ax - align 16 - - alignmode k8 - add ax,ax - align 16 - - alignmode p6 - add ax,ax - align 16 - - add ecx,ecx - align 32 - add edx,edx - align 128 - add ebx,ebx - align 256 - add esi,esi - align 512 - - add edi,edi diff --git a/test/test67.asm b/test/test67.asm index 16fd5ccb..7cf300d8 100644 --- a/test/test67.asm +++ b/test/test67.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-fbin -otest67.bin -O0; Files=.stdout .stderr test67.bin -;Testname=optimized; Arguments=-fbin -otest67.bin -Ox; Files=.stdout .stderr test67.bin +;Testname=unoptimized; Arguments=-fbin -otest67.bin -O0; Files=stdout stderr test67.bin +;Testname=optimized; Arguments=-fbin -otest67.bin -Ox; Files=stdout stderr test67.bin bits 16 diff --git a/test/testdos.asm b/test/testdos.asm index 4fdf87b6..2f6bf916 100644 --- a/test/testdos.asm +++ b/test/testdos.asm @@ -1,4 +1,4 @@ -;Testname=test; Arguments=-fbin -otestdos.bin; Files=.stdout .stderr testdos.bin +;Testname=test; Arguments=-fbin -otestdos.bin; Files=stdout stderr testdos.bin ; ; This file was known to miscompile with the 16-bit NASM built ; under Borland C++ 3.1, so keep it around for testing... diff --git a/test/testnos3.asm b/test/testnos3.asm index 9737e653..b243e159 100644 --- a/test/testnos3.asm +++ b/test/testnos3.asm @@ -1,4 +1,4 @@ -;Testname=test; Arguments=-fbin -otestnos3.bin; Files=.stdout .stderr testnos3.bin +;Testname=test; Arguments=-fbin -otestnos3.bin; Files=stdout stderr testnos3.bin ; ; Double-precision floating point tests, derived from Fred Tydeman's posting ; of 26 February 1996 to comp.arch.arithmetic, via David M. Gay's gdtoa diff --git a/test/uscore.asm b/test/uscore.asm index d8670ee3..ec614435 100644 --- a/test/uscore.asm +++ b/test/uscore.asm @@ -1,4 +1,4 @@ -;Testname=test; Arguments=-fbin -ouscore.bin; Files=.stdout .stderr uscore.bin +;Testname=test; Arguments=-fbin -ouscore.bin; Files=stdout stderr uscore.bin dd 0x1234_5678 dd 305_419_896 ; Same number as above it dd 0x1e16 ; NOT a floating-point number! diff --git a/test/utf.asm b/test/utf.asm index a12a9916..4b894f87 100644 --- a/test/utf.asm +++ b/test/utf.asm @@ -1,5 +1,5 @@ -;Testname=test; Arguments=-fbin -outf.bin; Files=.stdout .stderr utf.bin -;Testname=error; Arguments=-fbin -outf.bin -DERROR; Files=.stdout .stderr utf.bin +;Testname=test; Arguments=-fbin -outf.bin; Files=stdout stderr utf.bin +;Testname=error; Arguments=-fbin -outf.bin -DERROR; Files=stdout stderr utf.bin %define u(x) __utf16__(x) %define w(x) __utf32__(x) diff --git a/test/vmread.asm b/test/vmread.asm index fa559265..551c71a1 100644 --- a/test/vmread.asm +++ b/test/vmread.asm @@ -1,4 +1,4 @@ -;Testname=test; Arguments=-fbin -ovmread.bin; Files=.stdout .stderr vmread.bin +;Testname=test; Arguments=-fbin -ovmread.bin; Files=stdout stderr vmread.bin bits 32 vmread dword [0], eax diff --git a/test/xchg.asm b/test/xchg.asm index 4bd95e4a..9c826dd9 100644 --- a/test/xchg.asm +++ b/test/xchg.asm @@ -1,5 +1,5 @@ -;Testname=unoptimized; Arguments=-fbin -oxchg.bin -O0; Files=.stdout .stderr xchg.bin -;Testname=optimized; Arguments=-fbin -oxchg.bin -Ox; Files=.stdout .stderr xchg.bin +;Testname=unoptimized; Arguments=-fbin -oxchg.bin -O0; Files=stdout stderr xchg.bin +;Testname=optimized; Arguments=-fbin -oxchg.bin -Ox; Files=stdout stderr xchg.bin %macro x 2 xchg %1,%2 diff --git a/test/xcrypt.asm b/test/xcrypt.asm index 59f0dcab..55a3f5de 100644 --- a/test/xcrypt.asm +++ b/test/xcrypt.asm @@ -1,4 +1,4 @@ -;Testname=test; Arguments=-fbin -oxcrypt.bin; Files=.stdout .stderr xcrypt.bin +;Testname=test; Arguments=-fbin -oxcrypt.bin; Files=stdout stderr xcrypt.bin ; BR 2029829 bits 32 diff --git a/test/zerobyte.asm b/test/zerobyte.asm index 676ea657..ce531b57 100644 --- a/test/zerobyte.asm +++ b/test/zerobyte.asm @@ -1,4 +1,4 @@ -;Testname=test; Arguments=-fbin -ozerobyte.bin; Files=.stdout .stderr zerobyte.bin +;Testname=test; Arguments=-fbin -ozerobyte.bin; Files=stdout stderr zerobyte.bin bits 64 mov eax,bar-foo @@ -1,3 +1,36 @@ +## -------------------------------------------------------------------------- +## +## Copyright 1996-2009 The NASM Authors - All Rights Reserved +## See the file AUTHORS included with the NASM distribution for +## the specific copyright holders. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following +## conditions are met: +## +## * Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above +## copyright notice, this list of conditions and the following +## disclaimer in the documentation and/or other materials provided +## with the distribution. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## -------------------------------------------------------------------------- + # # Tokens other than instructions and registers # @@ -18,6 +51,7 @@ repne repnz repz times +wait % TOKEN_SPECIAL, 0, S_* abs @@ -1,4 +1,37 @@ #!/usr/bin/perl +## -------------------------------------------------------------------------- +## +## Copyright 1996-2009 The NASM Authors - All Rights Reserved +## See the file AUTHORS included with the NASM distribution for +## the specific copyright holders. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following +## conditions are met: +## +## * Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above +## copyright notice, this list of conditions and the following +## disclaimer in the documentation and/or other materials provided +## with the distribution. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## -------------------------------------------------------------------------- + # # Generate a perfect hash for token parsing # @@ -1 +1 @@ -2.04rc1 +2.07rc3 @@ -1,4 +1,37 @@ #!/usr/bin/perl +## -------------------------------------------------------------------------- +## +## Copyright 1996-2009 The NASM Authors - All Rights Reserved +## See the file AUTHORS included with the NASM distribution for +## the specific copyright holders. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following +## conditions are met: +## +## * Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above +## copyright notice, this list of conditions and the following +## disclaimer in the documentation and/or other materials provided +## with the distribution. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## -------------------------------------------------------------------------- + # # version.pl # @@ -60,7 +93,7 @@ if ( $line =~ /^([0-9]+)\.([0-9]+)(.*)$/ ) { die "$0: Invalid input format\n"; } -if ($tail =~ /^\-([0-9]+)/) { +if ($tail =~ /^\-([0-9]+)$/) { $snapshot = $1; } else { undef $snapshot; @@ -86,8 +119,13 @@ if ($is_rc) { $nasm_id = ($nmaj << 24)+($nmin << 16)+($nsmin << 8)+$nplvl; -$mangled_ver = sprintf("%d.%02d.%02d", $nmaj, $nmin, $nsmin); -$mangled_ver .= '.'.$nplvl if ($nplvl != 0); +$mangled_ver = sprintf("%d.%02d", $nmaj, $nmin); +if ($nsmin || $nplvl || defined($snapshot)) { + $mangled_ver .= sprintf(".%02d", $nsmin); + if ($nplvl || defined($snapshot)) { + $mangled_ver .= '.'.$nplvl; + } +} ($mtail = $tail) =~ tr/-/./; $mangled_ver .= $mtail; @@ -130,6 +168,12 @@ if ( $what eq 'h' ) { printf "NASM_MINOR_VER=%d\n", $nmin; printf "NASM_SUBMINOR_VER=%d\n", $nsmin; printf "NASM_PATCHLEVEL_VER=%d\n", $nplvl; +} elsif ( $what eq 'nsis' ) { + printf "!define VERSION \"%s\"\n", $line; + printf "!define MAJOR_VER %d\n", $nmin; + printf "!define MINOR_VER %d\n", $nmin; + printf "!define SUBMINOR_VER %d\n", $nsmin; + printf "!define PATCHLEVEL_VER %d\n", $nplvl; } elsif ( $what eq 'id' ) { print $nasm_id, "\n"; # Print ID in decimal } elsif ( $what eq 'xid' ) { |