Change \40 class opcodes to \254, except IMUL

Change \40 class opcodes which need to be changed to \254.  IMUL will
need a separate audit; I'm not convinced we are really sure what all
the IMUL conditions should be.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>

1 files changed, 12 insertions, 12 deletions

diff --git a/insns.dat b/insns.dat
index 1b28d639..7b70e9f0 100644
--- a/insns.dat
+++ b/insns.dat
@@ -63,7 +63,7 @@ ADC		rm64,imm8			\324\1\x83\202\15				X64
 ADC		reg_al,imm			\1\x14\21					8086,SM
 ADC		reg_ax,imm			\320\1\x15\31					8086,SM
 ADC		reg_eax,imm			\321\1\x15\41					386,SM
-ADC		reg_rax,imm			\324\1\x15\41					X64,SM
+ADC		reg_rax,imm			\324\1\x15\255					X64,SM
 ADC		rm8,imm				\1\x80\202\21					8086,SM
 ADC		rm16,imm			\320\145\x81\202\141				8086,SM
 ADC		rm32,imm			\321\155\x81\202\151				386,SM
@@ -93,7 +93,7 @@ ADD		rm64,imm8			\324\1\x83\200\275				X64
 ADD		reg_al,imm			\1\x04\21					8086,SM
 ADD		reg_ax,imm			\320\1\x05\31					8086,SM
 ADD		reg_eax,imm			\321\1\x05\41					386,SM
-ADD		reg_rax,imm			\324\1\x05\41					X64,SM
+ADD		reg_rax,imm			\324\1\x05\255					X64,SM
 ADD		rm8,imm				\1\x80\200\21					8086,SM
 ADD		rm16,imm			\320\145\x81\200\141				8086,SM
 ADD		rm32,imm			\321\155\x81\200\151				386,SM
@@ -123,7 +123,7 @@ AND		rm64,imm8			\324\1\x83\204\15				X64
 AND		reg_al,imm			\1\x24\21					8086,SM
 AND		reg_ax,imm			\320\1\x25\31					8086,SM
 AND		reg_eax,imm			\321\1\x25\41					386,SM
-AND		reg_rax,imm			\324\1\x25\41					X64,SM
+AND		reg_rax,imm			\324\1\x25\255					X64,SM
 AND		rm8,imm				\1\x80\204\21					8086,SM
 AND		rm16,imm			\320\145\x81\204\141				8086,SM
 AND		rm32,imm			\321\155\x81\204\151				386,SM
@@ -248,7 +248,7 @@ CMP		rm64,imm8			\324\1\x83\207\275				X64
 CMP		reg_al,imm			\1\x3C\21					8086,SM
 CMP		reg_ax,imm			\320\1\x3D\31					8086,SM
 CMP		reg_eax,imm			\321\1\x3D\41					386,SM
-CMP		reg_rax,imm			\324\1\x3D\41					X64,SM
+CMP		reg_rax,imm			\324\1\x3D\255					X64,SM
 CMP		rm8,imm				\1\x80\207\21					8086,SM
 CMP		rm16,imm			\320\145\x81\207\141				8086,SM
 CMP		rm32,imm			\321\155\x81\207\151				386,SM
@@ -570,7 +570,7 @@ IMUL		reg32,sbyte32			\321\1\x6B\100\15				386,SM,ND
 IMUL		reg32,imm32			\321\1\x69\100\41				386
 IMUL		reg32,imm			\321\155\x69\100\151				386,SM,ND
 IMUL		reg64,sbyte64			\324\1\x6B\100\15				X64,SM,ND
-IMUL		reg64,imm32			\324\1\x69\100\41				X64
+IMUL		reg64,imm32			\324\1\x69\100\255				X64
 IMUL		reg64,imm			\324\155\x69\100\251				X64,SM,ND
 IN		reg_al,imm			\1\xE4\25					8086,SB
 IN		reg_ax,imm			\320\1\xE5\25					8086,SB
@@ -772,7 +772,7 @@ MOV		reg64,imm32			\324\1\xC7\200\255				X64
 MOV		rm8,imm				\1\xC6\200\21					8086,SM
 MOV		rm16,imm			\320\1\xC7\200\31				8086,SM
 MOV		rm32,imm			\321\1\xC7\200\41				386,SM
-MOV		rm64,imm			\324\1\xC7\200\41				X64,SM
+MOV		rm64,imm			\324\1\xC7\200\255				X64,SM
 MOV		mem,imm8			\1\xC6\200\21					8086,SM
 MOV		mem,imm16			\320\1\xC7\200\31				8086,SM
 MOV		mem,imm32			\321\1\xC7\200\41				386,SM
@@ -846,7 +846,7 @@ OR		rm64,imm8			\324\1\x83\201\275				X64
 OR		reg_al,imm			\1\x0C\21					8086,SM
 OR		reg_ax,imm			\320\1\x0D\31					8086,SM
 OR		reg_eax,imm			\321\1\x0D\41					386,SM
-OR		reg_rax,imm			\324\1\x0D\41					X64,SM
+OR		reg_rax,imm			\324\1\x0D\255					X64,SM
 OR		rm8,imm				\1\x80\201\21					8086,SM
 OR		rm16,imm			\320\145\x81\201\141				8086,SM
 OR		rm32,imm			\321\155\x81\201\151				386,SM
@@ -1098,7 +1098,7 @@ SBB		rm64,imm8			\324\1\x83\203\275				X64
 SBB		reg_al,imm			\1\x1C\21					8086,SM
 SBB		reg_ax,imm			\320\1\x1D\31					8086,SM
 SBB		reg_eax,imm			\321\1\x1D\41					386,SM
-SBB		reg_rax,imm			\324\1\x1D\41					X64,SM
+SBB		reg_rax,imm			\324\1\x1D\255					X64,SM
 SBB		rm8,imm				\1\x80\203\21					8086,SM
 SBB		rm16,imm			\320\145\x81\203\141				8086,SM
 SBB		rm32,imm			\321\155\x81\203\151				386,SM
@@ -1211,7 +1211,7 @@ SUB		rm64,imm8			\324\1\x83\205\275				X64
 SUB		reg_al,imm			\1\x2C\21					8086,SM
 SUB		reg_ax,imm			\320\1\x2D\31					8086,SM
 SUB		reg_eax,imm			\321\1\x2D\41					386,SM
-SUB		reg_rax,imm			\324\1\x2D\41					X64,SM
+SUB		reg_rax,imm			\324\1\x2D\255					X64,SM
 SUB		rm8,imm				\1\x80\205\21					8086,SM
 SUB		rm16,imm			\320\145\x81\205\141				8086,SM
 SUB		rm32,imm			\321\155\x81\205\151				386,SM
@@ -1242,11 +1242,11 @@ TEST		reg64,mem			\324\1\x85\110					X64,SM
 TEST		reg_al,imm			\1\xA8\21					8086,SM
 TEST		reg_ax,imm			\320\1\xA9\31					8086,SM
 TEST		reg_eax,imm			\321\1\xA9\41					386,SM
-TEST		reg_rax,imm			\324\1\xA9\41					X64,SM
+TEST		reg_rax,imm			\324\1\xA9\255					X64,SM
 TEST		rm8,imm				\1\xF6\200\21					8086,SM
 TEST		rm16,imm			\320\1\xF7\200\31				8086,SM
 TEST		rm32,imm			\321\1\xF7\200\41				386,SM
-TEST		rm64,imm			\324\1\xF7\200\41				X64,SM
+TEST		rm64,imm			\324\1\xF7\200\255				X64,SM
 TEST		mem,imm8			\1\xF6\200\21					8086,SM
 TEST		mem,imm16			\320\1\xF7\200\31				8086,SM
 TEST		mem,imm32			\321\1\xF7\200\41				386,SM
@@ -1339,7 +1339,7 @@ XOR		rm64,imm8			\324\1\x83\206\275				X64
 XOR		reg_al,imm			\1\x34\21					8086,SM
 XOR		reg_ax,imm			\320\1\x35\31					8086,SM
 XOR		reg_eax,imm			\321\1\x35\41					386,SM
-XOR		reg_rax,imm			\324\1\x35\41					X64,SM
+XOR		reg_rax,imm			\324\1\x35\255					X64,SM
 XOR		rm8,imm				\1\x80\206\21					8086,SM
 XOR		rm16,imm			\320\145\x81\206\141				8086,SM
 XOR		rm32,imm			\321\155\x81\206\151				386,SM