AVX-512: Add AVX-512ER instructions

Added Exponential and Reciprocal (AVX-512ER) instructions.
These instructions are supported
if CPUID.(EAX=07H, ECX=0):EBX.AVX512ER[bit 27] = 1.
IF_AVX512 is now shared by all AVX-512* instructions as a bit mask.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>

4 files changed, 158 insertions, 3 deletions

diff --git a/assemble.c b/assemble.c
index ad345239..c0e316ae 100644
--- a/assemble.c
+++ b/assemble.c
@@ -2148,7 +2148,7 @@ static enum match_result matches(const struct itemplate *itemp,
                 opsizemissing = true;
             }
         } else if (nasm_regvals[instruction->oprs[i].basereg] >= 16 &&
-                   (itemp->flags & IF_INSMASK) != IF_AVX512) {
+                   !(itemp->flags & IF_AVX512)) {
             return MERR_ENCMISMATCH;
         }
     }
diff --git a/insns.dat b/insns.dat
index 3c59da2f..64f8b68a 100644
--- a/insns.dat
+++ b/insns.dat
@@ -4063,6 +4063,17 @@ VPLZCNTD         zmmreg|mask|z,zmmrm512|b32      [rm:fv:          evex.512.66.0f
 VPLZCNTQ         zmmreg|mask|z,zmmrm512|b64      [rm:fv:          evex.512.66.0f38.w1 44 /r ]  AVX512CD,FUTURE
 VPTESTNMD        kreg|mask,zmmreg,zmmrm512|b32   [rvm:fv:     evex.nds.512.f3.0f38.w0 27 /r ]  AVX512CD,FUTURE
 VPTESTNMQ        kreg|mask,zmmreg,zmmrm512|b64   [rvm:fv:     evex.nds.512.f3.0f38.w1 27 /r ]  AVX512CD,FUTURE
+; AVX-512ER (Exponential and Reciprocal) instructions
+VEXP2PD      zmmreg|mask|z,zmmrm512|b64|sae    [rm:fv:          evex.512.66.0f38.w1 c8 /r ]  AVX512ER,FUTURE
+VEXP2PS      zmmreg|mask|z,zmmrm512|b32|sae    [rm:fv:          evex.512.66.0f38.w0 c8 /r ]  AVX512ER,FUTURE
+VRCP28PD     zmmreg|mask|z,zmmrm512|b64|sae    [rm:fv:          evex.512.66.0f38.w1 ca /r ]  AVX512ER,FUTURE
+VRCP28PS     zmmreg|mask|z,zmmrm512|b32|sae    [rm:fv:          evex.512.66.0f38.w0 ca /r ]  AVX512ER,FUTURE
+VRCP28SD     xmmreg|mask|z,xmmreg,xmmrm64|sae  [rvm:t1s:    evex.nds.lig.66.0f38.w1 cb /r ]  AVX512ER,FUTURE
+VRCP28SS     xmmreg|mask|z,xmmreg,xmmrm32|sae  [rvm:t1s:    evex.nds.lig.66.0f38.w0 cb /r ]  AVX512ER,FUTURE
+VRSQRT28PD   zmmreg|mask|z,zmmrm512|b64|sae    [rm:fv:          evex.512.66.0f38.w1 cc /r ]  AVX512ER,FUTURE
+VRSQRT28PS   zmmreg|mask|z,zmmrm512|b32|sae    [rm:fv:          evex.512.66.0f38.w0 cc /r ]  AVX512ER,FUTURE
+VRSQRT28SD   xmmreg|mask|z,xmmreg,xmmrm64|sae  [rvm:t1s:    evex.nds.lig.66.0f38.w1 cd /r ]  AVX512ER,FUTURE
+VRSQRT28SS   xmmreg|mask|z,xmmreg,xmmrm32|sae  [rvm:t1s:    evex.nds.lig.66.0f38.w0 cd /r ]  AVX512ER,FUTURE
 
 
 ;# Systematic names for the hinting nop instructions
diff --git a/insns.h b/insns.h
index 3959a057..3b12ccf1 100644
--- a/insns.h
+++ b/insns.h
@@ -107,6 +107,7 @@ extern const uint8_t nasm_bytecodes[];
 /* These flags are currently not used for anything - intended for insn set */
 #define IF_UNDOC        0x8000000000UL    /* it's an undocumented instruction */
 #define IF_HLE          0x4000000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
+#define IF_AVX512       0x2000000000UL    /* it's an AVX-512F (512b) instruction */
 #define IF_FPU          0x0100000000UL    /* it's an FPU instruction */
 #define IF_MMX          0x0200000000UL    /* it's an MMX instruction */
 #define IF_3DNOW        0x0300000000UL    /* it's a 3DNow! instruction */
@@ -121,14 +122,14 @@ extern const uint8_t nasm_bytecodes[];
 #define IF_SSE5         0x0C00000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
 #define IF_AVX          0x0D00000000UL    /* it's an AVX     (128b) instruction */
 #define IF_AVX2         0x0E00000000UL    /* it's an AVX2    (256b) instruction */
-#define IF_AVX512       0x0F00000000UL    /* it's an AVX-512 (512b) instruction */
 #define IF_FMA          0x1000000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
 #define IF_BMI1         0x1100000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
 #define IF_BMI2         0x1200000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
 #define IF_TBM          0x1300000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
 #define IF_RTM          0x1400000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
 #define IF_INVPCID      0x1500000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
-#define IF_AVX512CD     0x1600000000UL    /* AVX-512 Conflict Detection insns */
+#define IF_AVX512CD     (0x1600000000UL|IF_AVX512) /* AVX-512 Conflict Detection insns */
+#define IF_AVX512ER     (0x1700000000UL|IF_AVX512) /* AVX-512 Exponential and Reciprocal */
 #define IF_INSMASK      0xFF00000000UL    /* the mask for instruction set types */
 #define IF_PMASK        0xFF000000UL    /* the mask for processor types */
 #define IF_PLEVEL       0x0F000000UL    /* the mask for processor instr. level */
diff --git a/test/avx512er.asm b/test/avx512er.asm
new file mode 100644
index 00000000..6e08e600
--- /dev/null
+++ b/test/avx512er.asm
@@ -0,0 +1,143 @@
+; AVX-512ER testcases from gas
+;------------------------
+;
+; This file is taken from there
+;     https://gnu.googlesource.com/binutils/+/master/gas/testsuite/gas/i386/x86-64-avx512er-intel.d
+; So the original author is "H.J. Lu" <hongjiu dot lu at intel dot com>
+;
+; Jin Kyu Song converted it for the nasm testing suite using gas2nasm.py
+
+%macro testcase 2
+ %ifdef BIN
+  db %1
+ %endif
+ %ifdef SRC
+  %2
+ %endif
+%endmacro
+
+
+bits 64
+
+testcase	{ 0x62, 0x02, 0x7d, 0x48, 0xc8, 0xf5                                     }, { vexp2ps zmm30,zmm29                                          }
+testcase	{ 0x62, 0x02, 0x7d, 0x18, 0xc8, 0xf5                                     }, { vexp2ps zmm30,zmm29,\{sae\}                                  }
+testcase	{ 0x62, 0x62, 0x7d, 0x48, 0xc8, 0x31                                     }, { vexp2ps zmm30,ZWORD [rcx]                                    }
+testcase	{ 0x62, 0x22, 0x7d, 0x48, 0xc8, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00       }, { vexp2ps zmm30,ZWORD [rax+r14*8+0x123]                        }
+testcase	{ 0x62, 0x62, 0x7d, 0x58, 0xc8, 0x31                                     }, { vexp2ps zmm30,DWORD [rcx]\{1to16\}                           }
+testcase	{ 0x62, 0x62, 0x7d, 0x48, 0xc8, 0x72, 0x7f                               }, { vexp2ps zmm30,ZWORD [rdx+0x1fc0]                             }
+testcase	{ 0x62, 0x62, 0x7d, 0x48, 0xc8, 0xb2, 0x00, 0x20, 0x00, 0x00             }, { vexp2ps zmm30,ZWORD [rdx+0x2000]                             }
+testcase	{ 0x62, 0x62, 0x7d, 0x48, 0xc8, 0x72, 0x80                               }, { vexp2ps zmm30,ZWORD [rdx-0x2000]                             }
+testcase	{ 0x62, 0x62, 0x7d, 0x48, 0xc8, 0xb2, 0xc0, 0xdf, 0xff, 0xff             }, { vexp2ps zmm30,ZWORD [rdx-0x2040]                             }
+testcase	{ 0x62, 0x62, 0x7d, 0x58, 0xc8, 0x72, 0x7f                               }, { vexp2ps zmm30,DWORD [rdx+0x1fc]\{1to16\}                     }
+testcase	{ 0x62, 0x62, 0x7d, 0x58, 0xc8, 0xb2, 0x00, 0x02, 0x00, 0x00             }, { vexp2ps zmm30,DWORD [rdx+0x200]\{1to16\}                     }
+testcase	{ 0x62, 0x62, 0x7d, 0x58, 0xc8, 0x72, 0x80                               }, { vexp2ps zmm30,DWORD [rdx-0x200]\{1to16\}                     }
+testcase	{ 0x62, 0x62, 0x7d, 0x58, 0xc8, 0xb2, 0xfc, 0xfd, 0xff, 0xff             }, { vexp2ps zmm30,DWORD [rdx-0x204]\{1to16\}                     }
+testcase	{ 0x62, 0x02, 0xfd, 0x48, 0xc8, 0xf5                                     }, { vexp2pd zmm30,zmm29                                          }
+testcase	{ 0x62, 0x02, 0xfd, 0x18, 0xc8, 0xf5                                     }, { vexp2pd zmm30,zmm29,\{sae\}                                  }
+testcase	{ 0x62, 0x62, 0xfd, 0x48, 0xc8, 0x31                                     }, { vexp2pd zmm30,ZWORD [rcx]                                    }
+testcase	{ 0x62, 0x22, 0xfd, 0x48, 0xc8, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00       }, { vexp2pd zmm30,ZWORD [rax+r14*8+0x123]                        }
+testcase	{ 0x62, 0x62, 0xfd, 0x58, 0xc8, 0x31                                     }, { vexp2pd zmm30,QWORD [rcx]\{1to8\}                            }
+testcase	{ 0x62, 0x62, 0xfd, 0x48, 0xc8, 0x72, 0x7f                               }, { vexp2pd zmm30,ZWORD [rdx+0x1fc0]                             }
+testcase	{ 0x62, 0x62, 0xfd, 0x48, 0xc8, 0xb2, 0x00, 0x20, 0x00, 0x00             }, { vexp2pd zmm30,ZWORD [rdx+0x2000]                             }
+testcase	{ 0x62, 0x62, 0xfd, 0x48, 0xc8, 0x72, 0x80                               }, { vexp2pd zmm30,ZWORD [rdx-0x2000]                             }
+testcase	{ 0x62, 0x62, 0xfd, 0x48, 0xc8, 0xb2, 0xc0, 0xdf, 0xff, 0xff             }, { vexp2pd zmm30,ZWORD [rdx-0x2040]                             }
+testcase	{ 0x62, 0x62, 0xfd, 0x58, 0xc8, 0x72, 0x7f                               }, { vexp2pd zmm30,QWORD [rdx+0x3f8]\{1to8\}                      }
+testcase	{ 0x62, 0x62, 0xfd, 0x58, 0xc8, 0xb2, 0x00, 0x04, 0x00, 0x00             }, { vexp2pd zmm30,QWORD [rdx+0x400]\{1to8\}                      }
+testcase	{ 0x62, 0x62, 0xfd, 0x58, 0xc8, 0x72, 0x80                               }, { vexp2pd zmm30,QWORD [rdx-0x400]\{1to8\}                      }
+testcase	{ 0x62, 0x62, 0xfd, 0x58, 0xc8, 0xb2, 0xf8, 0xfb, 0xff, 0xff             }, { vexp2pd zmm30,QWORD [rdx-0x408]\{1to8\}                      }
+testcase	{ 0x62, 0x02, 0x7d, 0x48, 0xca, 0xf5                                     }, { vrcp28ps zmm30,zmm29                                         }
+testcase	{ 0x62, 0x02, 0x7d, 0x4f, 0xca, 0xf5                                     }, { vrcp28ps zmm30\{k7\},zmm29                                   }
+testcase	{ 0x62, 0x02, 0x7d, 0xcf, 0xca, 0xf5                                     }, { vrcp28ps zmm30\{k7\}\{z\},zmm29                              }
+testcase	{ 0x62, 0x02, 0x7d, 0x18, 0xca, 0xf5                                     }, { vrcp28ps zmm30,zmm29,\{sae\}                                 }
+testcase	{ 0x62, 0x62, 0x7d, 0x48, 0xca, 0x31                                     }, { vrcp28ps zmm30,ZWORD [rcx]                                   }
+testcase	{ 0x62, 0x22, 0x7d, 0x48, 0xca, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00       }, { vrcp28ps zmm30,ZWORD [rax+r14*8+0x123]                       }
+testcase	{ 0x62, 0x62, 0x7d, 0x58, 0xca, 0x31                                     }, { vrcp28ps zmm30,DWORD [rcx]\{1to16\}                          }
+testcase	{ 0x62, 0x62, 0x7d, 0x48, 0xca, 0x72, 0x7f                               }, { vrcp28ps zmm30,ZWORD [rdx+0x1fc0]                            }
+testcase	{ 0x62, 0x62, 0x7d, 0x48, 0xca, 0xb2, 0x00, 0x20, 0x00, 0x00             }, { vrcp28ps zmm30,ZWORD [rdx+0x2000]                            }
+testcase	{ 0x62, 0x62, 0x7d, 0x48, 0xca, 0x72, 0x80                               }, { vrcp28ps zmm30,ZWORD [rdx-0x2000]                            }
+testcase	{ 0x62, 0x62, 0x7d, 0x48, 0xca, 0xb2, 0xc0, 0xdf, 0xff, 0xff             }, { vrcp28ps zmm30,ZWORD [rdx-0x2040]                            }
+testcase	{ 0x62, 0x62, 0x7d, 0x58, 0xca, 0x72, 0x7f                               }, { vrcp28ps zmm30,DWORD [rdx+0x1fc]\{1to16\}                    }
+testcase	{ 0x62, 0x62, 0x7d, 0x58, 0xca, 0xb2, 0x00, 0x02, 0x00, 0x00             }, { vrcp28ps zmm30,DWORD [rdx+0x200]\{1to16\}                    }
+testcase	{ 0x62, 0x62, 0x7d, 0x58, 0xca, 0x72, 0x80                               }, { vrcp28ps zmm30,DWORD [rdx-0x200]\{1to16\}                    }
+testcase	{ 0x62, 0x62, 0x7d, 0x58, 0xca, 0xb2, 0xfc, 0xfd, 0xff, 0xff             }, { vrcp28ps zmm30,DWORD [rdx-0x204]\{1to16\}                    }
+testcase	{ 0x62, 0x02, 0xfd, 0x48, 0xca, 0xf5                                     }, { vrcp28pd zmm30,zmm29                                         }
+testcase	{ 0x62, 0x02, 0xfd, 0x4f, 0xca, 0xf5                                     }, { vrcp28pd zmm30\{k7\},zmm29                                   }
+testcase	{ 0x62, 0x02, 0xfd, 0xcf, 0xca, 0xf5                                     }, { vrcp28pd zmm30\{k7\}\{z\},zmm29                              }
+testcase	{ 0x62, 0x02, 0xfd, 0x18, 0xca, 0xf5                                     }, { vrcp28pd zmm30,zmm29,\{sae\}                                 }
+testcase	{ 0x62, 0x62, 0xfd, 0x48, 0xca, 0x31                                     }, { vrcp28pd zmm30,ZWORD [rcx]                                   }
+testcase	{ 0x62, 0x22, 0xfd, 0x48, 0xca, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00       }, { vrcp28pd zmm30,ZWORD [rax+r14*8+0x123]                       }
+testcase	{ 0x62, 0x62, 0xfd, 0x58, 0xca, 0x31                                     }, { vrcp28pd zmm30,QWORD [rcx]\{1to8\}                           }
+testcase	{ 0x62, 0x62, 0xfd, 0x48, 0xca, 0x72, 0x7f                               }, { vrcp28pd zmm30,ZWORD [rdx+0x1fc0]                            }
+testcase	{ 0x62, 0x62, 0xfd, 0x48, 0xca, 0xb2, 0x00, 0x20, 0x00, 0x00             }, { vrcp28pd zmm30,ZWORD [rdx+0x2000]                            }
+testcase	{ 0x62, 0x62, 0xfd, 0x48, 0xca, 0x72, 0x80                               }, { vrcp28pd zmm30,ZWORD [rdx-0x2000]                            }
+testcase	{ 0x62, 0x62, 0xfd, 0x48, 0xca, 0xb2, 0xc0, 0xdf, 0xff, 0xff             }, { vrcp28pd zmm30,ZWORD [rdx-0x2040]                            }
+testcase	{ 0x62, 0x62, 0xfd, 0x58, 0xca, 0x72, 0x7f                               }, { vrcp28pd zmm30,QWORD [rdx+0x3f8]\{1to8\}                     }
+testcase	{ 0x62, 0x62, 0xfd, 0x58, 0xca, 0xb2, 0x00, 0x04, 0x00, 0x00             }, { vrcp28pd zmm30,QWORD [rdx+0x400]\{1to8\}                     }
+testcase	{ 0x62, 0x62, 0xfd, 0x58, 0xca, 0x72, 0x80                               }, { vrcp28pd zmm30,QWORD [rdx-0x400]\{1to8\}                     }
+testcase	{ 0x62, 0x62, 0xfd, 0x58, 0xca, 0xb2, 0xf8, 0xfb, 0xff, 0xff             }, { vrcp28pd zmm30,QWORD [rdx-0x408]\{1to8\}                     }
+testcase	{ 0x62, 0x02, 0x15, 0x07, 0xcb, 0xf4                                     }, { vrcp28ss xmm30\{k7\},xmm29,xmm28                             }
+testcase	{ 0x62, 0x02, 0x15, 0x87, 0xcb, 0xf4                                     }, { vrcp28ss xmm30\{k7\}\{z\},xmm29,xmm28                        }
+testcase	{ 0x62, 0x02, 0x15, 0x17, 0xcb, 0xf4                                     }, { vrcp28ss xmm30\{k7\},xmm29,xmm28,\{sae\}                     }
+testcase	{ 0x62, 0x62, 0x15, 0x07, 0xcb, 0x31                                     }, { vrcp28ss xmm30\{k7\},xmm29,DWORD [rcx]                       }
+testcase	{ 0x62, 0x22, 0x15, 0x07, 0xcb, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00       }, { vrcp28ss xmm30\{k7\},xmm29,DWORD [rax+r14*8+0x123]           }
+testcase	{ 0x62, 0x62, 0x15, 0x07, 0xcb, 0x72, 0x7f                               }, { vrcp28ss xmm30\{k7\},xmm29,DWORD [rdx+0x1fc]                 }
+testcase	{ 0x62, 0x62, 0x15, 0x07, 0xcb, 0xb2, 0x00, 0x02, 0x00, 0x00             }, { vrcp28ss xmm30\{k7\},xmm29,DWORD [rdx+0x200]                 }
+testcase	{ 0x62, 0x62, 0x15, 0x07, 0xcb, 0x72, 0x80                               }, { vrcp28ss xmm30\{k7\},xmm29,DWORD [rdx-0x200]                 }
+testcase	{ 0x62, 0x62, 0x15, 0x07, 0xcb, 0xb2, 0xfc, 0xfd, 0xff, 0xff             }, { vrcp28ss xmm30\{k7\},xmm29,DWORD [rdx-0x204]                 }
+testcase	{ 0x62, 0x02, 0x95, 0x07, 0xcb, 0xf4                                     }, { vrcp28sd xmm30\{k7\},xmm29,xmm28                             }
+testcase	{ 0x62, 0x02, 0x95, 0x87, 0xcb, 0xf4                                     }, { vrcp28sd xmm30\{k7\}\{z\},xmm29,xmm28                        }
+testcase	{ 0x62, 0x02, 0x95, 0x17, 0xcb, 0xf4                                     }, { vrcp28sd xmm30\{k7\},xmm29,xmm28,\{sae\}                     }
+testcase	{ 0x62, 0x62, 0x95, 0x07, 0xcb, 0x31                                     }, { vrcp28sd xmm30\{k7\},xmm29,QWORD [rcx]                       }
+testcase	{ 0x62, 0x22, 0x95, 0x07, 0xcb, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00       }, { vrcp28sd xmm30\{k7\},xmm29,QWORD [rax+r14*8+0x123]           }
+testcase	{ 0x62, 0x62, 0x95, 0x07, 0xcb, 0x72, 0x7f                               }, { vrcp28sd xmm30\{k7\},xmm29,QWORD [rdx+0x3f8]                 }
+testcase	{ 0x62, 0x62, 0x95, 0x07, 0xcb, 0xb2, 0x00, 0x04, 0x00, 0x00             }, { vrcp28sd xmm30\{k7\},xmm29,QWORD [rdx+0x400]                 }
+testcase	{ 0x62, 0x62, 0x95, 0x07, 0xcb, 0x72, 0x80                               }, { vrcp28sd xmm30\{k7\},xmm29,QWORD [rdx-0x400]                 }
+testcase	{ 0x62, 0x62, 0x95, 0x07, 0xcb, 0xb2, 0xf8, 0xfb, 0xff, 0xff             }, { vrcp28sd xmm30\{k7\},xmm29,QWORD [rdx-0x408]                 }
+testcase	{ 0x62, 0x02, 0x7d, 0x48, 0xcc, 0xf5                                     }, { vrsqrt28ps zmm30,zmm29                                       }
+testcase	{ 0x62, 0x02, 0x7d, 0x4f, 0xcc, 0xf5                                     }, { vrsqrt28ps zmm30\{k7\},zmm29                                 }
+testcase	{ 0x62, 0x02, 0x7d, 0xcf, 0xcc, 0xf5                                     }, { vrsqrt28ps zmm30\{k7\}\{z\},zmm29                            }
+testcase	{ 0x62, 0x02, 0x7d, 0x18, 0xcc, 0xf5                                     }, { vrsqrt28ps zmm30,zmm29,\{sae\}                               }
+testcase	{ 0x62, 0x62, 0x7d, 0x48, 0xcc, 0x31                                     }, { vrsqrt28ps zmm30,ZWORD [rcx]                                 }
+testcase	{ 0x62, 0x22, 0x7d, 0x48, 0xcc, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00       }, { vrsqrt28ps zmm30,ZWORD [rax+r14*8+0x123]                     }
+testcase	{ 0x62, 0x62, 0x7d, 0x58, 0xcc, 0x31                                     }, { vrsqrt28ps zmm30,DWORD [rcx]\{1to16\}                        }
+testcase	{ 0x62, 0x62, 0x7d, 0x48, 0xcc, 0x72, 0x7f                               }, { vrsqrt28ps zmm30,ZWORD [rdx+0x1fc0]                          }
+testcase	{ 0x62, 0x62, 0x7d, 0x48, 0xcc, 0xb2, 0x00, 0x20, 0x00, 0x00             }, { vrsqrt28ps zmm30,ZWORD [rdx+0x2000]                          }
+testcase	{ 0x62, 0x62, 0x7d, 0x48, 0xcc, 0x72, 0x80                               }, { vrsqrt28ps zmm30,ZWORD [rdx-0x2000]                          }
+testcase	{ 0x62, 0x62, 0x7d, 0x48, 0xcc, 0xb2, 0xc0, 0xdf, 0xff, 0xff             }, { vrsqrt28ps zmm30,ZWORD [rdx-0x2040]                          }
+testcase	{ 0x62, 0x62, 0x7d, 0x58, 0xcc, 0x72, 0x7f                               }, { vrsqrt28ps zmm30,DWORD [rdx+0x1fc]\{1to16\}                  }
+testcase	{ 0x62, 0x62, 0x7d, 0x58, 0xcc, 0xb2, 0x00, 0x02, 0x00, 0x00             }, { vrsqrt28ps zmm30,DWORD [rdx+0x200]\{1to16\}                  }
+testcase	{ 0x62, 0x62, 0x7d, 0x58, 0xcc, 0x72, 0x80                               }, { vrsqrt28ps zmm30,DWORD [rdx-0x200]\{1to16\}                  }
+testcase	{ 0x62, 0x62, 0x7d, 0x58, 0xcc, 0xb2, 0xfc, 0xfd, 0xff, 0xff             }, { vrsqrt28ps zmm30,DWORD [rdx-0x204]\{1to16\}                  }
+testcase	{ 0x62, 0x02, 0xfd, 0x48, 0xcc, 0xf5                                     }, { vrsqrt28pd zmm30,zmm29                                       }
+testcase	{ 0x62, 0x02, 0xfd, 0x4f, 0xcc, 0xf5                                     }, { vrsqrt28pd zmm30\{k7\},zmm29                                 }
+testcase	{ 0x62, 0x02, 0xfd, 0xcf, 0xcc, 0xf5                                     }, { vrsqrt28pd zmm30\{k7\}\{z\},zmm29                            }
+testcase	{ 0x62, 0x02, 0xfd, 0x18, 0xcc, 0xf5                                     }, { vrsqrt28pd zmm30,zmm29,\{sae\}                               }
+testcase	{ 0x62, 0x62, 0xfd, 0x48, 0xcc, 0x31                                     }, { vrsqrt28pd zmm30,ZWORD [rcx]                                 }
+testcase	{ 0x62, 0x22, 0xfd, 0x48, 0xcc, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00       }, { vrsqrt28pd zmm30,ZWORD [rax+r14*8+0x123]                     }
+testcase	{ 0x62, 0x62, 0xfd, 0x58, 0xcc, 0x31                                     }, { vrsqrt28pd zmm30,QWORD [rcx]\{1to8\}                         }
+testcase	{ 0x62, 0x62, 0xfd, 0x48, 0xcc, 0x72, 0x7f                               }, { vrsqrt28pd zmm30,ZWORD [rdx+0x1fc0]                          }
+testcase	{ 0x62, 0x62, 0xfd, 0x48, 0xcc, 0xb2, 0x00, 0x20, 0x00, 0x00             }, { vrsqrt28pd zmm30,ZWORD [rdx+0x2000]                          }
+testcase	{ 0x62, 0x62, 0xfd, 0x48, 0xcc, 0x72, 0x80                               }, { vrsqrt28pd zmm30,ZWORD [rdx-0x2000]                          }
+testcase	{ 0x62, 0x62, 0xfd, 0x48, 0xcc, 0xb2, 0xc0, 0xdf, 0xff, 0xff             }, { vrsqrt28pd zmm30,ZWORD [rdx-0x2040]                          }
+testcase	{ 0x62, 0x62, 0xfd, 0x58, 0xcc, 0x72, 0x7f                               }, { vrsqrt28pd zmm30,QWORD [rdx+0x3f8]\{1to8\}                   }
+testcase	{ 0x62, 0x62, 0xfd, 0x58, 0xcc, 0xb2, 0x00, 0x04, 0x00, 0x00             }, { vrsqrt28pd zmm30,QWORD [rdx+0x400]\{1to8\}                   }
+testcase	{ 0x62, 0x62, 0xfd, 0x58, 0xcc, 0x72, 0x80                               }, { vrsqrt28pd zmm30,QWORD [rdx-0x400]\{1to8\}                   }
+testcase	{ 0x62, 0x62, 0xfd, 0x58, 0xcc, 0xb2, 0xf8, 0xfb, 0xff, 0xff             }, { vrsqrt28pd zmm30,QWORD [rdx-0x408]\{1to8\}                   }
+testcase	{ 0x62, 0x02, 0x15, 0x07, 0xcd, 0xf4                                     }, { vrsqrt28ss xmm30\{k7\},xmm29,xmm28                           }
+testcase	{ 0x62, 0x02, 0x15, 0x87, 0xcd, 0xf4                                     }, { vrsqrt28ss xmm30\{k7\}\{z\},xmm29,xmm28                      }
+testcase	{ 0x62, 0x02, 0x15, 0x17, 0xcd, 0xf4                                     }, { vrsqrt28ss xmm30\{k7\},xmm29,xmm28,\{sae\}                   }
+testcase	{ 0x62, 0x62, 0x15, 0x07, 0xcd, 0x31                                     }, { vrsqrt28ss xmm30\{k7\},xmm29,DWORD [rcx]                     }
+testcase	{ 0x62, 0x22, 0x15, 0x07, 0xcd, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00       }, { vrsqrt28ss xmm30\{k7\},xmm29,DWORD [rax+r14*8+0x123]         }
+testcase	{ 0x62, 0x62, 0x15, 0x07, 0xcd, 0x72, 0x7f                               }, { vrsqrt28ss xmm30\{k7\},xmm29,DWORD [rdx+0x1fc]               }
+testcase	{ 0x62, 0x62, 0x15, 0x07, 0xcd, 0xb2, 0x00, 0x02, 0x00, 0x00             }, { vrsqrt28ss xmm30\{k7\},xmm29,DWORD [rdx+0x200]               }
+testcase	{ 0x62, 0x62, 0x15, 0x07, 0xcd, 0x72, 0x80                               }, { vrsqrt28ss xmm30\{k7\},xmm29,DWORD [rdx-0x200]               }
+testcase	{ 0x62, 0x62, 0x15, 0x07, 0xcd, 0xb2, 0xfc, 0xfd, 0xff, 0xff             }, { vrsqrt28ss xmm30\{k7\},xmm29,DWORD [rdx-0x204]               }
+testcase	{ 0x62, 0x02, 0x95, 0x07, 0xcd, 0xf4                                     }, { vrsqrt28sd xmm30\{k7\},xmm29,xmm28                           }
+testcase	{ 0x62, 0x02, 0x95, 0x87, 0xcd, 0xf4                                     }, { vrsqrt28sd xmm30\{k7\}\{z\},xmm29,xmm28                      }
+testcase	{ 0x62, 0x02, 0x95, 0x17, 0xcd, 0xf4                                     }, { vrsqrt28sd xmm30\{k7\},xmm29,xmm28,\{sae\}                   }
+testcase	{ 0x62, 0x62, 0x95, 0x07, 0xcd, 0x31                                     }, { vrsqrt28sd xmm30\{k7\},xmm29,QWORD [rcx]                     }
+testcase	{ 0x62, 0x22, 0x95, 0x07, 0xcd, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00       }, { vrsqrt28sd xmm30\{k7\},xmm29,QWORD [rax+r14*8+0x123]         }
+testcase	{ 0x62, 0x62, 0x95, 0x07, 0xcd, 0x72, 0x7f                               }, { vrsqrt28sd xmm30\{k7\},xmm29,QWORD [rdx+0x3f8]               }
+testcase	{ 0x62, 0x62, 0x95, 0x07, 0xcd, 0xb2, 0x00, 0x04, 0x00, 0x00             }, { vrsqrt28sd xmm30\{k7\},xmm29,QWORD [rdx+0x400]               }
+testcase	{ 0x62, 0x62, 0x95, 0x07, 0xcd, 0x72, 0x80                               }, { vrsqrt28sd xmm30\{k7\},xmm29,QWORD [rdx-0x400]               }
+testcase	{ 0x62, 0x62, 0x95, 0x07, 0xcd, 0xb2, 0xf8, 0xfb, 0xff, 0xff             }, { vrsqrt28sd xmm30\{k7\},xmm29,QWORD [rdx-0x408]               }