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| author | Geoff Berry <gberry@codeaurora.org> | 2016-02-09 20:47:21 +0000 |
|---|---|---|
| committer | Geoff Berry <gberry@codeaurora.org> | 2016-02-09 20:47:21 +0000 |
| commit | 173b14db7c9cef77787c629c6cd39436e1c4fbd4 (patch) | |
| tree | 18e8591724ff0e13738a34af13eec0bda3d5bf7a | |
| parent | cc5d61f98e5a3d5eee7547188cb250b8f2080675 (diff) | |
| download | llvm-173b14db7c9cef77787c629c6cd39436e1c4fbd4.tar.gz | |
[AArch64] AArch64LoadStoreOptimizer: fix bug in pre-inc check iterator
Summary:
Fix case where a pre-inc/dec load/store would not be formed if the
add/sub that forms the inc/dec part of the operation was the first
instruction in the block being examined.
Reviewers: mcrosier, jmolloy, t.p.northover, junbuml
Subscribers: aemerson, rengolin, mcrosier, llvm-commits
Differential Revision: http://reviews.llvm.org/D16785
llvm-svn: 260275
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp | 17 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-nvcast.ll | 4 |
2 files changed, 11 insertions, 10 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp index a283bc93706b..9d5098c6db55 100644 --- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp @@ -1023,6 +1023,8 @@ static void trackRegDefsUses(const MachineInstr *MI, BitVector &ModifiedRegs, if (!MO.isReg()) continue; unsigned Reg = MO.getReg(); + if (!Reg) + continue; if (MO.isDef()) { for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) ModifiedRegs.set(*AI); @@ -1496,15 +1498,14 @@ MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward( // (inclusive) and the second insn. ModifiedRegs.reset(); UsedRegs.reset(); - --MBBI; - for (unsigned Count = 0; MBBI != B && Count < Limit; --MBBI) { + unsigned Count = 0; + do { + --MBBI; MachineInstr *MI = MBBI; - // Skip DBG_VALUE instructions. - if (MI->isDebugValue()) - continue; - // Now that we know this is a real instruction, count it. - ++Count; + // Don't count DBG_VALUE instructions towards the search limit. + if (!MI->isDebugValue()) + ++Count; // If we found a match, return it. if (isMatchingUpdateInsn(I, MI, BaseReg, Offset)) @@ -1517,7 +1518,7 @@ MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward( // return early. if (ModifiedRegs[BaseReg] || UsedRegs[BaseReg]) return E; - } + } while (MBBI != B && Count < Limit); return E; } diff --git a/llvm/test/CodeGen/AArch64/arm64-nvcast.ll b/llvm/test/CodeGen/AArch64/arm64-nvcast.ll index 3cb1bf25fc34..944ded04e2ce 100644 --- a/llvm/test/CodeGen/AArch64/arm64-nvcast.ll +++ b/llvm/test/CodeGen/AArch64/arm64-nvcast.ll @@ -2,7 +2,7 @@ ; CHECK-LABEL: _test: ; CHECK: fmov.2d v0, #2.00000000 -; CHECK: str q0, [sp] +; CHECK: str q0, [sp, #-16]! ; CHECK: mov x8, sp ; CHECK: ldr s0, [x8, w1, sxtw #2] ; CHECK: str s0, [x0] @@ -16,7 +16,7 @@ entry: ; CHECK-LABEL: _test2 ; CHECK: movi.16b v0, #0x3f -; CHECK: str q0, [sp] +; CHECK: str q0, [sp, #-16]! ; CHECK: mov x8, sp ; CHECK: ldr s0, [x8, w1, sxtw #2] ; CHECK: str s0, [x0] |