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authorKonstantin Schwarz <konstantin.schwarz@hightec-rt.com>2020-06-18 14:19:47 +0200
committerKonstantin Schwarz <konstantin.schwarz@hightec-rt.com>2020-06-18 14:19:47 +0200
commit734193ac8db08b6cce73dbc99c02e4c53f07822a (patch)
treea045e9045152ce1c1497fc9a1bf253be3911cf03
parent3c6aa40046a0e39261e9719cd3c2bfe6b61cc2c5 (diff)
downloadllvm-734193ac8db08b6cce73dbc99c02e4c53f07822a.tar.gz
[DPWBS-1401] Inform observer that we are changing an instruction
-rw-r--r--llvm/lib/Target/TriCore/TriCoreLegalizerInfo.cpp6
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/TriCore/TriCoreLegalizerInfo.cpp b/llvm/lib/Target/TriCore/TriCoreLegalizerInfo.cpp
index 3ab9cd3041d5..19b0acc7b1d0 100644
--- a/llvm/lib/Target/TriCore/TriCoreLegalizerInfo.cpp
+++ b/llvm/lib/Target/TriCore/TriCoreLegalizerInfo.cpp
@@ -640,6 +640,9 @@ bool TriCoreLegalizerInfo::legalizeIntrinsic(
LLT SizeTy = MRI.getType(SizeReg);
if (SizeTy.getSizeInBits() > 32) {
+ // Inform the observer that we are about to modify the instruction
+ Observer.changingInstr(MI);
+
// If the len argument is a constant, simply create a new s32 constant
auto VRegAndVal = getConstantVRegValWithLookThrough(SizeReg, MRI);
if (VRegAndVal) {
@@ -653,6 +656,9 @@ bool TriCoreLegalizerInfo::legalizeIntrinsic(
MIRBuilder.buildTrunc(TruncReg, SizeReg);
SizeOp.setReg(TruncReg);
}
+
+ // Inform the observer that we are done changing the instruction
+ Observer.changedInstr(MI);
}
if (createMemLibcall(MIRBuilder, MRI, MI) ==