[InstCombine] add tests for rotate/funnel; NFC

2 files changed, 53 insertions, 4 deletions

diff --git a/llvm/test/Transforms/InstCombine/funnel.ll b/llvm/test/Transforms/InstCombine/funnel.ll
index 0aed0bd3005b..4d2d6ef5b7d5 100644
--- a/llvm/test/Transforms/InstCombine/funnel.ll
+++ b/llvm/test/Transforms/InstCombine/funnel.ll
@@ -258,7 +258,7 @@ define i8 @fshr_8bit(i8 %x, i8 %y, i3 %shift) {
   ret i8 %conv2
 }
 
-; The shifted value does not need to be a zexted value; here it is masked.
+; The right-shifted value does not need to be a zexted value; here it is masked.
 ; The shift mask could be less than the bitwidth, but this is still ok.
 
 define i8 @fshr_commute_8bit(i32 %x, i32 %y, i32 %shift) {
@@ -281,6 +281,31 @@ define i8 @fshr_commute_8bit(i32 %x, i32 %y, i32 %shift) {
   ret i8 %conv2
 }
 
+; TODO:
+; The left-shifted value does not need to be masked at all.
+
+define i8 @fshr_commute_8bit_unmasked_shl(i32 %x, i32 %y, i32 %shift) {
+; CHECK-LABEL: @fshr_commute_8bit_unmasked_shl(
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[SHIFT:%.*]], 3
+; CHECK-NEXT:    [[CONVX:%.*]] = and i32 [[X:%.*]], 255
+; CHECK-NEXT:    [[SHR:%.*]] = lshr i32 [[CONVX]], [[AND]]
+; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw i32 8, [[AND]]
+; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[Y:%.*]], [[SUB]]
+; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHR]], [[SHL]]
+; CHECK-NEXT:    [[CONV2:%.*]] = trunc i32 [[OR]] to i8
+; CHECK-NEXT:    ret i8 [[CONV2]]
+;
+  %and = and i32 %shift, 3
+  %convx = and i32 %x, 255
+  %shr = lshr i32 %convx, %and
+  %sub = sub i32 8, %and
+  %convy = and i32 %y, 255
+  %shl = shl i32 %y, %sub
+  %or = or i32 %shr, %shl
+  %conv2 = trunc i32 %or to i8
+  ret i8 %conv2
+}
+
 ; Convert select pattern to funnel shift that ends in 'or'.
 
 define i8 @fshr_select(i8 %x, i8 %y, i8 %shamt) {
diff --git a/llvm/test/Transforms/InstCombine/rotate.ll b/llvm/test/Transforms/InstCombine/rotate.ll
index 36e485158d63..4c77d44f024f 100644
--- a/llvm/test/Transforms/InstCombine/rotate.ll
+++ b/llvm/test/Transforms/InstCombine/rotate.ll
@@ -435,11 +435,11 @@ define i8 @rotate_right_8bit(i8 %v, i3 %shift) {
   ret i8 %conv2
 }
 
-; The shifted value does not need to be a zexted value; here it is masked.
+; The right-shifted value does not need to be a zexted value; here it is masked.
 ; The shift mask could be less than the bitwidth, but this is still ok.
 
-define i8 @rotate_right_commute_8bit(i32 %v, i32 %shift) {
-; CHECK-LABEL: @rotate_right_commute_8bit(
+define i8 @rotate_right_commute_8bit_unmasked_shl(i32 %v, i32 %shift) {
+; CHECK-LABEL: @rotate_right_commute_8bit_unmasked_shl(
 ; CHECK-NEXT:    [[TMP1:%.*]] = trunc i32 [[SHIFT:%.*]] to i8
 ; CHECK-NEXT:    [[TMP2:%.*]] = and i8 [[TMP1]], 3
 ; CHECK-NEXT:    [[TMP3:%.*]] = trunc i32 [[V:%.*]] to i8
@@ -456,6 +456,30 @@ define i8 @rotate_right_commute_8bit(i32 %v, i32 %shift) {
   ret i8 %conv2
 }
 
+; TODO:
+; The left-shifted value does not need to be masked at all.
+
+define i8 @rotate_right_commute_8bit(i32 %v, i32 %shift) {
+; CHECK-LABEL: @rotate_right_commute_8bit(
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[SHIFT:%.*]], 3
+; CHECK-NEXT:    [[CONV:%.*]] = and i32 [[V:%.*]], 255
+; CHECK-NEXT:    [[SHR:%.*]] = lshr i32 [[CONV]], [[AND]]
+; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw i32 8, [[AND]]
+; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[V]], [[SUB]]
+; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHR]], [[SHL]]
+; CHECK-NEXT:    [[CONV2:%.*]] = trunc i32 [[OR]] to i8
+; CHECK-NEXT:    ret i8 [[CONV2]]
+;
+  %and = and i32 %shift, 3
+  %conv = and i32 %v, 255
+  %shr = lshr i32 %conv, %and
+  %sub = sub i32 8, %and
+  %shl = shl i32 %v, %sub
+  %or = or i32 %shr, %shl
+  %conv2 = trunc i32 %or to i8
+  ret i8 %conv2
+}
+
 ; If the original source does not mask the shift amount,
 ; we still do the transform by adding masks to make it safe.