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| author | Craig Topper <craig.topper@sifive.com> | 2021-04-28 09:55:36 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-04-28 09:55:36 -0700 |
| commit | 1d4d6a96164ea9f7d24103ca6fa1ad500386aff6 (patch) | |
| tree | 7fd934e8e21593700943b5975460d94ed1e68dde | |
| parent | 671f0e2e189c561512511331d95de382e2d6d15d (diff) | |
| download | llvm-1d4d6a96164ea9f7d24103ca6fa1ad500386aff6.tar.gz | |
[RISCV] Add explanatory comment to RISCVOp::OPERAND_AVL.
| -rw-r--r-- | llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h index f86b65a01523..1a040a7e2523 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -118,6 +118,9 @@ enum OperandType : unsigned { OPERAND_UIMM20, OPERAND_UIMMLOG2XLEN, OPERAND_LAST_RISCV_IMM = OPERAND_UIMMLOG2XLEN, + // Operand is either a register or uimm5, this is used by V extension pseudo + // instructions to represent a value that be passed as AVL to either vsetvli + // or vsetivli. OPERAND_AVL, }; } // namespace RISCVOp |