summaryrefslogtreecommitdiff
path: root/drivers/pci/pcie/aspm.c
Commit message (Collapse)AuthorAgeFilesLines
...
* PCI ASPM: cleanup aspm state field in struct pcie_link_stateKenji Kaneshige2009-06-181-33/+38
| | | | | | | | | | | The "support_state", "enabled_state" and "bios_aspm_state" fields in the struct pcie_link_state take 2-bit value. So those fields don't need to be defined as unsigned int. This patch makes those fields 2-bit, and cleans up some related code. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI ASPM: fix typo in struct pcie_link_stateKenji Kaneshige2009-06-181-7/+7
| | | | | | | | | | | Fix a typo in struct pcie_link_state. The "sibiling" field in the struct pcie_link_state should be "sibling". Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: disable ASPM on VIA root-port-under-bridge configurationsShaohua Li2009-06-111-0/+4
| | | | | | | | | | VIA has a strange chipset, it has root port under a bridge. Disable ASPM for such strange chipset. Cc: stable@kernel.org Tested-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: properly clean up ASPM link state on device removeAlex Chiang2009-02-041-2/+2
| | | | | | | | | | | | | | | | | | | | | We only want to disable ASPM when the last function is removed from the parent's device list. We determine this by checking to see if the parent's device list is completely empty. Unfortunately, we never hit that code because the parent is considered an upstream port, and never had an ASPM link_state associated with it. The early check for !link_state causes us to return early, we never discover that our device list is empty, and thus we never remove the downstream ports' link_state nodes. Instead of checking to see if the parent's device list is empty, we can check to see if we are the last device on the list, and if so, then we know that we can clean up properly. Cc: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Alex Chiang <achiang@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: Use msleep instead of cpu_relax during ASPM link retrainingAndrew Patterson2009-01-071-4/+9
| | | | | | | | | | | | | | | | | | | | | | | The cpu_relax() function can be a noop on certain architectures like IA-64 when CPU threads are disabled, so use msleep instead during link retraining busy/wait loop. Introduce define LINK_RETRAIN_TIMEOUT instead of hard-coding timeout in pcie_aspm_configure_common_clock. Use time_after() to avoid jiffy wraparound when checking for expired timeout. After timeout expires, recheck link status register link training bit instead of checking for expired timeout to avoid possible false positive. Note that Matthew Wilcox came up with the first rough version of this patch. Reviewed-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Andrew Patterson <andrew.patterson@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: keep ASPM link state consistent throughout PCIe hierarchyShaohua Li2009-01-071-19/+106
| | | | | | | | | | | | | In a PCIe hierarchy with a switch present, if the link state of an endpoint device is changed, we must check the whole hierarchy from the endpoint device to root port, and for each link in the hierarchy, the new link state should be configured. Previously, the implementation checked the state but forgot to configure the links between root port to switch. Fixes Novell bz #448987. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Tested-by: Andrew Patterson <andrew.patterson@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* ACPI/PCI: PCIe ASPM _OSC support capabilities called when root bridge addedAndrew Patterson2009-01-071-18/+9
| | | | | | | | | | | The _OSC capabilities OSC_ACTIVE_STATE_PWR_SUPPORT and OSC_CLOCK_PWR_CAPABILITY_SUPPORT are set when the root bridge is added with pci_acpi_osc_support(), so we no longer need to do it in the ASPM driver. Also add the function pcie_aspm_enabled, which returns true if pcie_aspm=off is not on the kernel command-line. Signed-off-by: Andrew Patterson <andrew.patterson@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCIe: ASPM: Break out of endless loop waiting for PCI config bits to switchThomas Renninger2008-12-091-3/+26
| | | | | | | | | | | | Makes a Compaq 6735s boot reliably again. It used to hang in the loop on some boots. Give the link one second to train, otherwise break out of the loop and reset the previously set clock bits. Cc: stable@vger.kernel.org Signed-off-by: Thomas Renninger <trenn@suse.de> Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Matthew Garrett <mjg59@srcf.ucam.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: probing debug message uniformizationVincent Legoll2008-10-201-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | This patch uniformizes PCI probing debug boot messages with dev_printk() intead of manual printk() It changes adress range output from [%llx, %llx] to [%#llx-%#llx], like in pci_request_region(). For example, it goes from the mixed-style: PCI: 0000:00:1b.0 reg 10 64bit mmio: [f4280000, f4283fff] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold to uniform: pci 0000:00:1b.0: reg 10 64bit mmio: [0xf4280000-0xf4283fff] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold This patch has been runtime tested, boot log messages diffed, everything looks OK. Acked-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Vincent Legoll <vincent.legoll@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: Fix pcie_aspm=forceSitsofe Wheeler2008-09-161-1/+1
| | | | | | | | | pcie_aspm=force did not work because aspm_force was being double negated leading to the sanity check failing. Moving a bracket should fix this. Acked-by: Alan Cox <alan@redhat.com> Signed-off-by: Sitsofe Wheeler <sitsofe@yahoo.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: add an option to allow ASPM enabled forciblyShaohua Li2008-07-281-6/+14
| | | | | | | | A new option, pcie_aspm=force, will force ASPM to be enabled, even on system with PCIe 1.0 devices. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: disable ASPM on pre-1.1 PCIe devicesShaohua Li2008-07-281-0/+13
| | | | | | | | | Disable ASPM on pre-1.1 PCIe devices, as many of them don't implement it correctly. Tested-by: Jack Howarth <howarth@bromo.msbb.uc.edu> Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: disable ASPM per ACPI FADT settingShaohua Li2008-07-281-0/+5
| | | | | | | | | | The ACPI FADT table includes an ASPM control bit. If the bit is set, do not enable ASPM since it may indicate that the platform doesn't actually support the feature. Tested-by: Jack Howarth <howarth@bromo.msbb.uc.edu> Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: don't enable ASPM on devices with mixed PCIe/PCI functionsShaohua Li2008-05-211-0/+20
| | | | | | | | | | The Slot 03:00.* of JMicron controller has two functions, but one is PCIE endpoint the other isn't PCIE device, very strange. PCIE spec defines all functions should have the same config for ASPM, so disable ASPM for the whole slot in this case. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: add PCI Express ASPM supportShaohua Li2008-04-201-0/+811
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI Express ASPM defines a protocol for PCI Express components in the D0 state to reduce Link power by placing their Links into a low power state and instructing the other end of the Link to do likewise. This capability allows hardware-autonomous, dynamic Link power reduction beyond what is achievable by software-only controlled power management. However, The device should be configured by software appropriately. Enabling ASPM will save power, but will introduce device latency. This patch adds ASPM support in Linux. It introduces a global policy for ASPM, a sysfs file /sys/module/pcie_aspm/parameters/policy can control it. The interface can be used as a boot option too. Currently we have below setting: -default, BIOS default setting -powersave, highest power saving mode, enable all available ASPM state and clock power management -performance, highest performance, disable ASPM and clock power management By default, the 'default' policy is used currently. In my test, power difference between powersave mode and performance mode is about 1.3w in a system with 3 PCIE links. Note: some devices might not work well with aspm, either because chipset issue or device issue. The patch provide API (pci_disable_link_state), driver can disable ASPM for specific device. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* Revert "PCI: PCIE ASPM support"Greg Kroah-Hartman2008-02-021-802/+0
| | | | | | | | | | | This reverts commit 6c723d5bd89f03fc3ef627d50f89ade054d2ee3b. It caused build errors on non-x86 platforms, config file confusion, and even some boot errors on some x86-64 boxes. All around, not quite ready for prime-time :( Cc: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* PCI: PCIE ASPM supportShaohua Li2008-02-011-0/+802
PCI Express ASPM defines a protocol for PCI Express components in the D0 state to reduce Link power by placing their Links into a low power state and instructing the other end of the Link to do likewise. This capability allows hardware-autonomous, dynamic Link power reduction beyond what is achievable by software-only controlled power management. However, The device should be configured by software appropriately. Enabling ASPM will save power, but will introduce device latency. This patch adds ASPM support in Linux. It introduces a global policy for ASPM, a sysfs file /sys/module/pcie_aspm/parameters/policy can control it. The interface can be used as a boot option too. Currently we have below setting: -default, BIOS default setting -powersave, highest power saving mode, enable all available ASPM state and clock power management -performance, highest performance, disable ASPM and clock power management By default, the 'default' policy is used currently. In my test, power difference between powersave mode and performance mode is about 1.3w in a system with 3 PCIE links. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>