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path: root/drivers/clk/sunxi/clk-sunxi.c
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| * clk: sunxi: Propagate rate changes to parent for mux clocksChen-Yu Tsai2015-01-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The cpu clock on sunxi machines is just a mux clock, which is normally fed by the main PLL, but can be muxed to the main or low power oscillator. Make the mux clock propagate rate changes to its parent, so we can change the clock rate of the PLL, and thus actually implement rate changing on the cpu clock. This patch also removes the no reparenting limit. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: Give sunxi_factors_register a registers parameterHans de Goede2014-12-211-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit sunxi_factors_register uses of_iomap(node, 0) to get the clk registers. The sun6i prcm has factor clocks, for which we want to use sunxi_factors_register, but of_iomap(node, 0) does not work for the prcm factor clocks, because the prcm uses the mfd framework, so the registers are not part of the dt-node, instead they are added to the platform_device, as platform_device resources. This commit makes getting the registers the callers duty, so that sunxi_factors_register can be used with mfd instantiated platform device too. While at it also add error checking to the of_iomap calls. This commit also drops the __init function from sunxi_factors_register since platform driver probe functions are not __init. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-dividerChen-Yu Tsai2014-12-211-0/+208
| | | | | | | | | | | | | | | | | | | | This patch unifies the sun6i AHB1 clock, originally supported with separate mux and divider clks. It also adds support for the pre-divider on the PLL6 input, thus allowing the clock to be muxed to PLL6 with proper clock rate calculation. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: Remove ahb1_sdram from sun6i/sun8i protected clocks listChen-Yu Tsai2014-12-211-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ahb1_sdram clock gate is only used for accessing the sdram controller's registers over the bus. It is not used for actually clock the controller or the dram, hence it does not need to be protected. This also gets rid of the problem when the protected ahb1_sdram gate is prepared/enabled while it is still an orphan, and the operation is not propagated to the correct parent. This was confirmed on my A23 tablet and my A31 Hummingbird. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxiHans de Goede2015-01-051-0/+1
|/ | | | | | | | | | So far the A31s is 100% compatible with the A31, still lets do the same as what we've done for the A13 / A10s and give it its own compatible string, in case we need to differentiate later. Signed-off-by: Hans de Goede <hdegoede@redhat.com> [Maxime: Removed unusude CPU_OF_DECLARE_METHOD] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: Implement A31 PLL6 as a divs clock for 2x outputChen-Yu Tsai2014-11-231-12/+16
| | | | | | | | | | | | | | | Some clock modules on the A31 use PLL6x2 as one of their inputs. This patch changes the PLL6 implementation for A31 to a divs clock, i.e. clock with multiple outputs that have different dividers. The first output will be the normal PLL6 output, and the second will be PLL6x2. This patch fixes the PLL6 N factor in the clock driver, and removes any /2 dividers in the PLL6 factors clock part. The N factor counts from 1 to 32, mapping to values 0 to 31, as shown in the A31 manual. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: Specify number of child clocks for divs clocksChen-Yu Tsai2014-11-231-2/+9
| | | | | | | | | | | | | | | | Currently sunxi_divs_clk_setup assumes the number of child clocks to be the same as the number of clock-output-names, and a maximum of SUNXI_DIVS_MAX_QTY child clocks. On sun6i, PLL6 only has 1 child clock, but the parent would be used as well, thereby also having it's own clock-output-names entry. This results in an extra bogus clock being registered. This patch adds an entry for the number of child clocks alongside the data structures for them. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: Removed unused/incorrect sun6i-a31-apb2-clk driverChen-Yu Tsai2014-11-231-7/+0
| | | | | | | | | This driver does not match the hardware, which is actually compatible to sun4i-a10-apb1-clk. Since we've switch to the correct one, drop this driver. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: unify APB1 clockEmilio López2014-11-111-5/+2
| | | | | | | | | | This commit unifies the APB1 mux with the APB1 clock, using the new factors infrastructure. Signed-off-by: Emilio López <emilio@elopez.com.ar> [wens@csie.org: Add mux mask bits] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: Add support for bus clock gates on Allwinner A80 SoCChen-Yu Tsai2014-10-211-0/+31
| | | | | | | This adds the gate clocks for AHB/APB busses on the A80 SoC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: make factors clock mux mask configurableChen-Yu Tsai2014-10-211-0/+1
| | | | | | | | | | | | Some of the factors-style clocks on the A80 have different widths for the mux values in the registers. Add a .muxmask field to clk_factors_config to make it configurable. Passing a bitmask instead of a width parameter will allow reuse in case we support table-based muxes in the future. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: Move mbus to mod0 fileMaxime Ripard2014-09-271-57/+0
| | | | | | | | Move the MBUS clock to the module clocks file. It's pretty trivial, but still requires to enable the clocks to make sure it won't get disabled. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* clk: sunxi: Move mod0 clock to a file of its ownMaxime Ripard2014-09-271-1/+0
| | | | | | | | Since we know have the ability to declare factors clock outside of clk-sunxi, create a new mod0 driver to deal with the mod0 clocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* clk: sunxi: Introduce mbus compatibleMaxime Ripard2014-09-271-0/+1
| | | | | | | | | | Even though the mbus clock is a regular module clock, given its nature, it needs to be enabled all the time. Introduce a new compatible, to differentiate it from the other module clocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* clk: sunxi: factors: Invert the probing logicMaxime Ripard2014-09-271-92/+3
| | | | | | | | | | | | | | | | | Until now, the factors clock probing was done directly by sunxi_init_clocks, with the factors registration being called directly with the clocks data passed as an argument. This approch has shown its limits when we added more clocks, since we couldn't really split code with such a logic in smaller files, and led to a huge file having all the clocks. Introduce an intermediate probing function, so that factor clocks will be able to directly be called by CLK_OF_DECLARE, which will in turn ease the split into several files. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* clk: sunxi: add correct divider table for sun4i-apb0 clockChen-Yu Tsai2014-09-131-0/+9
| | | | | | | | | | | | | | | | | | The sun4i-apb0 clock, as found on all platforms using it, is a power-of-two-based divider clock, with a special divider of 2 for value 0. This was causing the clock framework to incorrectly calculate the clock rate for apb1 and related modules on sun6i and sun8i. On sun[4/5/7]i, u-boot SPL configures the divider with value 1 for /2 divider, so no suprises there. This patch adds a proper divider table for it, so the correct clock rate can be calculated. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: add __iomem markings to MMIO pointersEmilio López2014-07-281-5/+5
| | | | | | | | | | This commit adds __iomem thoughout the sunxi clock driver, in places where it was ommited. This cleans most of the sparse warnings we are getting here. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: sunxi: Add A23 clocks supportChen-Yu Tsai2014-07-041-0/+101
| | | | | | | | | | | | | | | | The clock control unit on the A23 is similar to the one found on the A31. The AHB1, APB1, APB2 gates on the A23 are almost identical to the ones on the A31, but some outputs are missing. The main CPU PLL (PLL1) however is like that on older Allwinner SoCs, such as the A10 or A20, but the N factor starts from 1 instead of 0. This patch adds support for PLL1 and all the basic clock muxes and gates. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: Add support for table-based divider clocksChen-Yu Tsai2014-07-041-4/+5
| | | | | | | | | | | | | A few of the clock modules have odd dividers, such as the 2 lowest dividers being the same (2), or have the same divider when the highest bit is set. This patch adds support for optional divider tables, so the clock framework will know about the odd values. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: move "ahb_sdram" to protected clock listChen-Yu Tsai2014-07-041-5/+3
| | | | | | | | | | | With sunxi_gates clocks registered with clkdev, we can use the protected clocks list to enable the "ahb_sdram" clock, instead of looking for it and adding CLK_IGNORE_UNUSED inline in the clock setup code. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: register clock gates with clkdevChen-Yu Tsai2014-07-041-0/+1
| | | | | | | | | | The new important clock protect code requires the clocks be registered with clkdev. This was missing for sunxi_gates type clocks. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sun6i: Protect SDRAM gating bitMaxime Ripard2014-06-111-0/+1
| | | | | | | | | Prevent the SDRAM controller from being gated by force-enabling it in the machine code. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sun6i: Protect CPU clockMaxime Ripard2014-06-111-0/+1
| | | | | | | | | | | | Right now, AHB is an indirect child clock of the CPU clock. If that happens to change, since the CPU clock has no other consumers declared in Linux, it would be shut down, which is not really a good idea. Prevent this by forcing it enabled. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Rework clock protection codeMaxime Ripard2014-06-111-28/+44
| | | | | | | | | | | | Since we start to have a lot of clocks to protect, some of them in a few SoCs only, it becomes difficult to handle the clock protection without having to add per machine exceptions. Add per-SoC data to tell which clock to leave enabled. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Move the GMAC clock to a file of its ownMaxime Ripard2014-06-111-98/+0
| | | | | | | | | | | | Since we have a folder of our own, we can actually make use of it by splitting the huge clock file into several sub drivers. The gmac clock is pretty easy to deal with, since it's pretty much isolated and doesn't have any dependency on the other clocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Move the 24M oscillator to a file of its ownMaxime Ripard2014-06-111-57/+0
| | | | | | | | | | | | Since we have a folder of our own, we can actually make use of it by splitting the huge clock file into several sub drivers. The main oscillator is pretty easy to deal with, since it's pretty much isolated. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Remove calls to clk_putMaxime Ripard2014-06-111-6/+2
| | | | | | | | | | | Callers of clk_put must disable the clock first. This also means that as long as the clock is enabled the driver should hold a reference to that clock. Hence, the call to clk_put here are bogus and should be removed. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Implement A31 USB clockMaxime Ripard2014-06-111-0/+6
| | | | | | | | | | | The A31 USB clock slightly differ from its older counterparts, mostly because it has a different gate for each PHY, while the older one had a single gate for all the phy. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* Merge tag 'clk-for-linus-3.16' of ↵nextLinus Torvalds2014-06-071-0/+37
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux into next Pull clock framework updates from Mike Turquette: "The clock framework changes for 3.16 are pretty typical: mostly clock driver additions and fixes. There are additions to the clock core code for some of the basic types (e.g. the common divider type has some fixes and featured added to it). One minor annoyance is a last-minute dependency that wasn't handled quite right. Commit ba0fae3b06a6 ("clk: berlin: add core clock driver for BG2/BG2CD") in this pull request depends on include/dt-bindings/clock/berlin2.h, which is already in your tree via the arm-soc pull request. Building for the berlin platform will break when the clk tree is built on it's own, but merged into your master branch everything should be fine" * tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/linux: (75 commits) mmc: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs clk: export __clk_round_rate for providers clk: versatile: free icst on error return clk: qcom: Return error pointers for unimplemented clocks clk: qcom: Support msm8974pro global clock control hardware clk: qcom: Properly support display clocks on msm8974 clk: qcom: Support display RCG clocks clk: qcom: Return highest rate when round_rate() exceeds plan clk: qcom: Fix mmcc-8974's PLL configurations clk: qcom: Fix clk_rcg2_is_enabled() check clk: berlin: add core clock driver for BG2Q clk: berlin: add core clock driver for BG2/BG2CD clk: berlin: add driver for BG2x complex divider cells clk: berlin: add driver for BG2x simple PLLs clk: berlin: add driver for BG2x audio/video PLL clk: st: Terminate of match table clk/exynos4: Fix compilation warning ARM: shmobile: r8a7779: Add clock index macros for DT sources clk: divider: Fix overflow in clk_divider_bestdiv clk: u300: Terminate of match table ...
| * clk: sunxi: Fixup clk_sunxi_mmc_phase_control to take a clk rather then a hw_clkHans de Goede2014-05-141-1/+2
| | | | | | | | | | | | | | | | __clk_get_hw is supposed to be used by clk providers, not clk consumers. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: sunxi: Implement MMC phase controlEmilio López2014-05-051-0/+36
| | | | | | | | | | | | | | | | HdG: add header exporting clk_sunxi_mmc_phase_control Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: sunxi: fix function type for CLK_OF_DECLARERob Herring2014-05-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | Adding function type checking to CLK_OF_DECLARE found a type mismatch with sunxi_init_clocks. The function takes a single struct device_node parameter. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Mike Turquette <mturquette@linaro.org> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
* | clk: sunxi: avoid double DT matchingRob Herring2014-05-201-2/+1
|/ | | | | | | | | | | | | | Use for_each_matching_node_and_match instead of for_each_matching_node plus of_match_node to avoid searching the DT twice for each node. The sunxi DT scanning code should really be re-worked rather than have its own private matching infrastructure. It is working around needing a function pointer and a data pointer for each compatible match. Signed-off-by: Rob Herring <robh@kernel.org> Cc: "Emilio López" <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: fix thinko in commentEmilio López2014-03-191-1/+1
| | | | | | | | This should read MOD0 and not MMC; MMC is just one example of a MOD0 clock. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: sunxi: fix some calculationsEmilio López2014-03-191-3/+3
| | | | | | | | | | Some divisor calculations were misrounded, causing higher than requested rates on some clocks. Fix them up using DIV_ROUND_UP, and replace one homebrew instance of it as well with the right macro. Reported-by: Boris BREZILLON <b.brezillon.dev@gmail.com> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: sunxi: fix A20 PLL4 calculationEmilio López2014-03-191-0/+7
| | | | | | | | | Allwinner actually reworked the PLL4 on A20; now it's compatible with the sun4i PLL5/6 design previous to any divisions, as well as to the new PLL8 in sun7i. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: sunxi: Add new clock compatiblesMaxime Ripard2014-02-181-15/+15
| | | | | | | | | | The Allwinner A10 compatibles were following a slightly different compatible patterns than the rest of the SoCs for historical reasons. Add compatibles matching the other pattern to the clock driver for consistency, and keep the older one for backward compatibility. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Add Allwinner A20/A31 GMAC clock unitChen-Yu Tsai2014-02-181-0/+96
| | | | | | | | | | The Allwinner A20/A31 clock module controls the transmit clock source and interface type of the GMAC ethernet controller. Model this as a single clock for GMAC drivers to use. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Add support for PLL6 on the A31Maxime Ripard2014-02-181-0/+45
| | | | | | | | The A31 has a slightly different PLL6 clock. Add support for this new clock in our driver. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Add USB clock register defintionsRoman Byshko2014-02-181-0/+12
| | | | | | | | | | Add register definitions for the usb-clk register found on sun4i, sun5i and sun7i SoCs. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Add support for USB clock-register reset bitsHans de Goede2014-02-181-0/+71
| | | | | | | | | | | The usb-clk register is special in that it not only contains clk gate bits, but also has a few reset bits. This commit adds support for this by allowing gates type sunxi clks to also register a reset controller. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: get divs parent clock name from parent factor clockChen-Yu Tsai2014-02-031-1/+2
| | | | | | | | | | | Divs clocks consist of a parent factor clock with multiple outputs, and seperate clocks for each output. Get the name of the parent clock from the parent factor clock, instead of the DT node name. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: add names for pll5, pll6 parent clocks to factors_dataChen-Yu Tsai2014-02-031-9/+18
| | | | | | | | | | | Some factor clocks, such as the parent clock of pll5 and pll6, have multiple output names. Add the corresponding names to factors_data tied to compatible string. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: add clock-output-names dt property supportChen-Yu Tsai2014-02-031-0/+6
| | | | | | | | | | | | sunxi clock drivers use dt node name as clock name, but clock nodes should be named clk@X, so the names would be the same. Let the drivers read clock names from dt clock-output-names property. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: fix overflow when setting up divided factorsEmilio López2014-01-271-1/+1
| | | | | | | | | | | Currently, we are allocating space for two pointers, when we actually may need to store three of them (two divisors plus the original clock). Fix this, and change sizeof(type) to sizeof(*var) to keep checkpatch.pl happy. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: sunxi: Allwinner A20 output clock supportChen-Yu Tsai2013-12-281-0/+57
| | | | | | | | | This patch adds support for the external clock outputs on the Allwinner A20 SoC. The clock outputs are similar to "module 0" type clocks, with different offsets and widths for clock factors. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: support better factor DT nodesEmilio López2013-12-281-0/+9
| | | | | | | | | | | | | | | | | | | | | The DT nodes should look like abc_clk: clk@deadbeef { ... clock-output-names = "abc"; } But our old DT nodes look like abc: abc@deadbeef { ... } So, let's support both formats, until we can transition everything to the new, correct one. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org>
* clk: sunxi: mod0 supportEmilio López2013-12-281-0/+57
| | | | | | | | This commit implements support for the "module 0" type of clocks, as used by MMC, IR, NAND, SATA and other components. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org>
* clk: sunxi: add PLL5 and PLL6 supportEmilio López2013-12-281-0/+230
| | | | | | | | This commit implements PLL5 and PLL6 support on the sunxi clock driver. These PLLs use a similar factor clock, but differ on their outputs. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org>
* clk: sunxi: make factors_clk_setup return the clock it registersEmilio López2013-12-281-7/+8
| | | | | | | | We will be needing this to register a factor clock as parent with leaf divisors on a single call. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org>
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