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* clk: ingenic-tcu: Fix missing TCU clock for X1000 SoCsAidan MacDonald2022-05-181-10/+25
| | | | | | | | | | | | | | | | The TCU clock gate on X1000 wasn't requested by the driver and could be gated automatically later on in boot, which prevents timers from running and breaks PWM. Add a workaround to support old device trees that don't specify the "tcu" clock gate. In this case the kernel will print a warning and attempt to continue without the clock, which is wrong, but it could work if "clk_ignore_unused" is in the kernel arguments. Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Link: https://lore.kernel.org/r/20220412122750.279058-3-aidanmacdonald.0x0@gmail.com Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: ingenic: Mark critical clocks in Ingenic SoCsAidan MacDonald2022-05-187-0/+76
| | | | | | | | | | | | | | | | | | | | | Consider CPU, L2 cache, and memory clocks as critical to prevent them -- and the parent clocks -- from being automatically gated, since nothing calls clk_get() on these clocks. Gating the CPU clock hangs the processor, and gating memory makes external DRAM inaccessible. Normal kernel code can't hope to deal with either situation so those clocks have to be critical. The L2 cache is required only if caches are running, and could be gated if the kernel takes care to flush and disable caches before gating the clock. There's no mechanism to do this, and probably no reason to do it, so it's simpler to mark the L2 cache as critical. Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20220428164454.17908-3-aidanmacdonald.0x0@gmail.com Tested-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> # On X1000 and X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: ingenic: Allow specifying common clock flagsAidan MacDonald2022-05-182-1/+4
| | | | | | | | | | | | | | Provide a flags field for clocks under the ingenic-cgu driver, which can be used to set generic common clock framework flags on the created clocks. For example, the CLK_IS_CRITICAL flag is needed for some clocks (such as CPU or memory) to stop them being automatically disabled. Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20220428164454.17908-2-aidanmacdonald.0x0@gmail.com Tested-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> # On X1000 and X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: jz4725b: fix mmc0 clock gatingSiarhei Volkau2022-02-171-2/+1
| | | | | | | | | | | | | | | | | The mmc0 clock gate bit was mistakenly assigned to "i2s" clock. You can find that the same bit is assigned to "mmc0" too. It leads to mmc0 hang for a long time after any sound activity also it prevented PM_SLEEP to work properly. I guess it was introduced by copy-paste from jz4740 driver where it is really controls I2S clock gate. Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver") Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Tested-by: Siarhei Volkau <lis8215@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220205171849.687805-2-lis8215@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: ingenic: Add MDMA and BDMA clocksPaul Cercueil2022-01-062-0/+15
| | | | | | | | | | | | | | | | The Ingenic JZ4760 and JZ4770 both have an extra DMA core named BDMA dedicated to the NAND and BCH controller, but which can also do memory-to-memory transfers. The JZ4760 additionally has a DMA core named MDMA dedicated to memory-to-memory transfers. The programming manual for the JZ4770 does have a bit for a MDMA clock, but does not seem to have the hardware wired in. Add the BDMA and MDMA clocks to the JZ4760 CGU code, and the BDMA clock to the JZ4770 code, so that the BDMA and MDMA controllers can be used. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20211220193319.114974-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* Merge tag 'devicetree-fixes-for-5.16-1' of ↵Linus Torvalds2021-11-147-7/+7
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree fixes from Rob Herring: - Two fixes due to DT node name changes on Arm, Ltd. boards - Treewide rename of Ingenic CGU headers - Update ST email addresses - Remove Netlogic DT bindings - Dropping few more cases of redundant 'maxItems' in schemas - Convert toshiba,tc358767 bridge binding to schema * tag 'devicetree-fixes-for-5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: dt-bindings: watchdog: sunxi: fix error in schema bindings: media: venus: Drop redundant maxItems for power-domain-names dt-bindings: Remove Netlogic bindings clk: versatile: clk-icst: Ensure clock names are unique of: Support using 'mask' in making device bus id dt-bindings: treewide: Update @st.com email address to @foss.st.com dt-bindings: media: Update maintainers for st,stm32-hwspinlock.yaml dt-bindings: media: Update maintainers for st,stm32-cec.yaml dt-bindings: mfd: timers: Update maintainers for st,stm32-timers dt-bindings: timer: Update maintainers for st,stm32-timer dt-bindings: i2c: imx: hardware do not restrict clock-frequency to only 100 and 400 kHz dt-bindings: display: bridge: Convert toshiba,tc358767.txt to yaml dt-bindings: Rename Ingenic CGU headers to ingenic,*.h
| * dt-bindings: Rename Ingenic CGU headers to ingenic,*.hPaul Cercueil2021-11-117-7/+7
| | | | | | | | | | | | | | | | | | | | | | Tidy up a bit the tree, by prefixing all include/dt-bindings/clock/ files related to Ingenic SoCs with 'ingenic,'. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211016133322.40771-1-paul@crapouillou.net
* | clk: ingenic: Fix bugs with divided dividersPaul Cercueil2021-11-021-3/+3
|/ | | | | | | | | | | | | | | | | | | | | Two fixes in one: - In the "impose hardware constraints" block, the "logical" divider value (aka. not translated to the hardware) was clamped to fit in the register area, but this totally ignored the fact that the divider value can itself have a fixed divider. - The code that made sure that the divider value returned by the function was a multiple of its own fixed divider could result in a wrong value being calculated, because it was rounded down instead of rounded up. Fixes: 4afe2d1a6ed5 ("clk: ingenic: Allow divider value to be divided") Co-developed-by: Artur Rojek <contact@artur-rojek.eu> Signed-off-by: Artur Rojek <contact@artur-rojek.eu> Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20211001172033.122329-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: ingenic: Add support for the JZ4760Paul Cercueil2021-06-274-0/+441
| | | | | | | | | Add the CGU code and the compatible string to the TCU driver to support the JZ4760 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-7-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: ingenic: Support overriding PLLs M/N/OD calc algorithmPaul Cercueil2021-06-272-13/+30
| | | | | | | | | | SoC-specific code can now provide a callback if they need to compute the M/N/OD values in a specific way. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1000-neo/X1000E Link: https://lore.kernel.org/r/20210530164923.18134-6-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: ingenic: Remove pll_info.no_bypass_bitPaul Cercueil2021-06-273-8/+6
| | | | | | | | | | We can express that a PLL has no bypass bit by simply setting the .bypass_bit field to a negative value. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-5-paul@crapouillou.net Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: ingenic: Read bypass register only when there is onePaul Cercueil2021-06-271-8/+11
| | | | | | | | | | Rework the clock code so that the bypass register is only read when there is actually a bypass functionality. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-4-paul@crapouillou.net Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: Support bypassing dividersPaul Cercueil2021-06-275-29/+42
| | | | | | | | | | | | | | | | | | | | When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU code expects the mux to be applied first, the divider second. On the JZ4760, and maybe on some other SoCs, some clocks also have a mux setting and a divider, but the divider is not applied to all parents selectable from the mux. This could be solved by creating two clocks, one with CGU_CLK_DIV and one with CGU_CLK_MUX, but that would increase the number of clocks. Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit corresponding to the parent clock's index is set, the divider is bypassed. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: ingenic: Fix divider calculation with div tablesPaul Cercueil2020-12-191-4/+10
| | | | | | | | | | | | | | | The previous code assumed that a higher hardware value always resulted in a bigger divider, which is correct for the regular clocks, but is an invalid assumption when a divider table is provided for the clock. Perfect example of this is the PLL0_HALF clock, which applies a /2 divider with the hardware value 0, and a /1 divider otherwise. Fixes: a9fa2893fcc6 ("clk: ingenic: Add support for divider tables") Cc: <stable@vger.kernel.org> # 5.2 Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20201212135733.38050-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_ratePaul Cercueil2020-10-131-0/+2
| | | | | | | | | | | | Clocks that don't have a divider are in our case all marked with the CLK_SET_RATE_PARENT flag. In this case, the .round_rate implementation should modify the value pointed to by parent_rate, in order to propagate the rate change to the parent, as explained in the documentation of clk_set_rate(). Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-5-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENTPaul Cercueil2020-10-131-7/+7
| | | | | | | | | The custom clocks have custom functions to round, get or set their rate. Therefore, we can't assume that they need the CLK_SET_RATE_PARENT flag. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-4-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: ingenic: Don't use CLK_SET_RATE_GATE for PLLPaul Cercueil2020-10-131-2/+7
| | | | | | | | | CLK_SET_RATE_GATE means that the clock must be gated when being reclocked. This is not the case for the PLLs in Ingenic SoCs. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: ingenic: Use readl_poll_timeout instead of custom loopPaul Cercueil2020-10-131-26/+29
| | | | | | | | | Use the readl_poll_timeout() function instead of rolling our own busy-wait loops. This makes the code simpler. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-2-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: ingenic: Use to_clk_info() macro for all clocksPaul Cercueil2020-10-131-39/+15
| | | | | | | | | | | | | The to_clk_info() previously had a BUG_ON() to check that it was only called for PLL clocks. Yet, all the other clocks were doing the exact same thing the macro does, in-line. Move the to_clk_info() macro to the top of the file, remove the hardcoded BUG_ON(), and use it everywhere it makes sense. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: X1000: Add support for calculat REFCLK of USB PHY.周琰杰 (Zhou Yanjie)2020-07-271-1/+83
| | | | | | | | | | Add functions for calculat the rate of REFCLK, which is needed by USB PHY in Ingenic X1000 SoC. Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20200630163852.47267-4-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: JZ4780: Reformat the code to align it.周琰杰 (Zhou Yanjie)2020-07-271-45/+45
| | | | | | | | | | Reformat the code (add one level of indentation before the values), to align the code in the macro definition section. Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20200630163852.47267-3-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: JZ4780: Add functions for enable and disable USB PHY.周琰杰 (Zhou Yanjie)2020-07-271-30/+35
| | | | | | | | | | Add new functions to "jz4780_otg_phy_ops" to enable or disable the USB PHY in the JZ4780 SoC. Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20200630163852.47267-2-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: Ingenic: Add RTC related clocks for Ingenic SoCs.周琰杰 (Zhou Yanjie)2020-07-273-0/+38
| | | | | | | | | | | | | The RTC unit in the Ingenic SoCs has two clock sources, one is from an external 32.768kHz clock, and the other is from an external 24MHz/48MHz main clock that is divided by 512. The choice of these two clocks is controlled by the ERCS bit in the OPCR register. The RNG unit will also use this clock. Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20200725051136.58220-4-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unusedStephen Boyd2020-05-281-1/+1
| | | | | | | | | | | | | | | | This device id table is passed to of_match_node() later on in probe, but on CONFIG_OF=n builds of_match_node() doesn't do anything with the arguments. Lets just mark the table unused so that the compiler doesn't complain about this. drivers/clk/ingenic/tcu.c:326:34: warning: unused variable 'ingenic_tcu_of_match' [-Wunused-const-variable] static const struct of_device_id ingenic_tcu_of_match[] __initconst = { ^ 1 warning generated. Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20200528233837.70269-1-sboyd@kernel.org
* clk: X1000: Add FIXDIV for SSI clock of X1000.周琰杰 (Zhou Yanjie)2020-05-281-6/+111
| | | | | | | | | | | | | | | | 1.The SSI clock of X1000 not like JZ4770 and JZ4780, they are not directly derived from the output of SSIPLL, but from the clock obtained by dividing the frequency by 2. "X1000_CLK_SSIPLL_DIV2" is added for this purpose, and ensure that it initialized before "X1000_CLK_SSIMUX" when initializing the clocks. 2.Clocks of LCD, OTG, EMC, EFUSE, OST, TCU, and gates of CPU, PCLK are also added. 3.Use "CLK_OF_DECLARE_DRIVER" like the other CGU drivers. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20200528031549.13846-8-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: Ingenic: Add CGU driver for X1830.周琰杰 (Zhou Yanjie)2020-05-283-0/+459
| | | | | | | | | | Add support for the clocks provided by the CGU in the Ingenic X1830 SoC, making use of the cgu code to do the heavy lifting. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20200528031549.13846-6-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: Ingenic: Adjust cgu code to make it compatible with X1830.周琰杰 (Zhou Yanjie)2020-05-287-4/+41
| | | | | | | | | | | | | | | | The PLL of X1830 Soc from Ingenic has been greatly changed, the bypass control is placed in another register, so now two registers may needed to control the PLL. To this end, a new "bypass_reg" was introduced. In addition, when calculating rate, the PLL of X1830 introduced an extra 2x multiplier, so a new "rate_multiplier" was introduced. And adjust the code in jz47xx-cgu.c and x1000-cgu.c, make it to be compatible with the new cgu code. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20200528031549.13846-3-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: Ingenic: Remove unnecessary spinlock when reading registers.周琰杰 (Zhou Yanjie)2020-05-281-11/+1
| | | | | | | | | | | | It is not necessary to use spinlock when reading registers, so remove it from cgu.c. Suggested-by: Paul Cercueil <paul@crapouillou.net> Suggested-by: Paul Burton <paulburton@kernel.org> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20200528031549.13846-2-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: ingenic/TCU: Fix round_rate returning errorPaul Cercueil2020-03-201-1/+1
| | | | | | | | | | | When requesting a rate superior to the parent's rate, it would return -EINVAL instead of simply returning the parent's rate like it should. Fixes: 4f89e4b8f121 ("clk: ingenic: Add driver for the TCU clocks") Cc: stable@vger.kernel.org Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20200213161952.37460-2-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: ingenic/jz4770: Exit with error if CGU init failedPaul Cercueil2020-03-201-1/+3
| | | | | | | | | | | | | Exit jz4770_cgu_init() if the 'cgu' pointer we get is NULL, since the pointer is passed as argument to functions later on. Fixes: 7a01c19007ad ("clk: Add Ingenic jz4770 CGU driver") Cc: stable@vger.kernel.org Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reported-by: kbuild test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lkml.kernel.org/r/20200213161952.37460-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: JZ4780: Add function for enable the second core.周琰杰 (Zhou Yanjie)2020-03-201-5/+50
| | | | | | | | | | | | Add "jz4780_core1_enable()" for enable the second core of JZ4780, prepare for later commits. Tested-by: H. Nikolaus Schaller <hns@goldelico.com> Tested-by: Paul Boddie <paul@boddie.org.uk> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Link: https://lkml.kernel.org/r/1582215889-113034-3-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: Ingenic: Add support for TCU of X1000.周琰杰 (Zhou Yanjie)2020-03-201-0/+8
| | | | | | | | | X1000 has a different TCU, since X1000 OST has been independent of TCU. This patch is add TCU support of X1000, and prepare for later OST driver. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lkml.kernel.org/r/1584457893-40418-3-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
*-. Merge branches 'clk-ingenic', 'clk-init-leak', 'clk-ux500' and 'clk-bitmain' ↵Stephen Boyd2019-11-273-1/+286
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into clk-next - Support CGU in Ingenix X1000 - Support Bitmain BM1880 clks * clk-ingenic: clk: ingenic: Allow drivers to be built with COMPILE_TEST clk: Ingenic: Add CGU driver for X1000. dt-bindings: clock: Add X1000 bindings. * clk-init-leak: clk: mark clk_disable_unused() as __init clk: Fix memory leak in clk_unregister() * clk-ux500: MAINTAINERS: Update section for Ux500 clock drivers * clk-bitmain: MAINTAINERS: Add entry for BM1880 SoC clock driver clk: Add common clock driver for BM1880 SoC dt-bindings: clock: Add devicetree binding for BM1880 SoC clk: Add clk_hw_unregister_composite helper function definition clk: Zero init clk_init_data in helpers
| * | clk: ingenic: Allow drivers to be built with COMPILE_TESTStephen Boyd2019-11-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't need the MIPS architecture or even a MIPS compiler to compile test these drivers. Let's add a COMPILE_TEST possibility on the menuconfig here so that we can build these drivers on more configurations. Cc: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20191114001925.159276-1-sboyd@kernel.org Reviewed-by: Paul Cercueil <paul@crapouillou.net>
| * | clk: Ingenic: Add CGU driver for X1000.Zhou Yanjie2019-11-133-0/+285
| |/ | | | | | | | | | | | | | | | | | | Add support for the clocks provided by the CGU in the Ingenic X1000 SoC, making use of the cgu code to do the heavy lifting. Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com> Link: https://lkml.kernel.org/r/1573378102-72380-3-git-send-email-zhouyanjie@zoho.com Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | drivers/clk: convert VL struct to struct_sizeStephen Kitt2019-11-081-2/+1
|/ | | | | | | | | | | | | | There are a few manually-calculated variable-length struct allocations left, this converts them to use struct_size. Found with the following git grep command git grep -A1 'kzalloc.*sizeof[^_].*+' Signed-off-by: Stephen Kitt <steve@sk2.org> Link: https://lkml.kernel.org/r/20190927185110.29897-1-steve@sk2.org Acked-by: Gustavo A. R. Silva <gustavo@embeddedor.com> [sboyd@kernel.org: Add grep command] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* Merge tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linuxLinus Torvalds2019-09-224-1/+490
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Paul Burton: "Main MIPS changes: - boot_mem_map is removed, providing a nice cleanup made possible by the recent removal of bootmem. - Some fixes to atomics, in general providing compiler barriers for smp_mb__{before,after}_atomic plus fixes specific to Loongson CPUs or MIPS32 systems using cmpxchg64(). - Conversion to the new generic VDSO infrastructure courtesy of Vincenzo Frascino. - Removal of undefined behavior in set_io_port_base(), fixing the behavior of some MIPS kernel configurations when built with recent clang versions. - Initial MIPS32 huge page support, functional on at least Ingenic SoCs. - pte_special() is now supported for some configurations, allowing among other things generic fast GUP to be used. - Miscellaneous fixes & cleanups. And platform specific changes: - Major improvements to Ingenic SoC support from Paul Cercueil, mostly enabled by the inclusion of the new TCU (timer-counter unit) drivers he's spent a very patient year or so working on. Plus some fixes for X1000 SoCs from Zhou Yanjie. - Netgear R6200 v1 systems are now supported by the bcm47xx platform. - DT updates for BMIPS, Lantiq & Microsemi Ocelot systems" * tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (89 commits) MIPS: Detect bad _PFN_SHIFT values MIPS: Disable pte_special() for MIPS32 with RiXi MIPS: ralink: deactivate PCI support for SOC_MT7621 mips: compat: vdso: Use legacy syscalls as fallback MIPS: Drop Loongson _CACHE_* definitions MIPS: tlbex: Remove cpu_has_local_ebase MIPS: tlbex: Simplify r3k check MIPS: Select R3k-style TLB in Kconfig MIPS: PCI: refactor ioc3 special handling mips: remove ioremap_cachable mips/atomic: Fix smp_mb__{before,after}_atomic() mips/atomic: Fix loongson_llsc_mb() wreckage mips/atomic: Fix cmpxchg64 barriers MIPS: Octeon: remove duplicated include from dma-octeon.c firmware: bcm47xx_nvram: Allow COMPILE_TEST firmware: bcm47xx_nvram: Correct size_t printf format MIPS: Treat Loongson Extensions as ASEs MIPS: Remove dev_err() usage after platform_get_irq() MIPS: dts: mscc: describe the PTP ready interrupt MIPS: dts: mscc: describe the PTP register range ...
| * clk: jz4740: Add TCU clockPaul Cercueil2019-08-081-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the missing TCU clock to the list of clocks supplied by the CGU for the JZ4740 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: Mathieu Malaterre <malat@debian.org> Tested-by: Artur Rojek <contact@artur-rojek.eu> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Lee Jones <lee.jones@linaro.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-doc@vger.kernel.org Cc: linux-mips@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: od@zcrc.me
| * clk: ingenic: Add driver for the TCU clocksPaul Cercueil2019-08-083-1/+484
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver to support the clocks provided by the Timer/Counter Unit (TCU) of the JZ47xx SoCs from Ingenic. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: Mathieu Malaterre <malat@debian.org> Tested-by: Artur Rojek <contact@artur-rojek.eu> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Lee Jones <lee.jones@linaro.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-doc@vger.kernel.org Cc: linux-mips@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: od@zcrc.me
* | clk: ingenic: Use CLK_OF_DECLARE_DRIVER macroPaul Cercueil2019-08-124-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | By using CLK_OF_DECLARE_DRIVER instead of the CLK_OF_DECLARE macro, we allow the driver to probe also as a platform driver. While this driver does not have code to probe as a platform driver, this is still useful for probing children devices in the case where the device node is compatible with "simple-mfd". Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20190810123620.27238-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: ingenic/jz4740: Fix "pll half" divider not read/written properlyPaul Cercueil2019-08-071-1/+8
|/ | | | | | | | | | | | | | | | | The code was setting the bit 21 of the CPCCR register to use a divider of 2 for the "pll half" clock, and clearing the bit to use a divider of 1. This is the opposite of how this register field works: a cleared bit means that the /2 divider is used, and a set bit means that the divider is 1. Restore the correct behaviour using the newly introduced .div_table field. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20190701113606.4130-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2019-07-179-128/+192
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This round of clk driver and framework updates is heavy on the driver update side. The two main highlights in the core framework are the addition of an bulk clk_get API that handles optional clks and an extra debugfs file that tells the developer about the current parent of a clk. The driver updates are dominated by i.MX in the diffstat, but that is mostly because that SoC has started converting to the clk_hw style of clk registration. The next big update is in the Amlogic meson clk driver that gained some support for audio, cpu, and temperature clks while fixing some PLL issues. Finally, the biggest thing that stands out is the conversion of a large part of the Allwinner sunxi-ng driver to the new clk parent scheme that uses less strings and more pointer comparisons to match clk parents and children up. In general, it looks like we have a lot of little fixes and tweaks here and there to clk data along with the normal addition of a handful of new drivers and a couple new core framework features. Core: - Add a 'clk_parent' file in clk debugfs - Add a clk_bulk_get_optional() API (with devm too) New Drivers: - Support gated clk controller on MIPS based BCM63XX SoCs - Support SiLabs Si5341 and Si5340 chips - Support for CPU clks on Raspberry Pi devices - Audsys clock driver for MediaTek MT8516 SoCs Updates: - Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme - Small frequency support for SiLabs Si544 chips - Slow clk support for AT91 SAM9X60 SoCs - Remove dead code in various clk drivers (-Wunused) - Support for Marvell 98DX1135 SoCs - Get duty cycle of generic pwm clks - Improvement in mmc phase calculation and cleanup of some rate defintions - Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs - Add GPIO, SNVS and GIC clocks for i.MX8 drivers - Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock - Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting - Add clks for new Exynos5422 Dynamic Memory Controller driver - Clock definition for Exynos4412 Mali - Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3 - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M - Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs - TI clock probing done from DT by default instead of firmware - Fix Amlogic Meson mpll fractional part and spread sprectrum issues - Add Amlogic meson8 audio clocks - Add Amlogic g12a temperature sensors clocks - Add Amlogic g12a and g12b cpu clocks - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N - Add CMM (Color Management Module) clocks on Renesas R-Car M3-W - Add Clock Domain support on Renesas RZ/N1" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (190 commits) clk: consoldiate the __clk_get_hw() declarations clk: sprd: Add check for return value of sprd_clk_regmap_init() clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK clk: Add Si5341/Si5340 driver dt-bindings: clock: Add silabs,si5341 clk: clk-si544: Implement small frequency change support clk: add BCM63XX gated clock controller driver devicetree: document the BCM63XX gated clock bindings clk: at91: sckc: use dedicated functions to unregister clock clk: at91: sckc: improve error path for sama5d4 sck registration clk: at91: sckc: remove unnecessary line clk: at91: sckc: improve error path for sam9x5 sck register clk: at91: sckc: add support to free slow clock osclillator clk: at91: sckc: add support to free slow rc oscillator clk: at91: sckc: add support to free slow oscillator clk: rockchip: export HDMIPHY clock on rk3228 clk: rockchip: add watchdog pclk on rk3328 clk: rockchip: add clock id for hdmi_phy special clock on rk3228 clk: rockchip: add clock id for watchdog pclk on rk3328 clk: at91: sckc: add support for SAM9X60 ...
| * clk: ingenic: Remove unused functionsPaul Cercueil2019-06-251-73/+0
| | | | | | | | | | | | | | | | These functions are not called anywhere anymore, they can safely be removed. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: ingenic: Handle setting the Low-Power Mode bitPaul Cercueil2019-06-257-32/+69
| | | | | | | | | | | | | | | | | | | | | | The Low-Power Mode, when enabled, will make the "wait" MIPS instruction suspend the system. This is not really clock-related, but this bit happens to be in the register set of the CGU. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: ingenic: Add missing header in cgu.hPaul Cercueil2019-06-251-0/+1
| | | | | | | | | | | | | | | | | | | | The cgu.h has structures that contain 'clk_onecell_data' and 'clk_hw' structures (no pointers), so the <linux/clk-provider.h> header should be included. Signed-off-by: Paul Cercueil <paul@crapouillou.net> [sboyd@kernel.org: Drop removal of includes in drivers] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: ingenic/jz4725b: Fix "pll half" divider not read/written properlyPaul Cercueil2019-06-071-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code was setting the bit 21 of the CPCCR register to use a divider of 2 for the "pll half" clock, and clearing the bit to use a divider of 1. This is the opposite of how this register field works: a cleared bit means that the /2 divider is used, and a set bit means that the divider is 1. Restore the correct behaviour using the newly introduced .div_table field. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: ingenic/jz4725b: Fix incorrect dividers for main clocksPaul Cercueil2019-06-071-5/+24
| | | | | | | | | | | | | | | | The main clocks (cclk, hclk, pclk, mclk, ipu) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: ingenic/jz4770: Fix incorrect dividers for main clocksPaul Cercueil2019-06-071-6/+28
| | | | | | | | | | | | | | | | The main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: ingenic/jz4740: Fix incorrect dividers for main clocksPaul Cercueil2019-06-071-5/+24
| | | | | | | | | | | | | | | | The main clocks (cclk, hclk, pclk, mclk, lcd) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: ingenic: Add support for divider tablesPaul Cercueil2019-06-072-6/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some clocks provided on Ingenic SoCs have dividers, whose hardware value as written in the register cannot be expressed as an affine function to the actual divider value. For instance, for the CPU clock on the JZ4770, the dividers are coded as follows: ------------------ | Bits | Div | ------------------ | 0 0 0 | 1 | | 0 0 1 | 2 | | 0 1 0 | 3 | | 0 1 1 | 4 | | 1 0 0 | 6 | | 1 0 1 | 8 | | 1 1 0 | 12 | ------------------ To support this setup, we introduce a new field in the ingenic_cgu_div_info structure that allows to specify the divider table. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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