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* ENGR00271136 Fix build break when CONFIG_CLK_DEBUG is disabledMahesh Mahadevan2013-07-151-2/+2
| | | | | | | | | | | clk structure member name is defined only when CONFIG_CLK_DEBUG is enabled. Hence need to encapsulate the code with this config. Patch received from imx community: https://community.freescale.com/thread/308482 Signed-off-by: xiongweihuang Signed-off-by: Mahesh Mahadevan <Mahesh.Mahadevan@freescale.com>
* ARM: 7670/1: fix the memset fixNicolas Pitre2013-07-091-20/+13
| | | | | | | | | | | | | | | | | | | | | Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by recent GCC (4.7.2) optimizations") attempted to fix a compliance issue with the memset return value. However the memset itself became broken by that patch for misaligned pointers. This fixes the above by branching over the entry code from the misaligned fixup code to avoid reloading the original pointer. Also, because the function entry alignment is wrong in the Thumb mode compilation, that fixup code is moved to the end. While at it, the entry instructions are slightly reworked to help dual issue pipelines. Signed-off-by: Nicolas Pitre <nico@linaro.org> Tested-by: Alexander Holler <holler@ahsoftware.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> (cherry picked from commit 418df63adac56841ef6b0f1fcf435bc64d4ed177)
* ARM: 7668/1: fix memset-related crashes caused by recent GCC (4.7.2) ↵Ivan Djelic2013-07-091-41/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | optimizations Recent GCC versions (e.g. GCC-4.7.2) perform optimizations based on assumptions about the implementation of memset and similar functions. The current ARM optimized memset code does not return the value of its first argument, as is usually expected from standard implementations. For instance in the following function: void debug_mutex_lock_common(struct mutex *lock, struct mutex_waiter *waiter) { memset(waiter, MUTEX_DEBUG_INIT, sizeof(*waiter)); waiter->magic = waiter; INIT_LIST_HEAD(&waiter->list); } compiled as: 800554d0 <debug_mutex_lock_common>: 800554d0: e92d4008 push {r3, lr} 800554d4: e1a00001 mov r0, r1 800554d8: e3a02010 mov r2, #16 ; 0x10 800554dc: e3a01011 mov r1, #17 ; 0x11 800554e0: eb04426e bl 80165ea0 <memset> 800554e4: e1a03000 mov r3, r0 800554e8: e583000c str r0, [r3, #12] 800554ec: e5830000 str r0, [r3] 800554f0: e5830004 str r0, [r3, #4] 800554f4: e8bd8008 pop {r3, pc} GCC assumes memset returns the value of pointer 'waiter' in register r0; causing register/memory corruptions. This patch fixes the return value of the assembly version of memset. It adds a 'mov' instruction and merges an additional load+store into existing load/store instructions. For ease of review, here is a breakdown of the patch into 4 simple steps: Step 1 ====== Perform the following substitutions: ip -> r8, then r0 -> ip, and insert 'mov ip, r0' as the first statement of the function. At this point, we have a memset() implementation returning the proper result, but corrupting r8 on some paths (the ones that were using ip). Step 2 ====== Make sure r8 is saved and restored when (! CALGN(1)+0) == 1: save r8: - str lr, [sp, #-4]! + stmfd sp!, {r8, lr} and restore r8 on both exit paths: - ldmeqfd sp!, {pc} @ Now <64 bytes to go. + ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go. (...) tst r2, #16 stmneia ip!, {r1, r3, r8, lr} - ldr lr, [sp], #4 + ldmfd sp!, {r8, lr} Step 3 ====== Make sure r8 is saved and restored when (! CALGN(1)+0) == 0: save r8: - stmfd sp!, {r4-r7, lr} + stmfd sp!, {r4-r8, lr} and restore r8 on both exit paths: bgt 3b - ldmeqfd sp!, {r4-r7, pc} + ldmeqfd sp!, {r4-r8, pc} (...) tst r2, #16 stmneia ip!, {r4-r7} - ldmfd sp!, {r4-r7, lr} + ldmfd sp!, {r4-r8, lr} Step 4 ====== Rewrite register list "r4-r7, r8" as "r4-r8". Signed-off-by: Ivan Djelic <ivan.djelic@parrot.com> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Dirk Behme <dirk.behme@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> (cherry picked from commit 455bd4c430b0c0a361f38e8658a0d6cb469942b5)
* ENGR00269935 Fix the build breakMahesh Mahadevan2013-07-051-1/+1
| | | | | | Add missing parenthesis Signed-off-by: Mahesh Mahadevan <Mahesh.Mahadevan@freescale.com>
* ENGR00269604 Fix the set clock-rate for audio & videoMahesh Mahadevan2013-07-051-1/+2
| | | | | | | | | | | | | | | | | There is single method to set clock-rate for both audio and video pll-s in i.MX6q clock system implementation. That's possible due to they have similar set of registers with a different bases. But there is also one common register: CCM_ANALOG_MISC2, which contains post-dividers. In current implementation, independently of whether audio or video clock is going to be set, the mask 0xc0000000 is applied to MISC2 register. This means, that if the audio clock rate is changed, the video clock post-dividers possibly will be corrupted. This patch fixes the issue described above. Signed-off-by: Alexander Smirnov <alex.bluesman.smirnov@gmail.com> Signed-off-by: Mahesh Mahadevan <Mahesh.Mahadevan@freescale.com>
* ENGR00267089 mx6: Amend the definitions of ANADIG_ANA_MISC2_REGx_STEP_TIME_MASKPeter Chan2013-06-201-3/+3
| | | | | | | Correct the definitions of ANADIG_ANA_MISC2_REG0_STEP_TIME_MASK and ANADIG_ANA_MISC2_REG2_STEP_TIME_MASK to 0x03000000 and 0x30000000 respectively Signed-off-by: Peter Chan <B18700@freescale.com>
* ENGR00181680-1 No audio when play 3 streams after 3~10 seconds sometimesb022472013-06-172-0/+30
| | | | | | | | | sdma: bd is bufferable dma buffer, interrupt handler can not get correct data after sdma script updated. Which will cause there is no interrupt after failed period number times in the interrupt handler. This is a workaround. Signed-off-by: b02247 <b02247@freescale.com>
* ENGR00266312 mx6dl: add i2c4 bus support for sabresd/auto, arm2 platformsFugang Duan2013-06-095-10/+33
| | | | | | | | | | imx6dq have 3 i2c controllers and 5 ecspi,imx6dl have 4 i2c4 controllers and 4 ecspi. imx6dl i2c4 clock source is routed from pll3 through to ecspi_root gate. Add i2c4 bus support for sabresd/auto, and arm2 platforms. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00259693 MX6DL/S-Enable routing of ENET interrupt to GPIORanjani Vaidyanathan2013-04-224-6/+25
| | | | | | | | | | | | In order to fix the performance issue on ENET when WAIT mode is activated, route the ENET interrupts to a GPIO on all MX6DL boards. This patch must be applied on top of: MX6Q/DL-Fix Ethernet performance issue when WAIT mode is active 808863866d2c17aeb3e70a7fcd094bd96db4b601 bae4d40849f3acdd9663f5a0857c9415ed7e6d5d Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00257847-1 MX6Q/DL-Fix Ethernet performance issue when WAIT mode is activeRanjani Vaidyanathan2013-04-1212-30/+154
| | | | | | | | | | | | | | | | | | | | | | | All of the interrupts from the ENET block are not routed to the GPC block. Hence ENET interrupts are not able to wake up the SOC when the system is in WAIT mode. And the ENET interrupt gets serviced only when another interrupt causes the SOC to exit WAIT mode. This impacts the ENET performance. To fix the issue two options: 1. Route the ENET interrupt to a GPIO. Need to enable the CONFIG_MX6_ENET_IRQ_TO_GPIO in the config. This patch provides support for routing the ENET interrupt to GPIO_1_6. Routing to this GPIO requires no HW board mods. If the GPIO_1_6 is being used for some other peripheral, this patch can be followed to route the ENET interrupt to any other GPIO though a HW mode maybe required. 2. If the GPIO mechanism cannot be used and is not enabled by the above mentioned config, the patch will disable entry to WAIT mode until ENET clock is active. When the ENET clock is disabled, WAIT mode will be automatically enetered. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00256417: MLB: can't receive data in wait modeTerry Lv2013-04-121-1/+6
| | | | | | | | For MLB uses iram for data transfer, and there's a missing of dependency on iram in MLB's clock setting, MLB can't receive data in wait mode. We need to add ocram clock dependency in MLB clock. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00257658 Revert "ENGR00256893-1 MX6Q/DL-Fix Ethernet performance issueJason Liu2013-04-0712-126/+10
| | | | | | | | | This reverts commit 067c8dcfa79a169d86809272569fe734c4222c79. i.mx6dl/dq sabreauto/sabresd board will boot up failed randomly with this patch-set, thus revert it. [Jason] Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00237365: board-mx6q_sabreauto fix mipi-csi2 settingsAdrian Alonso2013-04-031-6/+13
| | | | | | | | | | * Correct mipi-csi2 settings only one data line is used * Add mx6q_mipi_csi1_io_init ipu-csi setting callback use virtual channel 1 and attach it to CSI1 -> IPU0 * Set i2c slave address to 0x52 * Set ipu-csi clko_clk Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* ENGR00254896 mx6: hdmidongle: Fix compile error.Zhang Xiaodong2013-04-031-7/+0
| | | | | | | After enable PICE in kernel config, building will meet fatal error:linux/wakelock.h: No such file or directory Signed-off-by: Zhang Xiaodong <B39117@freescale.com>
* ENGR00256315-4 ARM: imx6: weim-nor: set proper PAD valueHuang Shijie2013-04-032-48/+48
| | | | | | Set the proper pad values for the pins used for address. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00256315-3 ARM: WEIM-NOR: set the proper timingHuang Shijie2013-04-031-5/+63
| | | | | | These timings are calculated from the M29W256GL7AN6E. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00256315-1 Revert "ENGR00244769-2 [NOR FLASH]-Improve WEIM NOR speed"Huang Shijie2013-04-032-47/+13
| | | | | | | | | This reverts commit 58209e14383520d58b1bf74e0e9f98f7d05b80c6. After apply these two patches, we can not pass the stress test. So revert these two patches. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00256893-1 MX6Q/DL-Fix Ethernet performance issue when WAIT mode is activeRanjani Vaidyanathan2013-04-0212-13/+129
| | | | | | | | | | | | | | | | | | | | | | | All of the interrupts from the ENET block are not routed to the GPC block. Hence ENET interrupts are not able to wake up the SOC when the system is in WAIT mode. And the ENET interrupt gets serviced only when another interrupt causes the SOC to exit WAIT mode. This impacts the ENET performance. To fix the issue two options: 1. Route the ENET interrupt to a GPIO. Need to enable the CONFIG_MX6_ENET_IRQ_TO_GPIO in the config. This patch provides support for routing the ENET interrupt to GPIO_1_6. Routing to this GPIO requires no HW board mods. If the GPIO_1_6 is being used for some other peripheral, this patch can be followed to route the ENET interrupt to any other GPIO though a HW mode maybe required. 2. If the GPIO mechanism cannot be used and is not enabled by the above mentioned config, the patch will disable entry to WAIT mode until ENET clock is active. When the ENET clock is disabled, WAIT mode will be automatically enetered. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00255484-3 msl: usb: add clock deinit at fail pathPeter Chen2013-03-222-0/+6
| | | | | | If not, the clocks usage will be mismatch Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00255484-1 msl: usb: add NULL poiner check for fsl_xcvr_opsPeter Chen2013-03-221-3/+3
| | | | | | Add NULL pointer check for global fsl_xcvr_ops Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00254442 Sabre ARD Include WEIM-NOR on imx6_updater_defconfigAlejandro Sierra2013-03-151-0/+1
| | | | | | | | Sabre ARD include WEIM-NOR configuration update to enable higher bandwidth on this interface for mfg tool support (imx6_updater_defconfig). Signed-off-by: Alex Sierra <b18039@freescale.com>
* ENGR00253355 ARM: imx6q/imx6dl: Set proper PAD value for WEIM NORHuang Shijie2013-03-152-33/+41
| | | | | | | Set proper pad value for WEIM NOR. Without setting these pad value the weim-nor can not work. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00254457 mx6dl: fix mx6dl TO1.1 can't enter 'mem'Robin Gong2013-03-151-2/+2
| | | | | | | | The previous patch ENGR00251630 didn't notice mx6q_revision() will return -EINVAL and will match 'mx6q_revision()<IMX_CHIP_REVISION_1_1' ,then mx6dl TO1.1 will also change suspend state to 'standby'. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00254267 MX6DL/MX6SL max freq: Fix max cpu freq at 1G on MX6DL ARDRobin Gong2013-03-141-4/+12
| | | | | | | | | For MX6DL,align max cpufreq judge by SPEED_GRADING fuse bit with MX6DQ. For MX6SL without the fuse bit, we need add condition check, if found arm_max_freq set by default , change to1G. Else decided by 'arm_freq' setting by cmdline. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00253418 IMX6 SabreSD Display: Support LVDS1 and HDMI dual displayWayne Zou2013-03-131-20/+3
| | | | | | | Support LVDS1 and HDMI dual display on SabreSD Rev.C board on i.mx6 By default, LVDS uses LDB_SEP1 mode due to the hardware design. Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00169384 imx6q: uart: config and enble uart5Jianzheng Zhou2013-03-124-4/+9
| | | | | | Config clock,irq,mux pad,data entry, etc to setup uart5. Signed-off-by: Jianzheng Zhou <jianzheng.zhou@freescale.com>
* ENGR00252071-3: mxc_v4l2_capture: enable auto detect of ov5642/5640 in sabresdSheng Nan2013-03-121-1/+1
| | | | | | - enable the auto detect for parallel ov5642 and ov5640 in sabresd board. Signed-off-by: Sheng Nan <b38800@freescale.com>
* ENGR00252071-4: mxc_v4l2_capture: enable auto detect of ov5642/5640 in sabreliteSheng Nan2013-03-121-1/+1
| | | | | | - enable the auto detect for parallel ov5642 and ov5640 in sabrelite board. Signed-off-by: Sheng Nan <b38800@freescale.com>
* ARM: 7417/1: vfp: ensure preemption is disabled when enabling VFP accessWill Deacon2013-03-061-4/+6
| | | | | | | | | | | | | | | | | | | | | The vfp_enable function enables access to the VFP co-processor register space (cp10 and cp11) on the current CPU and must be called with preemption disabled. Unfortunately, the vfp_init late initcall does not disable preemption and can lead to an oops during boot if thread migration occurs at the wrong time and we end up attempting to access the FPSID on a CPU with VFP access disabled. This patch fixes the initcall to call vfp_enable from a non-preemptible context on each CPU and adds a BUG_ON(preemptible) to ensure that any similar problems are easily spotted in the future. Cc: stable@vger.kernel.org Reported-by: Hyungwoo Yang <hwoo.yang@gmail.com> Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> [Fix merge conflict] Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00251209-9 msl: usb: make global variable as drvdataPeter Chen2013-03-061-10/+10
| | | | | | | | There is a bug when we try to remove wakeup module twice as g_ctrl is a globle variable, in fact, it is per controller wakeup driver, so the private data should be per device. Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00251209-6 msl-mx6: usb: keep the phy lower flag as true defaultlyPeter Chen2013-03-061-0/+1
| | | | | | | | | | | Keep the phy lower flag as true defaultly, the driver should mark it as false when the driver begins to use PHY. This fixes one bug that when build both host and gadget as loadable modules, the phy lower flag is false if the related module is not loaded, then, the wakeup interrupt will not be treated as happened if host module is loaded, but gadget is not loaded, or vice verse. Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00251209-4 msl-mx6: usb: Fix system hang when unload gadget modulePeter Chen2013-03-061-3/+0
| | | | | | | | | At gadget module remove function, it closes the clock, but at platform code, it still visits register. In fact, The PHY has already been low power mode when driver's remove before platform code is called. Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00251209-3 usb: fix below build warningPeter Chen2013-03-061-49/+49
| | | | | | | | | | | | | /home/b29397/work/projects/linux-2.6-imx/arch/arm/mach-mx6/usb_dr.c: In function 'mx6_usb_dr_init': /home/b29397/work/projects/linux-2.6-imx/arch/arm/mach-mx6/usb_dr.c: 615: warning: unused variable 'imx6q_mxc_ehci_otg_data' /home/b29397/work/projects/linux-2.6-imx/arch/arm/mach-mx6/usb_dr.c: At top level: /home/b29397/work/projects/linux-2.6-imx/arch/arm/mach-mx6/usb_dr.c: 77: warning: 'fsl_platform_otg_set_usb_phy_dis' defined but not used Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00251209-1 usb: add host 1 vbus callbackPeter Chen2013-03-062-6/+12
| | | | | | The callback will be used at probe and remove Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00252727-1 [mxc]Add fuse check for gpu platform deviceLoren Huang2013-03-051-6/+29
| | | | | | | | Add fuse check for gpu platform device. Bypass gpu core initialization if certain core is fused.If all gpu cores are fused, bypass gpu driver loading. Signed-off-by: Loren Huang <b02279@freescale.com>
* ENGR00237452 i.MX6:IEEE1588: disable phy Ar8031 SmartEEEFugang Duan2013-03-043-0/+31
| | | | | | | | | | | | | | | | | | | Connecting two boards directly more than 2 hours, Ar8031 phy link status generates glitch, which cause ethernet link down/up issue, but ethernet still be active. There have three cases to validate the issue: Item#1: If add performance stress test while runing IEEE1588, the link down/up issue cannot be found. Item#2: If insert switch between two net nodes and run IEEE1588 test, the issue also cannot be found. Item#3: If disable AR8031 SmartEEE feature, after two days overnight test, no such issue found. The issue is caused by phy Ar8031 SmartEEE feature, Item#1 and Item#2 can prevent phy enter lpm mode, which match the Item#3 test result, so disable SmartEEE feature to avoid the link issue generation. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00252418 imx6: add fuse check for available devicesDong Aisheng2013-03-0114-29/+244
| | | | | | | | | | | | | Since device availability may be different on the same SoC, so we add fuse check for the supported device before we really adding the device to the kernel. This may avoid kernel crash once the CPU at the slot are changed to a different one which with different device available but the kernel is the same one. Reviewed-by: Jason Liu <r64343@freescale.com> Acked-by: Jason Liu <r64343@freescale.com> Signed-off-by: Dong Aisheng <b29396@freescale.com>
* timer: fix the too many reries on the per-cpu event deviceJason Liu2013-03-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are so many retries happen on the per-cpu event device when run the command 'cat /proc/timer_list', as following: root@~$ cat /proc/timer_list Timer List Version: v0.6 HRTIMER_MAX_CLOCK_BASES: 3 now at 3297691988044 nsecs Tick Device: mode: 1 Per CPU device: 0 Clock Event Device: local_timer max_delta_ns: 8624432320 min_delta_ns: 1000 mult: 2138893713 shift: 32 mode: 3 next_event: 3297700000000 nsecs set_next_event: twd_set_next_event set_mode: twd_set_mode event_handler: hrtimer_interrupt retries: 36383 the reason is that the local timer will stop when enter C3 state, we need switch the local timer to bc timer when enter the state and switch back when exit from the that state.The code is like this: void arch_idle(void) { .... clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); enter_the_wait_mode(); clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); } when the broadcast timer interrupt arrives(this interrupt just wakeup the ARM, and ARM has no chance to handle it since local irq is disabled. In fact it's disabled in cpu_idle() of arch/arm/kernel/process.c) the broadcast timer interrupt will wake up the CPU and run: clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); -> tick_broadcast_oneshot_control(...); -> tick_program_event(dev->next_event, 1); -> tick_dev_program_event(dev, expires, force); -> for (i = 0;;) { int ret = clockevents_program_event(dev, expires, now); if (!ret || !force) return ret; dev->retries++; .... now = ktime_get(); expires = ktime_add_ns(now, dev->min_delta_ns); } clockevents_program_event(dev, expires, now); delta = ktime_to_ns(ktime_sub(expires, now)); if (delta <= 0) return -ETIME; when the bc timer interrupt arrives, which means the last local timer expires too. so, clockevents_program_event will return -ETIME, which will cause the dev->retries++ when retry to program the expired timer. Even under the worst case, after the re-program the expired timer, then CPU enter idle quickly before the re-progam timer expired, it will make system ping-pang forever if no interrupt happen. We have found the ping-pang issue during the video play-back test. system will freeze and video not playing for sometime until other interrupt occured to break the error condition. The detailed information, please refer to the LKML:https://lkml.org/lkml/2013/2/20/216 which posted by Jason Liu. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Jason Liu <r64343@freescale.com> Tested-by: Jason Liu <r64343@freescale.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
* ENGR00251849-2 ldo_bypass:print the ldo_bypass mode directly, not obscure numberRobin Gong2013-02-261-1/+2
| | | | | | You can see "cpu regulator mode:ldo_bypass" log directly from console when boot. not "cpu regulator init ldo=1" before. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00251849-1 cpufreq:print the max freq directly, not obscure numberRobin Gong2013-02-261-2/+3
| | | | | | | You can see "arm_max_freq=1GHz" log directly from console during boot. not "arm_max_freq=1" before. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00251630 MX6DQ: do not power off ARM in suspend on TO1.1Robin Gong2013-02-261-3/+7
| | | | | | | | | | | | System will resume back failed which caused by IPG clock glich issue. The issue (TKT094231) has been fixed on MX6DQ TO1.2 and MX6DL TO1.1.It is hard to reproduced on MX6DQ TO1.1/1.0 with 0xffffffff in GPC_PGC_CPU_PUPSCR which implemented on GA release. But it is easy to reproduced with 0xf0f0 on mainline now. As we focus on latest formal chip, the problem is cleaned up until now. We will aign with the workaround on MX6DL which do not power off ARM in suspend. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00244769-2 [NOR FLASH]-Improve WEIM NOR speedOliver Brown2013-02-142-13/+47
| | | | | | | Increase the NOR flash read speed. Added weimnor driver to use cached (and page mode) reads. Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
* ENGR00243348 imx: pcie: disable pcie phy in kernel initializationRichard Zhu2013-02-063-39/+46
| | | | | | | In order to save power consumption, disable pcie phy (enable IDDQ mode) in kernel initialization. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00243339 imx: sata: disable sata phy when sata is not enabledRichard Zhu2013-02-055-12/+88
| | | | | | | | In order to save power consumption, disable sata phy (enable PDDQ mode) in kernel level, if the sata module is not enabled in kernel configuration. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00243106 imx: pcie: enable pcie msi on imx6 platformsRichard Zhu2013-02-057-8/+293
| | | | | | | | | | | | | | | | | deprieved from boundary msi support patch add the following modifications * use the RC's line address 0x01FF8000 instead of one actual physical memory as the msi start address. The physical memory address is not mandatory required by the msi start address. * set PCI_MSI_FLAGS_ENABLE in RC's msi capability structure when the msi int is enabled. * the data of msg is only 16bit, set the upper 8bit cputype, and the msi int num to the lower 8bit. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00242672 MX6 local timer:Remove enable_wait_mode global variableLiu Ying2013-01-311-3/+1
| | | | | | | This patch removes the unnecessary global variable declaration for enable_wait_mode. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00242214 IMX PWM:Correct duty cycle calculationLiu Ying2013-01-311-6/+2
| | | | | | | | | | | | | | | | | | | | Since we've already reduced 2 cycles before writing PWMPR register, the real period cycle on PWMO is the value of period_cycles (before reducing 2). So, the following commit message of ENGR00170342, which changes the duty cycle calculation wrongly, is not reasonable: =================================================== The chip document says the counter counts up to period_cycles + 1 and then is reset to 0, so the actual period of the PWM wave is period_cycles + 2 =================================================== Revert "ENGR00170342 PWM: fix pwm output can't be set to 100% full duty" This reverts commit ac3711f7f24b94db9f78fd7e9bf134c2ecd025ab. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit b42be77aa7842834f0fb50924546701b668d7ab9)
* ENGR00242269 MX6 PCIE:Print out link up failure logLiu Ying2013-01-301-1/+1
| | | | | | | | | | | This patch contains code change only to print out link up failure log like below. link up failed, DB_R0:0x001b8400, DB_R1:0x08200000! Before the change, the present print code can never be called even if the link up fails. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00241003-1 mx6: need to add delay in LDO voltage settingAnson Huang2013-01-284-31/+118
| | | | | | | | | | | | | | | | | | | 1.LDO ramp up time may be modified by ROM code according to fuse setting, cpu freq driver use fixed delay time which assume the LDO ramp up time is the reset value of ANATOP register, need to set it to reset value in regulator init. 2.The regulator set voltage should take care of the ramp up time, calculate the ramp up time based of register setting and to the delay, make sure that when the set voltage function return, the voltage is stable enough. 3.CPUFreq no need to use delay, it is already taken care by regulator voltage setting. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00240990 MX6 HDMI dongle:Configure HDMI PHY registersLiu Ying2013-01-211-1/+3
| | | | | | | | | | | | This patch sets HDMI PHY register values in MXC HDMI driver platform data so that MXC HDMI driver can configure the 0x09 CKSYMTXCTRL register(Clock Symbol and Transmitter Control Register) and 0x0E VLEVCTRL register(Voltage Level Control Register), then we may pass HDMI compliance test for MX6 HDMI dongle board. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 788bcf52a2e4c37dc42e9605d31995f8dd80d674)
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