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* ARM: dts: kirkwood: set default pinctrl for NANDSebastian Hesselbarth2014-05-0511-20/+3
| | | | | | | | | | | | | There is only one valid pinctrl setting for NAND on Kirkwood. Now that we have the setting in the common SoC pinctrl, move it to the NAND controller node directly and remove it from the individual boards. While at it, also fix up status = "okay" to "ok" on one board's NAND node. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1398862602-29595-12-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: dts: kirkwood: set default pinctrl for SPI0Sebastian Hesselbarth2014-05-0510-22/+6
| | | | | | | | | | | | | | | Most Kirkwood boards use the default SPI0 pinctrl setting anyway. Add a default pinctrl setting to the toplevel SoC SPI0 node and put a note in front of the corresponding pinctrl node to overwrite the setting on board level. Currently, only T5325 is using a different setting and already overwrites the corresponding pinctrl node. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1398862602-29595-11-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: dts: kirkwood: set default pinctrl for UART0/1Sebastian Hesselbarth2014-05-0517-50/+18
| | | | | | | | | | | | | | | | Most boards use the default UART0/1 pinctrl setting without RTS/CTS. Add the pinctrl setting to the toplevel SoC UART nodes and put a note in front of the corresponding pinctrl node to overwrite the setting on board level. Currently, both boards using a different UART pinctrl setting (Openblocks A6, A7) already overwrite the pinctrl node. While at it, also fix up some status = "ok" to "okay" and again whitespace issues on mplcec4 uart nodes. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1398862602-29595-10-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: dts: kirkwood: set default pinctrl for GBE1Sebastian Hesselbarth2014-05-052-2/+2
| | | | | | | | | | | On Kirkwood, there is only one valid pinctrl setting for GBE1. With a common SoC pinctrl node, we can now set it in the node instead of in each board file. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1398862602-29595-9-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: dts: kirkwood: consolidate common pinctrl settingsSebastian Hesselbarth2014-05-056-96/+33
| | | | | | | | | | All SoCs have the same pinctrl setting for NAND, UART0/1, SPI, TWSI0, and GBE1. Move it to the common pinctrl node that we now have. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1398862602-29595-8-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: dts: kirkwood: add pinctrl node to common SoC includeSebastian Hesselbarth2014-05-055-4/+5
| | | | | | | | | | | | All Kirkwood SoCs have their pinctrl registers at the same address. Instead of replaying the same reg property on each SoC, have the reg property set in the common SoC file already. This also allows us to move common pinctrl settings to this node later on. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1398862602-29595-7-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: dts: kirkwood: rename pin-controller nodesSebastian Hesselbarth2014-05-0538-38/+38
| | | | | | | | | | To prepare pin-controller consolidation, first rename all pinctrl nodes to a more appropriate name regarding ePAPR recommended names. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1398862602-29595-6-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: dts: kirkwood: remove clock-frequency properties from UART nodesSebastian Hesselbarth2014-05-055-6/+0
| | | | | | | | | | | | | UART devices found on Kirkwood SoCs derive their baudrate from TCLK. With proper clocks property in the SoCs serial node, boards do not need to overwrite it anymore. Remove the remaining clock-frequency property from all Kirkwood boards. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1398862602-29595-5-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: dts: kirkwood: add stdout-path property to all boardsSebastian Hesselbarth2014-05-0547-3/+50
| | | | | | | | | | | | | | | ePAPR allows to reference the device used for console output by stdout-path property. With node labels for Kirkwood UART0, now reference it on all Kirkwood boards that already have ttyS0 in their bootargs property. While at it, fix some whitespace issues on mplcec4's chosen node (there are more, but we only fix the chosen node now) Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1398862602-29595-4-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: dts: kirkwood: add node labelsSebastian Hesselbarth2014-05-054-26/+26
| | | | | | | | | | This adds missing node labels to Kirkwood common and SoC specific nodes to allow to reference them more easily. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1398862602-29595-3-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: Enable the thermal sensor in Armada 380/385 SoCEzequiel Garcia2014-04-281-0/+6
| | | | | | | | This commit enables the thermal sensor found in Armada 380/385 SoCs. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1398371004-15807-11-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: Enable the thermal sensor in Armada 375 SoCEzequiel Garcia2014-04-261-0/+6
| | | | | | | | This commit enables the thermal sensor found in Armada 375 SoCs. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1398371004-15807-10-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: don't use clocks property in UART node for Netgear RN2120Thomas Petazzoni2014-04-261-1/+0
| | | | | | | | | | | | | | The Netgear RN2120 was not using the same strategy as the other Armada 370/375/38x/XP boards: it was using a 'clocks' property and not the 'clock-frequency' property in its UART controller Device Tree node. However, now that this clock reference is present at the SoC-level, there is no point in duplicating it at the board-level. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397806908-7550-6-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: remove clock-frequency of serial port Device Tree nodesThomas Petazzoni2014-04-2613-24/+0
| | | | | | | | | | | | | | | Now that the Armada 370/375/38x/XP SoC-level Device Tree files have the proper "clocks" property in their UART controllers node, it is no longer useful to have the clock-frequency property defined in the board-level Device Tree files. Therefore, this commit gets rid of all the useless 'clock-frequency' properties. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397806908-7550-5-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: use clocks property for serial portsThomas Petazzoni2014-04-264-0/+8
| | | | | | | | | | | | | | | | | | | | | | Back when the Armada 370 and Armada XP initial support was introduced, the only way to pass the clock frequency to the of_serial driver was through a clock-frequency Device Tree property. Thanks to 0bbeb3c3e84bc963d1c66661e082d207023b0e5c ('of serial port driver - add clk_get_rate() support'), it is possible to use the standard 'clocks' DT property to reference the clock used for a particular UART controller. This clock is then used by the of_serial driver to retrieve the clock rate. This commit modifies the SoC-level Device Tree files of Armada 370, Armada XP, Armada 375 and Armada 38x to use this possibility. Since there is no gatable clock for the UART controllers, we simply reference the TCLK, which is the main SoC clock for the peripherals. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397806908-7550-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: add Device Tree description of AHCI interfaces on Armada 38xThomas Petazzoni2014-04-262-0/+24
| | | | | | | | | | | | The Marvell Armada 38x processors contain two AHCI compatible interfaces. This commit adds the Device Tree description of those interfaces at the SoC level, and also enables them on the Armada 385 DB platform, which allows access to both interfaces through SATA ports. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397574006-5868-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: enable the SDHCI interface on Armada 385Thomas Petazzoni2014-04-252-0/+17
| | | | | | | | | | | | | | | In commit "mmc: sdhci-pxav3: add support for the Armada 38x SDHCI controller", the sdhci-pxav3 driver has been extended to also be usable on Armada 38x platforms. Therefore, this commit adds the necessary Device Tree informations to declare this SDHCI interface in the Armada 38x SoC, and also in the Armada 385 Development Board. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1397486478-16991-2-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: add SMP support in the Armada 38x device treeThomas Petazzoni2014-04-243-0/+14
| | | | | | | | | | | This commit improves the Armada 38x Device Tree to add the CPU reset and PMSU Device Tree nodes as well as the declaration of the enabling method for the CPUs. These are needed to get SMP working on Armada 38x platforms. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397483648-26611-12-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: add SMP support in the Armada 375 device treeGregory CLEMENT2014-04-241-0/+7
| | | | | | | | | | | | Improve the Armada 375 Device Tree to add the CPU reset Device Tree node and declare the enabling method for CPUs, both of which are necessary to get SMP working. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397483648-26611-11-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397483648-26611-11-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: add enable-method property for CPUsThomas Petazzoni2014-04-243-0/+3
| | | | | | | | | | | This commit updates the Armada XP Device Trees (for the three variants of Armada XP) to declare the "enable-method" property for the CPUs, which helps operating systems find the appropriate logic to manage the CPUs, especially to boot secondary CPUs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397483648-26611-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: switch to the new PMSU binding in Armada 370/XP Device TreeGregory CLEMENT2014-04-243-3/+13
| | | | | | | | | | | | | | | | | | | | | | | Following the introduction of the new PMSU Device Tree binding, as well as the separate CPU reset binding, this commit switches the Armada 370 and Armada XP Device Trees to use them. The PMSU node is moved from the Armada XP specific armada-xp.dtsi to the common Armada 370/XP armada-370-xp.dtsi because the PMSU is in fact available at the same location on both SOCs. The CPU reset node is then added on both Armada 370 and Armada XP, with a different compatible string. On Armada 370, the CPU reset driver is not really needed as Armada 370 is single core and the only use of the CPU reset driver is to boot secondary processors, but it still makes sense to have this CPU reset register described in the Device Tree. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397483433-25836-6-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397483433-25836-6-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: enable the coherency fabric on Armada 38xThomas Petazzoni2014-04-241-0/+10
| | | | | | | | | This commit adds the necessary Device Tree information to enable the coherency fabric on Armada 38x. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397483228-25625-11-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: enable the coherency fabric on Armada 375Thomas Petazzoni2014-04-241-0/+10
| | | | | | | | | This commit adds the necessary Device Tree information to enable the coherency fabric on Armada 375. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397483228-25625-10-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: Enable Armada 380/385 watchdog in the devicetreeEzequiel Garcia2014-04-241-0/+7
| | | | | | | | | | Add the DT nodes to enable the watchdog support available on Armada 380/385 SoC. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1397481813-4962-9-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: Enable Armada 375 watchdog in the devicetreeEzequiel Garcia2014-04-241-0/+6
| | | | | | | | | | Add the DT nodes to enable the watchdog support available on Armada 375 SoC. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1397481813-4962-8-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: kirkwood: rename kirwood-nsa310-common to 3x0-commonAdam Baker2014-04-244-3/+3
| | | | | | | | | | | | Rename the include file kirkwood-nsa310-common.dtsi as it is now also used for NSA320. There is also an NSA325 but that appears not to be as similar so is unlikely to want to share an include file. Signed-off-by: Adam Baker <linux@baker-net.org.uk> Link: https://lkml.kernel.org/r/53447978.2020206@baker-net.org.uk Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: kirkwood: Add DTS file for NSA320Adam Baker2014-04-241-0/+214
| | | | | | | | | | | | | | Add a new DTS file to support the Zyxel NSA320 dual bay NAS Drive. This DTS just describes the features that work with the current kernel drivers. New drivers still need writing to support the temperature sensor, the power on behaviour control and the buzzer. Signed-off-by: Adam Baker <linux@baker-net.org.uk> Link: https://lkml.kernel.org/r/1396820569-3841-2-git-send-email-linux@baker-net.org.uk Reviewed-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: kirkwood: Move NSA310 common parts to include fileAdam Baker2014-04-243-104/+54
| | | | | | | | | | | | | | Move definitions that are common to both nsa-310.dts and nsa310a.dts and that will also be used in nsa320 into kirkwood-nsa310-common.dtsi. Also rename the USB Regulator to remove the word off from its name as the state of a regulator shouldn't be part of its name. Signed-off-by: Adam Baker <linux@baker-net.org.uk> Link: https://lkml.kernel.org/r/1396820569-3841-1-git-send-email-linux@baker-net.org.uk Reviewed-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* Merge git://git.infradead.org/users/eparis/auditLinus Torvalds2014-04-122-3/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull audit updates from Eric Paris. * git://git.infradead.org/users/eparis/audit: (28 commits) AUDIT: make audit_is_compat depend on CONFIG_AUDIT_COMPAT_GENERIC audit: renumber AUDIT_FEATURE_CHANGE into the 1300 range audit: do not cast audit_rule_data pointers pointlesly AUDIT: Allow login in non-init namespaces audit: define audit_is_compat in kernel internal header kernel: Use RCU_INIT_POINTER(x, NULL) in audit.c sched: declare pid_alive as inline audit: use uapi/linux/audit.h for AUDIT_ARCH declarations syscall_get_arch: remove useless function arguments audit: remove stray newline from audit_log_execve_info() audit_panic() call audit: remove stray newlines from audit_log_lost messages audit: include subject in login records audit: remove superfluous new- prefix in AUDIT_LOGIN messages audit: allow user processes to log from another PID namespace audit: anchor all pid references in the initial pid namespace audit: convert PPIDs to the inital PID namespace. pid: get pid_t ppid of task in init_pid_ns audit: rename the misleading audit_get_context() to audit_take_context() audit: Add generic compat syscall support audit: Add CONFIG_HAVE_ARCH_AUDITSYSCALL ...
| * audit: use uapi/linux/audit.h for AUDIT_ARCH declarationsEric Paris2014-03-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The syscall.h headers were including linux/audit.h but really only needed the uapi/linux/audit.h to get the requisite defines. Switch to the uapi headers. Signed-off-by: Eric Paris <eparis@redhat.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mips@linux-mips.org Cc: linux-s390@vger.kernel.org Cc: x86@kernel.org
| * syscall_get_arch: remove useless function argumentsEric Paris2014-03-201-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Every caller of syscall_get_arch() uses current for the task and no implementors of the function need args. So just get rid of both of those things. Admittedly, since these are inline functions we aren't wasting stack space, but it just makes the prototypes better. Signed-off-by: Eric Paris <eparis@redhat.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mips@linux-mips.org Cc: linux390@de.ibm.com Cc: x86@kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-s390@vger.kernel.org Cc: linux-arch@vger.kernel.org
| * audit: Add CONFIG_HAVE_ARCH_AUDITSYSCALLAKASHI Takahiro2014-03-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently AUDITSYSCALL has a long list of architecture depencency: depends on AUDIT && (X86 || PARISC || PPC || S390 || IA64 || UML || SPARC64 || SUPERH || (ARM && AEABI && !OABI_COMPAT) || ALPHA) The purpose of this patch is to replace it with HAVE_ARCH_AUDITSYSCALL for simplicity. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> (arm) Acked-by: Richard Guy Briggs <rgb@redhat.com> (audit) Acked-by: Matt Turner <mattst88@gmail.com> (alpha) Acked-by: Michael Ellerman <mpe@ellerman.id.au> (powerpc) Signed-off-by: Eric Paris <eparis@redhat.com>
* | Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-armLinus Torvalds2014-04-1119-614/+685
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull second set of ARM changes from Russell King: "This is the remainder of the ARM changes for this merge window. Included in this request are: - fixes for kprobes for big-endian support - fix tracing in soft_restart - avoid phys address overflow in kdump code - fix reporting of read-only pmd bits in kernel page table dump - remove unnecessary (and possibly buggy) call to outer_flush_all() - fix a three sparse warnings (missing header file for function prototypes) - fix pj4 crashing single zImage (thanks to arm-soc merging changes which enables this with knowledge that the corresponding fix had not even been submitted for my tree before the merge window opened) - vfp macro cleanups - dump register state on undefined instruction userspace faults when debugging" * 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: Dump the registers on undefined instruction userspace faults ARM: 8018/1: Add {inc,dec}_preempt_count asm macros ARM: 8017/1: Move asm macro get_thread_info to asm/assembler.h ARM: 8016/1: Check cpu id in pj4_cp0_init. ARM: 8015/1: Add cpu_is_pj4 to distinguish PJ4 because it has some differences with V7 ARM: add missing system_misc.h include to process.c ARM: 8009/1: dcscb.c: remove call to outer_flush_all() ARM: 8014/1: mm: fix reporting of read-only PMD bits ARM: 8012/1: kdump: Avoid overflow when converting pfn to physaddr ARM: 8010/1: avoid tracers in soft_restart ARM: kprobes-test: Workaround GAS .align bug ARM: kprobes-test: use <asm/opcodes.h> for Thumb instruction building ARM: kprobes-test: use <asm/opcodes.h> for ARM instruction building ARM: kprobes-test: use <asm/opcodes.h> for instruction accesses ARM: probes: fix instruction fetch order with <asm/opcodes.h>
| * \ Merge branch 'devel-stable' into for-nextRussell King2014-04-118-551/+562
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| | * \ Merge tag 'for_russell/arm-be-probes' of ↵Russell King2014-04-018-551/+562
| | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/taras.kondratiuk/linux into devel-stable It is reworked initial Ben's series for big endian support [1]. Dropped patches that are not directly related to probes and rebased series on top of Dave Long's ARM uprobes series. Current set of patches is enough to have functional BE kprobes and uprobes. One ARM kprobe test fails on Cortex-A15 boards (TC2 and Keystone2 EVM), while it passes on Pandaboard. The issue is not related to this series and already present since v3.13-rc7. v1..v2: Rebased series on top of Dave Long's ARM uprobes series. Now this series fixes both BE kprobes and BE uprobes. Tested on Pandaboard ES and TI Keystone2 EVM. pull req v1: http://www.spinics.net/lists/arm-kernel/msg300227.html [1] http://www.spinics.net/lists/arm-kernel/msg285210.html
| | | * | ARM: kprobes-test: Workaround GAS .align bugTaras Kondratiuk2014-04-012-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default if no fill symbol is given to .align directive in a code section it fills gap with NOPs. If previous fragment is not instruction-aligned, additional pre-alignment is done by zero bytes before NOPs. These zero bytes are marked as data by special symbol $d in symbol table. Unfortunately GAS assumes that there is only code in the code section so it "puts back" code symbol $a at the end of this pre-alignment. So if there is some data after alignment it will be interpreted as code and will be swapped back to LE for BE8 system during a final linking. If explicit fill value is given to .align, the NOP-padding code is skipped and symbol table does not get messed-up. So the workaround for this issue: Use explicit fill value if data should be aligned in the code section. Acked-by: Ben Dooks <ben.dooks@codethink.co.uk> Acked-by: Jon Medhurst <tixy@linaro.org> Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
| | | * | ARM: kprobes-test: use <asm/opcodes.h> for Thumb instruction buildingBen Dooks2014-04-011-223/+224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kprobes test will build certain instructions incorrectly if building big endian as .word/.short output gets endian-swapped by the linker. Change to using <asm/opcodes.h> and __inst_thumbXX() to produce instructions. Acked-by: Jon Medhurst <tixy@linaro.org> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
| | | * | ARM: kprobes-test: use <asm/opcodes.h> for ARM instruction buildingBen Dooks2014-04-011-301/+302
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kprobes test will build certain instructions incorrectly if building big endian as .word output gets endian-swapped by the linker. Change to using <asm/opcodes.h> and __inst_arm() to produce instructions. Acked-by: Jon Medhurst <tixy@linaro.org> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> [taras.kondratiuk@linaro.org: fixed unsupported coprocessor instructions] Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
| | | * | ARM: kprobes-test: use <asm/opcodes.h> for instruction accessesBen Dooks2014-04-011-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure we read instructions in the correct endian-ness by using the <asm/opcodes.h> helper to transform them as necessary. Acked-by: Jon Medhurst <tixy@linaro.org> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> [taras.kondratiuk@linaro.org: fix next_instruction() function] Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
| | | * | ARM: probes: fix instruction fetch order with <asm/opcodes.h>Ben Dooks2014-04-014-20/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we are running BE8, the data and instruction endianness do not match, so use <asm/opcodes.h> to correctly translate memory accesses into ARM instructions. Acked-by: Jon Medhurst <tixy@linaro.org> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> [taras.kondratiuk@linaro.org: fixed Thumb instruction fetch order] Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
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| *-. \ \ \ Merge branches 'fixes' and 'misc' into for-nextRussell King2014-04-1111-63/+123
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| | | * | | | Dump the registers on undefined instruction userspace faultsRussell King2014-04-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | ARM: 8018/1: Add {inc,dec}_preempt_count asm macrosCatalin Marinas2014-04-093-29/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch adds asm macros for inc_preempt_count and dec_preempt_count_ti (which also gets the current thread_info) instead of open-coding them in arch/arm/vfp/*.S files. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Arun KS <getarunks@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | ARM: 8017/1: Move asm macro get_thread_info to asm/assembler.hCatalin Marinas2014-04-094-13/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | asm/assembler.h is a better place for this macro since it is used by asm files outside arch/arm/kernel/ Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Arun KS <getarunks@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | ARM: 8016/1: Check cpu id in pj4_cp0_init.Chao Xie Linux2014-04-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check cpu id in pj4_cp0_init. So for no-PJ4 V7 cpus, pj4_cpu0_init just return. This fix will help to make the all the V7 cpus(PJ4 and no-PJ4) can use code. Signed-off-by: Chao Xie <chao.xie@marvell.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Tested-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Matt Porter <mporter@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | ARM: 8015/1: Add cpu_is_pj4 to distinguish PJ4 because it has some ↵Chao Xie Linux2014-04-081-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | differences with V7 The patch add cpu_is_pj4 at arch/arm/include/asm/cputype.h PJ4 has some differences with V7, for example the coprocessor. To disinguish this kind of situation. cpu_is_pj4 is needed. Signed-off-by: Chao Xie <chao.xie@marvell.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Tested-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Matt Porter <mporter@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | ARM: add missing system_misc.h include to process.cRussell King2014-04-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arm_pm_restart(), arm_pm_idle() and soft_restart() are all declared in system_misc.h, but this file is not included in process.c. Add this missing include. Found via sparse: arch/arm/kernel/process.c:98:6: warning: symbol 'soft_restart' was not declared. Should it be static? arch/arm/kernel/process.c:127:6: warning: symbol 'arm_pm_restart' was not declared. Should it be static? arch/arm/kernel/process.c:134:6: warning: symbol 'arm_pm_idle' was not declared. Should it be static? Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | ARM: 8009/1: dcscb.c: remove call to outer_flush_all()Nicolas Pitre2014-04-071-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Strictly speaking this call is a no-op on the platform where dcscb.c is used since it only has architected caches. The call was there as a hint to people inspired by this code when writing their own backend, but the hint might not always be correct. For example, if a PL310 were to be used it wouldn't be safe to call the regular outer_flush_all() as atomic instructions for locking are involved in that case and those instructions cannot be assumed to still be operational after v7_exit_coherency_flush() has returned. Given no other CPUs (in the cluster) should be running at that point then standard concurrency concerns wouldn't apply. So let's simply kill this call for now and enhance the existing comment. Signed-off-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | ARM: 8014/1: mm: fix reporting of read-only PMD bitsKees Cook2014-04-071-15/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On non-LPAE ARMv6+, read-only PMD bits are defined with the combination "PMD_SECT_APX | PMD_SECT_AP_WRITE". Adjusted the bit masks to correctly report this. Signed-off-by: Kees Cook <keescook@chromium.org> Tested-by: Laura Abbott <lauraa@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | | | ARM: 8012/1: kdump: Avoid overflow when converting pfn to physaddrLiu Hua2014-04-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we configure CONFIG_ARM_LPAE=y, pfn << PAGE_SHIFT will overflow if pfn >= 0x100000 in copy_oldmem_page. So use __pfn_to_phys for converting. Signed-off-by: Liu Hua <sdu.liu@huawei.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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