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-rw-r--r--sound/soc/codecs/Kconfig10
-rw-r--r--sound/soc/codecs/Makefile2
-rw-r--r--sound/soc/codecs/cs35l41-lib.c10
-rw-r--r--sound/soc/codecs/cs47l15.c5
-rw-r--r--sound/soc/codecs/madera.c14
-rw-r--r--sound/soc/codecs/max98396.c279
-rw-r--r--sound/soc/codecs/max98396.h10
-rw-r--r--sound/soc/codecs/sgtl5000.c9
-rw-r--r--sound/soc/codecs/sgtl5000.h1
-rw-r--r--sound/soc/codecs/tas2552.c2
-rw-r--r--sound/soc/codecs/wcd-mbhc-v2.c10
-rw-r--r--sound/soc/codecs/wsa881x.c6
-rw-r--r--sound/soc/codecs/wsa883x.c1301
13 files changed, 1591 insertions, 68 deletions
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 5a60633a196c..ee7e028e8402 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -308,6 +308,7 @@ config SND_SOC_ALL_CODECS
imply SND_SOC_WM9712
imply SND_SOC_WM9713
imply SND_SOC_WSA881X
+ imply SND_SOC_WSA883X
imply SND_SOC_ZL38060
help
Normally ASoC codec drivers are only built if a machine driver which
@@ -1985,6 +1986,15 @@ config SND_SOC_WSA881X
This enables support for Qualcomm WSA8810/WSA8815 Class-D
Smart Speaker Amplifier.
+config SND_SOC_WSA883X
+ tristate "WSA883X Codec"
+ depends on SOUNDWIRE
+ select REGMAP_SOUNDWIRE
+ tristate
+ help
+ This enables support for Qualcomm WSA8830/WSA8835 Class-D
+ Smart Speaker Amplifier.
+
config SND_SOC_ZL38060
tristate "Microsemi ZL38060 Connected Home Audio Processor"
depends on SPI_MASTER
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index d32026ae326f..60354579fe5c 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -338,6 +338,7 @@ snd-soc-wm9712-objs := wm9712.o
snd-soc-wm9713-objs := wm9713.o
snd-soc-wm-hubs-objs := wm_hubs.o
snd-soc-wsa881x-objs := wsa881x.o
+snd-soc-wsa883x-objs := wsa883x.o
snd-soc-zl38060-objs := zl38060.o
# Amp
snd-soc-max9877-objs := max9877.o
@@ -690,6 +691,7 @@ obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o
obj-$(CONFIG_SND_SOC_WM_ADSP) += snd-soc-wm-adsp.o
obj-$(CONFIG_SND_SOC_WM_HUBS) += snd-soc-wm-hubs.o
obj-$(CONFIG_SND_SOC_WSA881X) += snd-soc-wsa881x.o
+obj-$(CONFIG_SND_SOC_WSA883X) += snd-soc-wsa883x.o
obj-$(CONFIG_SND_SOC_ZL38060) += snd-soc-zl38060.o
# Amp
diff --git a/sound/soc/codecs/cs35l41-lib.c b/sound/soc/codecs/cs35l41-lib.c
index 0c7d1c791279..04be71435491 100644
--- a/sound/soc/codecs/cs35l41-lib.c
+++ b/sound/soc/codecs/cs35l41-lib.c
@@ -37,8 +37,8 @@ static const struct reg_default cs35l41_reg[] = {
{ CS35L41_DAC_PCM1_SRC, 0x00000008 },
{ CS35L41_ASP_TX1_SRC, 0x00000018 },
{ CS35L41_ASP_TX2_SRC, 0x00000019 },
- { CS35L41_ASP_TX3_SRC, 0x00000020 },
- { CS35L41_ASP_TX4_SRC, 0x00000021 },
+ { CS35L41_ASP_TX3_SRC, 0x00000000 },
+ { CS35L41_ASP_TX4_SRC, 0x00000000 },
{ CS35L41_DSP1_RX1_SRC, 0x00000008 },
{ CS35L41_DSP1_RX2_SRC, 0x00000009 },
{ CS35L41_DSP1_RX3_SRC, 0x00000018 },
@@ -644,6 +644,8 @@ static const struct reg_sequence cs35l41_reva0_errata_patch[] = {
{ CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
{ CS35L41_PWR_CTRL2, 0x00000000 },
{ CS35L41_AMP_GAIN_CTRL, 0x00000000 },
+ { CS35L41_ASP_TX3_SRC, 0x00000000 },
+ { CS35L41_ASP_TX4_SRC, 0x00000000 },
};
static const struct reg_sequence cs35l41_revb0_errata_patch[] = {
@@ -655,6 +657,8 @@ static const struct reg_sequence cs35l41_revb0_errata_patch[] = {
{ CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
{ CS35L41_PWR_CTRL2, 0x00000000 },
{ CS35L41_AMP_GAIN_CTRL, 0x00000000 },
+ { CS35L41_ASP_TX3_SRC, 0x00000000 },
+ { CS35L41_ASP_TX4_SRC, 0x00000000 },
};
static const struct reg_sequence cs35l41_revb2_errata_patch[] = {
@@ -666,6 +670,8 @@ static const struct reg_sequence cs35l41_revb2_errata_patch[] = {
{ CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
{ CS35L41_PWR_CTRL2, 0x00000000 },
{ CS35L41_AMP_GAIN_CTRL, 0x00000000 },
+ { CS35L41_ASP_TX3_SRC, 0x00000000 },
+ { CS35L41_ASP_TX4_SRC, 0x00000000 },
};
static const struct reg_sequence cs35l41_fs_errata_patch[] = {
diff --git a/sound/soc/codecs/cs47l15.c b/sound/soc/codecs/cs47l15.c
index 0193173b8637..06c4214382e3 100644
--- a/sound/soc/codecs/cs47l15.c
+++ b/sound/soc/codecs/cs47l15.c
@@ -122,6 +122,9 @@ static int cs47l15_in1_adc_put(struct snd_kcontrol *kcontrol,
snd_soc_kcontrol_component(kcontrol);
struct cs47l15 *cs47l15 = snd_soc_component_get_drvdata(component);
+ if (!!ucontrol->value.integer.value[0] == cs47l15->in1_lp_mode)
+ return 0;
+
switch (ucontrol->value.integer.value[0]) {
case 0:
/* Set IN1 to normal mode */
@@ -150,7 +153,7 @@ static int cs47l15_in1_adc_put(struct snd_kcontrol *kcontrol,
break;
}
- return 0;
+ return 1;
}
static const struct snd_kcontrol_new cs47l15_snd_controls[] = {
diff --git a/sound/soc/codecs/madera.c b/sound/soc/codecs/madera.c
index 272041c6236a..b9f19fbd2911 100644
--- a/sound/soc/codecs/madera.c
+++ b/sound/soc/codecs/madera.c
@@ -618,7 +618,13 @@ int madera_out1_demux_put(struct snd_kcontrol *kcontrol,
end:
snd_soc_dapm_mutex_unlock(dapm);
- return snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL);
+ ret = snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL);
+ if (ret < 0) {
+ dev_err(madera->dev, "Failed to update demux power state: %d\n", ret);
+ return ret;
+ }
+
+ return change;
}
EXPORT_SYMBOL_GPL(madera_out1_demux_put);
@@ -893,7 +899,7 @@ static int madera_adsp_rate_put(struct snd_kcontrol *kcontrol,
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
const int adsp_num = e->shift_l;
const unsigned int item = ucontrol->value.enumerated.item[0];
- int ret;
+ int ret = 0;
if (item >= e->items)
return -EINVAL;
@@ -910,10 +916,10 @@ static int madera_adsp_rate_put(struct snd_kcontrol *kcontrol,
"Cannot change '%s' while in use by active audio paths\n",
kcontrol->id.name);
ret = -EBUSY;
- } else {
+ } else if (priv->adsp_rate_cache[adsp_num] != e->values[item]) {
/* Volatile register so defer until the codec is powered up */
priv->adsp_rate_cache[adsp_num] = e->values[item];
- ret = 0;
+ ret = 1;
}
mutex_unlock(&priv->rate_lock);
diff --git a/sound/soc/codecs/max98396.c b/sound/soc/codecs/max98396.c
index 225effede9d2..364b4b7ee033 100644
--- a/sound/soc/codecs/max98396.c
+++ b/sound/soc/codecs/max98396.c
@@ -5,11 +5,18 @@
#include <linux/i2c.h>
#include <linux/module.h>
#include <sound/pcm_params.h>
+#include <linux/regulator/consumer.h>
#include <sound/soc.h>
#include <linux/gpio.h>
#include <sound/tlv.h>
#include "max98396.h"
+static const char * const max98396_core_supplies[MAX98396_NUM_CORE_SUPPLIES] = {
+ "avdd",
+ "dvdd",
+ "dvddio",
+};
+
static struct reg_default max98396_reg[] = {
{MAX98396_R2000_SW_RESET, 0x00},
{MAX98396_R2001_INT_RAW1, 0x00},
@@ -342,12 +349,15 @@ static int max98396_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component);
- unsigned int format = 0;
+ unsigned int format_mask, format = 0;
unsigned int bclk_pol = 0;
int ret, status;
int reg;
bool update = false;
+ format_mask = MAX98396_PCM_MODE_CFG_FORMAT_MASK |
+ MAX98396_PCM_MODE_CFG_LRCLKEDGE;
+
dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
@@ -365,7 +375,8 @@ static int max98396_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
break;
default:
- dev_err(component->dev, "DAI invert mode unsupported\n");
+ dev_err(component->dev, "DAI invert mode %d unsupported\n",
+ fmt & SND_SOC_DAIFMT_INV_MASK);
return -EINVAL;
}
@@ -384,6 +395,8 @@ static int max98396_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
format |= MAX98396_PCM_FORMAT_TDM_MODE0;
break;
default:
+ dev_err(component->dev, "DAI format %d unsupported\n",
+ fmt & SND_SOC_DAIFMT_FORMAT_MASK);
return -EINVAL;
}
@@ -395,7 +408,7 @@ static int max98396_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
ret = regmap_read(max98396->regmap, MAX98396_R2041_PCM_MODE_CFG, &reg);
if (ret < 0)
return -EINVAL;
- if (format != (reg & MAX98396_PCM_BCLKEDGE_BSEL_MASK)) {
+ if (format != (reg & format_mask)) {
update = true;
} else {
ret = regmap_read(max98396->regmap,
@@ -412,8 +425,7 @@ static int max98396_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
regmap_update_bits(max98396->regmap,
MAX98396_R2041_PCM_MODE_CFG,
- MAX98396_PCM_BCLKEDGE_BSEL_MASK,
- format);
+ format_mask, format);
regmap_update_bits(max98396->regmap,
MAX98396_R2042_PCM_CLK_SETUP,
@@ -426,46 +438,68 @@ static int max98396_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
return 0;
}
-/* BCLKs per LRCLK */
-static const int bclk_sel_table[] = {
- 32, 48, 64, 96, 128, 192, 256, 384, 512, 320,
+#define MAX98396_BSEL_32 0x2
+#define MAX98396_BSEL_48 0x3
+#define MAX98396_BSEL_64 0x4
+#define MAX98396_BSEL_96 0x5
+#define MAX98396_BSEL_128 0x6
+#define MAX98396_BSEL_192 0x7
+#define MAX98396_BSEL_256 0x8
+#define MAX98396_BSEL_384 0x9
+#define MAX98396_BSEL_512 0xa
+#define MAX98396_BSEL_320 0xb
+#define MAX98396_BSEL_250 0xc
+#define MAX98396_BSEL_125 0xd
+
+/* Refer to table 5 in the datasheet */
+static const struct max98396_pcm_config {
+ int in, out, width, bsel, max_sr;
+} max98396_pcm_configs[] = {
+ { .in = 2, .out = 4, .width = 16, .bsel = MAX98396_BSEL_32, .max_sr = 192000 },
+ { .in = 2, .out = 6, .width = 24, .bsel = MAX98396_BSEL_48, .max_sr = 192000 },
+ { .in = 2, .out = 8, .width = 32, .bsel = MAX98396_BSEL_64, .max_sr = 192000 },
+ { .in = 3, .out = 15, .width = 32, .bsel = MAX98396_BSEL_125, .max_sr = 192000 },
+ { .in = 4, .out = 8, .width = 16, .bsel = MAX98396_BSEL_64, .max_sr = 192000 },
+ { .in = 4, .out = 12, .width = 24, .bsel = MAX98396_BSEL_96, .max_sr = 192000 },
+ { .in = 4, .out = 16, .width = 32, .bsel = MAX98396_BSEL_128, .max_sr = 192000 },
+ { .in = 5, .out = 15, .width = 24, .bsel = MAX98396_BSEL_125, .max_sr = 192000 },
+ { .in = 7, .out = 15, .width = 16, .bsel = MAX98396_BSEL_125, .max_sr = 192000 },
+ { .in = 2, .out = 4, .width = 16, .bsel = MAX98396_BSEL_32, .max_sr = 96000 },
+ { .in = 2, .out = 6, .width = 24, .bsel = MAX98396_BSEL_48, .max_sr = 96000 },
+ { .in = 2, .out = 8, .width = 32, .bsel = MAX98396_BSEL_64, .max_sr = 96000 },
+ { .in = 3, .out = 15, .width = 32, .bsel = MAX98396_BSEL_125, .max_sr = 96000 },
+ { .in = 4, .out = 8, .width = 16, .bsel = MAX98396_BSEL_64, .max_sr = 96000 },
+ { .in = 4, .out = 12, .width = 24, .bsel = MAX98396_BSEL_96, .max_sr = 96000 },
+ { .in = 4, .out = 16, .width = 32, .bsel = MAX98396_BSEL_128, .max_sr = 96000 },
+ { .in = 5, .out = 15, .width = 24, .bsel = MAX98396_BSEL_125, .max_sr = 96000 },
+ { .in = 7, .out = 15, .width = 16, .bsel = MAX98396_BSEL_125, .max_sr = 96000 },
+ { .in = 7, .out = 31, .width = 32, .bsel = MAX98396_BSEL_250, .max_sr = 96000 },
+ { .in = 8, .out = 16, .width = 16, .bsel = MAX98396_BSEL_128, .max_sr = 96000 },
+ { .in = 8, .out = 24, .width = 24, .bsel = MAX98396_BSEL_192, .max_sr = 96000 },
+ { .in = 8, .out = 32, .width = 32, .bsel = MAX98396_BSEL_256, .max_sr = 96000 },
+ { .in = 10, .out = 31, .width = 24, .bsel = MAX98396_BSEL_250, .max_sr = 96000 },
+ { .in = 15, .out = 31, .width = 16, .bsel = MAX98396_BSEL_250, .max_sr = 96000 },
+ { .in = 16, .out = 32, .width = 16, .bsel = MAX98396_BSEL_256, .max_sr = 96000 },
+ { .in = 7, .out = 31, .width = 32, .bsel = MAX98396_BSEL_250, .max_sr = 48000 },
+ { .in = 10, .out = 31, .width = 24, .bsel = MAX98396_BSEL_250, .max_sr = 48000 },
+ { .in = 10, .out = 40, .width = 32, .bsel = MAX98396_BSEL_320, .max_sr = 48000 },
+ { .in = 15, .out = 31, .width = 16, .bsel = MAX98396_BSEL_250, .max_sr = 48000 },
+ { .in = 16, .out = 48, .width = 24, .bsel = MAX98396_BSEL_384, .max_sr = 48000 },
+ { .in = 16, .out = 64, .width = 32, .bsel = MAX98396_BSEL_512, .max_sr = 48000 },
};
-static int max98396_get_bclk_sel(int bclk)
+static int max98396_pcm_config_index(int in_slots, int out_slots, int width)
{
int i;
- /* match BCLKs per LRCLK */
- for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
- if (bclk_sel_table[i] == bclk)
- return i + 2;
- }
- return 0;
-}
-static int max98396_set_clock(struct snd_soc_component *component,
- struct snd_pcm_hw_params *params)
-{
- struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component);
- /* BCLK/LRCLK ratio calculation */
- int blr_clk_ratio = params_channels(params) * max98396->ch_size;
- int value;
-
- if (!max98396->tdm_mode) {
- /* BCLK configuration */
- value = max98396_get_bclk_sel(blr_clk_ratio);
- if (!value) {
- dev_err(component->dev, "format unsupported %d\n",
- params_format(params));
- return -EINVAL;
- }
+ for (i = 0; i < ARRAY_SIZE(max98396_pcm_configs); i++) {
+ const struct max98396_pcm_config *c = &max98396_pcm_configs[i];
- regmap_update_bits(max98396->regmap,
- MAX98396_R2042_PCM_CLK_SETUP,
- MAX98396_PCM_CLK_SETUP_BSEL_MASK,
- value);
+ if (in_slots == c->in && out_slots <= c->out && width == c->width)
+ return i;
}
- return 0;
+ return -1;
}
static int max98396_dai_hw_params(struct snd_pcm_substream *substream,
@@ -476,8 +510,7 @@ static int max98396_dai_hw_params(struct snd_pcm_substream *substream,
struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component);
unsigned int sampling_rate = 0;
unsigned int chan_sz = 0;
- int ret, reg;
- int status;
+ int ret, reg, status, bsel = 0;
bool update = false;
/* pcm mode configuration */
@@ -497,8 +530,6 @@ static int max98396_dai_hw_params(struct snd_pcm_substream *substream,
goto err;
}
- max98396->ch_size = snd_pcm_format_width(params_format(params));
-
dev_dbg(component->dev, "format supported %d",
params_format(params));
@@ -546,6 +577,33 @@ static int max98396_dai_hw_params(struct snd_pcm_substream *substream,
goto err;
}
+ if (max98396->tdm_mode) {
+ if (params_rate(params) > max98396->tdm_max_samplerate) {
+ dev_err(component->dev, "TDM sample rate %d too high",
+ params_rate(params));
+ goto err;
+ }
+ } else {
+ /* BCLK configuration */
+ ret = max98396_pcm_config_index(params_channels(params),
+ params_channels(params),
+ snd_pcm_format_width(params_format(params)));
+ if (ret < 0) {
+ dev_err(component->dev,
+ "no PCM config for %d channels, format %d\n",
+ params_channels(params), params_format(params));
+ goto err;
+ }
+
+ bsel = max98396_pcm_configs[ret].bsel;
+
+ if (params_rate(params) > max98396_pcm_configs[ret].max_sr) {
+ dev_err(component->dev, "sample rate %d too high",
+ params_rate(params));
+ goto err;
+ }
+ }
+
ret = regmap_read(max98396->regmap, MAX98396_R210F_GLOBAL_EN, &status);
if (ret < 0)
goto err;
@@ -591,12 +649,16 @@ static int max98396_dai_hw_params(struct snd_pcm_substream *substream,
MAX98396_IVADC_SR_MASK,
sampling_rate << MAX98396_IVADC_SR_SHIFT);
- ret = max98396_set_clock(component, params);
+ if (bsel)
+ regmap_update_bits(max98396->regmap,
+ MAX98396_R2042_PCM_CLK_SETUP,
+ MAX98396_PCM_CLK_SETUP_BSEL_MASK,
+ bsel);
if (status && update)
max98396_global_enable_onoff(max98396->regmap, true);
- return ret;
+ return 0;
err:
return -EINVAL;
@@ -621,13 +683,16 @@ static int max98396_dai_tdm_slot(struct snd_soc_dai *dai,
max98396->tdm_mode = true;
/* BCLK configuration */
- bsel = max98396_get_bclk_sel(slots * slot_width);
- if (bsel == 0) {
- dev_err(component->dev, "BCLK %d not supported\n",
- slots * slot_width);
+ ret = max98396_pcm_config_index(slots, slots, slot_width);
+ if (ret < 0) {
+ dev_err(component->dev, "no TDM config for %d slots %d bits\n",
+ slots, slot_width);
return -EINVAL;
}
+ bsel = max98396_pcm_configs[ret].bsel;
+ max98396->tdm_max_samplerate = max98396_pcm_configs[ret].max_sr;
+
/* Channel size configuration */
switch (slot_width) {
case 16:
@@ -640,7 +705,7 @@ static int max98396_dai_tdm_slot(struct snd_soc_dai *dai,
chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_32;
break;
default:
- dev_err(component->dev, "format unsupported %d\n",
+ dev_err(component->dev, "slot width %d unsupported\n",
slot_width);
return -EINVAL;
}
@@ -1329,6 +1394,12 @@ static int max98396_probe(struct snd_soc_component *component)
regmap_write(max98396->regmap,
MAX98397_R2057_PCM_RX_SRC2, 0x10);
}
+ /* Supply control */
+ regmap_update_bits(max98396->regmap,
+ MAX98396_R20A0_AMP_SUPPLY_CTL,
+ MAX98396_AMP_SUPPLY_NOVBAT,
+ (max98396->vbat == NULL) ?
+ MAX98396_AMP_SUPPLY_NOVBAT : 0);
/* Enable DC blocker */
regmap_update_bits(max98396->regmap,
MAX98396_R2092_AMP_DSP_CFG, 1, 1);
@@ -1358,6 +1429,9 @@ static int max98396_probe(struct snd_soc_component *component)
regmap_write(max98396->regmap,
MAX98396_R2045_PCM_TX_CTRL_2,
max98396->i_slot);
+ regmap_write(max98396->regmap,
+ MAX98396_R204A_PCM_TX_CTRL_7,
+ max98396->spkfb_slot);
if (max98396->v_slot < 8)
if (max98396->device_id == CODEC_TYPE_MAX98396)
@@ -1424,12 +1498,38 @@ static int max98396_suspend(struct device *dev)
regcache_cache_only(max98396->regmap, true);
regcache_mark_dirty(max98396->regmap);
+ regulator_bulk_disable(MAX98396_NUM_CORE_SUPPLIES,
+ max98396->core_supplies);
+ if (max98396->pvdd)
+ regulator_disable(max98396->pvdd);
+
+ if (max98396->vbat)
+ regulator_disable(max98396->vbat);
+
return 0;
}
static int max98396_resume(struct device *dev)
{
struct max98396_priv *max98396 = dev_get_drvdata(dev);
+ int ret;
+
+ ret = regulator_bulk_enable(MAX98396_NUM_CORE_SUPPLIES,
+ max98396->core_supplies);
+ if (ret < 0)
+ return ret;
+
+ if (max98396->pvdd) {
+ ret = regulator_enable(max98396->pvdd);
+ if (ret < 0)
+ return ret;
+ }
+
+ if (max98396->vbat) {
+ ret = regulator_enable(max98396->vbat);
+ if (ret < 0)
+ return ret;
+ }
regcache_cache_only(max98396->regmap, false);
max98396_reset(max98396, dev);
@@ -1505,17 +1605,35 @@ static void max98396_read_device_property(struct device *dev,
else
max98396->i_slot = 1;
+ if (!device_property_read_u32(dev, "adi,spkfb-slot-no", &value))
+ max98396->spkfb_slot = value & 0xF;
+ else
+ max98396->spkfb_slot = 2;
+
if (!device_property_read_u32(dev, "adi,bypass-slot-no", &value))
max98396->bypass_slot = value & 0xF;
else
max98396->bypass_slot = 0;
}
+static void max98396_core_supplies_disable(void *priv)
+{
+ struct max98396_priv *max98396 = priv;
+
+ regulator_bulk_disable(MAX98396_NUM_CORE_SUPPLIES,
+ max98396->core_supplies);
+}
+
+static void max98396_supply_disable(void *r)
+{
+ regulator_disable((struct regulator *) r);
+}
+
static int max98396_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct max98396_priv *max98396 = NULL;
- int ret, reg;
+ int i, ret, reg;
max98396 = devm_kzalloc(&i2c->dev, sizeof(*max98396), GFP_KERNEL);
@@ -1541,6 +1659,69 @@ static int max98396_i2c_probe(struct i2c_client *i2c,
return ret;
}
+ /* Obtain regulator supplies */
+ for (i = 0; i < MAX98396_NUM_CORE_SUPPLIES; i++)
+ max98396->core_supplies[i].supply = max98396_core_supplies[i];
+
+ ret = devm_regulator_bulk_get(&i2c->dev, MAX98396_NUM_CORE_SUPPLIES,
+ max98396->core_supplies);
+ if (ret < 0) {
+ dev_err(&i2c->dev, "Failed to request core supplies: %d\n", ret);
+ return ret;
+ }
+
+ max98396->vbat = devm_regulator_get_optional(&i2c->dev, "vbat");
+ if (IS_ERR(max98396->vbat)) {
+ if (PTR_ERR(max98396->vbat) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ max98396->vbat = NULL;
+ }
+
+ max98396->pvdd = devm_regulator_get_optional(&i2c->dev, "pvdd");
+ if (IS_ERR(max98396->pvdd)) {
+ if (PTR_ERR(max98396->pvdd) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ max98396->pvdd = NULL;
+ }
+
+ ret = regulator_bulk_enable(MAX98396_NUM_CORE_SUPPLIES,
+ max98396->core_supplies);
+ if (ret < 0) {
+ dev_err(&i2c->dev, "Unable to enable core supplies: %d", ret);
+ return ret;
+ }
+
+ ret = devm_add_action_or_reset(&i2c->dev, max98396_core_supplies_disable,
+ max98396);
+ if (ret < 0)
+ return ret;
+
+ if (max98396->pvdd) {
+ ret = regulator_enable(max98396->pvdd);
+ if (ret < 0)
+ return ret;
+
+ ret = devm_add_action_or_reset(&i2c->dev,
+ max98396_supply_disable,
+ max98396->pvdd);
+ if (ret < 0)
+ return ret;
+ }
+
+ if (max98396->vbat) {
+ ret = regulator_enable(max98396->vbat);
+ if (ret < 0)
+ return ret;
+
+ ret = devm_add_action_or_reset(&i2c->dev,
+ max98396_supply_disable,
+ max98396->vbat);
+ if (ret < 0)
+ return ret;
+ }
+
/* update interleave mode info */
if (device_property_read_bool(&i2c->dev, "adi,interleave_mode"))
max98396->interleave_mode = true;
diff --git a/sound/soc/codecs/max98396.h b/sound/soc/codecs/max98396.h
index 694411038597..7278c779989a 100644
--- a/sound/soc/codecs/max98396.h
+++ b/sound/soc/codecs/max98396.h
@@ -274,6 +274,9 @@
#define MAX98396_DSP_SPK_SAFE_EN_SHIFT (5)
#define MAX98396_DSP_SPK_WB_FLT_EN_SHIFT (6)
+/* MAX98396_R20A0_AMP_SUPPLY_CTL */
+#define MAX98396_AMP_SUPPLY_NOVBAT (0x1 << 0)
+
/* MAX98396_R20E0_IV_SENSE_PATH_CFG */
#define MAX98396_IV_SENSE_DCBLK_EN_MASK (0x3 << 0)
#define MAX98396_IV_SENSE_DCBLK_EN_SHIFT (0)
@@ -291,15 +294,20 @@ enum {
CODEC_TYPE_MAX98397,
};
+#define MAX98396_NUM_CORE_SUPPLIES 3
+
struct max98396_priv {
struct regmap *regmap;
struct gpio_desc *reset_gpio;
+ struct regulator_bulk_data core_supplies[MAX98396_NUM_CORE_SUPPLIES];
+ struct regulator *pvdd, *vbat;
unsigned int v_slot;
unsigned int i_slot;
+ unsigned int spkfb_slot;
unsigned int bypass_slot;
bool interleave_mode;
- unsigned int ch_size;
bool tdm_mode;
+ int tdm_max_samplerate;
int device_id;
};
#endif
diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
index 0b8a377ba145..3fafd9fc5cfd 100644
--- a/sound/soc/codecs/sgtl5000.c
+++ b/sound/soc/codecs/sgtl5000.c
@@ -1794,6 +1794,9 @@ static int sgtl5000_i2c_remove(struct i2c_client *client)
{
struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
+ regmap_write(sgtl5000->regmap, SGTL5000_CHIP_DIG_POWER, SGTL5000_DIG_POWER_DEFAULT);
+ regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, SGTL5000_ANA_POWER_DEFAULT);
+
clk_disable_unprepare(sgtl5000->mclk);
regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
@@ -1801,6 +1804,11 @@ static int sgtl5000_i2c_remove(struct i2c_client *client)
return 0;
}
+static void sgtl5000_i2c_shutdown(struct i2c_client *client)
+{
+ sgtl5000_i2c_remove(client);
+}
+
static const struct i2c_device_id sgtl5000_id[] = {
{"sgtl5000", 0},
{},
@@ -1821,6 +1829,7 @@ static struct i2c_driver sgtl5000_i2c_driver = {
},
.probe_new = sgtl5000_i2c_probe,
.remove = sgtl5000_i2c_remove,
+ .shutdown = sgtl5000_i2c_shutdown,
.id_table = sgtl5000_id,
};
diff --git a/sound/soc/codecs/sgtl5000.h b/sound/soc/codecs/sgtl5000.h
index 56ec5863f250..3a808c762299 100644
--- a/sound/soc/codecs/sgtl5000.h
+++ b/sound/soc/codecs/sgtl5000.h
@@ -80,6 +80,7 @@
/*
* SGTL5000_CHIP_DIG_POWER
*/
+#define SGTL5000_DIG_POWER_DEFAULT 0x0000
#define SGTL5000_ADC_EN 0x0040
#define SGTL5000_DAC_EN 0x0020
#define SGTL5000_DAP_POWERUP 0x0010
diff --git a/sound/soc/codecs/tas2552.c b/sound/soc/codecs/tas2552.c
index bf3d8539a268..8bd667da8767 100644
--- a/sound/soc/codecs/tas2552.c
+++ b/sound/soc/codecs/tas2552.c
@@ -581,7 +581,7 @@ static int tas2552_component_probe(struct snd_soc_component *component)
gpiod_set_value(tas2552->enable_gpio, 1);
- ret = pm_runtime_get_sync(component->dev);
+ ret = pm_runtime_resume_and_get(component->dev);
if (ret < 0) {
dev_err(component->dev, "Enabling device failed: %d\n",
ret);
diff --git a/sound/soc/codecs/wcd-mbhc-v2.c b/sound/soc/codecs/wcd-mbhc-v2.c
index 31009283e7d4..98baef594bf3 100644
--- a/sound/soc/codecs/wcd-mbhc-v2.c
+++ b/sound/soc/codecs/wcd-mbhc-v2.c
@@ -714,12 +714,11 @@ static int wcd_mbhc_initialise(struct wcd_mbhc *mbhc)
struct snd_soc_component *component = mbhc->component;
int ret;
- ret = pm_runtime_get_sync(component->dev);
+ ret = pm_runtime_resume_and_get(component->dev);
if (ret < 0 && ret != -EACCES) {
dev_err_ratelimited(component->dev,
- "pm_runtime_get_sync failed in %s, ret %d\n",
+ "pm_runtime_resume_and_get failed in %s, ret %d\n",
__func__, ret);
- pm_runtime_put_noidle(component->dev);
return ret;
}
@@ -1097,12 +1096,11 @@ static void wcd_correct_swch_plug(struct work_struct *work)
mbhc = container_of(work, struct wcd_mbhc, correct_plug_swch);
component = mbhc->component;
- ret = pm_runtime_get_sync(component->dev);
+ ret = pm_runtime_resume_and_get(component->dev);
if (ret < 0 && ret != -EACCES) {
dev_err_ratelimited(component->dev,
- "pm_runtime_get_sync failed in %s, ret %d\n",
+ "pm_runtime_resume_and_get failed in %s, ret %d\n",
__func__, ret);
- pm_runtime_put_noidle(component->dev);
return;
}
micbias_mv = wcd_mbhc_get_micbias(mbhc);
diff --git a/sound/soc/codecs/wsa881x.c b/sound/soc/codecs/wsa881x.c
index f3a56f3ce487..dc954b85a988 100644
--- a/sound/soc/codecs/wsa881x.c
+++ b/sound/soc/codecs/wsa881x.c
@@ -749,11 +749,9 @@ static int wsa881x_put_pa_gain(struct snd_kcontrol *kc,
unsigned int mask = (1 << fls(max)) - 1;
int val, ret, min_gain, max_gain;
- ret = pm_runtime_get_sync(comp->dev);
- if (ret < 0 && ret != -EACCES) {
- pm_runtime_put_noidle(comp->dev);
+ ret = pm_runtime_resume_and_get(comp->dev);
+ if (ret < 0 && ret != -EACCES)
return ret;
- }
max_gain = (max - ucontrol->value.integer.value[0]) & mask;
/*
diff --git a/sound/soc/codecs/wsa883x.c b/sound/soc/codecs/wsa883x.c
new file mode 100644
index 000000000000..856709ec017e
--- /dev/null
+++ b/sound/soc/codecs/wsa883x.c
@@ -0,0 +1,1301 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/bitops.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/printk.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+#include <linux/soundwire/sdw.h>
+#include <linux/soundwire/sdw_registers.h>
+#include <linux/soundwire/sdw_type.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc-dapm.h>
+#include <sound/soc.h>
+#include <sound/tlv.h>
+
+#define WSA883X_BASE 0x3000
+#define WSA883X_ANA_BG_TSADC_BASE (WSA883X_BASE + 0x00000001)
+#define WSA883X_REF_CTRL (WSA883X_ANA_BG_TSADC_BASE + 0x0000)
+#define WSA883X_TEST_CTL_0 (WSA883X_ANA_BG_TSADC_BASE + 0x0001)
+#define WSA883X_BIAS_0 (WSA883X_ANA_BG_TSADC_BASE + 0x0002)
+#define WSA883X_OP_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0003)
+#define WSA883X_IREF_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0004)
+#define WSA883X_ISENS_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0005)
+#define WSA883X_CLK_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0006)
+#define WSA883X_TEST_CTL_1 (WSA883X_ANA_BG_TSADC_BASE + 0x0007)
+#define WSA883X_BIAS_1 (WSA883X_ANA_BG_TSADC_BASE + 0x0008)
+#define WSA883X_ADC_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0009)
+#define WSA883X_DOUT_MSB (WSA883X_ANA_BG_TSADC_BASE + 0x000A)
+#define WSA883X_DOUT_LSB (WSA883X_ANA_BG_TSADC_BASE + 0x000B)
+#define WSA883X_VBAT_SNS (WSA883X_ANA_BG_TSADC_BASE + 0x000C)
+#define WSA883X_ITRIM_CODE (WSA883X_ANA_BG_TSADC_BASE + 0x000D)
+
+#define WSA883X_ANA_IVSENSE_BASE (WSA883X_BASE + 0x0000000F)
+#define WSA883X_EN (WSA883X_ANA_IVSENSE_BASE + 0x0000)
+#define WSA883X_OVERRIDE1 (WSA883X_ANA_IVSENSE_BASE + 0x0001)
+#define WSA883X_OVERRIDE2 (WSA883X_ANA_IVSENSE_BASE + 0x0002)
+#define WSA883X_VSENSE1 (WSA883X_ANA_IVSENSE_BASE + 0x0003)
+#define WSA883X_ISENSE1 (WSA883X_ANA_IVSENSE_BASE + 0x0004)
+#define WSA883X_ISENSE2 (WSA883X_ANA_IVSENSE_BASE + 0x0005)
+#define WSA883X_ISENSE_CAL (WSA883X_ANA_IVSENSE_BASE + 0x0006)
+#define WSA883X_MISC (WSA883X_ANA_IVSENSE_BASE + 0x0007)
+#define WSA883X_ADC_0 (WSA883X_ANA_IVSENSE_BASE + 0x0008)
+#define WSA883X_ADC_1 (WSA883X_ANA_IVSENSE_BASE + 0x0009)
+#define WSA883X_ADC_2 (WSA883X_ANA_IVSENSE_BASE + 0x000A)
+#define WSA883X_ADC_3 (WSA883X_ANA_IVSENSE_BASE + 0x000B)
+#define WSA883X_ADC_4 (WSA883X_ANA_IVSENSE_BASE + 0x000C)
+#define WSA883X_ADC_5 (WSA883X_ANA_IVSENSE_BASE + 0x000D)
+#define WSA883X_ADC_6 (WSA883X_ANA_IVSENSE_BASE + 0x000E)
+#define WSA883X_ADC_7 (WSA883X_ANA_IVSENSE_BASE + 0x000F)
+#define WSA883X_STATUS (WSA883X_ANA_IVSENSE_BASE + 0x0010)
+
+#define WSA883X_ANA_SPK_TOP_BASE (WSA883X_BASE + 0x00000025)
+#define WSA883X_DAC_CTRL_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0000)
+#define WSA883X_DAC_EN_DEBUG_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0001)
+#define WSA883X_DAC_OPAMP_BIAS1_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0002)
+#define WSA883X_DAC_OPAMP_BIAS2_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0003)
+#define WSA883X_DAC_VCM_CTRL_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0004)
+#define WSA883X_DAC_VOLTAGE_CTRL_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0005)
+#define WSA883X_ATEST1_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0006)
+#define WSA883X_ATEST2_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0007)
+#define WSA883X_SPKR_TOP_BIAS_REG1 (WSA883X_ANA_SPK_TOP_BASE + 0x0008)
+#define WSA883X_SPKR_TOP_BIAS_REG2 (WSA883X_ANA_SPK_TOP_BASE + 0x0009)
+#define WSA883X_SPKR_TOP_BIAS_REG3 (WSA883X_ANA_SPK_TOP_BASE + 0x000A)
+#define WSA883X_SPKR_TOP_BIAS_REG4 (WSA883X_ANA_SPK_TOP_BASE + 0x000B)
+#define WSA883X_SPKR_CLIP_DET_REG (WSA883X_ANA_SPK_TOP_BASE + 0x000C)
+#define WSA883X_SPKR_DRV_LF_BLK_EN (WSA883X_ANA_SPK_TOP_BASE + 0x000D)
+#define WSA883X_SPKR_DRV_LF_EN (WSA883X_ANA_SPK_TOP_BASE + 0x000E)
+#define WSA883X_SPKR_DRV_LF_MASK_DCC_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x000F)
+#define WSA883X_SPKR_DRV_LF_MISC_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0010)
+#define WSA883X_SPKR_DRV_LF_REG_GAIN (WSA883X_ANA_SPK_TOP_BASE + 0x0011)
+#define WSA883X_SPKR_DRV_OS_CAL_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0012)
+#define WSA883X_SPKR_DRV_OS_CAL_CTL1 (WSA883X_ANA_SPK_TOP_BASE + 0x0013)
+#define WSA883X_SPKR_PWM_CLK_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0014)
+#define WSA883X_SPKR_PWM_FREQ_SEL_MASK BIT(3)
+#define WSA883X_SPKR_PWM_FREQ_F300KHZ 0
+#define WSA883X_SPKR_PWM_FREQ_F600KHZ 1
+#define WSA883X_SPKR_PDRV_HS_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0015)
+#define WSA883X_SPKR_PDRV_LS_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0016)
+#define WSA883X_SPKR_PWRSTG_DBG (WSA883X_ANA_SPK_TOP_BASE + 0x0017)
+#define WSA883X_SPKR_OCP_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0018)
+#define WSA883X_SPKR_BBM_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0019)
+#define WSA883X_PA_STATUS0 (WSA883X_ANA_SPK_TOP_BASE + 0x001A)
+#define WSA883X_PA_STATUS1 (WSA883X_ANA_SPK_TOP_BASE + 0x001B)
+#define WSA883X_PA_STATUS2 (WSA883X_ANA_SPK_TOP_BASE + 0x001C)
+
+#define WSA883X_ANA_BOOST_BASE (WSA883X_BASE + 0x00000043)
+#define WSA883X_EN_CTRL (WSA883X_ANA_BOOST_BASE + 0x0000)
+#define WSA883X_CURRENT_LIMIT (WSA883X_ANA_BOOST_BASE + 0x0001)
+#define WSA883X_IBIAS1 (WSA883X_ANA_BOOST_BASE + 0x0002)
+#define WSA883X_IBIAS2 (WSA883X_ANA_BOOST_BASE + 0x0003)
+#define WSA883X_IBIAS3 (WSA883X_ANA_BOOST_BASE + 0x0004)
+#define WSA883X_LDO_PROG (WSA883X_ANA_BOOST_BASE + 0x0005)
+#define WSA883X_STABILITY_CTRL1 (WSA883X_ANA_BOOST_BASE + 0x0006)
+#define WSA883X_STABILITY_CTRL2 (WSA883X_ANA_BOOST_BASE + 0x0007)
+#define WSA883X_PWRSTAGE_CTRL1 (WSA883X_ANA_BOOST_BASE + 0x0008)
+#define WSA883X_PWRSTAGE_CTRL2 (WSA883X_ANA_BOOST_BASE + 0x0009)
+#define WSA883X_BYPASS_1 (WSA883X_ANA_BOOST_BASE + 0x000A)
+#define WSA883X_BYPASS_2 (WSA883X_ANA_BOOST_BASE + 0x000B)
+#define WSA883X_ZX_CTRL_1 (WSA883X_ANA_BOOST_BASE + 0x000C)
+#define WSA883X_ZX_CTRL_2 (WSA883X_ANA_BOOST_BASE + 0x000D)
+#define WSA883X_MISC1 (WSA883X_ANA_BOOST_BASE + 0x000E)
+#define WSA883X_MISC2 (WSA883X_ANA_BOOST_BASE + 0x000F)
+#define WSA883X_GMAMP_SUP1 (WSA883X_ANA_BOOST_BASE + 0x0010)
+#define WSA883X_PWRSTAGE_CTRL3 (WSA883X_ANA_BOOST_BASE + 0x0011)
+#define WSA883X_PWRSTAGE_CTRL4 (WSA883X_ANA_BOOST_BASE + 0x0012)
+#define WSA883X_TEST1 (WSA883X_ANA_BOOST_BASE + 0x0013)
+#define WSA883X_SPARE1 (WSA883X_ANA_BOOST_BASE + 0x0014)
+#define WSA883X_SPARE2 (WSA883X_ANA_BOOST_BASE + 0x0015)
+
+#define WSA883X_ANA_PON_LDOL_BASE (WSA883X_BASE + 0x00000059)
+#define WSA883X_PON_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0000)
+#define WSA883X_PON_CLT_1 (WSA883X_ANA_PON_LDOL_BASE + 0x0001)
+#define WSA883X_PON_CTL_2 (WSA883X_ANA_PON_LDOL_BASE + 0x0002)
+#define WSA883X_PON_CTL_3 (WSA883X_ANA_PON_LDOL_BASE + 0x0003)
+#define WSA883X_CKWD_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0004)
+#define WSA883X_CKWD_CTL_1 (WSA883X_ANA_PON_LDOL_BASE + 0x0005)
+#define WSA883X_CKWD_CTL_2 (WSA883X_ANA_PON_LDOL_BASE + 0x0006)
+#define WSA883X_CKSK_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0007)
+#define WSA883X_PADSW_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0008)
+#define WSA883X_TEST_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0009)
+#define WSA883X_TEST_1 (WSA883X_ANA_PON_LDOL_BASE + 0x000A)
+#define WSA883X_STATUS_0 (WSA883X_ANA_PON_LDOL_BASE + 0x000B)
+#define WSA883X_STATUS_1 (WSA883X_ANA_PON_LDOL_BASE + 0x000C)
+
+#define WSA883X_DIG_CTRL_BASE (WSA883X_BASE + 0x00000400)
+#define WSA883X_CHIP_ID0 (WSA883X_DIG_CTRL_BASE + 0x0001)
+#define WSA883X_CHIP_ID1 (WSA883X_DIG_CTRL_BASE + 0x0002)
+#define WSA883X_CHIP_ID2 (WSA883X_DIG_CTRL_BASE + 0x0003)
+#define WSA883X_CHIP_ID3 (WSA883X_DIG_CTRL_BASE + 0x0004)
+#define WSA883X_BUS_ID (WSA883X_DIG_CTRL_BASE + 0x0005)
+#define WSA883X_CDC_RST_CTL (WSA883X_DIG_CTRL_BASE + 0x0006)
+#define WSA883X_TOP_CLK_CFG (WSA883X_DIG_CTRL_BASE + 0x0007)
+#define WSA883X_CDC_PATH_MODE (WSA883X_DIG_CTRL_BASE + 0x0008)
+#define WSA883X_RXD_MODE_MASK BIT(1)
+#define WSA883X_RXD_MODE_NORMAL 0
+#define WSA883X_RXD_MODE_HIFI 1
+#define WSA883X_CDC_CLK_CTL (WSA883X_DIG_CTRL_BASE + 0x0009)
+#define WSA883X_SWR_RESET_EN (WSA883X_DIG_CTRL_BASE + 0x000A)
+#define WSA883X_RESET_CTL (WSA883X_DIG_CTRL_BASE + 0x000B)
+#define WSA883X_PA_FSM_CTL (WSA883X_DIG_CTRL_BASE + 0x0010)
+#define WSA883X_GLOBAL_PA_EN_MASK BIT(0)
+#define WSA883X_GLOBAL_PA_ENABLE 1
+#define WSA883X_PA_FSM_TIMER0 (WSA883X_DIG_CTRL_BASE + 0x0011)
+#define WSA883X_PA_FSM_TIMER1 (WSA883X_DIG_CTRL_BASE + 0x0012)
+#define WSA883X_PA_FSM_STA (WSA883X_DIG_CTRL_BASE + 0x0013)
+#define WSA883X_PA_FSM_ERR_COND (WSA883X_DIG_CTRL_BASE + 0x0014)
+#define WSA883X_PA_FSM_MSK (WSA883X_DIG_CTRL_BASE + 0x0015)
+#define WSA883X_PA_FSM_BYP (WSA883X_DIG_CTRL_BASE + 0x0016)
+#define WSA883X_PA_FSM_DBG (WSA883X_DIG_CTRL_BASE + 0x0017)
+#define WSA883X_TADC_VALUE_CTL (WSA883X_DIG_CTRL_BASE + 0x0020)
+#define WSA883X_TEMP_DETECT_CTL (WSA883X_DIG_CTRL_BASE + 0x0021)
+#define WSA883X_TEMP_MSB (WSA883X_DIG_CTRL_BASE + 0x0022)
+#define WSA883X_TEMP_LSB (WSA883X_DIG_CTRL_BASE + 0x0023)
+#define WSA883X_TEMP_CONFIG0 (WSA883X_DIG_CTRL_BASE + 0x0024)
+#define WSA883X_TEMP_CONFIG1 (WSA883X_DIG_CTRL_BASE + 0x0025)
+#define WSA883X_VBAT_ADC_FLT_CTL (WSA883X_DIG_CTRL_BASE + 0x0026)
+#define WSA883X_VBAT_ADC_FLT_EN_MASK BIT(0)
+#define WSA883X_VBAT_ADC_COEF_SEL_MASK GENMASK(3, 1)
+#define WSA883X_VBAT_ADC_COEF_F_1DIV2 0x0
+#define WSA883X_VBAT_ADC_COEF_F_1DIV16 0x3
+#define WSA883X_VBAT_DIN_MSB (WSA883X_DIG_CTRL_BASE + 0x0027)
+#define WSA883X_VBAT_DIN_LSB (WSA883X_DIG_CTRL_BASE + 0x0028)
+#define WSA883X_VBAT_DOUT (WSA883X_DIG_CTRL_BASE + 0x0029)
+#define WSA883X_SDM_PDM9_LSB (WSA883X_DIG_CTRL_BASE + 0x002A)
+#define WSA883X_SDM_PDM9_MSB (WSA883X_DIG_CTRL_BASE + 0x002B)
+#define WSA883X_CDC_RX_CTL (WSA883X_DIG_CTRL_BASE + 0x0030)
+#define WSA883X_CDC_SPK_DSM_A1_0 (WSA883X_DIG_CTRL_BASE + 0x0031)
+#define WSA883X_CDC_SPK_DSM_A1_1 (WSA883X_DIG_CTRL_BASE + 0x0032)
+#define WSA883X_CDC_SPK_DSM_A2_0 (WSA883X_DIG_CTRL_BASE + 0x0033)
+#define WSA883X_CDC_SPK_DSM_A2_1 (WSA883X_DIG_CTRL_BASE + 0x0034)
+#define WSA883X_CDC_SPK_DSM_A3_0 (WSA883X_DIG_CTRL_BASE + 0x0035)
+#define WSA883X_CDC_SPK_DSM_A3_1 (WSA883X_DIG_CTRL_BASE + 0x0036)
+#define WSA883X_CDC_SPK_DSM_A4_0 (WSA883X_DIG_CTRL_BASE + 0x0037)
+#define WSA883X_CDC_SPK_DSM_A4_1 (WSA883X_DIG_CTRL_BASE + 0x0038)
+#define WSA883X_CDC_SPK_DSM_A5_0 (WSA883X_DIG_CTRL_BASE + 0x0039)
+#define WSA883X_CDC_SPK_DSM_A5_1 (WSA883X_DIG_CTRL_BASE + 0x003A)
+#define WSA883X_CDC_SPK_DSM_A6_0 (WSA883X_DIG_CTRL_BASE + 0x003B)
+#define WSA883X_CDC_SPK_DSM_A7_0 (WSA883X_DIG_CTRL_BASE + 0x003C)
+#define WSA883X_CDC_SPK_DSM_C_0 (WSA883X_DIG_CTRL_BASE + 0x003D)
+#define WSA883X_CDC_SPK_DSM_C_1 (WSA883X_DIG_CTRL_BASE + 0x003E)
+#define WSA883X_CDC_SPK_DSM_C_2 (WSA883X_DIG_CTRL_BASE + 0x003F)
+#define WSA883X_CDC_SPK_DSM_C_3 (WSA883X_DIG_CTRL_BASE + 0x0040)
+#define WSA883X_CDC_SPK_DSM_R1 (WSA883X_DIG_CTRL_BASE + 0x0041)
+#define WSA883X_CDC_SPK_DSM_R2 (WSA883X_DIG_CTRL_BASE + 0x0042)
+#define WSA883X_CDC_SPK_DSM_R3 (WSA883X_DIG_CTRL_BASE + 0x0043)
+#define WSA883X_CDC_SPK_DSM_R4 (WSA883X_DIG_CTRL_BASE + 0x0044)
+#define WSA883X_CDC_SPK_DSM_R5 (WSA883X_DIG_CTRL_BASE + 0x0045)
+#define WSA883X_CDC_SPK_DSM_R6 (WSA883X_DIG_CTRL_BASE + 0x0046)
+#define WSA883X_CDC_SPK_DSM_R7 (WSA883X_DIG_CTRL_BASE + 0x0047)
+#define WSA883X_CDC_SPK_GAIN_PDM_0 (WSA883X_DIG_CTRL_BASE + 0x0048)
+#define WSA883X_CDC_SPK_GAIN_PDM_1 (WSA883X_DIG_CTRL_BASE + 0x0049)
+#define WSA883X_CDC_SPK_GAIN_PDM_2 (WSA883X_DIG_CTRL_BASE + 0x004A)
+#define WSA883X_PDM_WD_CTL (WSA883X_DIG_CTRL_BASE + 0x004B)
+#define WSA883X_PDM_EN_MASK BIT(0)
+#define WSA883X_PDM_ENABLE BIT(0)
+#define WSA883X_DEM_BYPASS_DATA0 (WSA883X_DIG_CTRL_BASE + 0x004C)
+#define WSA883X_DEM_BYPASS_DATA1 (WSA883X_DIG_CTRL_BASE + 0x004D)
+#define WSA883X_DEM_BYPASS_DATA2 (WSA883X_DIG_CTRL_BASE + 0x004E)
+#define WSA883X_DEM_BYPASS_DATA3 (WSA883X_DIG_CTRL_BASE + 0x004F)
+#define WSA883X_WAVG_CTL (WSA883X_DIG_CTRL_BASE + 0x0050)
+#define WSA883X_WAVG_LRA_PER_0 (WSA883X_DIG_CTRL_BASE + 0x0051)
+#define WSA883X_WAVG_LRA_PER_1 (WSA883X_DIG_CTRL_BASE + 0x0052)
+#define WSA883X_WAVG_DELTA_THETA_0 (WSA883X_DIG_CTRL_BASE + 0x0053)
+#define WSA883X_WAVG_DELTA_THETA_1 (WSA883X_DIG_CTRL_BASE + 0x0054)
+#define WSA883X_WAVG_DIRECT_AMP_0 (WSA883X_DIG_CTRL_BASE + 0x0055)
+#define WSA883X_WAVG_DIRECT_AMP_1 (WSA883X_DIG_CTRL_BASE + 0x0056)
+#define WSA883X_WAVG_PTRN_AMP0_0 (WSA883X_DIG_CTRL_BASE + 0x0057)
+#define WSA883X_WAVG_PTRN_AMP0_1 (WSA883X_DIG_CTRL_BASE + 0x0058)
+#define WSA883X_WAVG_PTRN_AMP1_0 (WSA883X_DIG_CTRL_BASE + 0x0059)
+#define WSA883X_WAVG_PTRN_AMP1_1 (WSA883X_DIG_CTRL_BASE + 0x005A)
+#define WSA883X_WAVG_PTRN_AMP2_0 (WSA883X_DIG_CTRL_BASE + 0x005B)
+#define WSA883X_WAVG_PTRN_AMP2_1 (WSA883X_DIG_CTRL_BASE + 0x005C)
+#define WSA883X_WAVG_PTRN_AMP3_0 (WSA883X_DIG_CTRL_BASE + 0x005D)
+#define WSA883X_WAVG_PTRN_AMP3_1 (WSA883X_DIG_CTRL_BASE + 0x005E)
+#define WSA883X_WAVG_PTRN_AMP4_0 (WSA883X_DIG_CTRL_BASE + 0x005F)
+#define WSA883X_WAVG_PTRN_AMP4_1 (WSA883X_DIG_CTRL_BASE + 0x0060)
+#define WSA883X_WAVG_PTRN_AMP5_0 (WSA883X_DIG_CTRL_BASE + 0x0061)
+#define WSA883X_WAVG_PTRN_AMP5_1 (WSA883X_DIG_CTRL_BASE + 0x0062)
+#define WSA883X_WAVG_PTRN_AMP6_0 (WSA883X_DIG_CTRL_BASE + 0x0063)
+#define WSA883X_WAVG_PTRN_AMP6_1 (WSA883X_DIG_CTRL_BASE + 0x0064)
+#define WSA883X_WAVG_PTRN_AMP7_0 (WSA883X_DIG_CTRL_BASE + 0x0065)
+#define WSA883X_WAVG_PTRN_AMP7_1 (WSA883X_DIG_CTRL_BASE + 0x0066)
+#define WSA883X_WAVG_PER_0_1 (WSA883X_DIG_CTRL_BASE + 0x0067)
+#define WSA883X_WAVG_PER_2_3 (WSA883X_DIG_CTRL_BASE + 0x0068)
+#define WSA883X_WAVG_PER_4_5 (WSA883X_DIG_CTRL_BASE + 0x0069)
+#define WSA883X_WAVG_PER_6_7 (WSA883X_DIG_CTRL_BASE + 0x006A)
+#define WSA883X_WAVG_STA (WSA883X_DIG_CTRL_BASE + 0x006B)
+#define WSA883X_DRE_CTL_0 (WSA883X_DIG_CTRL_BASE + 0x006C)
+#define WSA883X_DRE_OFFSET_MASK GENMASK(2, 0)
+#define WSA883X_DRE_PROG_DELAY_MASK GENMASK(7, 4)
+#define WSA883X_DRE_CTL_1 (WSA883X_DIG_CTRL_BASE + 0x006D)
+#define WSA883X_DRE_GAIN_EN_MASK BIT(0)
+#define WSA883X_DRE_GAIN_FROM_CSR 1
+#define WSA883X_DRE_IDLE_DET_CTL (WSA883X_DIG_CTRL_BASE + 0x006E)
+#define WSA883X_CLSH_CTL_0 (WSA883X_DIG_CTRL_BASE + 0x0070)
+#define WSA883X_CLSH_CTL_1 (WSA883X_DIG_CTRL_BASE + 0x0071)
+#define WSA883X_CLSH_V_HD_PA (WSA883X_DIG_CTRL_BASE + 0x0072)
+#define WSA883X_CLSH_V_PA_MIN (WSA883X_DIG_CTRL_BASE + 0x0073)
+#define WSA883X_CLSH_OVRD_VAL (WSA883X_DIG_CTRL_BASE + 0x0074)
+#define WSA883X_CLSH_HARD_MAX (WSA883X_DIG_CTRL_BASE + 0x0075)
+#define WSA883X_CLSH_SOFT_MAX (WSA883X_DIG_CTRL_BASE + 0x0076)
+#define WSA883X_CLSH_SIG_DP (WSA883X_DIG_CTRL_BASE + 0x0077)
+#define WSA883X_TAGC_CTL (WSA883X_DIG_CTRL_BASE + 0x0078)
+#define WSA883X_TAGC_TIME (WSA883X_DIG_CTRL_BASE + 0x0079)
+#define WSA883X_TAGC_E2E_GAIN (WSA883X_DIG_CTRL_BASE + 0x007A)
+#define WSA883X_TAGC_FORCE_VAL (WSA883X_DIG_CTRL_BASE + 0x007B)
+#define WSA883X_VAGC_CTL (WSA883X_DIG_CTRL_BASE + 0x007C)
+#define WSA883X_VAGC_TIME (WSA883X_DIG_CTRL_BASE + 0x007D)
+#define WSA883X_VAGC_ATTN_LVL_1_2 (WSA883X_DIG_CTRL_BASE + 0x007E)
+#define WSA883X_VAGC_ATTN_LVL_3 (WSA883X_DIG_CTRL_BASE + 0x007F)
+#define WSA883X_INTR_MODE (WSA883X_DIG_CTRL_BASE + 0x0080)
+#define WSA883X_INTR_MASK0 (WSA883X_DIG_CTRL_BASE + 0x0081)
+#define WSA883X_INTR_MASK1 (WSA883X_DIG_CTRL_BASE + 0x0082)
+#define WSA883X_INTR_STATUS0 (WSA883X_DIG_CTRL_BASE + 0x0083)
+#define WSA883X_INTR_STATUS1 (WSA883X_DIG_CTRL_BASE + 0x0084)
+#define WSA883X_INTR_CLEAR0 (WSA883X_DIG_CTRL_BASE + 0x0085)
+#define WSA883X_INTR_CLEAR1 (WSA883X_DIG_CTRL_BASE + 0x0086)
+#define WSA883X_INTR_LEVEL0 (WSA883X_DIG_CTRL_BASE + 0x0087)
+#define WSA883X_INTR_LEVEL1 (WSA883X_DIG_CTRL_BASE + 0x0088)
+#define WSA883X_INTR_SET0 (WSA883X_DIG_CTRL_BASE + 0x0089)
+#define WSA883X_INTR_SET1 (WSA883X_DIG_CTRL_BASE + 0x008A)
+#define WSA883X_INTR_TEST0 (WSA883X_DIG_CTRL_BASE + 0x008B)
+#define WSA883X_INTR_TEST1 (WSA883X_DIG_CTRL_BASE + 0x008C)
+#define WSA883X_OTP_CTRL0 (WSA883X_DIG_CTRL_BASE + 0x0090)
+#define WSA883X_OTP_CTRL1 (WSA883X_DIG_CTRL_BASE + 0x0091)
+#define WSA883X_HDRIVE_CTL_GROUP1 (WSA883X_DIG_CTRL_BASE + 0x0092)
+#define WSA883X_PIN_CTL (WSA883X_DIG_CTRL_BASE + 0x0093)
+#define WSA883X_PIN_CTL_OE (WSA883X_DIG_CTRL_BASE + 0x0094)
+#define WSA883X_PIN_WDATA_IOPAD (WSA883X_DIG_CTRL_BASE + 0x0095)
+#define WSA883X_PIN_STATUS (WSA883X_DIG_CTRL_BASE + 0x0096)
+#define WSA883X_I2C_SLAVE_CTL (WSA883X_DIG_CTRL_BASE + 0x0097)
+#define WSA883X_PDM_TEST_MODE (WSA883X_DIG_CTRL_BASE + 0x00A0)
+#define WSA883X_ATE_TEST_MODE (WSA883X_DIG_CTRL_BASE + 0x00A1)
+#define WSA883X_DIG_DEBUG_MODE (WSA883X_DIG_CTRL_BASE + 0x00A3)
+#define WSA883X_DIG_DEBUG_SEL (WSA883X_DIG_CTRL_BASE + 0x00A4)
+#define WSA883X_DIG_DEBUG_EN (WSA883X_DIG_CTRL_BASE + 0x00A5)
+#define WSA883X_SWR_HM_TEST0 (WSA883X_DIG_CTRL_BASE + 0x00A6)
+#define WSA883X_SWR_HM_TEST1 (WSA883X_DIG_CTRL_BASE + 0x00A7)
+#define WSA883X_SWR_PAD_CTL (WSA883X_DIG_CTRL_BASE + 0x00A8)
+#define WSA883X_TADC_DETECT_DBG_CTL (WSA883X_DIG_CTRL_BASE + 0x00A9)
+#define WSA883X_TADC_DEBUG_MSB (WSA883X_DIG_CTRL_BASE + 0x00AA)
+#define WSA883X_TADC_DEBUG_LSB (WSA883X_DIG_CTRL_BASE + 0x00AB)
+#define WSA883X_SAMPLE_EDGE_SEL (WSA883X_DIG_CTRL_BASE + 0x00AC)
+#define WSA883X_SWR_EDGE_SEL (WSA883X_DIG_CTRL_BASE + 0x00AD)
+#define WSA883X_TEST_MODE_CTL (WSA883X_DIG_CTRL_BASE + 0x00AE)
+#define WSA883X_IOPAD_CTL (WSA883X_DIG_CTRL_BASE + 0x00AF)
+#define WSA883X_ANA_CSR_DBG_ADD (WSA883X_DIG_CTRL_BASE + 0x00B0)
+#define WSA883X_ANA_CSR_DBG_CTL (WSA883X_DIG_CTRL_BASE + 0x00B1)
+#define WSA883X_SPARE_R (WSA883X_DIG_CTRL_BASE + 0x00BC)
+#define WSA883X_SPARE_0 (WSA883X_DIG_CTRL_BASE + 0x00BD)
+#define WSA883X_SPARE_1 (WSA883X_DIG_CTRL_BASE + 0x00BE)
+#define WSA883X_SPARE_2 (WSA883X_DIG_CTRL_BASE + 0x00BF)
+#define WSA883X_SCODE (WSA883X_DIG_CTRL_BASE + 0x00C0)
+
+#define WSA883X_DIG_TRIM_BASE (WSA883X_BASE + 0x00000500)
+#define WSA883X_OTP_REG_0 (WSA883X_DIG_TRIM_BASE + 0x0080)
+#define WSA883X_ID_MASK GENMASK(3, 0)
+#define WSA883X_OTP_REG_1 (WSA883X_DIG_TRIM_BASE + 0x0081)
+#define WSA883X_OTP_REG_2 (WSA883X_DIG_TRIM_BASE + 0x0082)
+#define WSA883X_OTP_REG_3 (WSA883X_DIG_TRIM_BASE + 0x0083)
+#define WSA883X_OTP_REG_4 (WSA883X_DIG_TRIM_BASE + 0x0084)
+#define WSA883X_OTP_REG_5 (WSA883X_DIG_TRIM_BASE + 0x0085)
+#define WSA883X_OTP_REG_6 (WSA883X_DIG_TRIM_BASE + 0x0086)
+#define WSA883X_OTP_REG_7 (WSA883X_DIG_TRIM_BASE + 0x0087)
+#define WSA883X_OTP_REG_8 (WSA883X_DIG_TRIM_BASE + 0x0088)
+#define WSA883X_OTP_REG_9 (WSA883X_DIG_TRIM_BASE + 0x0089)
+#define WSA883X_OTP_REG_10 (WSA883X_DIG_TRIM_BASE + 0x008A)
+#define WSA883X_OTP_REG_11 (WSA883X_DIG_TRIM_BASE + 0x008B)
+#define WSA883X_OTP_REG_12 (WSA883X_DIG_TRIM_BASE + 0x008C)
+#define WSA883X_OTP_REG_13 (WSA883X_DIG_TRIM_BASE + 0x008D)
+#define WSA883X_OTP_REG_14 (WSA883X_DIG_TRIM_BASE + 0x008E)
+#define WSA883X_OTP_REG_15 (WSA883X_DIG_TRIM_BASE + 0x008F)
+#define WSA883X_OTP_REG_16 (WSA883X_DIG_TRIM_BASE + 0x0090)
+#define WSA883X_OTP_REG_17 (WSA883X_DIG_TRIM_BASE + 0x0091)
+#define WSA883X_OTP_REG_18 (WSA883X_DIG_TRIM_BASE + 0x0092)
+#define WSA883X_OTP_REG_19 (WSA883X_DIG_TRIM_BASE + 0x0093)
+#define WSA883X_OTP_REG_20 (WSA883X_DIG_TRIM_BASE + 0x0094)
+#define WSA883X_OTP_REG_21 (WSA883X_DIG_TRIM_BASE + 0x0095)
+#define WSA883X_OTP_REG_22 (WSA883X_DIG_TRIM_BASE + 0x0096)
+#define WSA883X_OTP_REG_23 (WSA883X_DIG_TRIM_BASE + 0x0097)
+#define WSA883X_OTP_REG_24 (WSA883X_DIG_TRIM_BASE + 0x0098)
+#define WSA883X_OTP_REG_25 (WSA883X_DIG_TRIM_BASE + 0x0099)
+#define WSA883X_OTP_REG_26 (WSA883X_DIG_TRIM_BASE + 0x009A)
+#define WSA883X_OTP_REG_27 (WSA883X_DIG_TRIM_BASE + 0x009B)
+#define WSA883X_OTP_REG_28 (WSA883X_DIG_TRIM_BASE + 0x009C)
+#define WSA883X_OTP_REG_29 (WSA883X_DIG_TRIM_BASE + 0x009D)
+#define WSA883X_OTP_REG_30 (WSA883X_DIG_TRIM_BASE + 0x009E)
+#define WSA883X_OTP_REG_31 (WSA883X_DIG_TRIM_BASE + 0x009F)
+#define WSA883X_OTP_REG_32 (WSA883X_DIG_TRIM_BASE + 0x00A0)
+#define WSA883X_OTP_REG_33 (WSA883X_DIG_TRIM_BASE + 0x00A1)
+#define WSA883X_OTP_REG_34 (WSA883X_DIG_TRIM_BASE + 0x00A2)
+#define WSA883X_OTP_REG_35 (WSA883X_DIG_TRIM_BASE + 0x00A3)
+#define WSA883X_OTP_REG_63 (WSA883X_DIG_TRIM_BASE + 0x00BF)
+
+#define WSA883X_DIG_EMEM_BASE (WSA883X_BASE + 0x000005C0)
+#define WSA883X_EMEM_0 (WSA883X_DIG_EMEM_BASE + 0x0000)
+#define WSA883X_EMEM_1 (WSA883X_DIG_EMEM_BASE + 0x0001)
+#define WSA883X_EMEM_2 (WSA883X_DIG_EMEM_BASE + 0x0002)
+#define WSA883X_EMEM_3 (WSA883X_DIG_EMEM_BASE + 0x0003)
+#define WSA883X_EMEM_4 (WSA883X_DIG_EMEM_BASE + 0x0004)
+#define WSA883X_EMEM_5 (WSA883X_DIG_EMEM_BASE + 0x0005)
+#define WSA883X_EMEM_6 (WSA883X_DIG_EMEM_BASE + 0x0006)
+#define WSA883X_EMEM_7 (WSA883X_DIG_EMEM_BASE + 0x0007)
+#define WSA883X_EMEM_8 (WSA883X_DIG_EMEM_BASE + 0x0008)
+#define WSA883X_EMEM_9 (WSA883X_DIG_EMEM_BASE + 0x0009)
+#define WSA883X_EMEM_10 (WSA883X_DIG_EMEM_BASE + 0x000A)
+#define WSA883X_EMEM_11 (WSA883X_DIG_EMEM_BASE + 0x000B)
+#define WSA883X_EMEM_12 (WSA883X_DIG_EMEM_BASE + 0x000C)
+#define WSA883X_EMEM_13 (WSA883X_DIG_EMEM_BASE + 0x000D)
+#define WSA883X_EMEM_14 (WSA883X_DIG_EMEM_BASE + 0x000E)
+#define WSA883X_EMEM_15 (WSA883X_DIG_EMEM_BASE + 0x000F)
+#define WSA883X_EMEM_16 (WSA883X_DIG_EMEM_BASE + 0x0010)
+#define WSA883X_EMEM_17 (WSA883X_DIG_EMEM_BASE + 0x0011)
+#define WSA883X_EMEM_18 (WSA883X_DIG_EMEM_BASE + 0x0012)
+#define WSA883X_EMEM_19 (WSA883X_DIG_EMEM_BASE + 0x0013)
+#define WSA883X_EMEM_20 (WSA883X_DIG_EMEM_BASE + 0x0014)
+#define WSA883X_EMEM_21 (WSA883X_DIG_EMEM_BASE + 0x0015)
+#define WSA883X_EMEM_22 (WSA883X_DIG_EMEM_BASE + 0x0016)
+#define WSA883X_EMEM_23 (WSA883X_DIG_EMEM_BASE + 0x0017)
+#define WSA883X_EMEM_24 (WSA883X_DIG_EMEM_BASE + 0x0018)
+#define WSA883X_EMEM_25 (WSA883X_DIG_EMEM_BASE + 0x0019)
+#define WSA883X_EMEM_26 (WSA883X_DIG_EMEM_BASE + 0x001A)
+#define WSA883X_EMEM_27 (WSA883X_DIG_EMEM_BASE + 0x001B)
+#define WSA883X_EMEM_28 (WSA883X_DIG_EMEM_BASE + 0x001C)
+#define WSA883X_EMEM_29 (WSA883X_DIG_EMEM_BASE + 0x001D)
+#define WSA883X_EMEM_30 (WSA883X_DIG_EMEM_BASE + 0x001E)
+#define WSA883X_EMEM_31 (WSA883X_DIG_EMEM_BASE + 0x001F)
+#define WSA883X_EMEM_32 (WSA883X_DIG_EMEM_BASE + 0x0020)
+#define WSA883X_EMEM_33 (WSA883X_DIG_EMEM_BASE + 0x0021)
+#define WSA883X_EMEM_34 (WSA883X_DIG_EMEM_BASE + 0x0022)
+#define WSA883X_EMEM_35 (WSA883X_DIG_EMEM_BASE + 0x0023)
+#define WSA883X_EMEM_36 (WSA883X_DIG_EMEM_BASE + 0x0024)
+#define WSA883X_EMEM_37 (WSA883X_DIG_EMEM_BASE + 0x0025)
+#define WSA883X_EMEM_38 (WSA883X_DIG_EMEM_BASE + 0x0026)
+#define WSA883X_EMEM_39 (WSA883X_DIG_EMEM_BASE + 0x0027)
+#define WSA883X_EMEM_40 (WSA883X_DIG_EMEM_BASE + 0x0028)
+#define WSA883X_EMEM_41 (WSA883X_DIG_EMEM_BASE + 0x0029)
+#define WSA883X_EMEM_42 (WSA883X_DIG_EMEM_BASE + 0x002A)
+#define WSA883X_EMEM_43 (WSA883X_DIG_EMEM_BASE + 0x002B)
+#define WSA883X_EMEM_44 (WSA883X_DIG_EMEM_BASE + 0x002C)
+#define WSA883X_EMEM_45 (WSA883X_DIG_EMEM_BASE + 0x002D)
+#define WSA883X_EMEM_46 (WSA883X_DIG_EMEM_BASE + 0x002E)
+#define WSA883X_EMEM_47 (WSA883X_DIG_EMEM_BASE + 0x002F)
+#define WSA883X_EMEM_48 (WSA883X_DIG_EMEM_BASE + 0x0030)
+#define WSA883X_EMEM_49 (WSA883X_DIG_EMEM_BASE + 0x0031)
+#define WSA883X_EMEM_50 (WSA883X_DIG_EMEM_BASE + 0x0032)
+#define WSA883X_EMEM_51 (WSA883X_DIG_EMEM_BASE + 0x0033)
+#define WSA883X_EMEM_52 (WSA883X_DIG_EMEM_BASE + 0x0034)
+#define WSA883X_EMEM_53 (WSA883X_DIG_EMEM_BASE + 0x0035)
+#define WSA883X_EMEM_54 (WSA883X_DIG_EMEM_BASE + 0x0036)
+#define WSA883X_EMEM_55 (WSA883X_DIG_EMEM_BASE + 0x0037)
+#define WSA883X_EMEM_56 (WSA883X_DIG_EMEM_BASE + 0x0038)
+#define WSA883X_EMEM_57 (WSA883X_DIG_EMEM_BASE + 0x0039)
+#define WSA883X_EMEM_58 (WSA883X_DIG_EMEM_BASE + 0x003A)
+#define WSA883X_EMEM_59 (WSA883X_DIG_EMEM_BASE + 0x003B)
+#define WSA883X_EMEM_60 (WSA883X_DIG_EMEM_BASE + 0x003C)
+#define WSA883X_EMEM_61 (WSA883X_DIG_EMEM_BASE + 0x003D)
+#define WSA883X_EMEM_62 (WSA883X_DIG_EMEM_BASE + 0x003E)
+#define WSA883X_EMEM_63 (WSA883X_DIG_EMEM_BASE + 0x003F)
+
+#define WSA883X_NUM_REGISTERS (WSA883X_EMEM_63 + 1)
+#define WSA883X_MAX_REGISTER (WSA883X_NUM_REGISTERS - 1)
+#define WSA883X_PROBE_TIMEOUT 1000
+
+#define WSA883X_VERSION_1_0 0
+#define WSA883X_VERSION_1_1 1
+
+#define WSA883X_MAX_SWR_PORTS 4
+#define WSA883X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
+ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
+ SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
+ SNDRV_PCM_RATE_384000)
+/* Fractional Rates */
+#define WSA883X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
+ SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
+
+#define WSA883X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
+ SNDRV_PCM_FMTBIT_S24_LE |\
+ SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
+
+struct wsa883x_priv {
+ struct regmap *regmap;
+ struct device *dev;
+ struct regulator *vdd;
+ struct sdw_slave *slave;
+ struct sdw_stream_config sconfig;
+ struct sdw_stream_runtime *sruntime;
+ struct sdw_port_config port_config[WSA883X_MAX_SWR_PORTS];
+ struct gpio_desc *sd_n;
+ bool port_prepared[WSA883X_MAX_SWR_PORTS];
+ bool port_enable[WSA883X_MAX_SWR_PORTS];
+ int version;
+ int variant;
+ int active_ports;
+ int dev_mode;
+ int comp_offset;
+};
+
+enum {
+ WSA8830 = 0,
+ WSA8835,
+ WSA8832,
+ WSA8835_V2 = 5,
+};
+
+enum {
+ COMP_OFFSET0,
+ COMP_OFFSET1,
+ COMP_OFFSET2,
+ COMP_OFFSET3,
+ COMP_OFFSET4,
+};
+
+enum wsa_port_ids {
+ WSA883X_PORT_DAC,
+ WSA883X_PORT_COMP,
+ WSA883X_PORT_BOOST,
+ WSA883X_PORT_VISENSE,
+};
+
+/* 4 ports */
+static struct sdw_dpn_prop wsa_sink_dpn_prop[WSA883X_MAX_SWR_PORTS] = {
+ {
+ /* DAC */
+ .num = 1,
+ .type = SDW_DPN_SIMPLE,
+ .min_ch = 1,
+ .max_ch = 1,
+ .simple_ch_prep_sm = true,
+ .read_only_wordlength = true,
+ }, {
+ /* COMP */
+ .num = 2,
+ .type = SDW_DPN_SIMPLE,
+ .min_ch = 1,
+ .max_ch = 1,
+ .simple_ch_prep_sm = true,
+ .read_only_wordlength = true,
+ }, {
+ /* BOOST */
+ .num = 3,
+ .type = SDW_DPN_SIMPLE,
+ .min_ch = 1,
+ .max_ch = 1,
+ .simple_ch_prep_sm = true,
+ .read_only_wordlength = true,
+ }, {
+ /* VISENSE */
+ .num = 4,
+ .type = SDW_DPN_SIMPLE,
+ .min_ch = 1,
+ .max_ch = 1,
+ .simple_ch_prep_sm = true,
+ .read_only_wordlength = true,
+ }
+};
+
+static struct sdw_port_config wsa883x_pconfig[WSA883X_MAX_SWR_PORTS] = {
+ {
+ .num = 1,
+ .ch_mask = 0x1,
+ }, {
+ .num = 2,
+ .ch_mask = 0xf,
+ }, {
+ .num = 3,
+ .ch_mask = 0x3,
+ }, { /* IV feedback */
+ .num = 4,
+ .ch_mask = 0x3,
+ },
+};
+
+static struct reg_default wsa883x_defaults[] = {
+ { WSA883X_REF_CTRL, 0xD5 },
+ { WSA883X_TEST_CTL_0, 0x06 },
+ { WSA883X_BIAS_0, 0xD2 },
+ { WSA883X_OP_CTL, 0xE0 },
+ { WSA883X_IREF_CTL, 0x57 },
+ { WSA883X_ISENS_CTL, 0x47 },
+ { WSA883X_CLK_CTL, 0x87 },
+ { WSA883X_TEST_CTL_1, 0x00 },
+ { WSA883X_BIAS_1, 0x51 },
+ { WSA883X_ADC_CTL, 0x01 },
+ { WSA883X_DOUT_MSB, 0x00 },
+ { WSA883X_DOUT_LSB, 0x00 },
+ { WSA883X_VBAT_SNS, 0x40 },
+ { WSA883X_ITRIM_CODE, 0x9F },
+ { WSA883X_EN, 0x20 },
+ { WSA883X_OVERRIDE1, 0x00 },
+ { WSA883X_OVERRIDE2, 0x08 },
+ { WSA883X_VSENSE1, 0xD3 },
+ { WSA883X_ISENSE1, 0xD4 },
+ { WSA883X_ISENSE2, 0x20 },
+ { WSA883X_ISENSE_CAL, 0x00 },
+ { WSA883X_MISC, 0x08 },
+ { WSA883X_ADC_0, 0x00 },
+ { WSA883X_ADC_1, 0x00 },
+ { WSA883X_ADC_2, 0x40 },
+ { WSA883X_ADC_3, 0x80 },
+ { WSA883X_ADC_4, 0x25 },
+ { WSA883X_ADC_5, 0x25 },
+ { WSA883X_ADC_6, 0x08 },
+ { WSA883X_ADC_7, 0x81 },
+ { WSA883X_STATUS, 0x00 },
+ { WSA883X_DAC_CTRL_REG, 0x53 },
+ { WSA883X_DAC_EN_DEBUG_REG, 0x00 },
+ { WSA883X_DAC_OPAMP_BIAS1_REG, 0x48 },
+ { WSA883X_DAC_OPAMP_BIAS2_REG, 0x48 },
+ { WSA883X_DAC_VCM_CTRL_REG, 0x88 },
+ { WSA883X_DAC_VOLTAGE_CTRL_REG, 0xA5 },
+ { WSA883X_ATEST1_REG, 0x00 },
+ { WSA883X_ATEST2_REG, 0x00 },
+ { WSA883X_SPKR_TOP_BIAS_REG1, 0x6A },
+ { WSA883X_SPKR_TOP_BIAS_REG2, 0x65 },
+ { WSA883X_SPKR_TOP_BIAS_REG3, 0x55 },
+ { WSA883X_SPKR_TOP_BIAS_REG4, 0xA9 },
+ { WSA883X_SPKR_CLIP_DET_REG, 0x9C },
+ { WSA883X_SPKR_DRV_LF_BLK_EN, 0x0F },
+ { WSA883X_SPKR_DRV_LF_EN, 0x0A },
+ { WSA883X_SPKR_DRV_LF_MASK_DCC_CTL, 0x00 },
+ { WSA883X_SPKR_DRV_LF_MISC_CTL, 0x3A },
+ { WSA883X_SPKR_DRV_LF_REG_GAIN, 0x00 },
+ { WSA883X_SPKR_DRV_OS_CAL_CTL, 0x00 },
+ { WSA883X_SPKR_DRV_OS_CAL_CTL1, 0x90 },
+ { WSA883X_SPKR_PWM_CLK_CTL, 0x00 },
+ { WSA883X_SPKR_PDRV_HS_CTL, 0x52 },
+ { WSA883X_SPKR_PDRV_LS_CTL, 0x48 },
+ { WSA883X_SPKR_PWRSTG_DBG, 0x08 },
+ { WSA883X_SPKR_OCP_CTL, 0xE2 },
+ { WSA883X_SPKR_BBM_CTL, 0x92 },
+ { WSA883X_PA_STATUS0, 0x00 },
+ { WSA883X_PA_STATUS1, 0x00 },
+ { WSA883X_PA_STATUS2, 0x80 },
+ { WSA883X_EN_CTRL, 0x44 },
+ { WSA883X_CURRENT_LIMIT, 0xCC },
+ { WSA883X_IBIAS1, 0x00 },
+ { WSA883X_IBIAS2, 0x00 },
+ { WSA883X_IBIAS3, 0x00 },
+ { WSA883X_LDO_PROG, 0x02 },
+ { WSA883X_STABILITY_CTRL1, 0x8E },
+ { WSA883X_STABILITY_CTRL2, 0x10 },
+ { WSA883X_PWRSTAGE_CTRL1, 0x06 },
+ { WSA883X_PWRSTAGE_CTRL2, 0x00 },
+ { WSA883X_BYPASS_1, 0x19 },
+ { WSA883X_BYPASS_2, 0x13 },
+ { WSA883X_ZX_CTRL_1, 0xF0 },
+ { WSA883X_ZX_CTRL_2, 0x04 },
+ { WSA883X_MISC1, 0x06 },
+ { WSA883X_MISC2, 0xA0 },
+ { WSA883X_GMAMP_SUP1, 0x82 },
+ { WSA883X_PWRSTAGE_CTRL3, 0x39 },
+ { WSA883X_PWRSTAGE_CTRL4, 0x5F },
+ { WSA883X_TEST1, 0x00 },
+ { WSA883X_SPARE1, 0x00 },
+ { WSA883X_SPARE2, 0x00 },
+ { WSA883X_PON_CTL_0, 0x10 },
+ { WSA883X_PON_CLT_1, 0xE0 },
+ { WSA883X_PON_CTL_2, 0x90 },
+ { WSA883X_PON_CTL_3, 0x70 },
+ { WSA883X_CKWD_CTL_0, 0x34 },
+ { WSA883X_CKWD_CTL_1, 0x0F },
+ { WSA883X_CKWD_CTL_2, 0x00 },
+ { WSA883X_CKSK_CTL_0, 0x00 },
+ { WSA883X_PADSW_CTL_0, 0x00 },
+ { WSA883X_TEST_0, 0x00 },
+ { WSA883X_TEST_1, 0x00 },
+ { WSA883X_STATUS_0, 0x00 },
+ { WSA883X_STATUS_1, 0x00 },
+ { WSA883X_CHIP_ID0, 0x00 },
+ { WSA883X_CHIP_ID1, 0x00 },
+ { WSA883X_CHIP_ID2, 0x02 },
+ { WSA883X_CHIP_ID3, 0x02 },
+ { WSA883X_BUS_ID, 0x00 },
+ { WSA883X_CDC_RST_CTL, 0x01 },
+ { WSA883X_TOP_CLK_CFG, 0x00 },
+ { WSA883X_CDC_PATH_MODE, 0x00 },
+ { WSA883X_CDC_CLK_CTL, 0xFF },
+ { WSA883X_SWR_RESET_EN, 0x00 },
+ { WSA883X_RESET_CTL, 0x00 },
+ { WSA883X_PA_FSM_CTL, 0x00 },
+ { WSA883X_PA_FSM_TIMER0, 0x80 },
+ { WSA883X_PA_FSM_TIMER1, 0x80 },
+ { WSA883X_PA_FSM_STA, 0x00 },
+ { WSA883X_PA_FSM_ERR_COND, 0x00 },
+ { WSA883X_PA_FSM_MSK, 0x00 },
+ { WSA883X_PA_FSM_BYP, 0x01 },
+ { WSA883X_PA_FSM_DBG, 0x00 },
+ { WSA883X_TADC_VALUE_CTL, 0x03 },
+ { WSA883X_TEMP_DETECT_CTL, 0x01 },
+ { WSA883X_TEMP_MSB, 0x00 },
+ { WSA883X_TEMP_LSB, 0x00 },
+ { WSA883X_TEMP_CONFIG0, 0x00 },
+ { WSA883X_TEMP_CONFIG1, 0x00 },
+ { WSA883X_VBAT_ADC_FLT_CTL, 0x00 },
+ { WSA883X_VBAT_DIN_MSB, 0x00 },
+ { WSA883X_VBAT_DIN_LSB, 0x00 },
+ { WSA883X_VBAT_DOUT, 0x00 },
+ { WSA883X_SDM_PDM9_LSB, 0x00 },
+ { WSA883X_SDM_PDM9_MSB, 0x00 },
+ { WSA883X_CDC_RX_CTL, 0xFE },
+ { WSA883X_CDC_SPK_DSM_A1_0, 0x00 },
+ { WSA883X_CDC_SPK_DSM_A1_1, 0x01 },
+ { WSA883X_CDC_SPK_DSM_A2_0, 0x96 },
+ { WSA883X_CDC_SPK_DSM_A2_1, 0x09 },
+ { WSA883X_CDC_SPK_DSM_A3_0, 0xAB },
+ { WSA883X_CDC_SPK_DSM_A3_1, 0x05 },
+ { WSA883X_CDC_SPK_DSM_A4_0, 0x1C },
+ { WSA883X_CDC_SPK_DSM_A4_1, 0x02 },
+ { WSA883X_CDC_SPK_DSM_A5_0, 0x17 },
+ { WSA883X_CDC_SPK_DSM_A5_1, 0x02 },
+ { WSA883X_CDC_SPK_DSM_A6_0, 0xAA },
+ { WSA883X_CDC_SPK_DSM_A7_0, 0xE3 },
+ { WSA883X_CDC_SPK_DSM_C_0, 0x69 },
+ { WSA883X_CDC_SPK_DSM_C_1, 0x54 },
+ { WSA883X_CDC_SPK_DSM_C_2, 0x02 },
+ { WSA883X_CDC_SPK_DSM_C_3, 0x15 },
+ { WSA883X_CDC_SPK_DSM_R1, 0xA4 },
+ { WSA883X_CDC_SPK_DSM_R2, 0xB5 },
+ { WSA883X_CDC_SPK_DSM_R3, 0x86 },
+ { WSA883X_CDC_SPK_DSM_R4, 0x85 },
+ { WSA883X_CDC_SPK_DSM_R5, 0xAA },
+ { WSA883X_CDC_SPK_DSM_R6, 0xE2 },
+ { WSA883X_CDC_SPK_DSM_R7, 0x62 },
+ { WSA883X_CDC_SPK_GAIN_PDM_0, 0x00 },
+ { WSA883X_CDC_SPK_GAIN_PDM_1, 0xFC },
+ { WSA883X_CDC_SPK_GAIN_PDM_2, 0x05 },
+ { WSA883X_PDM_WD_CTL, 0x00 },
+ { WSA883X_DEM_BYPASS_DATA0, 0x00 },
+ { WSA883X_DEM_BYPASS_DATA1, 0x00 },
+ { WSA883X_DEM_BYPASS_DATA2, 0x00 },
+ { WSA883X_DEM_BYPASS_DATA3, 0x00 },
+ { WSA883X_WAVG_CTL, 0x06 },
+ { WSA883X_WAVG_LRA_PER_0, 0xD1 },
+ { WSA883X_WAVG_LRA_PER_1, 0x00 },
+ { WSA883X_WAVG_DELTA_THETA_0, 0xE6 },
+ { WSA883X_WAVG_DELTA_THETA_1, 0x04 },
+ { WSA883X_WAVG_DIRECT_AMP_0, 0x50 },
+ { WSA883X_WAVG_DIRECT_AMP_1, 0x00 },
+ { WSA883X_WAVG_PTRN_AMP0_0, 0x50 },
+ { WSA883X_WAVG_PTRN_AMP0_1, 0x00 },
+ { WSA883X_WAVG_PTRN_AMP1_0, 0x50 },
+ { WSA883X_WAVG_PTRN_AMP1_1, 0x00 },
+ { WSA883X_WAVG_PTRN_AMP2_0, 0x50 },
+ { WSA883X_WAVG_PTRN_AMP2_1, 0x00 },
+ { WSA883X_WAVG_PTRN_AMP3_0, 0x50 },
+ { WSA883X_WAVG_PTRN_AMP3_1, 0x00 },
+ { WSA883X_WAVG_PTRN_AMP4_0, 0x50 },
+ { WSA883X_WAVG_PTRN_AMP4_1, 0x00 },
+ { WSA883X_WAVG_PTRN_AMP5_0, 0x50 },
+ { WSA883X_WAVG_PTRN_AMP5_1, 0x00 },
+ { WSA883X_WAVG_PTRN_AMP6_0, 0x50 },
+ { WSA883X_WAVG_PTRN_AMP6_1, 0x00 },
+ { WSA883X_WAVG_PTRN_AMP7_0, 0x50 },
+ { WSA883X_WAVG_PTRN_AMP7_1, 0x00 },
+ { WSA883X_WAVG_PER_0_1, 0x88 },
+ { WSA883X_WAVG_PER_2_3, 0x88 },
+ { WSA883X_WAVG_PER_4_5, 0x88 },
+ { WSA883X_WAVG_PER_6_7, 0x88 },
+ { WSA883X_WAVG_STA, 0x00 },
+ { WSA883X_DRE_CTL_0, 0x70 },
+ { WSA883X_DRE_CTL_1, 0x08 },
+ { WSA883X_DRE_IDLE_DET_CTL, 0x1F },
+ { WSA883X_CLSH_CTL_0, 0x37 },
+ { WSA883X_CLSH_CTL_1, 0x81 },
+ { WSA883X_CLSH_V_HD_PA, 0x0F },
+ { WSA883X_CLSH_V_PA_MIN, 0x00 },
+ { WSA883X_CLSH_OVRD_VAL, 0x00 },
+ { WSA883X_CLSH_HARD_MAX, 0xFF },
+ { WSA883X_CLSH_SOFT_MAX, 0xF5 },
+ { WSA883X_CLSH_SIG_DP, 0x00 },
+ { WSA883X_TAGC_CTL, 0x10 },
+ { WSA883X_TAGC_TIME, 0x20 },
+ { WSA883X_TAGC_E2E_GAIN, 0x02 },
+ { WSA883X_TAGC_FORCE_VAL, 0x00 },
+ { WSA883X_VAGC_CTL, 0x00 },
+ { WSA883X_VAGC_TIME, 0x08 },
+ { WSA883X_VAGC_ATTN_LVL_1_2, 0x21 },
+ { WSA883X_VAGC_ATTN_LVL_3, 0x03 },
+ { WSA883X_INTR_MODE, 0x00 },
+ { WSA883X_INTR_MASK0, 0x90 },
+ { WSA883X_INTR_MASK1, 0x00 },
+ { WSA883X_INTR_STATUS0, 0x00 },
+ { WSA883X_INTR_STATUS1, 0x00 },
+ { WSA883X_INTR_CLEAR0, 0x00 },
+ { WSA883X_INTR_CLEAR1, 0x00 },
+ { WSA883X_INTR_LEVEL0, 0x00 },
+ { WSA883X_INTR_LEVEL1, 0x00 },
+ { WSA883X_INTR_SET0, 0x00 },
+ { WSA883X_INTR_SET1, 0x00 },
+ { WSA883X_INTR_TEST0, 0x00 },
+ { WSA883X_INTR_TEST1, 0x00 },
+ { WSA883X_OTP_CTRL0, 0x00 },
+ { WSA883X_OTP_CTRL1, 0x00 },
+ { WSA883X_HDRIVE_CTL_GROUP1, 0x00 },
+ { WSA883X_PIN_CTL, 0x04 },
+ { WSA883X_PIN_CTL_OE, 0x00 },
+ { WSA883X_PIN_WDATA_IOPAD, 0x00 },
+ { WSA883X_PIN_STATUS, 0x00 },
+ { WSA883X_I2C_SLAVE_CTL, 0x00 },
+ { WSA883X_PDM_TEST_MODE, 0x00 },
+ { WSA883X_ATE_TEST_MODE, 0x00 },
+ { WSA883X_DIG_DEBUG_MODE, 0x00 },
+ { WSA883X_DIG_DEBUG_SEL, 0x00 },
+ { WSA883X_DIG_DEBUG_EN, 0x00 },
+ { WSA883X_SWR_HM_TEST0, 0x08 },
+ { WSA883X_SWR_HM_TEST1, 0x00 },
+ { WSA883X_SWR_PAD_CTL, 0x37 },
+ { WSA883X_TADC_DETECT_DBG_CTL, 0x00 },
+ { WSA883X_TADC_DEBUG_MSB, 0x00 },
+ { WSA883X_TADC_DEBUG_LSB, 0x00 },
+ { WSA883X_SAMPLE_EDGE_SEL, 0x7F },
+ { WSA883X_SWR_EDGE_SEL, 0x00 },
+ { WSA883X_TEST_MODE_CTL, 0x04 },
+ { WSA883X_IOPAD_CTL, 0x00 },
+ { WSA883X_ANA_CSR_DBG_ADD, 0x00 },
+ { WSA883X_ANA_CSR_DBG_CTL, 0x12 },
+ { WSA883X_SPARE_R, 0x00 },
+ { WSA883X_SPARE_0, 0x00 },
+ { WSA883X_SPARE_1, 0x00 },
+ { WSA883X_SPARE_2, 0x00 },
+ { WSA883X_SCODE, 0x00 },
+ { WSA883X_OTP_REG_0, 0x05 },
+ { WSA883X_OTP_REG_1, 0xFF },
+ { WSA883X_OTP_REG_2, 0xC0 },
+ { WSA883X_OTP_REG_3, 0xFF },
+ { WSA883X_OTP_REG_4, 0xC0 },
+ { WSA883X_OTP_REG_5, 0xFF },
+ { WSA883X_OTP_REG_6, 0xFF },
+ { WSA883X_OTP_REG_7, 0xFF },
+ { WSA883X_OTP_REG_8, 0xFF },
+ { WSA883X_OTP_REG_9, 0xFF },
+ { WSA883X_OTP_REG_10, 0xFF },
+ { WSA883X_OTP_REG_11, 0xFF },
+ { WSA883X_OTP_REG_12, 0xFF },
+ { WSA883X_OTP_REG_13, 0xFF },
+ { WSA883X_OTP_REG_14, 0xFF },
+ { WSA883X_OTP_REG_15, 0xFF },
+ { WSA883X_OTP_REG_16, 0xFF },
+ { WSA883X_OTP_REG_17, 0xFF },
+ { WSA883X_OTP_REG_18, 0xFF },
+ { WSA883X_OTP_REG_19, 0xFF },
+ { WSA883X_OTP_REG_20, 0xFF },
+ { WSA883X_OTP_REG_21, 0xFF },
+ { WSA883X_OTP_REG_22, 0xFF },
+ { WSA883X_OTP_REG_23, 0xFF },
+ { WSA883X_OTP_REG_24, 0x37 },
+ { WSA883X_OTP_REG_25, 0x3F },
+ { WSA883X_OTP_REG_26, 0x03 },
+ { WSA883X_OTP_REG_27, 0x00 },
+ { WSA883X_OTP_REG_28, 0x00 },
+ { WSA883X_OTP_REG_29, 0x00 },
+ { WSA883X_OTP_REG_30, 0x00 },
+ { WSA883X_OTP_REG_31, 0x03 },
+ { WSA883X_OTP_REG_32, 0x00 },
+ { WSA883X_OTP_REG_33, 0xFF },
+ { WSA883X_OTP_REG_34, 0x00 },
+ { WSA883X_OTP_REG_35, 0x00 },
+ { WSA883X_OTP_REG_63, 0x40 },
+ { WSA883X_EMEM_0, 0x00 },
+ { WSA883X_EMEM_1, 0x00 },
+ { WSA883X_EMEM_2, 0x00 },
+ { WSA883X_EMEM_3, 0x00 },
+ { WSA883X_EMEM_4, 0x00 },
+ { WSA883X_EMEM_5, 0x00 },
+ { WSA883X_EMEM_6, 0x00 },
+ { WSA883X_EMEM_7, 0x00 },
+ { WSA883X_EMEM_8, 0x00 },
+ { WSA883X_EMEM_9, 0x00 },
+ { WSA883X_EMEM_10, 0x00 },
+ { WSA883X_EMEM_11, 0x00 },
+ { WSA883X_EMEM_12, 0x00 },
+ { WSA883X_EMEM_13, 0x00 },
+ { WSA883X_EMEM_14, 0x00 },
+ { WSA883X_EMEM_15, 0x00 },
+ { WSA883X_EMEM_16, 0x00 },
+ { WSA883X_EMEM_17, 0x00 },
+ { WSA883X_EMEM_18, 0x00 },
+ { WSA883X_EMEM_19, 0x00 },
+ { WSA883X_EMEM_20, 0x00 },
+ { WSA883X_EMEM_21, 0x00 },
+ { WSA883X_EMEM_22, 0x00 },
+ { WSA883X_EMEM_23, 0x00 },
+ { WSA883X_EMEM_24, 0x00 },
+ { WSA883X_EMEM_25, 0x00 },
+ { WSA883X_EMEM_26, 0x00 },
+ { WSA883X_EMEM_27, 0x00 },
+ { WSA883X_EMEM_28, 0x00 },
+ { WSA883X_EMEM_29, 0x00 },
+ { WSA883X_EMEM_30, 0x00 },
+ { WSA883X_EMEM_31, 0x00 },
+ { WSA883X_EMEM_32, 0x00 },
+ { WSA883X_EMEM_33, 0x00 },
+ { WSA883X_EMEM_34, 0x00 },
+ { WSA883X_EMEM_35, 0x00 },
+ { WSA883X_EMEM_36, 0x00 },
+ { WSA883X_EMEM_37, 0x00 },
+ { WSA883X_EMEM_38, 0x00 },
+ { WSA883X_EMEM_39, 0x00 },
+ { WSA883X_EMEM_40, 0x00 },
+ { WSA883X_EMEM_41, 0x00 },
+ { WSA883X_EMEM_42, 0x00 },
+ { WSA883X_EMEM_43, 0x00 },
+ { WSA883X_EMEM_44, 0x00 },
+ { WSA883X_EMEM_45, 0x00 },
+ { WSA883X_EMEM_46, 0x00 },
+ { WSA883X_EMEM_47, 0x00 },
+ { WSA883X_EMEM_48, 0x00 },
+ { WSA883X_EMEM_49, 0x00 },
+ { WSA883X_EMEM_50, 0x00 },
+ { WSA883X_EMEM_51, 0x00 },
+ { WSA883X_EMEM_52, 0x00 },
+ { WSA883X_EMEM_53, 0x00 },
+ { WSA883X_EMEM_54, 0x00 },
+ { WSA883X_EMEM_55, 0x00 },
+ { WSA883X_EMEM_56, 0x00 },
+ { WSA883X_EMEM_57, 0x00 },
+ { WSA883X_EMEM_58, 0x00 },
+ { WSA883X_EMEM_59, 0x00 },
+ { WSA883X_EMEM_60, 0x00 },
+ { WSA883X_EMEM_61, 0x00 },
+ { WSA883X_EMEM_62, 0x00 },
+ { WSA883X_EMEM_63, 0x00 },
+};
+
+static bool wsa883x_readonly_register(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case WSA883X_DOUT_MSB:
+ case WSA883X_DOUT_LSB:
+ case WSA883X_STATUS:
+ case WSA883X_PA_STATUS0:
+ case WSA883X_PA_STATUS1:
+ case WSA883X_PA_STATUS2:
+ case WSA883X_STATUS_0:
+ case WSA883X_STATUS_1:
+ case WSA883X_CHIP_ID0:
+ case WSA883X_CHIP_ID1:
+ case WSA883X_CHIP_ID2:
+ case WSA883X_CHIP_ID3:
+ case WSA883X_BUS_ID:
+ case WSA883X_PA_FSM_STA:
+ case WSA883X_PA_FSM_ERR_COND:
+ case WSA883X_TEMP_MSB:
+ case WSA883X_TEMP_LSB:
+ case WSA883X_VBAT_DIN_MSB:
+ case WSA883X_VBAT_DIN_LSB:
+ case WSA883X_VBAT_DOUT:
+ case WSA883X_SDM_PDM9_LSB:
+ case WSA883X_SDM_PDM9_MSB:
+ case WSA883X_WAVG_STA:
+ case WSA883X_INTR_STATUS0:
+ case WSA883X_INTR_STATUS1:
+ case WSA883X_OTP_CTRL1:
+ case WSA883X_PIN_STATUS:
+ case WSA883X_ATE_TEST_MODE:
+ case WSA883X_SWR_HM_TEST1:
+ case WSA883X_SPARE_R:
+ case WSA883X_OTP_REG_0:
+ return true;
+ }
+ return false;
+}
+
+static bool wsa883x_writeable_register(struct device *dev, unsigned int reg)
+{
+ return !wsa883x_readonly_register(dev, reg);
+}
+
+static bool wsa883x_volatile_register(struct device *dev, unsigned int reg)
+{
+ return wsa883x_readonly_register(dev, reg);
+}
+
+static struct regmap_config wsa883x_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 8,
+ .cache_type = REGCACHE_RBTREE,
+ .reg_defaults = wsa883x_defaults,
+ .max_register = WSA883X_MAX_REGISTER,
+ .num_reg_defaults = ARRAY_SIZE(wsa883x_defaults),
+ .volatile_reg = wsa883x_volatile_register,
+ .writeable_reg = wsa883x_writeable_register,
+ .reg_format_endian = REGMAP_ENDIAN_NATIVE,
+ .val_format_endian = REGMAP_ENDIAN_NATIVE,
+ .can_multi_write = true,
+ .use_single_read = true,
+};
+
+static const struct reg_sequence reg_init[] = {
+ {WSA883X_PA_FSM_BYP, 0x00},
+ {WSA883X_ADC_6, 0x02},
+ {WSA883X_CDC_SPK_DSM_A2_0, 0x0A},
+ {WSA883X_CDC_SPK_DSM_A2_1, 0x08},
+ {WSA883X_CDC_SPK_DSM_A3_0, 0xF3},
+ {WSA883X_CDC_SPK_DSM_A3_1, 0x07},
+ {WSA883X_CDC_SPK_DSM_A4_0, 0x79},
+ {WSA883X_CDC_SPK_DSM_A4_1, 0x02},
+ {WSA883X_CDC_SPK_DSM_A5_0, 0x0B},
+ {WSA883X_CDC_SPK_DSM_A5_1, 0x02},
+ {WSA883X_CDC_SPK_DSM_A6_0, 0x8A},
+ {WSA883X_CDC_SPK_DSM_A7_0, 0x9B},
+ {WSA883X_CDC_SPK_DSM_C_0, 0x68},
+ {WSA883X_CDC_SPK_DSM_C_1, 0x54},
+ {WSA883X_CDC_SPK_DSM_C_2, 0xF2},
+ {WSA883X_CDC_SPK_DSM_C_3, 0x20},
+ {WSA883X_CDC_SPK_DSM_R1, 0x83},
+ {WSA883X_CDC_SPK_DSM_R2, 0x7F},
+ {WSA883X_CDC_SPK_DSM_R3, 0x9D},
+ {WSA883X_CDC_SPK_DSM_R4, 0x82},
+ {WSA883X_CDC_SPK_DSM_R5, 0x8B},
+ {WSA883X_CDC_SPK_DSM_R6, 0x9B},
+ {WSA883X_CDC_SPK_DSM_R7, 0x3F},
+ {WSA883X_VBAT_SNS, 0x20},
+ {WSA883X_DRE_CTL_0, 0x92},
+ {WSA883X_DRE_IDLE_DET_CTL, 0x0F},
+ {WSA883X_CURRENT_LIMIT, 0xC4},
+ {WSA883X_VAGC_TIME, 0x0F},
+ {WSA883X_VAGC_ATTN_LVL_1_2, 0x00},
+ {WSA883X_VAGC_ATTN_LVL_3, 0x01},
+ {WSA883X_VAGC_CTL, 0x01},
+ {WSA883X_TAGC_CTL, 0x1A},
+ {WSA883X_TAGC_TIME, 0x2C},
+ {WSA883X_TEMP_CONFIG0, 0x02},
+ {WSA883X_TEMP_CONFIG1, 0x02},
+ {WSA883X_OTP_REG_1, 0x49},
+ {WSA883X_OTP_REG_2, 0x80},
+ {WSA883X_OTP_REG_3, 0xC9},
+ {WSA883X_OTP_REG_4, 0x40},
+ {WSA883X_TAGC_CTL, 0x1B},
+ {WSA883X_ADC_2, 0x00},
+ {WSA883X_ADC_7, 0x85},
+ {WSA883X_ADC_7, 0x87},
+ {WSA883X_CKWD_CTL_0, 0x14},
+ {WSA883X_CKWD_CTL_1, 0x1B},
+ {WSA883X_GMAMP_SUP1, 0xE2},
+};
+
+static void wsa883x_init(struct wsa883x_priv *wsa883x)
+{
+ struct regmap *regmap = wsa883x->regmap;
+ int variant, version;
+
+ regmap_read(regmap, WSA883X_OTP_REG_0, &variant);
+ wsa883x->variant = variant & WSA883X_ID_MASK;
+
+ regmap_read(regmap, WSA883X_CHIP_ID0, &version);
+ wsa883x->version = version;
+
+ switch (wsa883x->variant) {
+ case WSA8830:
+ dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8830\n",
+ wsa883x->version);
+ break;
+ case WSA8835:
+ dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8835\n",
+ wsa883x->version);
+ break;
+ case WSA8832:
+ dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8832\n",
+ wsa883x->version);
+ break;
+ case WSA8835_V2:
+ dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8835_V2\n",
+ wsa883x->version);
+ break;
+ default:
+ break;
+ }
+
+ wsa883x->comp_offset = COMP_OFFSET2;
+
+ /* Initial settings */
+ regmap_multi_reg_write(regmap, reg_init, ARRAY_SIZE(reg_init));
+
+ if (wsa883x->variant == WSA8830 || wsa883x->variant == WSA8832) {
+ wsa883x->comp_offset = COMP_OFFSET3;
+ regmap_update_bits(regmap, WSA883X_DRE_CTL_0,
+ WSA883X_DRE_OFFSET_MASK,
+ wsa883x->comp_offset);
+ }
+}
+
+static int wsa883x_update_status(struct sdw_slave *slave,
+ enum sdw_slave_status status)
+{
+ struct wsa883x_priv *wsa883x = dev_get_drvdata(&slave->dev);
+
+ if (status == SDW_SLAVE_ATTACHED && slave->dev_num > 0)
+ wsa883x_init(wsa883x);
+
+ return 0;
+}
+
+static int wsa883x_port_prep(struct sdw_slave *slave,
+ struct sdw_prepare_ch *prepare_ch,
+ enum sdw_port_prep_ops state)
+{
+ struct wsa883x_priv *wsa883x = dev_get_drvdata(&slave->dev);
+
+ if (state == SDW_OPS_PORT_POST_PREP)
+ wsa883x->port_prepared[prepare_ch->num - 1] = true;
+ else
+ wsa883x->port_prepared[prepare_ch->num - 1] = false;
+
+ return 0;
+}
+
+static struct sdw_slave_ops wsa883x_slave_ops = {
+ .update_status = wsa883x_update_status,
+ .port_prep = wsa883x_port_prep,
+};
+
+static int wsa883x_codec_probe(struct snd_soc_component *comp)
+{
+ struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(comp);
+
+ snd_soc_component_init_regmap(comp, wsa883x->regmap);
+
+ return 0;
+}
+
+static const struct snd_soc_component_driver wsa883x_component_drv = {
+ .name = "WSA883x",
+ .probe = wsa883x_codec_probe,
+};
+
+static int wsa883x_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct wsa883x_priv *wsa883x = dev_get_drvdata(dai->dev);
+ int i;
+
+ wsa883x->active_ports = 0;
+ for (i = 0; i < WSA883X_MAX_SWR_PORTS; i++) {
+ if (!wsa883x->port_enable[i])
+ continue;
+
+ wsa883x->port_config[wsa883x->active_ports] = wsa883x_pconfig[i];
+ wsa883x->active_ports++;
+ }
+
+ wsa883x->sconfig.frame_rate = params_rate(params);
+
+ return sdw_stream_add_slave(wsa883x->slave, &wsa883x->sconfig,
+ wsa883x->port_config, wsa883x->active_ports,
+ wsa883x->sruntime);
+}
+
+static int wsa883x_hw_free(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct wsa883x_priv *wsa883x = dev_get_drvdata(dai->dev);
+
+ sdw_stream_remove_slave(wsa883x->slave, wsa883x->sruntime);
+
+ return 0;
+}
+
+static int wsa883x_set_sdw_stream(struct snd_soc_dai *dai,
+ void *stream, int direction)
+{
+ struct wsa883x_priv *wsa883x = dev_get_drvdata(dai->dev);
+
+ wsa883x->sruntime = stream;
+
+ return 0;
+}
+
+static int wsa883x_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
+{
+ struct snd_soc_component *component = dai->component;
+
+ if (mute) {
+ snd_soc_component_write_field(component, WSA883X_DRE_CTL_1,
+ WSA883X_DRE_GAIN_EN_MASK, 0);
+ snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL,
+ WSA883X_GLOBAL_PA_EN_MASK, 0);
+
+ } else {
+ snd_soc_component_write_field(component, WSA883X_DRE_CTL_1,
+ WSA883X_DRE_GAIN_EN_MASK,
+ WSA883X_DRE_GAIN_FROM_CSR);
+ snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL,
+ WSA883X_GLOBAL_PA_EN_MASK, 1);
+
+ }
+
+ return 0;
+}
+
+static const struct snd_soc_dai_ops wsa883x_dai_ops = {
+ .hw_params = wsa883x_hw_params,
+ .hw_free = wsa883x_hw_free,
+ .mute_stream = wsa883x_digital_mute,
+ .set_stream = wsa883x_set_sdw_stream,
+};
+
+static struct snd_soc_dai_driver wsa883x_dais[] = {
+ {
+ .name = "SPKR",
+ .playback = {
+ .stream_name = "SPKR Playback",
+ .rates = WSA883X_RATES | WSA883X_FRAC_RATES,
+ .formats = WSA883X_FORMATS,
+ .rate_max = 8000,
+ .rate_min = 352800,
+ .channels_min = 1,
+ .channels_max = 1,
+ },
+ .ops = &wsa883x_dai_ops,
+ },
+};
+
+static int wsa883x_probe(struct sdw_slave *pdev,
+ const struct sdw_device_id *id)
+{
+ struct wsa883x_priv *wsa883x;
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ wsa883x = devm_kzalloc(&pdev->dev, sizeof(*wsa883x), GFP_KERNEL);
+ if (!wsa883x)
+ return -ENOMEM;
+
+ wsa883x->vdd = devm_regulator_get(dev, "vdd");
+ if (IS_ERR(wsa883x->vdd)) {
+ dev_err(dev, "No vdd regulator found\n");
+ return PTR_ERR(wsa883x->vdd);
+ }
+
+ ret = regulator_enable(wsa883x->vdd);
+ if (ret) {
+ dev_err(dev, "Failed to enable vdd regulator (%d)\n", ret);
+ return ret;
+ }
+
+ wsa883x->sd_n = devm_gpiod_get_optional(&pdev->dev, "powerdown",
+ GPIOD_FLAGS_BIT_NONEXCLUSIVE);
+ if (IS_ERR(wsa883x->sd_n)) {
+ dev_err(&pdev->dev, "Shutdown Control GPIO not found\n");
+ ret = PTR_ERR(wsa883x->sd_n);
+ goto err;
+ }
+
+ dev_set_drvdata(&pdev->dev, wsa883x);
+ wsa883x->slave = pdev;
+ wsa883x->dev = &pdev->dev;
+ wsa883x->sconfig.ch_count = 1;
+ wsa883x->sconfig.bps = 1;
+ wsa883x->sconfig.direction = SDW_DATA_DIR_RX;
+ wsa883x->sconfig.type = SDW_STREAM_PDM;
+
+ pdev->prop.sink_ports = GENMASK(WSA883X_MAX_SWR_PORTS, 0);
+ pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop;
+ pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
+ gpiod_direction_output(wsa883x->sd_n, 1);
+
+ wsa883x->regmap = devm_regmap_init_sdw(pdev, &wsa883x_regmap_config);
+ if (IS_ERR(wsa883x->regmap)) {
+ dev_err(&pdev->dev, "regmap_init failed\n");
+ ret = PTR_ERR(wsa883x->regmap);
+ goto err;
+ }
+ pm_runtime_set_autosuspend_delay(dev, 3000);
+ pm_runtime_use_autosuspend(dev);
+ pm_runtime_mark_last_busy(dev);
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+
+ ret = devm_snd_soc_register_component(&pdev->dev,
+ &wsa883x_component_drv,
+ wsa883x_dais,
+ ARRAY_SIZE(wsa883x_dais));
+err:
+ if (ret)
+ regulator_disable(wsa883x->vdd);
+
+ return ret;
+
+}
+
+static int __maybe_unused wsa883x_runtime_suspend(struct device *dev)
+{
+ struct regmap *regmap = dev_get_regmap(dev, NULL);
+ struct wsa883x_priv *wsa883x = dev_get_drvdata(dev);
+
+ gpiod_direction_output(wsa883x->sd_n, 0);
+
+ regcache_cache_only(regmap, true);
+ regcache_mark_dirty(regmap);
+
+ regulator_disable(wsa883x->vdd);
+ return 0;
+}
+
+static int __maybe_unused wsa883x_runtime_resume(struct device *dev)
+{
+ struct sdw_slave *slave = dev_to_sdw_dev(dev);
+ struct regmap *regmap = dev_get_regmap(dev, NULL);
+ struct wsa883x_priv *wsa883x = dev_get_drvdata(dev);
+ int ret;
+
+ ret = regulator_enable(wsa883x->vdd);
+ if (ret) {
+ dev_err(dev, "Failed to enable vdd regulator (%d)\n", ret);
+ return ret;
+ }
+
+ gpiod_direction_output(wsa883x->sd_n, 1);
+
+ wait_for_completion_timeout(&slave->initialization_complete,
+ msecs_to_jiffies(WSA883X_PROBE_TIMEOUT));
+
+ usleep_range(20000, 20010);
+ regcache_cache_only(regmap, false);
+ regcache_sync(regmap);
+
+ return 0;
+}
+
+static const struct dev_pm_ops wsa883x_pm_ops = {
+ SET_RUNTIME_PM_OPS(wsa883x_runtime_suspend, wsa883x_runtime_resume, NULL)
+};
+
+static const struct sdw_device_id wsa883x_swr_id[] = {
+ SDW_SLAVE_ENTRY(0x0217, 0x0202, 0),
+ {},
+};
+
+static struct sdw_driver wsa883x_codec_driver = {
+ .driver = {
+ .name = "wsa883x-codec",
+ .pm = &wsa883x_pm_ops,
+ .suppress_bind_attrs = true,
+ },
+ .probe = wsa883x_probe,
+ .ops = &wsa883x_slave_ops,
+ .id_table = wsa883x_swr_id,
+};
+
+module_sdw_driver(wsa883x_codec_driver);
+
+MODULE_DESCRIPTION("WSA883x codec driver");
+MODULE_LICENSE("GPL");
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