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| author | Fugang Duan <B38611@freescale.com> | 2012-09-20 15:26:49 +0800 |
|---|---|---|
| committer | Fugang Duan <B38611@freescale.com> | 2012-11-09 16:05:53 +0800 |
| commit | 5722518fcba2dffcabcf3c2d5e2bd6c390392699 (patch) | |
| tree | bdb4ffbac0ff1743cedb1b58e682b7729a084c75 /drivers/net | |
| parent | 3d248d1c069504c98c76a0b7fb04d739270ab837 (diff) | |
| download | linux-5722518fcba2dffcabcf3c2d5e2bd6c390392699.tar.gz | |
ENGR00224109 - MX6 : FEC : optimize ENET_REF_CLK PAD configuration.
In MX6 Arik and Rigel platforms, RGMII tx_clk clock source is from
ENET_REF_CLK pad supplied by phy. To optimize the clk signal path,
the ENET_REF_CLK I/O must have this configuration:
1. Disable on-chip pull-up, pull-down, and keeper
2. Disable hysteresis
3. Speed = 100 MHz
4. Slew rate = fast
The optimizition make the bias point match the optimum point, which
can maximize design margin.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Diffstat (limited to 'drivers/net')
0 files changed, 0 insertions, 0 deletions