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author | Tuomas Tynkkynen <ttynkkynen@nvidia.com> | 2014-08-21 00:04:31 +0300 |
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committer | Paul Sherwood <paul.sherwood@codethink.co.uk> | 2014-12-06 22:44:49 +0000 |
commit | f804d65b455e9ace7960944c07d7fe8c75e03e9b (patch) | |
tree | 4fa01bf14b42e087dc9a635480a479ec71cb6908 /drivers/clk/tegra/cvb.h | |
parent | c8df4810b80727061966b61076e18e9177c4901d (diff) | |
download | linux-f804d65b455e9ace7960944c07d7fe8c75e03e9b.tar.gz |
clk: tegra: Add closed loop support for the DFLL
With closed loop support, the clock rate of the DFLL can be adjusted.
The oscillator itself in the DFLL is a free-running oscillator whose
rate is directly determined the supply voltage. However, the DFLL
module contains logic to compare the DFLL output rate to a fixed
reference clock (51 MHz) and make a decision to either lower or raise
the DFLL supply voltage. The DFLL module can then autonomously change
the supply voltage by communicating with an off-chip PMIC via either I2C
or PWM signals. This driver currently supports only I2C.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Diffstat (limited to 'drivers/clk/tegra/cvb.h')
0 files changed, 0 insertions, 0 deletions