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authorLei Wen <leiwen@marvell.com>2011-06-21 02:54:18 -0700
committerEric Miao <eric.y.miao@gmail.com>2011-07-06 23:51:22 +0800
commitd204b2c5b16df935fa9a546c528e168859fddcc0 (patch)
treed7558ad5b3ade59bdc11686b3b9d74229255c57d /arch/arm/mach-mmp/pxa910.c
parentbeb0c9b056b1c23d2029b46a425362e9ccbeba01 (diff)
downloadlinux-d204b2c5b16df935fa9a546c528e168859fddcc0.tar.gz
ARM: pxa910: correct nand pmu setting
The original pair of <0x01db, 208000000> is invalid. Correct to the valid value. Signed-off-by: Lei Wen <leiwen@marvell.com> Cc: stable@kernel.org Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Diffstat (limited to 'arch/arm/mach-mmp/pxa910.c')
-rw-r--r--arch/arm/mach-mmp/pxa910.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 8f92ccd26edf..1464607aa60d 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -110,7 +110,7 @@ static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
-static APMU_CLK(nand, NAND, 0x01db, 208000000);
+static APMU_CLK(nand, NAND, 0x19b, 156000000);
static APMU_CLK(u2o, USB, 0x1b, 480000000);
/* device and clock bindings */