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| author | Tuomas Tynkkynen <ttynkkynen@nvidia.com> | 2014-08-21 00:04:37 +0300 |
|---|---|---|
| committer | Paul Sherwood <paul.sherwood@codethink.co.uk> | 2014-12-06 22:44:51 +0000 |
| commit | e8b863100d104a54d3acacf6f2b356c0b9309461 (patch) | |
| tree | db81a194d74e458de5187f86e2179a892a612aca | |
| parent | c971fa210693ec61df286a3fee3c5247c8fd5dc9 (diff) | |
| download | linux-e8b863100d104a54d3acacf6f2b356c0b9309461.tar.gz | |
ARM: tegra: Add the DFLL to Tegra124 device tree
The DFLL clocksource is a separate IP block from the usual
clock-and-reset controller, so it gets its own device tree node.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
| -rw-r--r-- | arch/arm/boot/dts/tegra124.dtsi | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index df2b06b29985..38300e9b9664 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -640,6 +640,28 @@ status = "disabled"; }; + dfll: dfll@0,70110000 { + compatible = "nvidia,tegra124-dfll"; + reg = <0 0x70110000 0 0x100>, /* DFLL control */ + <0 0x70110000 0 0x100>, /* I2C output control */ + <0 0x70110100 0 0x100>, /* Integrated I2C controller */ + <0 0x70110200 0 0x100>; /* Look-up table RAM */ + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, + <&tegra_car TEGRA124_CLK_DFLL_REF>, + <&tegra_car TEGRA124_CLK_I2C5>; + clock-names = "soc", "ref", "i2c"; + #clock-cells = <0>; + clock-output-names = "dfllCPU_out"; + nvidia,sample-rate = <12500>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,cf = <10>; + nvidia,ci = <0>; + nvidia,cg = <2>; + status = "disabled"; + }; + ahub@0,70300000 { compatible = "nvidia,tegra124-ahub"; reg = <0x0 0x70300000 0x0 0x200>, |