diff options
| author | Tuomas Tynkkynen <ttynkkynen@nvidia.com> | 2014-08-21 00:04:36 +0300 |
|---|---|---|
| committer | Paul Sherwood <paul.sherwood@codethink.co.uk> | 2014-12-06 22:44:51 +0000 |
| commit | c971fa210693ec61df286a3fee3c5247c8fd5dc9 (patch) | |
| tree | 70874a6508056372783ed3fcd5be54cf2528069c | |
| parent | c46f236de634b0d5b8d108d705183abb8fb93971 (diff) | |
| download | linux-c971fa210693ec61df286a3fee3c5247c8fd5dc9.tar.gz | |
clk: tegra: Add the DFLL as a possible parent of the cclk_g clock
The DFLL clocksource was missing from the list of possible parents for
the fast CPU cluster. Add it to the list.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
| -rw-r--r-- | drivers/clk/tegra/clk-tegra-super-gen4.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c index feb3201c85ce..f1f441034b86 100644 --- a/drivers/clk/tegra/clk-tegra-super-gen4.c +++ b/drivers/clk/tegra/clk-tegra-super-gen4.c @@ -44,7 +44,9 @@ static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", "pll_p", "pll_p_out4", "unused", - "unused", "pll_x" }; + "unused", "pll_x", "unused", "unused", + "unused", "unused", "unused", "unused", + "dfllCPU_out" }; static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", "pll_p", "pll_p_out4", "unused", |