diff options
| author | Terry Lv <r65388@freescale.com> | 2013-04-11 17:05:00 +0800 |
|---|---|---|
| committer | Terry Lv <r65388@freescale.com> | 2013-04-12 14:43:24 +0800 |
| commit | cb9bf3fbddd6a4fa1c763207575cdf36925a62a7 (patch) | |
| tree | ea39363a64333cd0827620acc5d19cbf85006949 | |
| parent | dc5e48a118558ba1964c6b69ffa307f15197dde3 (diff) | |
| download | linux-cb9bf3fbddd6a4fa1c763207575cdf36925a62a7.tar.gz | |
ENGR00256417: MLB: can't receive data in wait mode
For MLB uses iram for data transfer, and there's a missing of dependency
on iram in MLB's clock setting, MLB can't receive data in wait mode.
We need to add ocram clock dependency in MLB clock.
Signed-off-by: Terry Lv <r65388@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx6/clock.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 83544284776e..c70a1c088027 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -1152,7 +1152,11 @@ static int _clk_pll_mlb_main_enable(struct clk *clk) reg = __raw_readl(pllbase); reg &= ~ANADIG_PLL_BYPASS; - reg = 0x0da20800; + reg = (0x3 << ANADIG_PLL_MLB_FLT_RES_CFG_OFFSET) | + (0x3 << ANADIG_PLL_MLB_RX_CLK_DELAY_CFG_OFFSET) | + (0x2 << ANADIG_PLL_MLB_VDDD_DELAY_CFG_OFFSET) | + (0x1 << ANADIG_PLL_MLB_VDDA_DELAY_CFG_OFFSET) | + (ANADIG_PLL_HOLD_RING_OFF); __raw_writel(reg, pllbase); return 0; @@ -4888,6 +4892,7 @@ static int _clk_mlb_set_parent(struct clk *clk, struct clk *parent) static struct clk mlb150_clk = { __INIT_CLK_DEBUG(mlb150_clk) .id = 0, + .secondary = &ocram_clk, .set_parent = _clk_mlb_set_parent, .enable_reg = MXC_CCM_CCGR3, .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, |