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| author | Ben Dooks <ben.dooks@codethink.co.uk> | 2013-02-01 10:36:22 +0000 |
|---|---|---|
| committer | Ben Dooks <ben.dooks@codethink.co.uk> | 2013-02-12 19:03:28 +0000 |
| commit | 20866326849bdea048f1d0fd6e99474f96181871 (patch) | |
| tree | f107e67c8d15346533948569dc4a52c2bed2b202 | |
| parent | 581bf104d36a727031c60762e4fa91ac06cd17f9 (diff) | |
| download | linux-baserock/bjdooks/arm_be8_v3.tar.gz | |
mvebu: support running big-endianbaserock/bjdooks/arm_be8_v3
Add indication we can run these cores in BE mode, and ensure that the
secondary CPU is set to big-endian mode in the initialisation code as
the initial code runs little-endian.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
| -rw-r--r-- | arch/arm/mach-mvebu/Kconfig | 1 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/coherency_ll.S | 3 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/headsmp.S | 2 |
3 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 440b13ef1fed..2afa026d1e49 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -1,5 +1,6 @@ config ARCH_MVEBU bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7 + select ARCH_SUPPORTS_BIG_ENDIAN select CLKSRC_MMIO select COMMON_CLK select GENERIC_CLOCKEVENTS diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S index 53e8391192cd..bc2d70d06c2f 100644 --- a/arch/arm/mach-mvebu/coherency_ll.S +++ b/arch/arm/mach-mvebu/coherency_ll.S @@ -20,6 +20,8 @@ #define ARMADA_XP_CFB_CTL_REG_OFFSET 0x0 #define ARMADA_XP_CFB_CFG_REG_OFFSET 0x4 +#include <asm/assembler.h> + .text /* * r0: Coherency fabric base register address @@ -29,6 +31,7 @@ ENTRY(ll_set_cpu_coherent) /* Create bit by cpu index */ mov r3, #(1 << 24) lsl r1, r3, r1 +ARM_BE8(rev r1, r1) /* Add CPU to SMP group - Atomic */ add r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S index a06e0ede8c08..3b77eaca3f3e 100644 --- a/arch/arm/mach-mvebu/headsmp.S +++ b/arch/arm/mach-mvebu/headsmp.S @@ -36,6 +36,8 @@ */ ENTRY(armada_xp_secondary_startup) + ARM_BE8(setend be ) @ go BE8 if booted LE + /* Read CPU id */ mrc p15, 0, r1, c0, c0, 5 and r1, r1, #0xF |