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| author | Ben Dooks <ben.dooks@codethink.co.uk> | 2013-02-01 10:36:22 +0000 |
|---|---|---|
| committer | Ben Dooks <ben.dooks@codethink.co.uk> | 2013-02-08 16:30:32 +0000 |
| commit | 4f1aecf5a8595a1e0d429bff35b945375dc83394 (patch) | |
| tree | 603b141e5a2fca711ac1b80f1024ab83413abd35 | |
| parent | 0ff6832a1954458fa6536f7ae14e525970befe94 (diff) | |
| download | linux-4f1aecf5a8595a1e0d429bff35b945375dc83394.tar.gz | |
mvebu: support running big-endian
Add indication we can run these cores in BE mode, and ensure that the
secondary CPU is set to big-endian mode in the initialisation code as
the initial code runs little-endian.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Conflicts:
arch/arm/mach-mvebu/headsmp.S
| -rw-r--r-- | arch/arm/mach-mvebu/Kconfig | 1 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/headsmp.S | 53 |
2 files changed, 54 insertions, 0 deletions
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 416d46ef7ebd..6fb0f0618cae 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -1,5 +1,6 @@ config ARCH_MVEBU bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7 + select ARCH_SUPPORTS_BIG_ENDIAN select CLKSRC_MMIO select COMMON_CLK select GENERIC_CLOCKEVENTS diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S new file mode 100644 index 000000000000..8b09f8d0d3fd --- /dev/null +++ b/arch/arm/mach-mvebu/headsmp.S @@ -0,0 +1,53 @@ +/* + * SMP support: Entry point for secondary CPUs + * + * Copyright (C) 2012 Marvell + * + * Yehuda Yitschak <yehuday@marvell.com> + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * This file implements the assembly entry point for secondary CPUs in + * an SMP kernel. The only thing we need to do is to add the CPU to + * the coherency fabric by writing to 2 registers. Currently the base + * register addresses are hard coded due to the early initialisation + * problems. + */ + +#include <linux/linkage.h> +#include <linux/init.h> + +/* + * At this stage the secondary CPUs don't have acces yet to the MMU, so + * we have to provide physical addresses + */ +#define ARMADA_XP_CFB_BASE 0xD0020200 + + __CPUINIT + +/* + * Armada XP specific entry point for secondary CPUs. + * We add the CPU to the coherency fabric and then jump to secondary + * startup + */ +ENTRY(armada_xp_secondary_startup) + +#ifdef CONFIG_CPU_BE8_BOOT_LE + setend be +#endif + + /* Read CPU id */ + mrc p15, 0, r1, c0, c0, 5 + and r1, r1, #0xF + + /* Add CPU to coherency fabric */ + ldr r0, =ARMADA_XP_CFB_BASE + + bl ll_set_cpu_coherent + b secondary_startup + +ENDPROC(armada_xp_secondary_startup) |