diff options
Diffstat (limited to 'drivers/net/ftgmac100_26.c')
| -rw-r--r-- | drivers/net/ftgmac100_26.c | 22 |
1 files changed, 16 insertions, 6 deletions
diff --git a/drivers/net/ftgmac100_26.c b/drivers/net/ftgmac100_26.c index 8575293015e7..fdc77fca1b5d 100644 --- a/drivers/net/ftgmac100_26.c +++ b/drivers/net/ftgmac100_26.c @@ -120,6 +120,8 @@ #err "Not define include for GMAC" #endif +#define PHY_DEFAULT_ADDR 0x1F + /*------------------------------------------------------------------------ . . Configuration options, for the experienced user to change. @@ -269,9 +271,11 @@ no_phy_access: if (out->miiPhyId == 0xFFFF) { //Realtek PHY at address 1 out->phyAddr = 1; } +#if 0 if (out->miiPhyId == 0x0362) { out->phyAddr = 1; } +#endif out->miiPhyId = ftgmac100_read_phy_register(dev->base_addr, out->phyAddr, 0x02); out->miiPhyId = (out->miiPhyId & 0xffff) << 16; out->miiPhyId |= ftgmac100_read_phy_register(dev->base_addr, out->phyAddr, 0x03) & 0xffff; @@ -280,7 +284,7 @@ no_phy_access: case 0x0040: // Broadcom case 0x0141: // Marvell case 0x001c: // Realtek - case 0x0362: // BCM54612 + case 0x0362: // BCM54612, BCM54616 break; default: @@ -334,7 +338,8 @@ static void ftgmac100_reset( struct net_device* dev ) speed = (tmp & PHY_SPEED_mask)>>14; netif_carrier_on(dev); } - else if (priv->ids.miiPhyId == PHYID_BCM54612E) { + else if (priv->ids.miiPhyId == PHYID_BCM54612E + || priv->ids.miiPhyId == PHYID_BCM54616S) { // Get link status // First Switch shadow register selector ftgmac100_write_phy_register(dev->base_addr, priv->ids.phyAddr, 0x1C, 0x2000); @@ -558,7 +563,8 @@ Re_Get_Link_Status: ,dev->base_addr + IER_REG ); } - else if (priv->ids.miiPhyId == PHYID_BCM54612E) { + else if (priv->ids.miiPhyId == PHYID_BCM54612E + || priv->ids.miiPhyId == PHYID_BCM54616S) { outl( // no link PHY link status pin PHYSTS_CHG_bit | AHB_ERR_bit | @@ -612,7 +618,8 @@ static void aspeed_mac_timer(unsigned long data) duplex = (tmp & PHY_DUPLEX_mask)>>13; speed = (tmp & PHY_SPEED_mask)>>14; } - else if (priv->ids.miiPhyId == PHYID_BCM54612E) { + else if (priv->ids.miiPhyId == PHYID_BCM54612E + || priv->ids.miiPhyId == PHYID_BCM54616S) { // Get link status // First Switch shadow register selector ftgmac100_write_phy_register(dev->base_addr, priv->ids.phyAddr, 0x1C, 0x2000); @@ -913,6 +920,7 @@ static void ftgmac100_phy_configure(struct net_device* dev) case PHYID_VENDOR_BROADCOM: switch (priv->ids.miiPhyId) { case PHYID_BCM54612E: + case PHYID_BCM54616S: ftgmac100_write_phy_register(ioaddr, priv->ids.phyAddr, 0x1C, 0x8C00); // Disable GTXCLK Clock Delay Enable ftgmac100_write_phy_register(ioaddr, priv->ids.phyAddr, 0x18, 0xF0E7); // Disable RGMII RXD to RXC Skew break; @@ -1303,7 +1311,8 @@ static irqreturn_t ftgmac100_interrupt(int irq, void * dev_id, struct pt_regs * // Bits [3:1] are {duplex, speed, link} change interrupts. tmp &= 0x000e; } - else if (priv->ids.miiPhyId == PHYID_BCM54612E) { + else if (priv->ids.miiPhyId == PHYID_BCM54612E + || priv->ids.miiPhyId == PHYID_BCM54616S) { tmp = ftgmac100_read_phy_register(ioaddr, priv->ids.phyAddr, 0x1A); PRINTK("%s: PHY interrupt status, read_phy_reg(0x1A) = 0x%04x\n", dev->name, tmp); @@ -1644,7 +1653,8 @@ static int ftgmac100_open(struct net_device *netdev) if (((priv->ids.miiPhyId & PHYID_VENDOR_MASK) == PHYID_VENDOR_BROADCOM) || ((priv->ids.miiPhyId & PHYID_VENDOR_MODEL_MASK) == PHYID_RTL8201EL) || - (priv->ids.miiPhyId == PHYID_BCM54612E)) { + (priv->ids.miiPhyId == PHYID_BCM54612E) || + (priv->ids.miiPhyId == PHYID_BCM54616S)) { init_timer(&priv->timer); priv->timer.data = (unsigned long)netdev; |