diff options
Diffstat (limited to 'arch/arm')
141 files changed, 27886 insertions, 3 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9722f8bb506c..71db83ffe935 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -199,6 +199,14 @@ choice prompt "ARM system type" default ARCH_VERSATILE +config ARCH_ASPEED + bool "ASPEED AST Family" + select ARM_AMBA + select PLAT_ASPEED + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB + + config ARCH_AAEC2000 bool "Agilent AAEC-2000 based" select ARM_AMBA @@ -551,6 +559,8 @@ config ARCH_MSM endchoice +source "arch/arm/mach-aspeed/Kconfig" + source "arch/arm/mach-clps711x/Kconfig" source "arch/arm/mach-ep93xx/Kconfig" @@ -637,6 +647,9 @@ config PLAT_IOP config PLAT_ORION bool +config PLAT_ASPEED + bool + source arch/arm/mm/Kconfig config IWMMXT diff --git a/arch/arm/Makefile b/arch/arm/Makefile index bd6e28115ebb..b039927112f2 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -144,6 +144,8 @@ endif machine-$(CONFIG_ARCH_MSM) := msm machine-$(CONFIG_ARCH_LOKI) := loki machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 + machine-$(CONFIG_ARCH_ASPEED) := aspeed + plat-$(CONFIG_PLAT_ASPEED) := aspeed ifeq ($(CONFIG_ARCH_EBSA110),y) # This is what happens if you forget the IOCS16 line. diff --git a/arch/arm/configs/ast2300_ast1070_defconfig b/arch/arm/configs/ast2300_ast1070_defconfig new file mode 100644 index 000000000000..2285e61351b5 --- /dev/null +++ b/arch/arm/configs/ast2300_ast1070_defconfig @@ -0,0 +1,1037 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.28.9 +# Fri Nov 1 16:40:08 2013 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_GENERIC_TIME is not set +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_ARCH_ASPEED=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +CONFIG_IRMP=y +# CONFIG_PCEXT is not set +# CONFIG_REMOTEFX is not set +# CONFIG_ARCH_AST1100 is not set +# CONFIG_ARCH_AST2100 is not set +# CONFIG_ARCH_AST2200 is not set +CONFIG_ARCH_AST2300=y +# CONFIG_ARCH_AST2400 is not set +# CONFIG_ARCH_AST2500 is not set + +# +# FLASH Chip Select +# +CONFIG_AST_CS0_NOR=y +# CONFIG_AST_CS0_NAND is not set +# CONFIG_AST_CS0_SPI is not set +# CONFIG_AST_CS0_NONE is not set +CONFIG_AST_CS1_NOR=y +# CONFIG_AST_CS1_NAND is not set +# CONFIG_AST_CS1_SPI is not set +# CONFIG_AST_CS1_NONE is not set +CONFIG_AST_CS2_NOR=y +# CONFIG_AST_CS2_NAND is not set +# CONFIG_AST_CS2_SPI is not set +# CONFIG_AST_CS2_NONE is not set +CONFIG_AST_CS3_NOR=y +# CONFIG_AST_CS3_NAND is not set +# CONFIG_AST_CS3_SPI is not set +# CONFIG_AST_CS3_NONE is not set +CONFIG_AST_CS4_NOR=y +# CONFIG_AST_CS4_NAND is not set +# CONFIG_AST_CS4_SPI is not set +# CONFIG_AST_CS4_NONE is not set +CONFIG_ARCH_AST1070=y +CONFIG_AST1070_NR=1 +# CONFIG_AST_LPC_PLUS is not set +CONFIG_AST_LPC=y +# CONFIG_AST_SCU_LOCK is not set + +# +# Boot options +# + +# +# Power management +# +CONFIG_PLAT_ASPEED=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_ARM_AMBA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_AEABI is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +CONFIG_FPE_NWFPE_XP=y +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +CONFIG_BINFMT_AOUT=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_ARTHUR is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +CONFIG_WAN_ROUTER=y +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_TGT=y +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=m +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_NET_ETHERNET is not set +CONFIG_NETDEV_1000=y +CONFIG_ASPEEDMAC=y +# CONFIG_MAC0_PHY_LINK is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_SERIAL=y +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +# CONFIG_RIO is not set +# CONFIG_STALDRV is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +CONFIG_SERIAL_AST_DMA_UART=y +CONFIG_AST_NR_DMA_UARTS=8 +CONFIG_AST_RUNTIME_DMA_UARTS=8 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_AST is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_AST_MISC is not set +# CONFIG_HW_RANDOM is not set +CONFIG_NVRAM=y +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_AST=y +CONFIG_I2C_AST1070=y +CONFIG_AST_I2C_SLAVE_MODE=y +CONFIG_AST_I2C_SLAVE_EEPROM=y +# CONFIG_AST_I2C_SLAVE_RDWR is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_AT24 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_TPS65010 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/ast2300_defconfig b/arch/arm/configs/ast2300_defconfig new file mode 100644 index 000000000000..5ac21209d3f1 --- /dev/null +++ b/arch/arm/configs/ast2300_defconfig @@ -0,0 +1,1464 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.28.9 +# Wed Aug 7 16:52:42 2013 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_GENERIC_TIME is not set +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_ARCH_ASPEED=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +CONFIG_IRMP=y +# CONFIG_PCEXT is not set +# CONFIG_REMOTEFX is not set +# CONFIG_ARCH_AST1100 is not set +# CONFIG_ARCH_AST2100 is not set +# CONFIG_ARCH_AST2200 is not set +CONFIG_ARCH_AST2300=y +# CONFIG_ARCH_AST2400 is not set +# CONFIG_ARCH_AST2500 is not set + +# +# FLASH Chip Select +# +CONFIG_AST_CS0_NOR=y +# CONFIG_AST_CS0_NAND is not set +# CONFIG_AST_CS0_SPI is not set +# CONFIG_AST_CS0_NONE is not set +CONFIG_AST_CS1_NOR=y +# CONFIG_AST_CS1_NAND is not set +# CONFIG_AST_CS1_SPI is not set +# CONFIG_AST_CS1_NONE is not set +CONFIG_AST_CS2_NOR=y +# CONFIG_AST_CS2_NAND is not set +# CONFIG_AST_CS2_SPI is not set +# CONFIG_AST_CS2_NONE is not set +CONFIG_AST_CS3_NOR=y +# CONFIG_AST_CS3_NAND is not set +# CONFIG_AST_CS3_SPI is not set +# CONFIG_AST_CS3_NONE is not set +CONFIG_AST_CS4_NOR=y +# CONFIG_AST_CS4_NAND is not set +# CONFIG_AST_CS4_SPI is not set +# CONFIG_AST_CS4_NONE is not set +# CONFIG_ARCH_AST1070 is not set +# CONFIG_AST_SCU_LOCK is not set + +# +# Boot options +# + +# +# Power management +# +CONFIG_PLAT_ASPEED=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_ARM_AMBA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_AEABI is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +CONFIG_FPE_NWFPE_XP=y +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +CONFIG_BINFMT_AOUT=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_ARTHUR is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +CONFIG_WAN_ROUTER=y +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +CONFIG_FIB_RULES=y +# CONFIG_WIRELESS is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +CONFIG_MTD_DATAFLASH=y +# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set +# CONFIG_MTD_DATAFLASH_OTP is not set +CONFIG_MTD_M25P80=y +CONFIG_M25PXX_USE_FAST_READ=y +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_AST=y +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_TGT=y +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=m +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +CONFIG_BONDING=y +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_NET_ETHERNET is not set +CONFIG_NETDEV_1000=y +CONFIG_ASPEEDMAC=y +CONFIG_MAC0_PHY_LINK=y +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_SERIAL=y +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +# CONFIG_RIO is not set +# CONFIG_STALDRV is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_SERIAL_AST_DMA_UART is not set +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_AST is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_AST_MISC is not set +# CONFIG_HW_RANDOM is not set +CONFIG_NVRAM=y +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_AST is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +CONFIG_AT24=y +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_TPS65010 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_AST is not set +CONFIG_SPI_FMC=y +CONFIG_SPI_BITBANG=y + +# +# SPI Protocol Masters +# +# CONFIG_SPI_AT25 is not set +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_AST_ADC is not set +CONFIG_SENSORS_AST_PWM_FAN=y +# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_AST_WATCHDOG is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HID_DEBUG=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# AST USB Drivers +# +CONFIG_AST_USB_UHCI_HCD=y +# CONFIG_AST_USB_UHCI_MULTIPORT_1 is not set +# CONFIG_AST_USB_UHCI_MULTIPORT_2 is not set +CONFIG_AST_USB_UHCI_MULTIPORT_4=y + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +# + +# +# see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_ARMMMCI is not set +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_AST is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_HCTOSYS is not set +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +CONFIG_RTC_DRV_ASPEED=y +# CONFIG_DMADEVICES is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_YAFFS_FS=y +CONFIG_YAFFS_YAFFS1=y +# CONFIG_YAFFS_9BYTE_TAGS is not set +# CONFIG_YAFFS_DOES_ECC is not set +CONFIG_YAFFS_YAFFS2=y +CONFIG_YAFFS_AUTO_YAFFS2=y +# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set +# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set +# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set +# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set +CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y +# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/ast2300_fb_defconfig b/arch/arm/configs/ast2300_fb_defconfig new file mode 100644 index 000000000000..817e089deef1 --- /dev/null +++ b/arch/arm/configs/ast2300_fb_defconfig @@ -0,0 +1,1514 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.28.9 +# Thu Jan 10 10:44:05 2013 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_GENERIC_TIME is not set +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_ARCH_ASPEED=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +CONFIG_IRMP=y +# CONFIG_PCEXT is not set +# CONFIG_REMOTEFX is not set +# CONFIG_ARCH_AST1100 is not set +# CONFIG_ARCH_AST2100 is not set +# CONFIG_ARCH_AST2200 is not set +CONFIG_ARCH_AST2300=y +# CONFIG_ARCH_AST2400 is not set + +# +# FLASH Chip Select +# +# CONFIG_ASPEED_CS0_NOR is not set +# CONFIG_ASPEED_CS0_NAND is not set +CONFIG_ASPEED_CS0_SPI=y +# CONFIG_ASPEED_CS0_NONE is not set +# CONFIG_ASPEED_CS1_NOR is not set +# CONFIG_ASPEED_CS1_NAND is not set +# CONFIG_ASPEED_CS1_SPI is not set +CONFIG_ASPEED_CS1_NONE=y +# CONFIG_ASPEED_CS2_NOR is not set +# CONFIG_ASPEED_CS2_NAND is not set +# CONFIG_ASPEED_CS2_SPI is not set +CONFIG_ASPEED_CS2_NONE=y +# CONFIG_ASPEED_CS3_NOR is not set +# CONFIG_ASPEED_CS3_NAND is not set +# CONFIG_ASPEED_CS3_SPI is not set +CONFIG_ASPEED_CS3_NONE=y +# CONFIG_ASPEED_CS4_NOR is not set +CONFIG_ASPEED_CS4_NAND=y +# CONFIG_ASPEED_CS4_SPI is not set +# CONFIG_ASPEED_CS4_NONE is not set +# CONFIG_ARCH_AST1070 is not set +# CONFIG_ASPEED_SCU_LOCK is not set + +# +# Boot options +# + +# +# Power management +# +CONFIG_PLAT_ASPEED=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_ARM_AMBA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_AEABI is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +CONFIG_FPE_NWFPE_XP=y +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +CONFIG_BINFMT_AOUT=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_ARTHUR is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +CONFIG_WAN_ROUTER=y +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +CONFIG_FIB_RULES=y +# CONFIG_WIRELESS is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +CONFIG_MTD_DATAFLASH=y +# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set +# CONFIG_MTD_DATAFLASH_OTP is not set +CONFIG_MTD_M25P80=y +CONFIG_M25PXX_USE_FAST_READ=y +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_AST=y +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_TGT=y +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=m +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +CONFIG_BONDING=y +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_NET_ETHERNET is not set +CONFIG_NETDEV_1000=y +CONFIG_ASPEEDMAC=y +CONFIG_MAC0_PHY_LINK=y +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_SERIAL=y +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +# CONFIG_RIO is not set +# CONFIG_STALDRV is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +CONFIG_SERIAL_ASPEED=y +CONFIG_SERIAL_ASPEED_CONSOLE=y +CONFIG_SERIAL_ASPEED_CONSOLE_BAUD=115200 +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +CONFIG_NVRAM=y +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_ASPEED=y +CONFIG_AST_I2C_SLAVE_MODE=y +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +CONFIG_AT24=y +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_TPS65010 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_AST=y +# CONFIG_SPI_FMC is not set +CONFIG_SPI_BITBANG=y + +# +# SPI Protocol Masters +# +# CONFIG_SPI_AT25 is not set +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_AST_ADC is not set +CONFIG_SENSORS_AST_PWM_FAN=y +# CONFIG_SENSORS_AST_PECI is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_ASPEED_WATCHDOG=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_AST=y +CONFIG_AST_DAC=y +# CONFIG_AST_DVO is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LCD_PLATFORM is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=m +# CONFIG_BACKLIGHT_CORGI is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +# CONFIG_LOGO is not set +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HID_DEBUG=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# AST USB Drivers +# +CONFIG_AST_USB_UHCI_HCD=y +# CONFIG_AST_USB_UHCI_MULTIPORT_1 is not set +# CONFIG_AST_USB_UHCI_MULTIPORT_2 is not set +CONFIG_AST_USB_UHCI_MULTIPORT_4=y + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +# + +# +# see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_ARMMMCI is not set +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_ASPEED=y +# CONFIG_MMC_SPI is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_HCTOSYS is not set +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +CONFIG_RTC_DRV_ASPEED=y +# CONFIG_DMADEVICES is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_YAFFS_FS=y +CONFIG_YAFFS_YAFFS1=y +# CONFIG_YAFFS_9BYTE_TAGS is not set +# CONFIG_YAFFS_DOES_ECC is not set +CONFIG_YAFFS_YAFFS2=y +CONFIG_YAFFS_AUTO_YAFFS2=y +# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set +# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set +# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set +# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set +CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y +# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/ast2400_ast1070-1_defconfig b/arch/arm/configs/ast2400_ast1070-1_defconfig new file mode 100644 index 000000000000..93f3df9e1e74 --- /dev/null +++ b/arch/arm/configs/ast2400_ast1070-1_defconfig @@ -0,0 +1,1038 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.28.9 +# Fri Nov 8 16:04:52 2013 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_GENERIC_TIME is not set +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_ARCH_ASPEED=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +CONFIG_IRMP=y +# CONFIG_PCEXT is not set +# CONFIG_REMOTEFX is not set +# CONFIG_ARCH_AST1100 is not set +# CONFIG_ARCH_AST2100 is not set +# CONFIG_ARCH_AST2200 is not set +# CONFIG_ARCH_AST2300 is not set +CONFIG_ARCH_AST2400=y +# CONFIG_ARCH_AST2500 is not set + +# +# FLASH Chip Select +# +CONFIG_AST_CS0_NOR=y +# CONFIG_AST_CS0_NAND is not set +# CONFIG_AST_CS0_SPI is not set +# CONFIG_AST_CS0_NONE is not set +CONFIG_AST_CS1_NOR=y +# CONFIG_AST_CS1_NAND is not set +# CONFIG_AST_CS1_SPI is not set +# CONFIG_AST_CS1_NONE is not set +CONFIG_AST_CS2_NOR=y +# CONFIG_AST_CS2_NAND is not set +# CONFIG_AST_CS2_SPI is not set +# CONFIG_AST_CS2_NONE is not set +CONFIG_AST_CS3_NOR=y +# CONFIG_AST_CS3_NAND is not set +# CONFIG_AST_CS3_SPI is not set +# CONFIG_AST_CS3_NONE is not set +CONFIG_AST_CS4_NOR=y +# CONFIG_AST_CS4_NAND is not set +# CONFIG_AST_CS4_SPI is not set +# CONFIG_AST_CS4_NONE is not set +CONFIG_ARCH_AST1070=y +CONFIG_AST1070_NR=1 +CONFIG_AST_LPC_PLUS=y +# CONFIG_AST_LPC is not set +# CONFIG_AST_SCU_LOCK is not set + +# +# Boot options +# + +# +# Power management +# +CONFIG_PLAT_ASPEED=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_ARM_AMBA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_AEABI is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +CONFIG_FPE_NWFPE_XP=y +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +CONFIG_BINFMT_AOUT=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_ARTHUR is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +CONFIG_WAN_ROUTER=y +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_TGT=y +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=m +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_NET_ETHERNET is not set +CONFIG_NETDEV_1000=y +CONFIG_ASPEEDMAC=y +# CONFIG_MAC0_PHY_LINK is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_SERIAL=y +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +# CONFIG_RIO is not set +# CONFIG_STALDRV is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +CONFIG_SERIAL_AST_DMA_UART=y +CONFIG_AST_NR_DMA_UARTS=4 +CONFIG_AST_RUNTIME_DMA_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_AST is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_AST_MISC is not set +# CONFIG_HW_RANDOM is not set +CONFIG_NVRAM=y +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_AST=y +CONFIG_I2C_AST1070=y +CONFIG_AST_I2C_SLAVE_MODE=y +CONFIG_AST_I2C_SLAVE_EEPROM=y +# CONFIG_AST_I2C_SLAVE_RDWR is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_AT24 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_TPS65010 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/ast2400_ast1070_defconfig b/arch/arm/configs/ast2400_ast1070_defconfig new file mode 100644 index 000000000000..552523e538cc --- /dev/null +++ b/arch/arm/configs/ast2400_ast1070_defconfig @@ -0,0 +1,1036 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.28.9 +# Mon Jul 15 18:21:08 2013 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_GENERIC_TIME is not set +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_ARCH_ASPEED=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +CONFIG_IRMP=y +# CONFIG_PCEXT is not set +# CONFIG_REMOTEFX is not set +# CONFIG_ARCH_AST1100 is not set +# CONFIG_ARCH_AST2100 is not set +# CONFIG_ARCH_AST2200 is not set +# CONFIG_ARCH_AST2300 is not set +CONFIG_ARCH_AST2400=y +# CONFIG_ARCH_AST2500 is not set + +# +# FLASH Chip Select +# +CONFIG_AST_CS0_NOR=y +# CONFIG_AST_CS0_NAND is not set +# CONFIG_AST_CS0_SPI is not set +# CONFIG_AST_CS0_NONE is not set +CONFIG_AST_CS1_NOR=y +# CONFIG_AST_CS1_NAND is not set +# CONFIG_AST_CS1_SPI is not set +# CONFIG_AST_CS1_NONE is not set +CONFIG_AST_CS2_NOR=y +# CONFIG_AST_CS2_NAND is not set +# CONFIG_AST_CS2_SPI is not set +# CONFIG_AST_CS2_NONE is not set +CONFIG_AST_CS3_NOR=y +# CONFIG_AST_CS3_NAND is not set +# CONFIG_AST_CS3_SPI is not set +# CONFIG_AST_CS3_NONE is not set +CONFIG_AST_CS4_NOR=y +# CONFIG_AST_CS4_NAND is not set +# CONFIG_AST_CS4_SPI is not set +# CONFIG_AST_CS4_NONE is not set +CONFIG_ARCH_AST1070=y +CONFIG_AST1070_NR=2 +CONFIG_AST_LPC_PLUS=y +# CONFIG_AST_LPC is not set +# CONFIG_AST_SCU_LOCK is not set + +# +# Boot options +# + +# +# Power management +# +CONFIG_PLAT_ASPEED=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_ARM_AMBA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_AEABI is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +CONFIG_FPE_NWFPE_XP=y +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +CONFIG_BINFMT_AOUT=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_ARTHUR is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +CONFIG_WAN_ROUTER=y +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_TGT=y +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=m +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_NET_ETHERNET is not set +CONFIG_NETDEV_1000=y +CONFIG_ASPEEDMAC=y +# CONFIG_MAC0_PHY_LINK is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_SERIAL=y +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +# CONFIG_RIO is not set +# CONFIG_STALDRV is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +CONFIG_SERIAL_AST_DMA_UART=y +CONFIG_AST_NR_DMA_UARTS=8 +CONFIG_AST_RUNTIME_DMA_UARTS=8 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_AST is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_AST_MISC is not set +# CONFIG_HW_RANDOM is not set +CONFIG_NVRAM=y +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_AST=y +CONFIG_I2C_AST1070=y +CONFIG_AST_I2C_SLAVE_MODE=y +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_AT24 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_TPS65010 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/ast2400_defconfig b/arch/arm/configs/ast2400_defconfig new file mode 100644 index 000000000000..22b76fe6da26 --- /dev/null +++ b/arch/arm/configs/ast2400_defconfig @@ -0,0 +1,1412 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.28.9 +# Tue Jan 20 09:41:35 2015 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_GENERIC_TIME is not set +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_ARCH_ASPEED=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +CONFIG_IRMP=y +# CONFIG_PCEXT is not set +# CONFIG_REMOTEFX is not set +# CONFIG_ARCH_AST1100 is not set +# CONFIG_ARCH_AST2100 is not set +# CONFIG_ARCH_AST2200 is not set +# CONFIG_ARCH_AST2300 is not set +CONFIG_ARCH_AST2400=y +# CONFIG_ARCH_AST2500 is not set + +# +# FLASH Chip Select +# +# CONFIG_AST_CS0_NOR is not set +# CONFIG_AST_CS0_NAND is not set +# CONFIG_AST_CS0_SPI is not set +CONFIG_AST_CS0_NONE=y +# CONFIG_AST_CS1_NOR is not set +# CONFIG_AST_CS1_NAND is not set +# CONFIG_AST_CS1_SPI is not set +CONFIG_AST_CS1_NONE=y +# CONFIG_AST_CS2_NOR is not set +# CONFIG_AST_CS2_NAND is not set +# CONFIG_AST_CS2_SPI is not set +CONFIG_AST_CS2_NONE=y +# CONFIG_AST_CS3_NOR is not set +# CONFIG_AST_CS3_NAND is not set +# CONFIG_AST_CS3_SPI is not set +CONFIG_AST_CS3_NONE=y +# CONFIG_AST_CS4_NOR is not set +# CONFIG_AST_CS4_NAND is not set +# CONFIG_AST_CS4_SPI is not set +CONFIG_AST_CS4_NONE=y +# CONFIG_ARCH_AST1070 is not set +# CONFIG_AST_SCU_LOCK is not set + +# +# Boot options +# + +# +# Power management +# +CONFIG_PLAT_ASPEED=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_ARM_AMBA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_AEABI is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +CONFIG_FPE_NWFPE_XP=y +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +CONFIG_BINFMT_AOUT=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_ARTHUR is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +CONFIG_WAN_ROUTER=y +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_NBD=y +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_TGT=y +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=m +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +CONFIG_BONDING=y +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_NET_ETHERNET is not set +CONFIG_NETDEV_1000=y +CONFIG_ASPEEDMAC=y +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_SERIAL=y +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +# CONFIG_RIO is not set +# CONFIG_STALDRV is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_AST_DMA_UART is not set +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_AST is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_AST_MISC=y +# CONFIG_AST_VIDEO is not set +# CONFIG_ADC_CAT9883 is not set +# CONFIG_AST_SPI_BIOS is not set +CONFIG_AST_PECI=y +# CONFIG_AST_KCS is not set +# CONFIG_AST_GPIO is not set +# CONFIG_HW_RANDOM is not set +CONFIG_NVRAM=y +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_AST=y +CONFIG_AST_I2C_SLAVE_MODE=y +CONFIG_AST_I2C_SLAVE_EEPROM=y +# CONFIG_AST_I2C_SLAVE_RDWR is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +CONFIG_AT24=y +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_TPS65010 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_SENSORS_AST_ADC=y +CONFIG_SENSORS_AST_PWM_FAN=y +# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_AST_WATCHDOG=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HID_DEBUG=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_AST=y +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# AST USB Drivers +# +CONFIG_AST_USB_UHCI_HCD=y +# CONFIG_AST_USB_UHCI_MULTIPORT_1 is not set +# CONFIG_AST_USB_UHCI_MULTIPORT_2 is not set +CONFIG_AST_USB_UHCI_MULTIPORT_4=y +# CONFIG_USB_EHCI_SPLIT_ISO is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +# + +# +# see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_ARMMMCI is not set +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_AST=y +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_HCTOSYS is not set +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +CONFIG_RTC_DRV_ASPEED=y +# CONFIG_DMADEVICES is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_YAFFS_FS=y +CONFIG_YAFFS_YAFFS1=y +# CONFIG_YAFFS_9BYTE_TAGS is not set +# CONFIG_YAFFS_DOES_ECC is not set +CONFIG_YAFFS_YAFFS2=y +CONFIG_YAFFS_AUTO_YAFFS2=y +# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set +# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set +# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set +# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set +CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y +# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/ast2400_fb_defconfig b/arch/arm/configs/ast2400_fb_defconfig new file mode 100644 index 000000000000..71a1239c711c --- /dev/null +++ b/arch/arm/configs/ast2400_fb_defconfig @@ -0,0 +1,1516 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.28.9 +# Thu Jan 10 10:40:53 2013 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_GENERIC_TIME is not set +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_ARCH_ASPEED=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +CONFIG_IRMP=y +# CONFIG_PCEXT is not set +# CONFIG_REMOTEFX is not set +# CONFIG_ARCH_AST1100 is not set +# CONFIG_ARCH_AST2100 is not set +# CONFIG_ARCH_AST2200 is not set +# CONFIG_ARCH_AST2300 is not set +CONFIG_ARCH_AST2400=y + +# +# FLASH Chip Select +# +# CONFIG_ASPEED_CS0_NOR is not set +# CONFIG_ASPEED_CS0_NAND is not set +CONFIG_ASPEED_CS0_SPI=y +# CONFIG_ASPEED_CS0_NONE is not set +# CONFIG_ASPEED_CS1_NOR is not set +# CONFIG_ASPEED_CS1_NAND is not set +# CONFIG_ASPEED_CS1_SPI is not set +CONFIG_ASPEED_CS1_NONE=y +# CONFIG_ASPEED_CS2_NOR is not set +# CONFIG_ASPEED_CS2_NAND is not set +# CONFIG_ASPEED_CS2_SPI is not set +CONFIG_ASPEED_CS2_NONE=y +# CONFIG_ASPEED_CS3_NOR is not set +# CONFIG_ASPEED_CS3_NAND is not set +# CONFIG_ASPEED_CS3_SPI is not set +CONFIG_ASPEED_CS3_NONE=y +# CONFIG_ASPEED_CS4_NOR is not set +CONFIG_ASPEED_CS4_NAND=y +# CONFIG_ASPEED_CS4_SPI is not set +# CONFIG_ASPEED_CS4_NONE is not set +# CONFIG_ARCH_AST1070 is not set +# CONFIG_ASPEED_SCU_LOCK is not set + +# +# Boot options +# + +# +# Power management +# +CONFIG_PLAT_ASPEED=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_ARM_AMBA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_AEABI is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +CONFIG_FPE_NWFPE_XP=y +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +CONFIG_BINFMT_AOUT=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_ARTHUR is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +CONFIG_WAN_ROUTER=y +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +CONFIG_FIB_RULES=y +# CONFIG_WIRELESS is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +CONFIG_MTD_DATAFLASH=y +# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set +# CONFIG_MTD_DATAFLASH_OTP is not set +CONFIG_MTD_M25P80=y +CONFIG_M25PXX_USE_FAST_READ=y +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_AST=y +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_TGT=y +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=m +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +CONFIG_BONDING=y +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_NET_ETHERNET is not set +CONFIG_NETDEV_1000=y +CONFIG_ASPEEDMAC=y +CONFIG_MAC0_PHY_LINK=y +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_SERIAL=y +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +# CONFIG_RIO is not set +# CONFIG_STALDRV is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_ASPEED is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +CONFIG_NVRAM=y +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_ASPEED=y +CONFIG_AST_I2C_SLAVE_MODE=y +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +CONFIG_AT24=y +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_TPS65010 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_AST is not set +CONFIG_SPI_FMC=y +CONFIG_SPI_BITBANG=y + +# +# SPI Protocol Masters +# +# CONFIG_SPI_AT25 is not set +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_AST_ADC is not set +CONFIG_SENSORS_AST_PWM_FAN=y +# CONFIG_SENSORS_AST_PECI is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_ASPEED_WATCHDOG=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_ARMCLCD is not set +CONFIG_FB_UVESA=y +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_AST=y +CONFIG_AST_DAC=y +# CONFIG_AST_DVO is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HID_DEBUG=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_AST=y +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# AST USB Drivers +# +CONFIG_AST_USB_UHCI_HCD=y +# CONFIG_AST_USB_UHCI_MULTIPORT_1 is not set +# CONFIG_AST_USB_UHCI_MULTIPORT_2 is not set +CONFIG_AST_USB_UHCI_MULTIPORT_4=y +# CONFIG_USB_EHCI_SPLIT_ISO is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +# + +# +# see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_ARMMMCI is not set +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_ASPEED=y +# CONFIG_MMC_SPI is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_HCTOSYS is not set +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +CONFIG_RTC_DRV_ASPEED=y +# CONFIG_DMADEVICES is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_YAFFS_FS=y +CONFIG_YAFFS_YAFFS1=y +# CONFIG_YAFFS_9BYTE_TAGS is not set +# CONFIG_YAFFS_DOES_ECC is not set +CONFIG_YAFFS_YAFFS2=y +CONFIG_YAFFS_AUTO_YAFFS2=y +# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set +# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set +# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set +# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set +CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y +# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/ast2400_slt_defconfig b/arch/arm/configs/ast2400_slt_defconfig new file mode 100644 index 000000000000..fece826af0a3 --- /dev/null +++ b/arch/arm/configs/ast2400_slt_defconfig @@ -0,0 +1,1015 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.28.9 +# Thu Mar 27 14:10:01 2014 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_GENERIC_TIME is not set +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_ARCH_ASPEED=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +CONFIG_IRMP=y +# CONFIG_PCEXT is not set +# CONFIG_REMOTEFX is not set +# CONFIG_ARCH_AST1100 is not set +# CONFIG_ARCH_AST2100 is not set +# CONFIG_ARCH_AST2200 is not set +# CONFIG_ARCH_AST2300 is not set +CONFIG_ARCH_AST2400=y +# CONFIG_ARCH_AST2500 is not set + +# +# FLASH Chip Select +# +# CONFIG_AST_CS0_NOR is not set +# CONFIG_AST_CS0_NAND is not set +CONFIG_AST_CS0_SPI=y +# CONFIG_AST_CS0_NONE is not set +# CONFIG_AST_CS1_NOR is not set +# CONFIG_AST_CS1_NAND is not set +# CONFIG_AST_CS1_SPI is not set +CONFIG_AST_CS1_NONE=y +# CONFIG_AST_CS2_NOR is not set +# CONFIG_AST_CS2_NAND is not set +# CONFIG_AST_CS2_SPI is not set +CONFIG_AST_CS2_NONE=y +# CONFIG_AST_CS3_NOR is not set +# CONFIG_AST_CS3_NAND is not set +# CONFIG_AST_CS3_SPI is not set +CONFIG_AST_CS3_NONE=y +# CONFIG_AST_CS4_NOR is not set +# CONFIG_AST_CS4_NAND is not set +# CONFIG_AST_CS4_SPI is not set +CONFIG_AST_CS4_NONE=y +# CONFIG_ARCH_AST1070 is not set +# CONFIG_AST_SCU_LOCK is not set + +# +# Boot options +# + +# +# Power management +# +CONFIG_PLAT_ASPEED=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_ARM_AMBA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_AEABI is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +CONFIG_FPE_NWFPE_XP=y +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +CONFIG_BINFMT_AOUT=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_ARTHUR is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +CONFIG_MTD_DATAFLASH=y +# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set +# CONFIG_MTD_DATAFLASH_OTP is not set +CONFIG_MTD_M25P80=y +CONFIG_M25PXX_USE_FAST_READ=y +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_AST=y +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_TGT=y +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_SERIAL=y +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +# CONFIG_RIO is not set +# CONFIG_STALDRV is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_AST_DMA_UART is not set +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_AST is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_AST_MISC=y +# CONFIG_AST_VIDEO is not set +# CONFIG_ADC_CAT9883 is not set +# CONFIG_AST_SPI_BIOS is not set +CONFIG_AST_PECI=y +# CONFIG_AST_KCS is not set +# CONFIG_AST_GPIO is not set +# CONFIG_HW_RANDOM is not set +CONFIG_NVRAM=y +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_AST_I2C_SLAVE_EEPROM is not set +# CONFIG_AST_I2C_SLAVE_RDWR is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_AST is not set +CONFIG_SPI_FMC=y +# CONFIG_SPI_BITBANG is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_AT25 is not set +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_TLE62X0 is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_AST_WATCHDOG=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TC6393XB is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_AST=y +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# AST USB Drivers +# +CONFIG_AST_USB_UHCI_HCD=y +# CONFIG_AST_USB_UHCI_MULTIPORT_1 is not set +# CONFIG_AST_USB_UHCI_MULTIPORT_2 is not set +CONFIG_AST_USB_UHCI_MULTIPORT_4=y +# CONFIG_USB_EHCI_SPLIT_ISO is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +# + +# +# see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_ARMMMCI is not set +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_AST=y +# CONFIG_MMC_SPI is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_YAFFS_FS=y +CONFIG_YAFFS_YAFFS1=y +# CONFIG_YAFFS_9BYTE_TAGS is not set +# CONFIG_YAFFS_DOES_ECC is not set +CONFIG_YAFFS_YAFFS2=y +CONFIG_YAFFS_AUTO_YAFFS2=y +# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set +# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set +# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set +# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set +CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y +# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 21e17dc94cb5..8ff0e2379fd8 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -21,6 +21,7 @@ #include <asm/memory.h> #include <asm/thread_info.h> #include <asm/system.h> +#include <asm/mach-types.h> #if (PHYS_OFFSET & 0x001fffff) #error "PHYS_OFFSET must be at an even 2MiB boundary!" @@ -76,13 +77,14 @@ */ .section ".text.head", "ax" ENTRY(stext) + ldr r5, =machine_arch_type @ find the machine type msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode @ and irqs disabled mrc p15, 0, r9, c0, c0 @ get processor id bl __lookup_processor_type @ r5=procinfo r9=cpuid movs r10, r5 @ invalid processor (r5=0)? beq __error_p @ yes, error 'p' - bl __lookup_machine_type @ r5=machinfo +@ bl __lookup_machine_type @ r5=machinfo movs r8, r5 @ invalid machine (r5=0)? beq __error_a @ yes, error 'a' bl __vet_atags diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig new file mode 100644 index 000000000000..a948ab8c4167 --- /dev/null +++ b/arch/arm/mach-aspeed/Kconfig @@ -0,0 +1,214 @@ +if ARCH_ASPEED + +choice + prompt "ASPEED Processor Family" + default CONFIG_IRMP + +config IRMP + bool "IRMP Serials" + +config PCEXT + bool "PC Extender Serials" + +config REMOTEFX + bool "RemoteFX Zero-Client Serials" + +endchoice + +if IRMP + +choice + prompt "IRMP Serials" + default CONFIG_ARCH_AST2300 + +config ARCH_AST1100 + bool "AST1100" + +config ARCH_AST2100 + bool "AST2100" + +config ARCH_AST2200 + bool "AST2200" + +config ARCH_AST2300 + bool "AST2300" + +config ARCH_AST2400 + select USB_ARCH_HAS_EHCI + bool "AST2400" + +config ARCH_AST2500 + select USB_ARCH_HAS_EHCI + bool "AST2500" + +endchoice + +endif + +if PCEXT + +choice + prompt "PC Extender Serials" + default CONFIG_ARCH_AST1510 + +config ARCH_AST1500 + bool "AST1500" + +config ARCH_AST1510 + bool "AST1510" + +config ARCH_AST1520 + select USB_ARCH_HAS_EHCI + bool "AST1520" + +endchoice + +endif + +if REMOTEFX + +choice + prompt "RemoteFX Zero-Client Serials" + default CONFIG_ARCH_AST3100 + +config ARCH_AST3100 + select USB_ARCH_HAS_EHCI + bool "AST3100" + +config ARCH_AST3200 + select USB_ARCH_HAS_EHCI + bool "AST3200" + +endchoice + +endif + +menu "FLASH Chip Select" + +choice + prompt "CS0 Config" + default CONFIG_AST_CS0_SPI + +config AST_CS0_NOR + bool "NOR" + +config AST_CS0_NAND + bool "NAND" + +config AST_CS0_SPI + bool "SPI_NOR" + +config AST_CS0_NONE + bool "NONE" + +endchoice + +choice + prompt "CS1 Config" + default CONFIG_AST_CS1_SPI + +config AST_CS1_NOR + bool "NOR" + +config AST_CS1_NAND + bool "NAND" + +config AST_CS1_SPI + bool "SPI_NOR" + +config AST_CS1_NONE + bool "NONE" + +endchoice + +choice + prompt "CS2 Config" + default CONFIG_AST_CS2_SPI + +config AST_CS2_NOR + bool "NOR" + +config AST_CS2_NAND + bool "NAND" + +config AST_CS2_SPI + bool "SPI_NOR" + +config AST_CS2_NONE + bool "NONE" + +endchoice + +choice + prompt "CS3 Config" + default CONFIG_AST_CS3_SPI + +config AST_CS3_NOR + bool "NOR" + +config AST_CS3_NAND + bool "NAND" + +config AST_CS3_SPI + bool "SPI_NOR" + +config AST_CS3_NONE + bool "NONE" + +endchoice + +choice + prompt "CS4 Config" + default CONFIG_AST_CS4_SPI + +config AST_CS4_NOR + bool "NOR" + +config AST_CS4_NAND + bool "NAND" + +config AST_CS4_SPI + bool "SPI_NOR" + +config AST_CS4_NONE + bool "NONE" + +endchoice + +endmenu + +config ARCH_AST1070 + bool "AST1070 Comapnion chip combination" + +config AST1070_NR + int "Number of AST1070 Comapniion Chip combination" + depends on ARCH_AST1070 + default "1" + help + Set this to the number of ast1070 + +choice + prompt "Connect Bus Interface" + depends on ARCH_AST1070 + default CONFIG_AST_LPC_PLUS + +config AST_LPC_PLUS + bool "LPC PLUS" + +config AST_LPC + bool "LPC" + +endchoice + +config AST_SCU_LOCK + bool "AST SCU Protection Key" + +# Support PCIE +config PCIE + bool "ASPEED PCIE support" + depends on PCI && ARCH_ASPEED + select ARCH_SUPPORTS_MSI + help + Socle PCIE support + +endif diff --git a/arch/arm/mach-aspeed/Makefile b/arch/arm/mach-aspeed/Makefile new file mode 100644 index 000000000000..ae63d8cfc8b8 --- /dev/null +++ b/arch/arm/mach-aspeed/Makefile @@ -0,0 +1,22 @@ +# +# Makefile for the linux kernel. +# + +# Common support (must be linked before board specific support) + +# Specific board support +obj-$(CONFIG_ARCH_AST1100) += ast1100.o +obj-$(CONFIG_ARCH_AST2100) += ast2100.o +obj-$(CONFIG_ARCH_AST2300) += ast2300.o gpio.o ast-lpc.o +obj-$(CONFIG_ARCH_AST2400) += ast2400.o gpio.o ast-lpc.o ast-lpc_plus.o +obj-$(CONFIG_ARCH_AST2500) += ast2500.o ast-mctp.o +#PC Ext +obj-$(CONFIG_ARCH_AST1510) += ast1510.o gpio.o +obj-$(CONFIG_ARCH_AST1520) += ast1520.o ast-mctp.o + +#RemoteFx Zero client +obj-$(CONFIG_ARCH_AST3100) += ast3100.o gpio.o +obj-$(CONFIG_ARCH_AST3200) += ast3200.o ast-mctp.o + +#BMC Comapnion Controller +obj-$(CONFIG_ARCH_AST1070) += ast1070.o diff --git a/arch/arm/mach-aspeed/Makefile.boot b/arch/arm/mach-aspeed/Makefile.boot new file mode 100644 index 000000000000..a1e3bf8001bd --- /dev/null +++ b/arch/arm/mach-aspeed/Makefile.boot @@ -0,0 +1,42 @@ +ifeq ($(CONFIG_ARCH_AST1510),y) + zreladdr-y := 0x40008000 +params_phys-y := 0x40000100 +initrd_phys-y := 0x40800000 +endif + +ifeq ($(CONFIG_ARCH_AST2300),y) + zreladdr-y := 0x40008000 +params_phys-y := 0x40000100 +initrd_phys-y := 0x40800000 +endif + +ifeq ($(CONFIG_ARCH_AST2400),y) + zreladdr-y := 0x40008000 +params_phys-y := 0x40000100 +initrd_phys-y := 0x40800000 +endif + +ifeq ($(CONFIG_ARCH_AST2500),y) + zreladdr-y := 0x80008000 +params_phys-y := 0x80000100 +initrd_phys-y := 0x80800000 +endif + +ifeq ($(CONFIG_ARCH_AST3100),y) + zreladdr-y := 0x40008000 +params_phys-y := 0x40000100 +initrd_phys-y := 0x40800000 +endif + +ifeq ($(CONFIG_ARCH_AST1520),y) + zreladdr-y := 0x80008000 +params_phys-y := 0x80000100 +initrd_phys-y := 0x80800000 +endif + +ifeq ($(CONFIG_ARCH_AST3200),y) + zreladdr-y := 0x80008000 +params_phys-y := 0x80000100 +initrd_phys-y := 0x80800000 +endif + diff --git a/arch/arm/mach-aspeed/ast-lpc.c b/arch/arm/mach-aspeed/ast-lpc.c new file mode 100644 index 000000000000..b26e2ccdc6ea --- /dev/null +++ b/arch/arm/mach-aspeed/ast-lpc.c @@ -0,0 +1,423 @@ +/******************************************************************************** +* File Name : arch/arm/mach-aspeed/ast-lpc.c +* Author : Ryan Chen +* Description : AST LPC +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2013/05/15 Ryan Chen Create +* +********************************************************************************/ +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/delay.h> + +#include <mach/platform.h> +#include <asm/io.h> +#include <linux/interrupt.h> + +#include <mach/hardware.h> + +#include <plat/regs-lpc.h> +#include <plat/ast-snoop.h> +#include <plat/ast-lpc.h> +#ifdef CONFIG_ARCH_AST1070 +#include <plat/ast1070-scu.h> +#include <plat/ast1070-devs.h> +#include <plat/regs-ast1070-intc.h> +#include <plat/ast1070-uart-dma.h> +#endif + +//#define AST_LPC_DEBUG + +#ifdef AST_LPC_DEBUG +#define LPCDBUG(fmt, args...) printk("%s() " fmt, __FUNCTION__, ## args) +#else +#define LPCDBUG(fmt, args...) +#endif + +#if 0 +static inline u32 +ast_lpc_read(u32 reg) +{ + u32 val; + + val = readl(ast_lpc_base + reg); + + LPCDBUG("ast_lpc_read : reg = 0x%08x, val = 0x%08x\n", reg, val); + + return val; +} + +static inline void +ast_lpc_write(u32 val, u32 reg) +{ + LPCDBUG("ast_lpc_write : reg = 0x%08x, val = 0x%08x\n", reg, val); + writel(val, ast_lpc_base + reg); +} + +/******************************************************************************/ + +//Suppose you are going to snoop 0x80 ~ 0x87 +//snoop_init(0x80, 0x7, WORD_MODE, buf_dma, (SNOOP_DMA_BOUNDARY / 4)); //register in unit of DWORD +#if 0 +extern void +ast_lpc_snoop_dma_enable(u16 port_number, u8 port_mask, u8 mode, dma_addr_t dma_base, u16 size) +{ + write_register(0x1e789134, (port_mask << 16) + port_number); + write_register(0x1e7890d0, dma_base); + write_register(0x1e7890d4, (size - 1)); + write_register(0x1e789130, (mode << 4) | ENABLE_DMA_INTERRUPT | ENABLE_POST_CODE_FUNCTION | ENABLE_SNOOP_DMA_MODE); + + //Enable error interrupt to check LPC reset + write_register_or(0x1e789008, 1); + +} + +EXPORT_SYMBOL(ast_lpc_snoop_dma_init); +#endif + +extern irqreturn_t ast_snoop_handler(int this_irq, void *dev_id) +{ + u32 snoop_sts; + struct ast_snoop *snoop = dev_id; + + snoop_sts = ast_lpc_read(AST_LPC_HICR6); + if((snoop_sts & (LPC_HICR6_STR_SNP1W | LPC_HICR6_STR_SNP0W)) == 0) + return IRQ_NONE; + + if(snoop_sts & LPC_HICR6_STR_SNP0W) { + snoop->snoop_ch0->snoop_data = GET_LPC_SNPD0(ast_lpc_read(AST_LPC_SNPWDR)); + //clear + ast_lpc_write(LPC_HICR6_STR_SNP0W, AST_LPC_HICR6); + } + + if(snoop_sts & LPC_HICR6_STR_SNP1W) { + snoop->snoop_ch1->snoop_data = GET_LPC_SNPD1(ast_lpc_read(AST_LPC_SNPWDR)); + //clear + ast_lpc_write(LPC_HICR6_STR_SNP1W, AST_LPC_HICR6); + + } + + return IRQ_HANDLED; + +} +EXPORT_SYMBOL(ast_snoop_handler); + +extern irqreturn_t ast_snoop_dma_handler(int this_irq, void *dev_id) +{ + u32 snoop_dma_sts, lpc_sts; + struct ast_snoop_dma_channel *snoop_dma_ch = dev_id; + + snoop_dma_sts = ast_lpc_read(AST_LPC_PCCR2); + + lpc_sts = ast_lpc_read(AST_LPC_HICR2); + + printk("ISR : snoop_dma_sts = %x , lpc_sts = %x \n",snoop_dma_sts, lpc_sts); + + if(lpc_sts & LPC_LRST) { + printk("LPC RST === > \n"); + //clear fifo ?? + ast_lpc_write(ast_lpc_read(AST_LPC_PCCR0) | LPC_RX_FIFO_CLR, AST_LPC_PCCR0); + //clear + ast_lpc_write(lpc_sts & ~LPC_LRST, AST_LPC_HICR2); + + } + + if(snoop_dma_sts & LPC_POST_CODE_DMA_RDY) { + + + } + + + return IRQ_HANDLED; + +} +EXPORT_SYMBOL(ast_snoop_dma_handler); + +extern void ast_snoop_channel_int_enable(struct ast_snoop_channel *ast_ch, u8 enable) +{ + printk("ch[%d]int : %s , snoop port : %x",ast_ch->snoop_ch, enable? "Enable":"Disable", ast_ch->snoop_port); + + if(enable) { + switch(ast_ch->snoop_ch) { + case 0: + //enable + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) | LPC_HICR5_SNP0INT_EN, + AST_LPC_HICR5); + break; + case 1: + //enable + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) | LPC_HICR5_SNP1INT_EN, + AST_LPC_HICR5); + break; + }; + + } else { + switch(ast_ch->snoop_ch) { + case 0: + //disable + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) & ~LPC_HICR5_SNP0INT_EN, + AST_LPC_HICR5); + + break; + case 1: + //disable + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) & ~LPC_HICR5_SNP1INT_EN, + AST_LPC_HICR5); + }; + + } + +} +EXPORT_SYMBOL(ast_snoop_channel_int_enable); + +extern void ast_snoop_channel_enable(struct ast_snoop_channel *ast_ch, u8 enable) +{ + printk("ch[%d] : %s , snoop port : %x",ast_ch->snoop_ch, enable? "Enable":"Disable", ast_ch->snoop_port); + + if(enable) { + switch(ast_ch->snoop_ch) { + case 0: + //disable + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) & ~LPC_HICR5_SNP0W_EN, + AST_LPC_HICR5); + + //set port address + ast_lpc_write((ast_lpc_read(AST_LPC_SNPWADR) & ~LPC_SNOOP_ADDR0_MASK) | + ast_ch->snoop_port, + AST_LPC_SNPWADR); + //enable + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) | LPC_HICR5_SNP0W_EN, + AST_LPC_HICR5); + break; + case 1: + //disable + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) & ~LPC_HICR5_SNP1W_EN, + AST_LPC_HICR5); + + //set port address + ast_lpc_write((ast_lpc_read(AST_LPC_SNPWADR) & ~LPC_SNOOP_ADDR1_MASK) | + ast_ch->snoop_port, + AST_LPC_SNPWADR); + //enable + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) | LPC_HICR5_SNP1W_EN, + AST_LPC_HICR5); + break; + }; + + } else { + switch(ast_ch->snoop_ch) { + case 0: + //disable + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) & ~LPC_HICR5_SNP0W_EN, + AST_LPC_HICR5); + + break; + case 1: + //disable + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) & ~LPC_HICR5_SNP1W_EN, + AST_LPC_HICR5); + + }; + + } + +} +EXPORT_SYMBOL(ast_snoop_channel_enable); + +extern void ast_snoop_dma_ch_enable(struct ast_snoop_dma_channel *ast_dma_ch, u8 enable) +{ + printk("ch[%d] : %s , snoop port : %x",ast_dma_ch->snoop_ch, enable? "Enable":"Disable", ast_dma_ch->snoop_port); + + if(enable) { + //disable + ast_lpc_write(ast_lpc_read(AST_LPC_PCCR0) & ~LPC_POST_CODE_EN, + AST_LPC_PCCR0); + + //set port address + ast_lpc_write((ast_lpc_read(AST_LPC_PCCR0) & ~LPC_POST_ADDR_MASK) | + LPC_CAPTURE_ADDR_MASK(ast_dma_ch->snoop_mask) | + LPC_CAPTURE_BASE_ADDR(ast_dma_ch->snoop_port), + AST_LPC_PCCR0); + + ast_lpc_write(ast_dma_ch->dma_addr, AST_LPC_PCCR4); + ast_lpc_write(ast_dma_ch->dma_size - 1 , AST_LPC_PCCR5); + + //enable + ast_lpc_write((ast_lpc_read(AST_LPC_PCCR0) & ~LPC_POST_CODE_MODE_MASK) | + LPC_POST_CODE_MODE(ast_dma_ch->snoop_mode) | + LPC_POST_DMA_MODE_EN | + LPC_POST_CODE_EN, + AST_LPC_PCCR0); + + } else { + //disable + ast_lpc_write(ast_lpc_read(AST_LPC_PCCR0) & ~LPC_POST_CODE_EN, + AST_LPC_PCCR0); + } + +} +EXPORT_SYMBOL(ast_snoop_dma_ch_enable); + +extern int ast_snoop_init(struct ast_snoop *snoop) +{ + int ret=0; + + ast_snoop_channel_enable(snoop->snoop_ch0, 1); + ast_snoop_channel_enable(snoop->snoop_ch1, 1); + //request irq + ret = request_irq(IRQ_LPC, ast_snoop_handler, IRQF_SHARED, + "ast-snoop", snoop); + + //enable irq + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) | LPC_HICR5_SNP0INT_EN | LPC_HICR5_SNP1INT_EN, + AST_LPC_HICR5); + return ret; +} +EXPORT_SYMBOL(ast_snoop_init); + +extern void ast_snoop_dma_init(struct ast_snoop_dma_channel *ast_dma_ch) +{ + int ret=0; + + ast_snoop_dma_ch_enable(ast_dma_ch, 1); + + //request irq + ret = request_irq(IRQ_LPC, ast_snoop_dma_handler, IRQF_SHARED, + "ast-snoop", ast_dma_ch); + + //enable irq + ast_lpc_write(ast_lpc_read(AST_LPC_PCCR0) | + LPC_POST_DMA_INT_EN, + AST_LPC_PCCR0); + + return ret; + +} +EXPORT_SYMBOL(ast_snoop_dma_init); +#endif +static struct ast_lpc_driver_data *lpc_driver_data; + +static int __devinit ast_lpc_probe(struct platform_device *pdev) +{ +// const struct platform_device_id *id = platform_get_device_id(pdev); + struct resource *res; + int ret = 0; + int i; + + lpc_driver_data = kzalloc(sizeof(struct ast_lpc_driver_data), GFP_KERNEL); + if (lpc_driver_data == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } + + lpc_driver_data->pdev = pdev; + + lpc_driver_data->bus_info = pdev->dev.platform_data; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "no memory resource defined\n"); + ret = -ENODEV; + goto err_free; + } + + res = request_mem_region(res->start, resource_size(res), pdev->name); + if (res == NULL) { + dev_err(&pdev->dev, "failed to request memory resource\n"); + ret = -EBUSY; + goto err_free; + } + + lpc_driver_data->reg_base = ioremap(res->start, resource_size(res)); + if (lpc_driver_data->reg_base == NULL) { + dev_err(&pdev->dev, "failed to ioremap() registers\n"); + ret = -ENODEV; + goto err_free_mem; + } + +#ifdef CONFIG_ARCH_AST1070 + if(lpc_driver_data->bus_info->bus_scan) { + printk("LPC Scan Device... \n"); + for(i=0;i<lpc_driver_data->bus_info->scan_node;i++) { + ast1070_scu_init(i ,lpc_driver_data->bus_info->bridge_phy_addr + i*0x10000); + printk("C%d-[%x] ", i, ast1070_revision_id_info(i)); + ast1070_vic_init(i, (lpc_driver_data->bus_info->bridge_phy_addr + i*0x10000), IRQ_C0_VIC_CHAIN + i, IRQ_C0_VIC_CHAIN_START + (i*AST_CVIC_NUM)); + ast1070_scu_dma_init(i); + ast1070_uart_dma_init(i, lpc_driver_data->bus_info->bridge_phy_addr); + ast_add_device_cuart(i,lpc_driver_data->bus_info->bridge_phy_addr + i*0x10000); + ast_add_device_ci2c(i,lpc_driver_data->bus_info->bridge_phy_addr + i*0x10000); + } + printk("\n"); + + } + +#endif + + platform_set_drvdata(pdev, lpc_driver_data); + return 0; + +err_free_mem: + release_mem_region(res->start, resource_size(res)); +err_free: + kfree(lpc_driver_data); + + return ret; +} + +static int __devexit ast_lpc_remove(struct platform_device *pdev) +{ + struct ast_lpc_driver_data *lpc_driver_data; + struct resource *res; + + lpc_driver_data = platform_get_drvdata(pdev); + if (lpc_driver_data == NULL) + return -ENODEV; + + iounmap(lpc_driver_data->reg_base); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(res->start, resource_size(res)); + + kfree(lpc_driver_data); + + return 0; +} + +static struct platform_driver ast_lpc_driver = { + .driver = { + .name = "ast_lpc", + .owner = THIS_MODULE, + }, + .probe = ast_lpc_probe, + .remove = __devexit_p(ast_lpc_remove), +// .id_table = pwm_id_table, +}; + +static int __init ast_lpc_init(void) +{ + return platform_driver_register(&ast_lpc_driver); +} +arch_initcall(ast_lpc_init); + +static void __exit ast_lpc_exit(void) +{ + platform_driver_unregister(&ast_lpc_driver); +} +module_exit(ast_lpc_exit); + +MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/mach-aspeed/ast-lpc_plus.c b/arch/arm/mach-aspeed/ast-lpc_plus.c new file mode 100644 index 000000000000..187b8b816b55 --- /dev/null +++ b/arch/arm/mach-aspeed/ast-lpc_plus.c @@ -0,0 +1,182 @@ +/******************************************************************************** +* File Name : arch/arm/mach-aspeed/ast-lpc_plus.c +* Author : Ryan Chen +* Description : AST LPC +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2013/05/15 Ryan Chen Create +* +********************************************************************************/ +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/delay.h> + +#include <mach/platform.h> +#include <asm/io.h> +#include <linux/interrupt.h> + +#include <mach/hardware.h> + +#include <plat/regs-lpc.h> +#include <plat/ast-snoop.h> +#include <plat/ast-lpc.h> +#ifdef CONFIG_ARCH_AST1070 +#include <plat/ast1070-scu.h> +#include <plat/ast1070-devs.h> +#include <plat/regs-ast1070-intc.h> +#include <plat/ast1070-uart-dma.h> +#endif + +//#define AST_LPCP_DEBUG + +#ifdef AST_LPCP_DEBUG +#define LPCP_DBUG(fmt, args...) printk("%s() " fmt, __FUNCTION__, ## args) +#else +#define LPCP_DBUG(fmt, args...) +#endif + +#if 0 +static inline u32 +ast_lpc_plus_write(u32 reg) +{ + u32 val; + + val = readl(ast_lpc_base + reg); + + LPCDBUG("ast_lpc_read : reg = 0x%08x, val = 0x%08x\n", reg, val); + + return val; +} + +static inline void +ast_lpc_plus_write(u32 val, u32 reg) +{ + LPCDBUG("ast_lpc_write : reg = 0x%08x, val = 0x%08x\n", reg, val); + writel(val, ast_lpc_base + reg); +} +#endif + +static int __devinit ast_lpc_plus_probe(struct platform_device *pdev) +{ + static struct ast_lpc_driver_data *lpc_plus_driver_data; +// const struct platform_device_id *id = platform_get_device_id(pdev); + struct resource *res; + int ret = 0; + int i; + + lpc_plus_driver_data = kzalloc(sizeof(struct ast_lpc_driver_data), GFP_KERNEL); + if (lpc_plus_driver_data == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } + + lpc_plus_driver_data->pdev = pdev; + + lpc_plus_driver_data->bus_info = pdev->dev.platform_data; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "no memory resource defined\n"); + ret = -ENODEV; + goto err_free; + } + + res = request_mem_region(res->start, resource_size(res), pdev->name); + if (res == NULL) { + dev_err(&pdev->dev, "failed to request memory resource\n"); + ret = -EBUSY; + goto err_free; + } + + lpc_plus_driver_data->reg_base = ioremap(res->start, resource_size(res)); + if (lpc_plus_driver_data->reg_base == NULL) { + dev_err(&pdev->dev, "failed to ioremap() registers\n"); + ret = -ENODEV; + goto err_free_mem; + } + +#ifdef CONFIG_ARCH_AST1070 + if(lpc_plus_driver_data->bus_info->bus_scan) { + printk("LPC PLUS Scan Device... "); + for(i=0;i<lpc_plus_driver_data->bus_info->scan_node;i++) { + ast1070_scu_init(i ,lpc_plus_driver_data->bus_info->bridge_phy_addr + i*0x10000); + printk("C%d-[%x] ", i, ast1070_revision_id_info(i)); + ast1070_vic_init(i, (lpc_plus_driver_data->bus_info->bridge_phy_addr + i*0x10000), IRQ_C0_VIC_CHAIN + i, IRQ_C0_VIC_CHAIN_START + (i*AST_CVIC_NUM)); + ast1070_scu_dma_init(i); + ast1070_uart_dma_init(i, lpc_plus_driver_data->bus_info->bridge_phy_addr); + ast_add_device_cuart(i,lpc_plus_driver_data->bus_info->bridge_phy_addr + i*0x10000); + ast_add_device_ci2c(i,lpc_plus_driver_data->bus_info->bridge_phy_addr + i*0x10000); + } + printk("\n"); + + } + +#endif + + platform_set_drvdata(pdev, lpc_plus_driver_data); + return 0; + +err_free_mem: + release_mem_region(res->start, resource_size(res)); +err_free: + kfree(lpc_plus_driver_data); + + return ret; +} + +static int __devexit ast_lpc_plus_remove(struct platform_device *pdev) +{ + struct ast_lpc_driver_data *lpc_plus_driver_data; + struct resource *res; + + lpc_plus_driver_data = platform_get_drvdata(pdev); + if (lpc_plus_driver_data == NULL) + return -ENODEV; + + iounmap(lpc_plus_driver_data->reg_base); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(res->start, resource_size(res)); + + kfree(lpc_plus_driver_data); + + return 0; +} + +static struct platform_driver ast_lpc_plus_driver = { + .driver = { + .name = "ast_lpc_plus", + .owner = THIS_MODULE, + }, + .probe = ast_lpc_plus_probe, + .remove = __devexit_p(ast_lpc_plus_remove), +// .id_table = pwm_id_table, +}; + +static int __init ast_lpc_plus_init(void) +{ + return platform_driver_register(&ast_lpc_plus_driver); +} +arch_initcall(ast_lpc_plus_init); + +static void __exit ast_lpc_plus_exit(void) +{ + platform_driver_unregister(&ast_lpc_plus_driver); +} +module_exit(ast_lpc_plus_exit); + +MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/mach-aspeed/ast-mctp.c b/arch/arm/mach-aspeed/ast-mctp.c new file mode 100644 index 000000000000..1dd746b2bbe2 --- /dev/null +++ b/arch/arm/mach-aspeed/ast-mctp.c @@ -0,0 +1,153 @@ +/******************************************************************************** +* File Name : arch/arm/mach-aspeed/ast-mctp.c +* Author : Ryan Chen +* Description : AST MCTP Ctrl +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +* History : +* 1. 2013/07/15 Ryan Chen Create +* +********************************************************************************/ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/delay.h> + +#include <mach/platform.h> +#include <asm/io.h> + +#include <mach/hardware.h> +#include <plat/regs-mctp.h> +#include <plat/ast_mctp.h> + +//#define AST_MCTP_DEBUG 1 + +#ifdef AST_MCTP_DEBUG +#define MCTPDBUG(fmt, args...) printk("%s() " fmt, __FUNCTION__, ## args) +#else +#define MCTPDBUG(fmt, args...) +#endif + +static u32 ast_mctp_base = 0; +static u8 txTag = 0; +static inline u32 +ast_mctp_read(u32 reg) +{ + u32 val; + + val = readl(ast_mctp_base + reg); + + MCTPDBUG("reg = 0x%08x, val = 0x%08x\n", reg, val); + + return val; +} + +static inline void +ast_mctp_write(u32 val, u32 reg) +{ + MCTPDBUG("reg = 0x%08x, val = 0x%08x\n", reg, val); + + writel(val, ast_mctp_base + reg); +} + +//***********************************Information *********************************** + +extern void ast_pcie_cfg_read(u8 type, u32 bdf_offset, u32 *value) +{ + u32 timeout =0; + u32 desc3,desc2; + txTag %= 0xf; +// printf("type = %d, busfunc = %x \n",type, bdf); + if((ast_mctp_read(AST_MCTP_INT) & MCTP_RX_COMPLETE) != 0) + printk("EEEEEEEE \n"); + + ast_mctp_write(0x4000001 | (type << 24), AST_MCTP_TX_DESC3); + ast_mctp_write(0x200f | (txTag << 8), AST_MCTP_TX_DESC2); + ast_mctp_write(bdf_offset, AST_MCTP_TX_DESC1); + ast_mctp_write(0, AST_MCTP_TX_DESC0); +// ast_mctp_write(0, AST_MCTP_TX_DATA); + + //trigger + ast_mctp_write(7, AST_MCTP_CTRL); + //wait +// printf("trigger \n"); + while(!(ast_mctp_read(AST_MCTP_INT) & MCTP_RX_COMPLETE)) { + timeout++; + if(timeout > 10000) { + printk("time out \n"); + *value = 0xffffffff; + goto out; + } + }; + + //read + desc3 = ast_mctp_read(AST_MCTP_RX_DESC3); + desc2 = ast_mctp_read(AST_MCTP_RX_DESC2); + ast_mctp_read(AST_MCTP_RX_DESC1); + + if( ((desc3 >> 24) == 0x4A) && + ((desc3 & 0xfff) == 0x1) && + ((desc2 & 0xe000) == 0)) { + *value = ast_mctp_read(AST_MCTP_RX_DATA); + + } else { + *value = 0xffffffff; + + } + +out: + txTag++; + ast_mctp_write(0x15, AST_MCTP_CTRL); + ast_mctp_write(0x3, AST_MCTP_INT); + //wait + while(ast_mctp_read(AST_MCTP_INT) & MCTP_RX_COMPLETE); + +} + +extern void ast_pcie_cfg_write(u8 type, u32 bdf_offset, u32 data) +{ + txTag %= 0xf; + + ast_mctp_write(0x44000001 | (type << 24), AST_MCTP_TX_DESC3); + ast_mctp_write(0x200f | (txTag << 8), AST_MCTP_TX_DESC2); + ast_mctp_write(bdf_offset, AST_MCTP_TX_DESC1); + ast_mctp_write(0, AST_MCTP_TX_DESC0); + ast_mctp_write(data, AST_MCTP_TX_DATA); + + //trigger + ast_mctp_write(7, AST_MCTP_CTRL); +// printf("trigger \n"); + //wait + while(!(ast_mctp_read(AST_MCTP_INT) & MCTP_RX_COMPLETE)); + + //read + ast_mctp_read(AST_MCTP_RX_DESC3); + ast_mctp_read(AST_MCTP_RX_DESC2); + ast_mctp_read(AST_MCTP_RX_DESC1); + txTag++; + ast_mctp_write(0x15, AST_MCTP_CTRL); + ast_mctp_write(0x3, AST_MCTP_INT); + //wait + while(ast_mctp_read(AST_MCTP_INT) & MCTP_RX_COMPLETE); + +} + +static int __init ast_mctp_init(void) +{ + MCTPDBUG("\n"); + ast_mctp_base = (u32)ioremap(AST_MCTP_BASE , SZ_256); + return 0; +} + +subsys_initcall(ast_mctp_init); + diff --git a/arch/arm/mach-aspeed/ast1070.c b/arch/arm/mach-aspeed/ast1070.c new file mode 100644 index 000000000000..12ede8b700c8 --- /dev/null +++ b/arch/arm/mach-aspeed/ast1070.c @@ -0,0 +1,60 @@ +/* + * linux/arch/arm/mach-ast1070/ast1070.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +//#include <linux/config.h> +#include <linux/types.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/init.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <plat/devs.h> +#include <plat/ast1070-scu.h> +#include <plat/ast1070-uart-dma.h> +#include <mach/time.h> +#include <mach/gpio.h> + +static int __init ast1070_init(void) +{ + int i=0; + u8 num = 0; + if(gpio_get_value(PIN_GPIOI2)) + num = 2; //dual 1070 + else + num = 1; //single 1070 + + if(CONFIG_AST1070_NR != num) + printk("Please check Configuration !!! \n"); + +#if 0 + if(gpio_get_value(PIN_GPIOI1)) + printk("Use LPC+ Bus Access \n"); + else + printk("Use LPC Bus Access \n"); +#endif + + for(i=0; i< CONFIG_AST1070_NR;i++) { + ast1070_scu_revision_id(i); + ast1070_dma_init(i); + ast1070_uart_dma_init(i); + } + + return 0; +} + +subsys_initcall(ast1070_init); + diff --git a/arch/arm/mach-aspeed/ast1100.c b/arch/arm/mach-aspeed/ast1100.c new file mode 100644 index 000000000000..e2629f1f78ea --- /dev/null +++ b/arch/arm/mach-aspeed/ast1100.c @@ -0,0 +1,49 @@ +/* + * linux/arch/arm/mach-ast2000/ast2000.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +//#include <linux/config.h> +#include <linux/types.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/init.h> + +#include <mach/hardware.h> +#include <asm/irq.h> +#include <asm/setup.h> +#include <asm/mach-types.h> + +#include <asm/mach/arch.h> +#include <mach/time.h> + +extern void aspeed_map_io(void); +extern void aspeed_init_irq(void); +extern struct sys_timer aspeed_timer; + +static void __init aspeed_init(void) +{ + ast_add_all_devices(); +} + +MACHINE_START(ASPEED, "AST1100") + .phys_io = ASPEED_IO_START, +// .phys_ram = ASPEED_SDRAM_BASE, + .io_pg_offst = (IO_ADDRESS(IO_START)>>18) & 0xfffc, + .map_io = aspeed_map_io, + .timer = &aspeed_timer, + .init_irq = aspeed_init_irq, + .init_machine = aspeed_init, +MACHINE_END diff --git a/arch/arm/mach-aspeed/ast2100.c b/arch/arm/mach-aspeed/ast2100.c new file mode 100644 index 000000000000..06da6537ec87 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2100.c @@ -0,0 +1,49 @@ +/* + * linux/arch/arm/mach-ast2100/ast2100.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +//#include <linux/config.h> +#include <linux/types.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/init.h> + +#include <mach/hardware.h> +#include <asm/irq.h> +#include <asm/setup.h> +#include <asm/mach-types.h> + +#include <asm/mach/arch.h> +#include <mach/time.h> + +extern void aspeed_map_io(void); +extern void aspeed_init_irq(void); +extern struct sys_timer aspeed_timer; + +static void __init aspeed_init(void) +{ + ast_add_all_devices(); +} + +MACHINE_START(ASPEED, "AST1100") + .phys_io = ASPEED_IO_START, +// .phys_ram = ASPEED_SDRAM_BASE, + .io_pg_offst = (IO_ADDRESS(IO_START)>>18) & 0xfffc, + .map_io = aspeed_map_io, + .timer = &aspeed_timer, + .init_irq = aspeed_init_irq, + .init_machine = aspeed_init, +MACHINE_END diff --git a/arch/arm/mach-aspeed/ast2300.c b/arch/arm/mach-aspeed/ast2300.c new file mode 100644 index 000000000000..a223d741736e --- /dev/null +++ b/arch/arm/mach-aspeed/ast2300.c @@ -0,0 +1,206 @@ +/* + * linux/arch/arm/mach-ast2300/ast2300.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/list.h> +#include <linux/slab.h> +#include <linux/string.h> +#include <linux/sysdev.h> +#include <asm/mach-types.h> +#include <asm/mach/irq.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <mach/time.h> +#include <mach/hardware.h> +#include <plat/devs.h> + +#include "core.h" + +static struct map_desc ast_io_desc[] __initdata = { + { + .virtual = IO_ADDRESS(AST_VIC_BASE), + .pfn = __phys_to_pfn(AST_VIC_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_SCU_BASE), + .pfn = __phys_to_pfn(AST_SCU_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_SDMC_BASE), + .pfn = __phys_to_pfn(AST_SDMC_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MAC0_BASE), + .pfn = __phys_to_pfn(AST_MAC0_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MAC1_BASE), + .pfn = __phys_to_pfn(AST_MAC1_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_CRYPTO_BASE), + .pfn = __phys_to_pfn(AST_CRYPTO_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_XDMA_BASE), + .pfn = __phys_to_pfn(AST_XDMA_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MCTP_BASE), + .pfn = __phys_to_pfn(AST_MCTP_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_SRAM_BASE), + .pfn = __phys_to_pfn(AST_SRAM_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_2D_BASE), + .pfn = __phys_to_pfn(AST_2D_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_GPIO_BASE), + .pfn = __phys_to_pfn(AST_GPIO_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_TIMER_BASE), + .pfn = __phys_to_pfn(AST_TIMER_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART0_BASE), + .pfn = __phys_to_pfn(AST_UART0_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART4_BASE), + .pfn = __phys_to_pfn(AST_UART4_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_WDT_BASE), + .pfn = __phys_to_pfn(AST_WDT_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_VUART0_BASE), + .pfn = __phys_to_pfn(AST_VUART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_PUART_BASE), + .pfn = __phys_to_pfn(AST_PUART_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_LPC_BASE), + .pfn = __phys_to_pfn(AST_LPC_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_PECI_BASE), + .pfn = __phys_to_pfn(AST_PECI_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { +#if defined(CONFIG_ARCH_AST1070) + .virtual = IO_ADDRESS2(AST_C0_VIC_BASE), + .pfn = __phys_to_pfn(AST_C0_VIC_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_SCU_BASE), + .pfn = __phys_to_pfn(AST_C0_SCU_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_I2C_BASE), + .pfn = __phys_to_pfn(AST_C0_I2C_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_UART0_BASE), + .pfn = __phys_to_pfn(AST_C0_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_UART1_BASE), + .pfn = __phys_to_pfn(AST_C0_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_UART2_BASE), + .pfn = __phys_to_pfn(AST_C0_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_UART3_BASE), + .pfn = __phys_to_pfn(AST_C0_UART0_BASE), + + .length = SZ_1K, + .type = MT_DEVICE, + }, { +#endif + .virtual = IO_ADDRESS(AST_UART1_BASE), + .pfn = __phys_to_pfn(AST_UART1_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART2_BASE), + .pfn = __phys_to_pfn(AST_UART2_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART3_BASE), + .pfn = __phys_to_pfn(AST_UART3_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +void __init ast_map_io(void) +{ + iotable_init(ast_io_desc, ARRAY_SIZE(ast_io_desc)); +} + +static void __init ast_init(void) +{ + ast_add_all_devices(); +} + +MACHINE_START(ASPEED, "AST2300") + .phys_io = AST_IO_START, +// .phys_ram = AST_SDRAM_BASE, + .io_pg_offst = (IO_ADDRESS(AST_IO_START)>>18) & 0xfffc, + .boot_params = 0x40000100, + .map_io = ast_map_io, + .timer = &ast_timer, + .init_irq = ast_init_irq, + .init_machine = ast_init, +MACHINE_END diff --git a/arch/arm/mach-aspeed/ast2400.c b/arch/arm/mach-aspeed/ast2400.c new file mode 100644 index 000000000000..3567d3c599bd --- /dev/null +++ b/arch/arm/mach-aspeed/ast2400.c @@ -0,0 +1,255 @@ +/* + * linux/arch/arm/mach-ast2300/ast2300.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/list.h> +#include <linux/slab.h> +#include <linux/string.h> +#include <linux/sysdev.h> +#include <asm/mach-types.h> +#include <asm/mach/irq.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <mach/time.h> +#include <mach/hardware.h> +#include <plat/devs.h> + +#include "core.h" + +static struct map_desc ast_io_desc[] __initdata = { + { + .virtual = IO_ADDRESS(AST_VIC_BASE), + .pfn = __phys_to_pfn(AST_VIC_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_SCU_BASE), + .pfn = __phys_to_pfn(AST_SCU_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_SDMC_BASE), + .pfn = __phys_to_pfn(AST_SDMC_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_VIDEO_BASE), + .pfn = __phys_to_pfn(AST_VIDEO_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MAC0_BASE), + .pfn = __phys_to_pfn(AST_MAC0_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MAC1_BASE), + .pfn = __phys_to_pfn(AST_MAC1_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_CRYPTO_BASE), + .pfn = __phys_to_pfn(AST_CRYPTO_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_JTAG_BASE), + .pfn = __phys_to_pfn(AST_JTAG_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_XDMA_BASE), + .pfn = __phys_to_pfn(AST_XDMA_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MCTP_BASE), + .pfn = __phys_to_pfn(AST_MCTP_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_SRAM_BASE), + .pfn = __phys_to_pfn(AST_SRAM_BASE), + .length = SZ_16K*2, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_2D_BASE), + .pfn = __phys_to_pfn(AST_2D_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_GPIO_BASE), + .pfn = __phys_to_pfn(AST_GPIO_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_TIMER_BASE), + .pfn = __phys_to_pfn(AST_TIMER_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART0_BASE), + .pfn = __phys_to_pfn(AST_UART0_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART4_BASE), + .pfn = __phys_to_pfn(AST_UART4_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_WDT_BASE), + .pfn = __phys_to_pfn(AST_WDT_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UDC11_BASE ), + .pfn = __phys_to_pfn(AST_UDC11_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_VUART0_BASE), + .pfn = __phys_to_pfn(AST_VUART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_PUART_BASE), + .pfn = __phys_to_pfn(AST_PUART_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_LPC_BASE), + .pfn = __phys_to_pfn(AST_LPC_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_PECI_BASE), + .pfn = __phys_to_pfn(AST_PECI_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { +#if defined(CONFIG_ARCH_AST1070) + .virtual = IO_ADDRESS2(AST_C0_VIC_BASE), + .pfn = __phys_to_pfn(AST_C0_VIC_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_SCU_BASE), + .pfn = __phys_to_pfn(AST_C0_SCU_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_I2C_BASE), + .pfn = __phys_to_pfn(AST_C0_I2C_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C1_VIC_BASE), + .pfn = __phys_to_pfn(AST_C1_VIC_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C1_SCU_BASE), + .pfn = __phys_to_pfn(AST_C1_SCU_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C1_I2C_BASE), + .pfn = __phys_to_pfn(AST_C1_I2C_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_UART0_BASE), + .pfn = __phys_to_pfn(AST_C0_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_UART1_BASE), + .pfn = __phys_to_pfn(AST_C0_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_UART2_BASE), + .pfn = __phys_to_pfn(AST_C0_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_UART3_BASE), + .pfn = __phys_to_pfn(AST_C0_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C1_UART0_BASE), + .pfn = __phys_to_pfn(AST_C1_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C1_UART1_BASE), + .pfn = __phys_to_pfn(AST_C1_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C1_UART2_BASE), + .pfn = __phys_to_pfn(AST_C1_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C1_UART3_BASE), + .pfn = __phys_to_pfn(AST_C1_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { +#endif + .virtual = IO_ADDRESS(AST_UART1_BASE), + .pfn = __phys_to_pfn(AST_UART1_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART2_BASE), + .pfn = __phys_to_pfn(AST_UART2_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART3_BASE), + .pfn = __phys_to_pfn(AST_UART3_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +void __init ast_map_io(void) +{ + iotable_init(ast_io_desc, ARRAY_SIZE(ast_io_desc)); +} + +static void __init ast_init(void) +{ + ast_add_all_devices(); +} + +MACHINE_START(ASPEED, "AST2400") + .phys_io = AST_IO_START, +// .phys_ram = AST_SDRAM_BASE, + .io_pg_offst = (IO_ADDRESS(AST_IO_START)>>18) & 0xfffc, + .boot_params = 0x40000100, + .map_io = ast_map_io, + .timer = &ast_timer, + .init_irq = ast_init_irq, + .init_machine = ast_init, +MACHINE_END diff --git a/arch/arm/mach-aspeed/ast3100.c b/arch/arm/mach-aspeed/ast3100.c new file mode 100644 index 000000000000..cf220e732e15 --- /dev/null +++ b/arch/arm/mach-aspeed/ast3100.c @@ -0,0 +1,230 @@ +/* + * linux/arch/arm/mach-ast2300/ast2300.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +//#include <linux/config.h> +#include <linux/types.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/init.h> + +#include <mach/hardware.h> +#include <asm/irq.h> +#include <asm/setup.h> +#include <asm/mach-types.h> + +#include <asm/mach/arch.h> +#include <mach/time.h> + +#include <asm/mach/map.h> +#include <plat/devs.h> + +#include "core.h" + +static struct map_desc ast_io_desc[] __initdata = { + { + .virtual = IO_ADDRESS(AST_AHB_CTRL_BASE), + .pfn = __phys_to_pfn(AST_AHB_CTRL_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_NEW_SMC_CONTROLLER_BASE), + .pfn = __phys_to_pfn(AST_NEW_SMC_CONTROLLER_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_LPC_SPI_CONTROLLER_BASE), + .pfn = __phys_to_pfn(AST_LPC_SPI_CONTROLLER_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MIC_BASE), + .pfn = __phys_to_pfn(AST_MIC_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MAC1_BASE), + .pfn = __phys_to_pfn(AST_MAC1_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MAC2_BASE), + .pfn = __phys_to_pfn(AST_MAC2_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_VIC_BASE), + .pfn = __phys_to_pfn(AST_VIC_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_SCU_BASE), + .pfn = __phys_to_pfn(AST_SCU_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_CRYPTO_BASE), + .pfn = __phys_to_pfn(AST_CRYPTO_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_JTAG_BASE), + .pfn = __phys_to_pfn(AST_JTAG_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_I2S_BASE), + .pfn = __phys_to_pfn(AST_I2S_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_GRAPHIC_BASE), + .pfn = __phys_to_pfn(AST_GRAPHIC_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_XDMA_BASE), + .pfn = __phys_to_pfn(AST_XDMA_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MCTP_BASE), + .pfn = __phys_to_pfn(AST_MCTP_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_ADC_BASE), + .pfn = __phys_to_pfn(AST_ADC_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_VIDEO_BASE), + .pfn = __phys_to_pfn(AST_VIDEO_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_SRAM_BASE), + .pfn = __phys_to_pfn(AST_SRAM_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_SDHC_BASE), + .pfn = __phys_to_pfn(AST_SDHC_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_2D_BASE), + .pfn = __phys_to_pfn(AST_2D_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_GPIO_BASE), + .pfn = __phys_to_pfn(AST_GPIO_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_RTC_BASE), + .pfn = __phys_to_pfn(AST_RTC_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_TIMER_BASE), + .pfn = __phys_to_pfn(AST_TIMER_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART0_BASE), + .pfn = __phys_to_pfn(AST_UART0_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART1_BASE), + .pfn = __phys_to_pfn(AST_UART1_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_WDT_BASE), + .pfn = __phys_to_pfn(AST_WDT_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_PWM_BASE), + .pfn = __phys_to_pfn(AST_PWM_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_VUART0_BASE), + .pfn = __phys_to_pfn(AST_VUART0_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_PUART_BASE), + .pfn = __phys_to_pfn(AST_PUART_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_LPC_BASE), + .pfn = __phys_to_pfn(AST_LPC_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_I2C_BASE), + .pfn = __phys_to_pfn(AST_I2C_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_PECI_BASE), + .pfn = __phys_to_pfn(AST_PECI_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART2_BASE), + .pfn = __phys_to_pfn(AST_UART2_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART3_BASE), + .pfn = __phys_to_pfn(AST_UART2_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART4_BASE), + .pfn = __phys_to_pfn(AST_UART2_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +void __init ast_map_io(void) +{ + iotable_init(ast_io_desc, ARRAY_SIZE(ast_io_desc)); +} + +static void __init ast_init(void) +{ + ast_add_all_devices(); +} + +MACHINE_START(ASPEED, "AST2300") + .phys_io = AST_IO_START, +// .phys_ram = AST_SDRAM_BASE, + .io_pg_offst = (IO_ADDRESS(AST_IO_START)>>18) & 0xfffc, + .boot_params = 0x40000100, + .map_io = ast_map_io, + .timer = &ast_timer, + .init_irq = ast_init_irq, + .init_machine = ast_init, +MACHINE_END diff --git a/arch/arm/mach-aspeed/core.h b/arch/arm/mach-aspeed/core.h new file mode 100644 index 000000000000..eb5ac89490bd --- /dev/null +++ b/arch/arm/mach-aspeed/core.h @@ -0,0 +1,25 @@ +/* + * linux/arch/arm/mach-aspeed/core.h + * +* Copyright (C) ASPEED Tech. Corp. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +* + */ + +#ifndef __ASM_ARCH_ASPEED_CORE_H +#define __ASM_ARCH_ASPEED_CORE_H + +extern struct sys_timer ast_timer; + +extern void __init ast_init_irq(void); +#endif diff --git a/arch/arm/mach-aspeed/gpio.c b/arch/arm/mach-aspeed/gpio.c new file mode 100644 index 000000000000..3a633e92827c --- /dev/null +++ b/arch/arm/mach-aspeed/gpio.c @@ -0,0 +1,635 @@ +/* + * linux/arch/arm/plat-aspeed/gpio.c + * + * Support functions for ASPEED GPIO + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * Written by Ryan Chen <ryan_chen@aspeedtech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/sysdev.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include <mach/hardware.h> +#include <asm/irq.h> +#include <mach/irqs.h> +#include <mach/gpio.h> +#include <asm/mach/irq.h> + +#include <plat/regs-gpio.h> +#include <asm-generic/gpio.h> + +//#define AST_GPIO_DEBUG + +#ifdef AST_GPIO_DEBUG +//#define GPIODBUG(fmt, args...) printk("%s() " fmt, __FUNCTION__, ## args) +#define GPIODBUG(fmt, args...) printk(fmt, ## args) + +#else +#define GPIODBUG(fmt, args...) +#endif + +/*************************************************************/ +//GPIO group structure +struct ast_gpio_bank { + int irq; + u32 base; +//TODO remove base + u32 index; + u32 data_offset; + u32 dir_offset; + u32 int_en_offset; + u32 int_type_offset; + u32 int_sts_offset; + u32 rst_tol_offset; + u32 debounce_offset; + u32 cmd_source_offset; + struct gpio_chip chip; + +//#ifdef CONFIG_PM +//#define NR_REGS (7) +// u32 regs[NR_REGS]; +//#endif +}; + +int ast_gpio_to_irq(unsigned gpio) +{ + return (gpio + IRQ_GPIO_CHAIN_START); +} + +EXPORT_SYMBOL(ast_gpio_to_irq); + +int ast_irq_to_gpio(unsigned irq) +{ + return (irq - IRQ_GPIO_CHAIN_START); +} + +EXPORT_SYMBOL(ast_irq_to_gpio); + +static inline u32 +ast_gpio_read(struct ast_gpio_bank *ast_gpio ,u32 offset) +{ + GPIODBUG("base = 0x%08x, offset = 0x%08x \n", ast_gpio->base, offset); + + return readl(ast_gpio->base + offset); +} + +static inline void +ast_gpio_write(struct ast_gpio_bank *ast_gpio , u32 val, u32 offset) +{ + GPIODBUG("base = 0x%08x, offset = 0x%08x, val = 0x%08x\n", ast_gpio->base, offset, val); + writel(val, ast_gpio->base + offset); +} + +/***************************************************************************************/ +static int +ast_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + struct ast_gpio_bank *ast_gpio = container_of(chip, struct ast_gpio_bank, chip); + unsigned long flags; + u32 v; + int ret = -1; + + GPIODBUG("dir_in %s[%d] \n",chip->label, offset); + + local_irq_save(flags); + + v = ast_gpio_read(ast_gpio, ast_gpio->dir_offset); + + v &= ~(GPIO_OUTPUT_MODE << (offset + (ast_gpio->index * 8))); + ast_gpio_write(ast_gpio, v, ast_gpio->dir_offset); + + ret = 0; + + local_irq_restore(flags); + return ret; + +} + +static int +ast_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int val) +{ + struct ast_gpio_bank *ast_gpio = container_of(chip, struct ast_gpio_bank, chip); + unsigned long flags; + u32 v; + int ret = -1; + GPIODBUG("dir_out %s[%d], val %d \n",chip->label, offset, val); + + local_irq_save(flags); + + /* Drive as an output */ + v = ast_gpio_read(ast_gpio, ast_gpio->dir_offset); + + v |= (GPIO_OUTPUT_MODE << (offset + (ast_gpio->index * 8))); + + ast_gpio_write(ast_gpio, v, ast_gpio->dir_offset); + + local_irq_restore(flags); + + ret = 0; + return ret; +} + +static int +ast_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct ast_gpio_bank *ast_gpio = container_of(chip, struct ast_gpio_bank, chip); + unsigned long flags; + u32 v; + + GPIODBUG("Get %s[%d] \n",chip->label, offset); + + local_irq_save(flags); + + v = ast_gpio_read(ast_gpio, ast_gpio->data_offset); + + v &= (1 << (offset + (ast_gpio->index * 8))); + + if(v) + v = 1; + else + v = 0; + + local_irq_restore(flags); + + return v; +} + +static void +ast_gpio_set(struct gpio_chip *chip, unsigned offset, int val) +{ + struct ast_gpio_bank *ast_gpio = container_of(chip, struct ast_gpio_bank, chip); + unsigned long flags; + u32 v; + GPIODBUG("Set %s[%d] = %d\n",chip->label, offset, val); + + local_irq_save(flags); + + /* Set the value */ + + v = ast_gpio_read(ast_gpio, ast_gpio->data_offset); + + if (val) + v |= (1 << (offset + (ast_gpio->index * 8))); + else + v &= ~(1 << (offset + (ast_gpio->index * 8))); + + ast_gpio_write(ast_gpio, v, ast_gpio->data_offset); + + local_irq_restore(flags); +} + + +#define AST_GPIO_BANK(name, gpio_base, index_no, data, dir, int_en, int_type, int_sts, rst_tol, debounce, cmd_s) \ + { \ + .base = gpio_base, \ + .index = index_no, \ + .data_offset = data, \ + .dir_offset = dir, \ + .int_en_offset = int_en, \ + .int_type_offset = int_type, \ + .int_sts_offset = int_sts, \ + .rst_tol_offset = rst_tol, \ + .debounce_offset = debounce, \ + .cmd_source_offset = cmd_s, \ + .chip = { \ + .label = name, \ + .direction_input = ast_gpio_direction_input, \ + .direction_output = ast_gpio_direction_output, \ + .get = ast_gpio_get, \ + .set = ast_gpio_set, \ + .ngpio = GPIO_PER_PORT_PIN_NUM, \ + }, \ + } + +static struct ast_gpio_bank ast_gpio_gp[] = { + AST_GPIO_BANK("GPIOA", IO_ADDRESS(AST_GPIO_BASE), 0, 0x000, 0x004, 0x008, 0x00c, 0x018, 0x01c, 0x040, 0x060), + AST_GPIO_BANK("GPIOB", IO_ADDRESS(AST_GPIO_BASE), 1, 0x000, 0x004, 0x008, 0x00c, 0x018, 0x01c, 0x040, 0x060), + AST_GPIO_BANK("GPIOC", IO_ADDRESS(AST_GPIO_BASE), 2, 0x000, 0x004, 0x008, 0x00c, 0x018, 0x01c, 0x040, 0x060), + AST_GPIO_BANK("GPIOD", IO_ADDRESS(AST_GPIO_BASE), 3, 0x000, 0x004, 0x008, 0x00c, 0x018, 0x01c, 0x040, 0x060), + AST_GPIO_BANK("GPIOE", IO_ADDRESS(AST_GPIO_BASE), 0, 0x020, 0x024, 0x028, 0x02c, 0x038, 0x03c, 0x048, 0x068), + AST_GPIO_BANK("GPIOF", IO_ADDRESS(AST_GPIO_BASE), 1, 0x020, 0x024, 0x028, 0x02c, 0x038, 0x03c, 0x048, 0x068), + AST_GPIO_BANK("GPIOG", IO_ADDRESS(AST_GPIO_BASE), 2, 0x020, 0x024, 0x028, 0x02c, 0x038, 0x03c, 0x048, 0x068), + AST_GPIO_BANK("GPIOH", IO_ADDRESS(AST_GPIO_BASE), 3, 0x020, 0x024, 0x028, 0x02c, 0x038, 0x03c, 0x048, 0x068), + AST_GPIO_BANK("GPIOI", IO_ADDRESS(AST_GPIO_BASE), 0, 0x070, 0x074, 0x098, 0x09c, 0x0a8, 0x0ac, 0x0b0, 0x090), + AST_GPIO_BANK("GPIOJ", IO_ADDRESS(AST_GPIO_BASE), 1, 0x070, 0x074, 0x098, 0x09c, 0x0a8, 0x0ac, 0x0b0, 0x090), + AST_GPIO_BANK("GPIOK", IO_ADDRESS(AST_GPIO_BASE), 2, 0x070, 0x074, 0x098, 0x09c, 0x0a8, 0x0ac, 0x0b0, 0x090), + AST_GPIO_BANK("GPIOL", IO_ADDRESS(AST_GPIO_BASE), 3, 0x070, 0x074, 0x098, 0x09c, 0x0a8, 0x0ac, 0x0b0, 0x090), + AST_GPIO_BANK("GPIOM", IO_ADDRESS(AST_GPIO_BASE), 0, 0x078, 0x07c, 0x0e8, 0x0ec, 0x0f8, 0x0fc, 0x100, 0x0e0), + AST_GPIO_BANK("GPION", IO_ADDRESS(AST_GPIO_BASE), 1, 0x078, 0x07c, 0x0e8, 0x0ec, 0x0f8, 0x0fc, 0x100, 0x0e0), + AST_GPIO_BANK("GPIOO", IO_ADDRESS(AST_GPIO_BASE), 2, 0x078, 0x07c, 0x0e8, 0x0ec, 0x0f8, 0x0fc, 0x100, 0x0e0), + AST_GPIO_BANK("GPIOP", IO_ADDRESS(AST_GPIO_BASE), 3, 0x078, 0x07c, 0x0e8, 0x0ec, 0x0f8, 0x0fc, 0x100, 0x0e0), + AST_GPIO_BANK("GPIOQ", IO_ADDRESS(AST_GPIO_BASE), 0, 0x080, 0x084, 0x118, 0x11c, 0x128, 0x12c, 0x130, 0x110), + AST_GPIO_BANK("GPIOR", IO_ADDRESS(AST_GPIO_BASE), 1, 0x080, 0x084, 0x118, 0x11c, 0x128, 0x12c, 0x130, 0x110), + AST_GPIO_BANK("GPIOS", IO_ADDRESS(AST_GPIO_BASE), 2, 0x080, 0x084, 0x118, 0x11c, 0x128, 0x12c, 0x130, 0x110), +#if defined(CONFIG_ARCH_AST2400) + AST_GPIO_BANK("GPIOT", IO_ADDRESS(AST_GPIO_BASE), 4, 0x080, 0x084, 0x118, 0x11c, 0x128, 0x12c, 0x130, 0x110), + AST_GPIO_BANK("GPIOU", IO_ADDRESS(AST_GPIO_BASE), 0, 0x088, 0x08c, 0x148, 0x14c, 0x158, 0x15c, 0x160, 0x140), + AST_GPIO_BANK("GPIOV", IO_ADDRESS(AST_GPIO_BASE), 1, 0x088, 0x08c, 0x148, 0x14c, 0x158, 0x15c, 0x160, 0x140), + AST_GPIO_BANK("GPIOW", IO_ADDRESS(AST_GPIO_BASE), 2, 0x088, 0x08c, 0x148, 0x14c, 0x158, 0x15c, 0x160, 0x140), + AST_GPIO_BANK("GPIOX", IO_ADDRESS(AST_GPIO_BASE), 3, 0x088, 0x08c, 0x148, 0x14c, 0x158, 0x15c, 0x160, 0x140), + AST_GPIO_BANK("GPIOY", IO_ADDRESS(AST_GPIO_BASE), 0, 0x1e0, 0x1e4, 0x178, 0x17c, 0x188, 0x18c, 0x190, 0x170), + AST_GPIO_BANK("GPIOZ", IO_ADDRESS(AST_GPIO_BASE), 1, 0x1e0, 0x1e4, 0x178, 0x17c, 0x188, 0x18c, 0x190, 0x170), + AST_GPIO_BANK("GPIOAA", IO_ADDRESS(AST_GPIO_BASE), 2, 0x1e0, 0x1e4, 0x178, 0x17c, 0x188, 0x18c, 0x190, 0x170), + AST_GPIO_BANK("GPIOAB", IO_ADDRESS(AST_GPIO_BASE), 3, 0x1e0, 0x1e4, 0x178, 0x17c, 0x188, 0x18c, 0x190, 0x170), +#endif +}; + + +/***************************************************************************************/ +/* + * assuming the pin is muxed as a gpio output, set its value. + */ +int ast_set_gpio_value(unsigned gpio_pin, int value) +{ + u32 data; + u32 gp, pin; + gp = gpio_pin / 8; + pin = gpio_pin % 32; + data = ast_gpio_read(&ast_gpio_gp[gp], ast_gpio_gp[gp].data_offset); + if(value) + data |= (1 << pin); + else + data &= ~(1 << pin); + + GPIODBUG("gp : %d, pin %d, data = %x \n ", gp, pin, data); + ast_gpio_write(&ast_gpio_gp[gp], data, ast_gpio_gp[gp].data_offset); + + return 0; +} +EXPORT_SYMBOL(ast_set_gpio_value); + + +/* + * read the pin's value (works even if it's not muxed as a gpio). + */ +int ast_get_gpio_value(unsigned gpio_pin) +{ + u32 data; + u32 gp, pin; + gp = gpio_pin / 8; + pin = gpio_pin % 32; + data = ast_gpio_read(&ast_gpio_gp[gp], ast_gpio_gp[gp].data_offset); + + GPIODBUG("gp : %d, pin %d, data = %x, value = %d \n ", gp, pin, data, (data >> pin) & 1); + + return ((data >> pin) & 1); +} +EXPORT_SYMBOL(ast_get_gpio_value); + +//timer 0/1/2 +//Debounce time = PCLK * (val+1) +void ast_set_gpio_debounce_timer(int timer, int val) +{ + switch(timer) { + case 0: + writel(val, IO_ADDRESS(AST_GPIO_BASE) + 0x50); + break; + case 1: + writel(val, IO_ADDRESS(AST_GPIO_BASE) + 0x54); + break; + case 2: + writel(val, IO_ADDRESS(AST_GPIO_BASE) + 0x58); + break; + } +} + +EXPORT_SYMBOL(ast_set_gpio_debounce_timer); + +//TODO ...... +//mode 0 : no debounce , 1: set 0x50, 2: 0x54, 3: 0x58 +void ast_set_gpio_debounce(int gpio_port, int mode) +{ +#if 0 + u32 set0, set1; + u16 gp, port; + gp = gpio_port / 4; + port = gpio_port % 4; + set0 = ast_gpio_read(&ast_gpio_gp[gp], ast_gpio_gp[gp].debounce_offset); + set1 = ast_gpio_read(&ast_gpio_gp[gp], ast_gpio_gp[gp].debounce_offset + 0x04); + + switch(port) { + case 0: //A , H , ...... + set0 = port + ast_gpio_write(ast_gpio, val, 0x50); + break; + case 1: + ast_gpio_write(ast_gpio, val, 0x54); + break; + case 2: + ast_gpio_write(ast_gpio, val, 0x58); + break; + case 3: + ast_gpio_write(ast_gpio, val, 0x58); + break; + default: + GPIODBUG("not support \n"); + return; + break; + + } + + ast_gpio_write(&ast_gpio_gp[gp], set0, ast_gpio_gp[gp].debounce_offset); + ast_gpio_write(&ast_gpio_gp[gp], set1, ast_gpio_gp[gp].debounce_offset + 0x04); +#endif +} + +EXPORT_SYMBOL(ast_set_gpio_debounce); + +//TODO ...... +// +void ast_set_gpio_tolerant(int gpio_port, int mode) +{ +#if 0 + u32 set0, set1; + u16 gp, port; + gp = gpio_port / 4; + port = gpio_port % 4; + set0 = ast_gpio_read(&ast_gpio_gp[gp], ast_gpio_gp[gp].debounce_offset); + set1 = ast_gpio_read(&ast_gpio_gp[gp], ast_gpio_gp[gp].debounce_offset + 0x04); + + switch(port) { + case 0: //A , H , ...... + set0 = port + ast_gpio_write(ast_gpio, val, 0x50); + break; + case 1: + ast_gpio_write(ast_gpio, val, 0x54); + break; + case 2: + ast_gpio_write(ast_gpio, val, 0x58); + break; + case 3: + ast_gpio_write(ast_gpio, val, 0x58); + break; + default: + GPIODBUG("not support \n"); + return; + break; + + } + + ast_gpio_write(&ast_gpio_gp[gp], set0, ast_gpio_gp[gp].debounce_offset); + ast_gpio_write(&ast_gpio_gp[gp], set1, ast_gpio_gp[gp].debounce_offset + 0x04); +#endif +} + +EXPORT_SYMBOL(ast_set_gpio_tolerant); + +/* + * We need to unmask the GPIO bank interrupt as soon as possible to + * avoid missing GPIO interrupts for other lines in the bank. + * Then we need to mask-read-clear-unmask the triggered GPIO lines + * in the bank to avoid missing nested interrupts for a GPIO line. + * If we wait to unmask individual GPIO lines in the bank after the + * line's interrupt handler has been run, we may miss some nested + * interrupts. + */ +static void +ast_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + u32 isr; + int i,j; + struct ast_gpio_bank *ast_gpio; + + if(irq != IRQ_GPIO) + BUG(); + + GPIODBUG("ast_gpio_irq_handler %d \n ", irq); + +// ast_gpio = get_irq_data(irq); + +// GPIODBUG("[%s] ------\n ",ast_gpio->chip.label ); + + desc->chip->ack(IRQ_GPIO); + + for (i = 0; i < GPIO_PORT_NUM; i++) { + ast_gpio = &ast_gpio_gp[i]; + isr = ast_gpio_read(ast_gpio, ast_gpio->int_sts_offset); + GPIODBUG("isr %x \n", isr); + isr = (isr >> (8 * ast_gpio->index)) & 0xff; + GPIODBUG("[%s] isr %x \n", ast_gpio->chip.label, isr); + if(isr != 0) { + //get gpio isr and --> to IRQ number .... + for (j=0; j<8;j++) { + if((1<<j) & isr) { + // dispach interrupt +// GPIODBUG("[%s] pin %d -> irq [%d]\n",ast_gpio->chip.label, j, j + IRQ_GPIO_CHAIN_START + (8 * i)); + generic_handle_irq(j + IRQ_GPIO_CHAIN_START + (8 * i)); + } + } +// GPIODBUG("isr -- ? %x \n",ast_gpio_read(ast_gpio, ast_gpio->int_sts_offset)); + } + } + +#if 0 + while(1) { + isr = ast_gpio_read(ast_gpio, ast_gpio->int_sts_offset); + printk("isr %x \n", isr); + isr = isr >> (8 * ast_gpio->index); + //get gpio isr and --> to IRQ number .... + for (i=0; i<8;i++) { + if((1<<i) & isr) { + // dispach interrupt + printk("[%s] pin %d -> irq [%d]\n",ast_gpio->chip.label, i,i + IRQ_GPIO_CHAIN_START + (8 * ast_gpio->index)); + generic_handle_irq(i + IRQ_GPIO_CHAIN_START + (8 * ast_gpio->index)); + } + } + if(isr == 0) + break; + } +#endif + desc->chip->unmask(IRQ_GPIO); + /* now it may re-trigger */ + +} + +static void ast_gpio_ack_irq(unsigned int irq) +{ + struct ast_gpio_bank *ast_gpio = get_irq_chip_data(irq); + + unsigned int gpio_irq = irq - IRQ_GPIO_CHAIN_START; + + gpio_irq = gpio_irq % 8; + + GPIODBUG("irq [%d] : ast_gpio_ack_irq [%s] pin %d\n ",irq, ast_gpio->chip.label, gpio_irq); + + GPIODBUG("write clr [%x] %x\n ",ast_gpio->int_sts_offset, 1<< (gpio_irq + (ast_gpio->index * 8))); + + ast_gpio_write(ast_gpio, 1<< (gpio_irq + (ast_gpio->index * 8)), ast_gpio->int_sts_offset); + + GPIODBUG("read sts %x\n ",ast_gpio_read(ast_gpio, ast_gpio->int_sts_offset)); + +} + +static void ast_gpio_mask_irq(unsigned int irq) +{ + struct ast_gpio_bank *ast_gpio = get_irq_chip_data(irq); + unsigned int gpio_irq = irq - IRQ_GPIO_CHAIN_START; + gpio_irq = gpio_irq%8; + + + GPIODBUG("irq [%d] : ast_gpio_mask_irq [%s] pin %d\n ",irq, ast_gpio->chip.label, gpio_irq); + + //disable irq + ast_gpio_write(ast_gpio, ast_gpio_read(ast_gpio, ast_gpio->int_en_offset) & + ~(1<< (gpio_irq + (ast_gpio->index * 8))), ast_gpio->int_en_offset); +} + +static void ast_gpio_unmask_irq(unsigned int irq) +{ + struct ast_gpio_bank *ast_gpio = get_irq_chip_data(irq); + unsigned int gpio_irq = irq - IRQ_GPIO_CHAIN_START; + gpio_irq = gpio_irq%8; + + + GPIODBUG("irq[%d], [%s] pin %d\n",irq, ast_gpio->chip.label, gpio_irq); + + //Enable IRQ .. + ast_gpio_write(ast_gpio, 1<< (gpio_irq + (ast_gpio->index * 8)), ast_gpio->int_sts_offset); + + ast_gpio_write(ast_gpio, ast_gpio_read(ast_gpio, ast_gpio->int_en_offset) | + (1<< (gpio_irq + (ast_gpio->index * 8))), ast_gpio->int_en_offset); + +} + +static int +ast_gpio_irq_type(unsigned int irq, unsigned int type) +{ + u32 type0, type1, type2; + struct ast_gpio_bank *ast_gpio; + int retval = 0; + unsigned int gpio_irq = irq - IRQ_GPIO_CHAIN_START; + gpio_irq = gpio_irq%32; + + + + GPIODBUG("ast_gpio_irq_type %d : %x \n",irq,type); + if (type & ~IRQ_TYPE_SENSE_MASK) + return -EINVAL; + + ast_gpio = get_irq_chip_data(irq); + + type0 = ast_gpio_read(ast_gpio, ast_gpio->int_type_offset); + type1 = ast_gpio_read(ast_gpio, ast_gpio->int_type_offset + 0x04); + type2 = ast_gpio_read(ast_gpio, ast_gpio->int_type_offset + 0x08); + + switch(type) { + /* Edge rising type */ + case IRQ_TYPE_EDGE_RISING: + type0 |=(1<<irq); + type1 &=~(1<<irq); + type2 &=~(1<<irq); + break; + /* Edge falling type */ + case IRQ_TYPE_EDGE_FALLING: + type2 |=(1<<irq); + break; + case IRQ_TYPE_EDGE_BOTH: + type0 &=~(1<<irq); + type1 |=(1<<irq); + type2 &=~(1<<irq); + break; + case IRQ_TYPE_LEVEL_HIGH: + type0 |=(1<<irq); + type1 |=(1<<irq); + type2 &=~(1<<irq); + break; + case IRQ_TYPE_LEVEL_LOW: + type0 &=~(1<<irq); + type1 |=(1<<irq); + type2 &=~(1<<irq); + break; + default: + GPIODBUG("not support trigger"); + return -EINVAL; + break; + } + + ast_gpio_write(ast_gpio, type0, ast_gpio->int_type_offset); + ast_gpio_write(ast_gpio, type1, ast_gpio->int_type_offset + 0x04); + ast_gpio_write(ast_gpio, type2, ast_gpio->int_type_offset + 0x08); + + return retval; + +} + +static struct irq_chip ast_gpio_irq_chip = { + .name = "GPIO", + .ack = ast_gpio_ack_irq, + .mask = ast_gpio_mask_irq, + .unmask = ast_gpio_unmask_irq, + .set_type = ast_gpio_irq_type, +}; + +/*---------------------------------------------------------------------*/ +static int __init ast_gpio_init(void) +{ + int i,j; + struct ast_gpio_bank *ast_gpio; + + GPIODBUG("gpio port num %d, total gpio pin : %d\n", + GPIO_PORT_NUM, ARCH_NR_GPIOS); + + GPIODBUG("gpio chain start %d \n",IRQ_GPIO_CHAIN_START); + for (i = 0; i < GPIO_PORT_NUM; i++) { + ast_gpio = &ast_gpio_gp[i]; + + GPIODBUG("add gpio_chip [%s] : %d\n",ast_gpio->chip.label, i); + +#if 0 + bank->chip.direction_input = ast_gpio_direction_input; + bank->chip.get = ast_gpio_get; + bank->chip.direction_output = ast_gpio_direction_output; + bank->chip.set = ast_gpio_set; + + bank->chip.label = "gpio"; +#endif + ast_gpio->chip.base = i*8; + ast_gpio->chip.ngpio = 8; + + gpiochip_add(&ast_gpio->chip); + +#if 1 + //Set Level Trigger + ast_gpio_write(ast_gpio, 0xffffffff, ast_gpio->int_type_offset); + ast_gpio_write(ast_gpio, 0xffffffff, ast_gpio->int_type_offset + 0x04); + ast_gpio_write(ast_gpio, 0, ast_gpio->int_type_offset + 0x08); + //remove clear direction for keep orignal state +// ast_gpio_write(ast_gpio, 0, ast_gpio->dir_offset); + //Enable IRQ +// ast_gpio_write(ast_gpio, 0xffffffff, ast_gpio->int_en_offset); + +#endif + + for(j=0;j<8;j++) { + GPIODBUG("inst chip data %d\n",i*8 + j + IRQ_GPIO_CHAIN_START); + set_irq_chip_data(i*8 + j + IRQ_GPIO_CHAIN_START, ast_gpio); + set_irq_chip(i*8 + j + IRQ_GPIO_CHAIN_START, &ast_gpio_irq_chip); + set_irq_handler(i*8 + j + IRQ_GPIO_CHAIN_START, handle_level_irq); + set_irq_flags(i*8 + j + IRQ_GPIO_CHAIN_START, IRQF_VALID); + } + set_irq_chained_handler(IRQ_GPIO, ast_gpio_irq_handler); +// set_irq_chip_data(IRQ_GPIO, ast_gpio); +// set_irq_data(IRQ_GPIO, ast_gpio_gp[]); + + + } + + return 0; + +} + +core_initcall(ast_gpio_init); + +//arch_initcall(ast_gpio_init); + diff --git a/arch/arm/mach-aspeed/include/mach/aspeed_serial.h b/arch/arm/mach-aspeed/include/mach/aspeed_serial.h new file mode 100644 index 000000000000..33bf333881ca --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/aspeed_serial.h @@ -0,0 +1,61 @@ +/* + * file : aspeed_serial.h + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef ASM_ARM_HARDWARE_AST_SERIAL_H +#define ASM_ARM_HARDWARE_AST_SERIAL_H + +#define UART_RBR 0x00 /* Receiver Buffer Register */ +#define UART_THR 0x00 /* Transmit Holding Register */ +#define UART_DLL 0x00 /* Divisor Latch Low Register */ +#define UART_DLH 0x04 /* Divisor Latch High Register */ +#define UART_IER 0x04 /* Interrupt Enable Register */ +#define UART_IIR 0x08 /* Interrupt Identity Register */ +#define UART_FCR 0x08 /* FIFO Control Register */ +#define UART_LCR 0x0C /* Line Control Register */ +#define UART_MCR 0x10 /* Modem Control Register */ +#define UART_LSR 0x14 /* Line Status Register */ +#define UART_MSR 0x18 /* Modem Status Register */ +#define UART_SCR 0x1C /* Scratch Register */ + +/* Interrupt Enable Register */ +#define UART_IER_EMSI 0x08 /* Enable Modem Status Interrupt */ +#define UART_IER_ELSI 0x04 /* Enable Line Status Interrupt */ +#define UART_IER_ETEI 0x02 /* Enable Transmit Holding Empty Interrupt */ +#define UART_IER_ERDI 0X01 /* Enable Received Data Interrupt */ + +/* FIFO Control Register */ +#define UART_FCR_XMITR 0x04 /* XMIT FIFO Reset */ +#define UART_FCR_RCVRR 0x02 /* RCVR FIFO Reset */ +#define UART_FCR_FIFOE 0x01 /* FIEO Enable */ + +/* Line Control Register */ +#define UART_LCR_DLAB 0x80 /* Divisor Latch Address Bit */ +#define UART_LCR_BRK 0x40 /* Break Control */ +#define UART_LCR_EPS 0x10 /* Even Parity Select */ +#define UART_LCR_PEN 0x08 /* Parity Enable */ +#define UART_LCR_STOP 0x04 /* Stop Bit */ +#define UART_LCR_WLEN_MASK 0x03 /* bits per character mask */ +#define UART_LCR_WLEN_8 0x03 /* 8 bits per character */ +#define UART_LCR_WLEN_7 0x02 /* 7 bits per character */ +#define UART_LCR_WLEN_6 0x01 /* 6 bits per character */ +#define UART_LCR_WLEN_5 0x00 /* 5 bits per character */ + +/* Line Status Register */ +#define UART_LSR_TEMT 0x40 /* Transmitter Empty */ +#define UART_LSR_THRE 0x20 /* Transmitter Holding Register Empty */ +#define UART_LSR_BE 0x10 /* Break Error */ +#define UART_LSR_FE 0x08 /* Framing Error */ +#define UART_LSR_PE 0x04 /* Parity Error */ +#define UART_LSR_OE 0x02 /* Overrun Error */ +#define UART_LSR_DR 0x01 /* Data Ready */ +#define UART_LSR_ANY (UART_LSR_BE|UART_LSR_FE|UART_LSR_PE|UART_LSR_OE) + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast-uart-dma.h b/arch/arm/mach-aspeed/include/mach/ast-uart-dma.h new file mode 100644 index 000000000000..2ac2b41319c6 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast-uart-dma.h @@ -0,0 +1,86 @@ +/******************************************************************************** +* File Name : ast-uart-dma.h +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +********************************************************************************/ +#ifndef AST_UART_DMA_H_INCLUDED +#define AST_UART_DMA_H_INCLUDED + + +#define DMA_BUFF_SIZE 0x1000 //4096 + +struct ast_uart_dma_data { + u8 chip_no; //campain chip number + u8 dma_ch; //dma channel number +}; + + +/* enum ast_uart_chan_op + * + * operation codes passed to the DMA code by the user, and also used + * to inform the current channel owner of any changes to the system state +*/ + +enum ast_uart_chan_op { + AST_UART_DMAOP_TRIGGER, + AST_UART_DMAOP_STOP, +}; + +struct ast1070_dma_ch; + +/* ast_uart_dma_cbfn_t * * buffer callback routine type */ +typedef void (*ast_uart_dma_cbfn_t)(struct ast1070_dma_ch *,void *dev_id, u16 len); + +struct uart_dma_desc { + u32 desc0; + u32 desc1; + u32 desc2; + u32 desc3; +} __attribute__ ((aligned(16))); + +struct ast1070_dma_ch { + u8 ch_no; + u8 direction; + u8 enable; + u32 ctrl_offset; + u32 desc_offset; + void *priv; + struct uart_dma_desc *desc; + dma_addr_t desc_dma_addr; /* Mapped descr. table */ + /* cdriver callbacks */ + ast_uart_dma_cbfn_t callback_fn; /* buffer done callback */ +}; + +#define AST1070_UART_DMA_CH 4 + +struct ast1070_dma { + void __iomem *reg_base; + struct ast1070_dma_ch dma_tx_ch[AST1070_UART_DMA_CH]; + struct ast1070_dma_ch dma_rx_ch[AST1070_UART_DMA_CH]; +}; + + +/* ast_uart_dma_request * * request a dma channel exclusivley */ +extern int ast_uart_rx_dma_request(u8 node, u8 channel, ast_uart_dma_cbfn_t rtn, void *id); +extern int ast_uart_tx_dma_request(u8 node, u8 channel, ast_uart_dma_cbfn_t rtn, void *id); + +/* ast_uart_dma_ctrl * * change the state of the dma channel */ +extern int ast_uart_rx_dma_ctrl(u8 node, u8 ch, enum ast_uart_chan_op op); +extern int ast_uart_tx_dma_ctrl(u8 node, u8 ch, enum ast_uart_chan_op op); + +extern int ast_uart_rx_dma_enqueue(u8 node, u8 ch, dma_addr_t rx_buff, u16 len); +extern int ast_uart_tx_dma_enqueue(u8 node, u8 ch, dma_addr_t tx_buff, u16 len); + + + +#endif + diff --git a/arch/arm/mach-aspeed/include/mach/ast1070_irqs.h b/arch/arm/mach-aspeed/include/mach/ast1070_irqs.h new file mode 100644 index 000000000000..0774417b0956 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast1070_irqs.h @@ -0,0 +1,142 @@ +/* + * arch/arm/plat-aspeed/include/plat/irqs.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST1070_IRQS_H_ +#define _AST1070_IRQS_H_ 1 + +#define IRQ_C0_VIC_CHAIN IRQ_EXT0 +#define IRQ_C0_VIC_CHAIN_START (AST_VIC_NUM) + +#define IRQ_C1_VIC_CHAIN IRQ_EXT1 +#define IRQ_C1_VIC_CHAIN_START (IRQ_C0_VIC_CHAIN_START + AST_CVIC_NUM) + +#define IRQ_C2_VIC_CHAIN IRQ_EXT2 +#define IRQ_C2_VIC_CHAIN_START (IRQ_C1_VIC_CHAIN_START + AST_CVIC_NUM) + +#define IRQ_C3_VIC_CHAIN IRQ_EXT3 +#define IRQ_C3_VIC_CHAIN_START (IRQ_C2_VIC_CHAIN_START + AST_CVIC_NUM) + +#define AST_CVIC_NUM 25 + +#define IRQ_C0_N1_KCS (IRQ_C0_VIC_CHAIN_START + 0) +#define IRQ_C0_N1_UART (IRQ_C0_VIC_CHAIN_START + 1) +#define IRQ_C0_N1_MAILBOX (IRQ_C0_VIC_CHAIN_START + 2) +#define IRQ_C0_N1_PORT80 (IRQ_C0_VIC_CHAIN_START + 3) +#define IRQ_C0_N1_RESET (IRQ_C0_VIC_CHAIN_START + 4) +#define IRQ_C0_N2_KCS (IRQ_C0_VIC_CHAIN_START + 5) +#define IRQ_C0_N2_UART (IRQ_C0_VIC_CHAIN_START + 6) +#define IRQ_C0_N2_MAILBOX (IRQ_C0_VIC_CHAIN_START + 7) +#define IRQ_C0_N2_PORT80 (IRQ_C0_VIC_CHAIN_START + 8) +#define IRQ_C0_N2_RESET (IRQ_C0_VIC_CHAIN_START + 9) +#define IRQ_C0_N3_KCS (IRQ_C0_VIC_CHAIN_START + 10) +#define IRQ_C0_N3_UART (IRQ_C0_VIC_CHAIN_START + 11) +#define IRQ_C0_N3_MAILBOX (IRQ_C0_VIC_CHAIN_START + 12) +#define IRQ_C0_N3_PORT80 (IRQ_C0_VIC_CHAIN_START + 13) +#define IRQ_C0_N3_RESET (IRQ_C0_VIC_CHAIN_START + 14) +#define IRQ_C0_N4_KCS (IRQ_C0_VIC_CHAIN_START + 15) +#define IRQ_C0_N4_UART (IRQ_C0_VIC_CHAIN_START + 16) +#define IRQ_C0_N4_MAILBOX (IRQ_C0_VIC_CHAIN_START + 17) +#define IRQ_C0_N4_PORT80 (IRQ_C0_VIC_CHAIN_START + 18) +#define IRQ_C0_N4_RESET (IRQ_C0_VIC_CHAIN_START + 19) +#define IRQ_C0_N1_UART_DMA (IRQ_C0_VIC_CHAIN_START + 20) +#define IRQ_C0_N2_UART_DMA (IRQ_C0_VIC_CHAIN_START + 21) +#define IRQ_C0_N3_UART_DMA (IRQ_C0_VIC_CHAIN_START + 22) +#define IRQ_C0_N4_UART_DMA (IRQ_C0_VIC_CHAIN_START + 23) +#define IRQ_C0_I2C (IRQ_C0_VIC_CHAIN_START + 24) + +#define IRQ_C1_N1_KCS (IRQ_C1_VIC_CHAIN_START + 0) +#define IRQ_C1_N1_UART (IRQ_C1_VIC_CHAIN_START + 1) +#define IRQ_C1_N1_MAILBOX (IRQ_C1_VIC_CHAIN_START + 2) +#define IRQ_C1_N1_PORT80 (IRQ_C1_VIC_CHAIN_START + 3) +#define IRQ_C1_N1_RESET (IRQ_C1_VIC_CHAIN_START + 4) +#define IRQ_C1_N2_KCS (IRQ_C1_VIC_CHAIN_START + 5) +#define IRQ_C1_N2_UART (IRQ_C1_VIC_CHAIN_START + 6) +#define IRQ_C1_N2_MAILBOX (IRQ_C1_VIC_CHAIN_START + 7) +#define IRQ_C1_N2_PORT80 (IRQ_C1_VIC_CHAIN_START + 8) +#define IRQ_C1_N2_RESET (IRQ_C1_VIC_CHAIN_START + 9) +#define IRQ_C1_N3_KCS (IRQ_C1_VIC_CHAIN_START + 10) +#define IRQ_C1_N3_UART (IRQ_C1_VIC_CHAIN_START + 11) +#define IRQ_C1_N3_MAILBOX (IRQ_C1_VIC_CHAIN_START + 12) +#define IRQ_C1_N3_PORT80 (IRQ_C1_VIC_CHAIN_START + 13) +#define IRQ_C1_N3_RESET (IRQ_C1_VIC_CHAIN_START + 14) +#define IRQ_C1_N4_KCS (IRQ_C1_VIC_CHAIN_START + 15) +#define IRQ_C1_N4_UART (IRQ_C1_VIC_CHAIN_START + 16) +#define IRQ_C1_N4_MAILBOX (IRQ_C1_VIC_CHAIN_START + 17) +#define IRQ_C1_N4_PORT80 (IRQ_C1_VIC_CHAIN_START + 18) +#define IRQ_C1_N4_RESET (IRQ_C1_VIC_CHAIN_START + 19) +#define IRQ_C1_N1_UART_DMA (IRQ_C1_VIC_CHAIN_START + 20) +#define IRQ_C1_N2_UART_DMA (IRQ_C1_VIC_CHAIN_START + 21) +#define IRQ_C1_N3_UART_DMA (IRQ_C1_VIC_CHAIN_START + 22) +#define IRQ_C1_N4_UART_DMA (IRQ_C1_VIC_CHAIN_START + 23) +#define IRQ_C1_I2C (IRQ_C1_VIC_CHAIN_START + 24) + +#define IRQ_C2_N1_KCS (IRQ_C2_VIC_CHAIN_START + 0) +#define IRQ_C2_N1_UART (IRQ_C2_VIC_CHAIN_START + 1) +#define IRQ_C2_N1_MAILBOX (IRQ_C2_VIC_CHAIN_START + 2) +#define IRQ_C2_N1_PORT80 (IRQ_C2_VIC_CHAIN_START + 3) +#define IRQ_C2_N1_RESET (IRQ_C2_VIC_CHAIN_START + 4) +#define IRQ_C2_N2_KCS (IRQ_C2_VIC_CHAIN_START + 5) +#define IRQ_C2_N2_UART (IRQ_C2_VIC_CHAIN_START + 6) +#define IRQ_C2_N2_MAILBOX (IRQ_C2_VIC_CHAIN_START + 7) +#define IRQ_C2_N2_PORT80 (IRQ_C2_VIC_CHAIN_START + 8) +#define IRQ_C2_N2_RESET (IRQ_C2_VIC_CHAIN_START + 9) +#define IRQ_C2_N3_KCS (IRQ_C2_VIC_CHAIN_START + 10) +#define IRQ_C2_N3_UART (IRQ_C2_VIC_CHAIN_START + 11) +#define IRQ_C2_N3_MAILBOX (IRQ_C2_VIC_CHAIN_START + 12) +#define IRQ_C2_N3_PORT80 (IRQ_C2_VIC_CHAIN_START + 13) +#define IRQ_C2_N3_RESET (IRQ_C2_VIC_CHAIN_START + 14) +#define IRQ_C2_N4_KCS (IRQ_C2_VIC_CHAIN_START + 15) +#define IRQ_C2_N4_UART (IRQ_C2_VIC_CHAIN_START + 16) +#define IRQ_C2_N4_MAILBOX (IRQ_C2_VIC_CHAIN_START + 17) +#define IRQ_C2_N4_PORT80 (IRQ_C2_VIC_CHAIN_START + 18) +#define IRQ_C2_N4_RESET (IRQ_C2_VIC_CHAIN_START + 19) +#define IRQ_C2_N1_UART_DMA (IRQ_C2_VIC_CHAIN_START + 20) +#define IRQ_C2_N2_UART_DMA (IRQ_C2_VIC_CHAIN_START + 21) +#define IRQ_C2_N3_UART_DMA (IRQ_C2_VIC_CHAIN_START + 22) +#define IRQ_C2_N4_UART_DMA (IRQ_C2_VIC_CHAIN_START + 23) +#define IRQ_C2_I2C (IRQ_C2_VIC_CHAIN_START + 24) + +#define IRQ_C3_N1_KCS (IRQ_C3_VIC_CHAIN_START + 0) +#define IRQ_C3_N1_UART (IRQ_C3_VIC_CHAIN_START + 1) +#define IRQ_C3_N1_MAILBOX (IRQ_C3_VIC_CHAIN_START + 2) +#define IRQ_C3_N1_PORT80 (IRQ_C3_VIC_CHAIN_START + 3) +#define IRQ_C3_N1_RESET (IRQ_C3_VIC_CHAIN_START + 4) +#define IRQ_C3_N2_KCS (IRQ_C3_VIC_CHAIN_START + 5) +#define IRQ_C3_N2_UART (IRQ_C3_VIC_CHAIN_START + 6) +#define IRQ_C3_N2_MAILBOX (IRQ_C3_VIC_CHAIN_START + 7) +#define IRQ_C3_N2_PORT80 (IRQ_C3_VIC_CHAIN_START + 8) +#define IRQ_C3_N2_RESET (IRQ_C3_VIC_CHAIN_START + 9) +#define IRQ_C3_N3_KCS (IRQ_C3_VIC_CHAIN_START + 10) +#define IRQ_C3_N3_UART (IRQ_C3_VIC_CHAIN_START + 11) +#define IRQ_C3_N3_MAILBOX (IRQ_C3_VIC_CHAIN_START + 12) +#define IRQ_C3_N3_PORT80 (IRQ_C3_VIC_CHAIN_START + 13) +#define IRQ_C3_N3_RESET (IRQ_C3_VIC_CHAIN_START + 14) +#define IRQ_C3_N4_KCS (IRQ_C3_VIC_CHAIN_START + 15) +#define IRQ_C3_N4_UART (IRQ_C3_VIC_CHAIN_START + 16) +#define IRQ_C3_N4_MAILBOX (IRQ_C3_VIC_CHAIN_START + 17) +#define IRQ_C3_N4_PORT80 (IRQ_C3_VIC_CHAIN_START + 18) +#define IRQ_C3_N4_RESET (IRQ_C3_VIC_CHAIN_START + 19) +#define IRQ_C3_N1_UART_DMA (IRQ_C3_VIC_CHAIN_START + 20) +#define IRQ_C3_N2_UART_DMA (IRQ_C3_VIC_CHAIN_START + 21) +#define IRQ_C3_N3_UART_DMA (IRQ_C3_VIC_CHAIN_START + 22) +#define IRQ_C3_N4_UART_DMA (IRQ_C3_VIC_CHAIN_START + 23) +#define IRQ_C3_I2C (IRQ_C3_VIC_CHAIN_START + 24) + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast1070_platform.h b/arch/arm/mach-aspeed/include/mach/ast1070_platform.h new file mode 100644 index 000000000000..feefd913521b --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast1070_platform.h @@ -0,0 +1,100 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST1070_PLATFORM_H_ +#define _AST1070_PLATFORM_H_ 1 + +#define AST_C0_BASE (AST_LPC_BRIDGE) + +#define AST_C0_UART0_BASE (AST_C0_BASE) /* Companion UART1 */ +#define AST_C0_UART1_BASE (AST_C0_BASE + 0x400) /* Companion UART2 */ +#define AST_C0_UART2_BASE (AST_C0_BASE + 0x800) /* Companion UART3 */ +#define AST_C0_UART3_BASE (AST_C0_BASE + 0xc00) /* Companion UART4 */ +#define AST_C0_LPC0_BASE (AST_C0_BASE + 0x1000) /* Companion LPC1 */ +#define AST_C0_LPC1_BASE (AST_C0_BASE + 0x1400) /* Companion LPC2 */ +#define AST_C0_LPC2_BASE (AST_C0_BASE + 0x1800) /* Companion LPC3 */ +#define AST_C0_LPC3_BASE (AST_C0_BASE + 0x1c00) /* Companion LPC4 */ +#define AST_C0_SCU_BASE (AST_C0_BASE + 0x2000) /* Companion SCU */ +#define AST_C0_VIC_BASE (AST_C0_BASE + 0x2400) /* Companion VIC */ +#define AST_C0_LPC_SLAVE_BASE (AST_C0_BASE + 0x2c00) /* Companion LPC SlLAVE */ +#define AST_C0_I2C_BASE (AST_C0_BASE + 0x3000) /* Companion I2C */ +#define AST_C0_SPI_BASE (AST_C0_BASE + 0x4000) /* Companion SPI */ +#define AST_C0_LPC_SPI_BASE (AST_C0_BASE + 0x4400) /* Companion LPC SPI */ +#define AST_C0_UART_DMA_BASE (AST_C0_BASE + 0x4800) /* Companion UART DMA */ +#define AST_C0_SPI_CONTROL_BASE (AST_C0_BASE + 0x4c00) /* Companion SPI CONTROL */ +#define AST_C0_SPI_SHADOW_SRAM_BASE (AST_C0_BASE + 0x5000) /* Companion SPI SHADOW SRAM */ + +#define AST_C1_BASE (AST_LPC_BRIDGE + 0x10000) + +#define AST_C1_UART0_BASE (AST_C1_BASE) /* Companion UART1 */ +#define AST_C1_UART1_BASE (AST_C1_BASE + 0x400) /* Companion UART2 */ +#define AST_C1_UART2_BASE (AST_C1_BASE + 0x800) /* Companion UART3 */ +#define AST_C1_UART3_BASE (AST_C1_BASE + 0xc00) /* Companion UART4 */ +#define AST_C1_LPC0_BASE (AST_C1_BASE + 0x1000) /* Companion LPC1 */ +#define AST_C1_LPC1_BASE (AST_C1_BASE + 0x1400) /* Companion LPC2 */ +#define AST_C1_LPC2_BASE (AST_C1_BASE + 0x1800) /* Companion LPC3 */ +#define AST_C1_LPC3_BASE (AST_C1_BASE + 0x1c00) /* Companion LPC4 */ +#define AST_C1_SCU_BASE (AST_C1_BASE + 0x2000) /* Companion SCU */ +#define AST_C1_VIC_BASE (AST_C1_BASE + 0x2400) /* Companion VIC */ +#define AST_C1_LPC_SLAVE_BASE (AST_C1_BASE + 0x2c00) /* Companion LPC SlLAVE */ +#define AST_C1_I2C_BASE (AST_C1_BASE + 0x3000) /* Companion I2C */ +#define AST_C1_SPI_BASE (AST_C1_BASE + 0x4000) /* Companion SPI */ +#define AST_C1_LPC_SPI_BASE (AST_C1_BASE + 0x4400) /* Companion LPC SPI */ +#define AST_C1_UART_DMA_BASE (AST_C1_BASE + 0x4800) /* Companion UART DMA */ +#define AST_C1_SPI_CONTROL_BASE (AST_C1_BASE + 0x4c00) /* Companion SPI CONTROL */ +#define AST_C1_SPI_SHADOW_SRAM_BASE (AST_C1_BASE + 0x5000) /* Companion SPI SHADOW SRAM */ + +#define AST_C2_BASE (AST_LPC_BRIDGE + 0x20000) + +#define AST_C2_UART0_BASE (AST_C2_BASE) /* Companion UART1 */ +#define AST_C2_UART1_BASE (AST_C2_BASE + 0x400) /* Companion UART2 */ +#define AST_C2_UART2_BASE (AST_C2_BASE + 0x800) /* Companion UART3 */ +#define AST_C2_UART3_BASE (AST_C2_BASE + 0xc00) /* Companion UART4 */ +#define AST_C2_LPC1_BASE (AST_C2_BASE + 0x1000) /* Companion LPC1 */ +#define AST_C2_LPC2_BASE (AST_C2_BASE + 0x1400) /* Companion LPC2 */ +#define AST_C2_LPC3_BASE (AST_C2_BASE + 0x1800) /* Companion LPC3 */ +#define AST_C2_LPC4_BASE (AST_C2_BASE + 0x1c00) /* Companion LPC4 */ +#define AST_C2_SCU_BASE (AST_C2_BASE + 0x2000) /* Companion SCU */ +#define AST_C2_VIC_BASE (AST_C2_BASE + 0x2400) /* Companion VIC */ +#define AST_C2_LPC_SLAVE_BASE (AST_C2_BASE + 0x2c00) /* Companion LPC SlLAVE */ +#define AST_C2_I2C_BASE (AST_C2_BASE + 0x3000) /* Companion I2C */ +#define AST_C2_SPI_BASE (AST_C2_BASE + 0x4000) /* Companion SPI */ +#define AST_C2_LPC_SPI_BASE (AST_C2_BASE + 0x4400) /* Companion LPC SPI */ +#define AST_C2_UART_DMA_BASE (AST_C2_BASE + 0x4800) /* Companion UART DMA */ +#define AST_C2_SPI_CONTROL_BASE (AST_C2_BASE + 0x4c00) /* Companion SPI CONTROL */ +#define AST_C2_SPI_SHADOW_SRAM_BASE (AST_C2_BASE + 0x5000) /* Companion SPI SHADOW SRAM */ + +#define AST_C3_BASE (AST_LPC_BRIDGE + 0x30000) + +#define AST_C3_UART0_BASE (AST_C3_BASE) /* Companion UART1 */ +#define AST_C3_UART1_BASE (AST_C3_BASE + 0x400) /* Companion UART2 */ +#define AST_C3_UART2_BASE (AST_C3_BASE + 0x800) /* Companion UART3 */ +#define AST_C3_UART3_BASE (AST_C3_BASE + 0xc00) /* Companion UART4 */ +#define AST_C3_LPC0_BASE (AST_C3_BASE + 0x1000) /* Companion LPC1 */ +#define AST_C3_LPC1_BASE (AST_C3_BASE + 0x1400) /* Companion LPC2 */ +#define AST_C3_LPC2_BASE (AST_C3_BASE + 0x1800) /* Companion LPC3 */ +#define AST_C3_LPC3_BASE (AST_C3_BASE + 0x1c00) /* Companion LPC4 */ +#define AST_C3_SCU_BASE (AST_C3_BASE + 0x2000) /* Companion SCU */ +#define AST_C3_VIC_BASE (AST_C3_BASE + 0x2400) /* Companion VIC */ +#define AST_C3_LPC_SLAVE_BASE (AST_C3_BASE + 0x2c00) /* Companion LPC SlLAVE */ +#define AST_C3_I2C_BASE (AST_C3_BASE + 0x3000) /* Companion I2C */ +#define AST_C3_SPI_BASE (AST_C3_BASE + 0x4000) /* Companion SPI */ +#define AST_C3_LPC_SPI_BASE (AST_C3_BASE + 0x4400) /* Companion LPC SPI */ +#define AST_C3_UART_DMA_BASE (AST_C3_BASE + 0x4800) /* Companion UART DMA */ +#define AST_C3_SPI_CONTROL_BASE (AST_C3_BASE + 0x4c00) /* Companion SPI CONTROL */ +#define AST_C3_SPI_SHADOW_SRAM_BASE (AST_C3_BASE + 0x5000) /* Companion SPI SHADOW SRAM */ + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast1520_irqs.h b/arch/arm/mach-aspeed/include/mach/ast1520_irqs.h new file mode 100644 index 000000000000..3ebc91b404d7 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast1520_irqs.h @@ -0,0 +1,107 @@ +/* + * arch/arm/plat-aspeed/include/plat/irqs.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST1520_IRQS_H_ +#define _AST1520_IRQS_H_ 1 + + +#ifdef CONFIG_PCIE +#define NR_IRQS (ARCH_NR_GPIOS +ARCH_NR_PCIE + AST_VIC_NUM) + +//--------------GPIO --------------------------------------------------------------- +#define ARCH_NR_GPIOS (GPIO_PORT_NUM*8) +#define IRQ_GPIO_CHAIN_START AST_VIC_NUM +//------------------- --------------------------------------------------------------- + +#define ARCH_NR_PCIE 5 +#define IRQ_PCIE_CHAIN IRQ_PCIE +#define IRQ_PCIE_CHAIN_START (ARCH_NR_GPIOS + AST_VIC_NUM) + +#define IRQ_PCIE_INTA (IRQ_PCIE_CHAIN_START) +#define IRQ_PCIE_INTB (IRQ_PCIE_CHAIN_START + 1) +#define IRQ_PCIE_INTC (IRQ_PCIE_CHAIN_START + 2) +#define IRQ_PCIE_INTD (IRQ_PCIE_CHAIN_START + 3) +#define IRQ_PCIE_MSI0 (IRQ_PCIE_INTD + 1) // support max 32 MSI + +#else +#define NR_IRQS (AST_VIC_NUM + ARCH_NR_GPIOS) +//--------------GPIO --------------------------------------------------------------- +#define ARCH_NR_GPIOS (GPIO_PORT_NUM*8) +#define IRQ_GPIO_CHAIN_START AST_VIC_NUM +//------------------- --------------------------------------------------------------- +#endif + +#define AST_VIC_NUM 51 + +//#define IRQ_SDRAM_ECC 0 +//#define IRQ_MIC 1 +#define IRQ_MAC0 2 /* MAC 1 interrupt */ +//#define IRQ_MAC1 3 /* MAC 2 interrupt */ +#define IRQ_CRYPTO 4 +#define IRQ_USB20_HUB 5 +#define IRQ_EHCI 5 +#define IRQ_XDMA 6 +#define IRQ_VIDEO 7 +//#define IRQ_LPC 8 +#define IRQ_UART1 9 /* UART 1 interrupt */ +#define IRQ_UART0 10 /* UART 3 interrupt */ +//11 Reserved +#define IRQ_I2C 12 +//#define IRQ_UDC11 13 +#define IRQ_UHCI 14 +//#define IRQ_PECI 15 +#define IRQ_TIMER0 16 /* TIMER 1 interrupt */ +#define IRQ_TIMER1 17 /* TIMER 2 interrupt */ +#define IRQ_TIMER2 18 /* TIMER 3 interrupt */ +//#define IRQ_SMC 19 +#define IRQ_GPIO 20 +#define IRQ_SCU 21 +#define IRQ_RTC 22 +//23 , 24 reserverd +#define IRQ_CRT 25 +#define IRQ_SDHC 26 +#define IRQ_WDT 27 +#define IRQ_TACHO 28 +#define IRQ_2D 29 +#define IRQ_SYS_WAKEUP 30 +//#define IRQ_ADC 31 +#define IRQ_UART2 32 /* UART 2 interrupt */ +//#define IRQ_UART2 33 /* UART 3 interrupt */ +//#define IRQ_UART3 34 /* UART 4 interrupt */ +//#define IRQ_TIMER3 35 /* TIMER 4 interrupt */ +//#define IRQ_TIMER4 36 +//#define IRQ_TIMER5 37 +//#define IRQ_TIMER6 38 +//#define IRQ_TIMER7 39 /* TIMER 8 interrupt */ +//#define IRQ_SGPIO_MASTER 40 +//#define IRQ_SGPIO_SLAVE 41 +#define IRQ_PCIE 41 + +#define IRQ_MCTP 42 +//#define IRQ_JTAG 43 +#define IRQ_PS2 44 +#define IRQ_CPU1 45 +//#define IRQ_MAILBOX 46 +#define IRQ_EXT0_GPIOL1 47 +#define IRQ_EXT1_GPIOL3 48 +#define IRQ_EXT2_GPIOM3 49 +#define IRQ_EXT3_GPIOM3 50 + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast1520_platform.h b/arch/arm/mach-aspeed/include/mach/ast1520_platform.h new file mode 100644 index 000000000000..daded5d73004 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast1520_platform.h @@ -0,0 +1,61 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST1520_PLATFORM_H_ +#define _AST1520_PLATFORM_H_ 1 + +#define AST_SRAM_SIZE (SZ_8K) + +#define AST_AHB_CTRL_BASE 0x1E600000 /* AHB CONTROLLER */ + +#define AST_SPI_BASE 0x1E620000 /* SPI CONTROLLER */ + +#define AST_MAC0_BASE 0x1E660000 /* MAC1 */ + +#define AST_USB20_BASE 0x1E6A0000 /* USB 2.0 VIRTUAL HUB CONTROLLER */ +#define AST_EHCI_BASE 0x1E6A1000 /* USB 2.0 HOST CONTROLLER */ +#define AST_UHCI_BASE 0x1E6B0000 /* USB 1.1 HOST CONTROLLER */ +#define AST_VIC_BASE 0x1E6C0000 /* VIC */ +#define AST_SDMC_BASE 0x1E6E0000 /* MMC SDRAM*/ +#define AST_SCU_BASE 0x1E6E2000 /* SCU */ +#define AST_CRYPTO_BASE 0x1E6E3000 /* Crypto */ + +#define AST_I2S_BASE 0x1E6E5000 /* I2S */ +#define AST_GRAPHIC_BASE 0x1E6E6000 /* Graphics */ +#define AST_XDMA_BASE 0x1E6E7000 /* XDMA */ +#define AST_MCTP_BASE 0x1E6E8000 /* MCTP */ +#define AST_PCIE_BASE 0x1E6ED000 /* PCIE */ + +#define AST_VIDEO_BASE 0x1E700000 /* VIDEO ENGINE */ +#define AST_SRAM_BASE 0x1E720000 /* SRAM */ +#define AST_SDHC_BASE 0x1E740000 /* SD */ +#define AST_2D_BASE 0x1E760000 /* 2D */ +#define AST_GPIO_BASE 0x1E780000 /* GPIO */ +#define AST_RTC_BASE 0x1E781000 /* RTC */ +#define AST_TIMER_BASE 0x1E782000 /* TIMER #0~2*/ +#define AST_UART1_BASE 0x1E783000 /* UART1 */ +#define AST_UART0_BASE 0x1E784000 /* UART3 */ +#define AST_WDT_BASE 0x1E785000 /* WDT */ + +#define AST_I2C_BASE 0x1E78A000 /* I2C */ +#define AST_UART2_BASE 0x1E78D000 /* UART2 */ + +#define AST_SPI0_MEM 0x20000000 + +#define AST_PCIE_WIN_BASE 0x70000000 +#define AST_PCIE_WIN_SIZE 0x01000000 + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast2000_irqs.h b/arch/arm/mach-aspeed/include/mach/ast2000_irqs.h new file mode 100644 index 000000000000..50aece9fc487 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast2000_irqs.h @@ -0,0 +1,64 @@ +/* + * arch/arm/plat-aspeed/include/plat/irqs.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST2000_IRQS_H_ +#define _AST2000_IRQS_H_ 1 + +#define NR_IRQS (AST_VIC_NUM + ARCH_NR_GPIOS) +//--------------GPIO --------------------------------------------------------------- +#define ARCH_NR_GPIOS (GPIO_PORT_NUM*8) +#define IRQ_GPIO_CHAIN_START AST_VIC_NUM + +#define AST_VIC_NUM 32 + +#define IRQ_SPI 0 +#define IRQ_UART0 1 +#define IRQ_UART1 2 +#define IRQ_TIMER0 3 +#define IRQ_TIMER1 4 +#define IRQ_TIMER2 5 +#define IRQ_RTC 6 +#define IRQ_MAC0 7 +#define IRQ_GPIO_B0 8 +#define IRQ_UDC 9 +#define IRQ_PCI 10 +#define IRQ_GPIO_B1 11 +#define IRQ_GPIO_B2 12 +#define IRQ_GPIO_B3 13 +#define IRQ_LPC 14 +#define IRQ_I2C 15 +#define IRQ_USB11 16 +#define IRQ_VIDEO 17 +#define IRQ_CRYPTO 18 +#define IRQ_SCU 19 +#define IRQ_GPIO_B4 20 +#define IRQ_GPIO_B5 21 +#define IRQ_GPIO_B6 22 +#define IRQ_GPIO_A0 23 +#define IRQ_GPIO_A1 24 +#define IRQ_GPIO_A2 25 +#define IRQ_GPIO_A3 26 +#define IRQ_HDMA 27 +#define IRQ_GPIO_A4 28 +#define IRQ_GPIO_A5 29 +#define IRQ_GPIO_A6 30 +#define IRQ_WDT 31 + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast2000_platform.h b/arch/arm/mach-aspeed/include/mach/ast2000_platform.h new file mode 100644 index 000000000000..ff34f5b480dc --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast2000_platform.h @@ -0,0 +1,40 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST2000_PLATFORM_H_ +#define _AST2000_PLATFORM_H_ 1 + +#define AST_MAC0_BASE 0x19c80000 /* MAC1 */ +#define AST_CRYPTO_BASE 0x1E6E0040 /* Crypto */ +#define AST_UDC11_BASE 0x1E6E0080 /* USB11 */ +#define AST_SCU0_BASE 0x1E6E0100 /* SCU1 */ +#define AST_LPC_BASE 0x1E6E0400 /* LPC */ +#define AST_I2C_BASE 0x1E6E0800 /* I2C */ +//---// +#define AST_VIDEO_BASE 0x1E700000 /* VIDEO ENGINE */ +#define AST_AHB_TO_PBUS_BASE 0x1E720000 /* APB -> PBUS */ +//...// +#define AST_HDMA_BASE 0x1E7c0000 /* HDMA */ +#define AST_TIMER_BASE 0x1E800000 /* TIMER0/1/2 */ +#define AST_RTC_BASE 0x1E820000 /* RTC */ +#define AST_UART0_BASE 0x1E840000 /* UART0 */ +#define AST_UART1_BASE 0x1E860000 /* UART1 */ +#define AST_SPI_BASE 0x1E880000 /* SPI */ +#define AST_GPIO_BASE 0x1E8A0000 /* GPIO */ +#define AST_WDT_BASE 0x1E8C0000 /* WDT */ +#define AST_SCU0_BASE 0x1E8E000c /* SCU2 */ + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast2100_irqs.h b/arch/arm/mach-aspeed/include/mach/ast2100_irqs.h new file mode 100644 index 000000000000..8513909b541b --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast2100_irqs.h @@ -0,0 +1,64 @@ +/* + * arch/arm/plat-aspeed/include/plat/irqs.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST2100_IRQS_H_ +#define _AST2100_IRQS_H_ 1 + + +#define NR_IRQS (AST_VIC_NUM + ARCH_NR_GPIOS) +//--------------GPIO --------------------------------------------------------------- +#define ARCH_NR_GPIOS (GPIO_PORT_NUM*8) +#define IRQ_GPIO_CHAIN_START AST_VIC_NUM + +#define AST_VIC_NUM 32 +#define IRQ_SDRAM_ECC 0 +#define IRQ_MIC 1 +#define IRQ_MAC0 2 /* MAC 1 interrupt */ +#define IRQ_MAC1 3 /* MAC 2 interrupt */ +#define IRQ_CRYPTO 4 +#define IRQ_USB20_HUB 5 +#define IRQ_EHCI 5 +#define IRQ_XDMA 6 +#define IRQ_VIDEO 7 +#define IRQ_LPC 8 +#define IRQ_UART0 9 /* UART 1 interrupt */ +#define IRQ_UART1 10 /* UART 2 interrupt */ +//11 reserved +#define IRQ_I2C 12 +#define IRQ_UDC11 13 +//14 reserved +#define IRQ_PECI 15 +#define IRQ_TIMER0 16 /* TIMER 1 interrupt */ +#define IRQ_TIMER1 17 /* TIMER 2 interrupt */ +#define IRQ_TIMER2 18 /* TIMER 3 interrupt */ +#define IRQ_SMC 19 +#define IRQ_GPIO 20 +#define IRQ_SCU 21 +#define IRQ_RTC_SEC 22 +#define IRQ_RTC_DAY 23 +#define IRQ_RTC_HOUR 24 +#define IRQ_RTC_MIN 25 +#define IRQ_RTC 26 +#define IRQ_WDT 27 +#define IRQ_TACHO 28 +#define IRQ_2D 29 +#define IRQ_PCI 30 +#define IRQ_AHBC 31 +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast2100_platform.h b/arch/arm/mach-aspeed/include/mach/ast2100_platform.h new file mode 100644 index 000000000000..6d59ca41ce72 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast2100_platform.h @@ -0,0 +1,56 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST2100_PLATFORM_H_ +#define _AST2100_PLATFORM_H_ 1 + +#define AST_OLD_SMC_BASE 0x10000000 /*Legacy BMC Static Memory */ +#define AST_OLD_SMC_CTRL_BASE 0x16000000 /*Legacy BMC Static Memory Ctrl*/ + +#define AST_AHB_CTRL_BASE 0x1E600000 /* AHB CONTROLLER */ + +#define AST_MIC_BASE 0x1E640000 /* MIC CONTROLLER */ +#define AST_MAC1_BASE 0x1E660000 /* MAC1 */ +#define AST_MAC2_BASE 0x1E680000 /* MAC2 */ + +#define AST_USB20_BASE 0x1E6A0000 /* USB 2.0 VIRTUAL HUB CONTROLLER */ +#define AST_VIC_BASE 0x1E6C0000 /* VIC */ +#define AST_SDMC_BASE 0x1E6E0000 /* MMC */ +#define AST_UDC11_BASE 0x1E6E1000 /* USB11 */ +#define AST_SCU_BASE 0x1E6E2000 /* SCU */ +#define AST_CRYPTO_BASE 0x1E6E3000 /* Crypto */ + +#define AST_GRAPHIC_BASE 0x1E6E6000 /* Graphics */ + +#define AST_VIDEO_BASE 0x1E700000 /* VIDEO ENGINE */ +#define AST_AHB_TO_PBUS_BASE 0x1E720000 /* APB -> PBUS */ +#define AST_MDMA_BASE 0x1E740000 /* MDMA */ +#define AST_2D_BASE 0x1E760000 /* 2D */ +#define AST_GPIO_BASE 0x1E780000 /* GPIO */ +#define AST_RTC_BASE 0x1E781000 /* RTC */ +#define AST_TIMER_BASE 0x1E782000 /* TIMER #0~7*/ +#define AST_UART0_BASE 0x1E783000 /* UART1 */ +#define AST_UART1_BASE 0x1E784000 /* UART2 */ +#define AST_WDT_BASE 0x1E785000 /* WDT */ +#define AST_PWM_BASE 0x1E786000 /* PWM */ +#define AST_VUART0_BASE 0x1E787000 /* VUART1 */ +#define AST_PUART_BASE 0x1E788000 /* PUART */ +#define AST_LPC_BASE 0x1E789000 /* LPC */ +#define AST_I2C_BASE 0x1E78A000 /* I2C */ +#define AST_PECI_BASE 0x1E78B000 /* PECI */ +#define AST_PCIARBITER_BASE 0x1E78C000 /* PCI ARBITER */ + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast2200_irqs.h b/arch/arm/mach-aspeed/include/mach/ast2200_irqs.h new file mode 100644 index 000000000000..f0b880fadf62 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast2200_irqs.h @@ -0,0 +1,65 @@ +/* + * arch/arm/plat-aspeed/include/plat/irqs.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST2200_IRQS_H_ +#define _AST2200_IRQS_H_ 1 + +#define NR_IRQS (AST_VIC_NUM + ARCH_NR_GPIOS) +//--------------GPIO --------------------------------------------------------------- +#define ARCH_NR_GPIOS (GPIO_PORT_NUM*8) +#define IRQ_GPIO_CHAIN_START AST_VIC_NUM + +#define AST_VIC_NUM 32 + +#define IRQ_SDRAM_ECC 0 +#define IRQ_MIC 1 +#define IRQ_MAC0 2 /* MAC 1 interrupt */ +#define IRQ_MAC1 3 /* MAC 2 interrupt */ +#define IRQ_CRYPTO 4 +#define IRQ_USB20_HUB 5 +#define IRQ_EHCI 5 +#define IRQ_XDMA 6 +#define IRQ_VIDEO 7 +#define IRQ_LPC 8 +#define IRQ_UART0 9 /* UART 1 interrupt */ +#define IRQ_UART1 10 /* UART 2 interrupt */ +//11 reserved +#define IRQ_I2C 12 +#define IRQ_UDC11 13 +//14 reserved +#define IRQ_PECI 15 +#define IRQ_TIMER0 16 /* TIMER 1 interrupt */ +#define IRQ_TIMER1 17 /* TIMER 2 interrupt */ +#define IRQ_TIMER2 18 /* TIMER 3 interrupt */ +#define IRQ_SMC 19 +#define IRQ_GPIO 20 +#define IRQ_SCU 21 +#define IRQ_RTC_SEC 22 +#define IRQ_RTC_DAY 23 +#define IRQ_RTC_HOUR 24 +#define IRQ_RTC_MIN 25 +#define IRQ_RTC 26 +#define IRQ_WDT 27 +#define IRQ_TACHO 28 +#define IRQ_2D 29 +#define IRQ_PCI 30 +#define IRQ_AHBC 31 + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast2200_platform.h b/arch/arm/mach-aspeed/include/mach/ast2200_platform.h new file mode 100644 index 000000000000..324e15b1288a --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast2200_platform.h @@ -0,0 +1,55 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST2200_PLATFORM_H_ +#define _AST2200_PLATFORM_H_ 1 + +#define AST_OLD_SMC_BASE 0x10000000 /*Legacy BMC Static Memory */ +#define AST_OLD_SMC_CTRL_BASE 0x16000000 /*Legacy BMC Static Memory Ctrl*/ + +#define AST_AHB_CTRL_BASE 0x1E600000 /* AHB CONTROLLER */ + +#define AST_MIC_BASE 0x1E640000 /* MIC CONTROLLER */ +#define AST_MAC1_BASE 0x1E660000 /* MAC1 */ +#define AST_MAC2_BASE 0x1E680000 /* MAC2 */ + +#define AST_USB20_BASE 0x1E6A0000 /* USB 2.0 VIRTUAL HUB CONTROLLER */ +#define AST_VIC_BASE 0x1E6C0000 /* VIC */ +#define AST_SDMC_BASE 0x1E6E0000 /* MMC */ +#define AST_UDC11_BASE 0x1E6E1000 /* USB11 */ +#define AST_SCU_BASE 0x1E6E2000 /* SCU */ +#define AST_CRYPTO_BASE 0x1E6E3000 /* Crypto */ + +#define AST_GRAPHIC_BASE 0x1E6E6000 /* Graphics */ + +#define AST_VIDEO_BASE 0x1E700000 /* VIDEO ENGINE */ +#define AST_AHB_TO_PBUS_BASE 0x1E720000 /* APB -> PBUS */ +#define AST_MDMA_BASE 0x1E740000 /* MDMA */ +#define AST_2D_BASE 0x1E760000 /* 2D */ +#define AST_GPIO_BASE 0x1E780000 /* GPIO */ +#define AST_RTC_BASE 0x1E781000 /* RTC */ +#define AST_TIMER_BASE 0x1E782000 /* TIMER #0~7*/ +#define AST_UART0_BASE 0x1E783000 /* UART1 */ +#define AST_UART1_BASE 0x1E784000 /* UART2 */ +#define AST_WDT_BASE 0x1E785000 /* WDT */ +#define AST_PWM_BASE 0x1E786000 /* PWM */ +#define AST_VUART0_BASE 0x1E787000 /* VUART1 */ +#define AST_PUART_BASE 0x1E788000 /* PUART */ +#define AST_LPC_BASE 0x1E789000 /* LPC */ +#define AST_I2C_BASE 0x1E78A000 /* I2C */ +#define AST_PECI_BASE 0x1E78B000 /* PECI */ + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast2300_irqs.h b/arch/arm/mach-aspeed/include/mach/ast2300_irqs.h new file mode 100644 index 000000000000..2d7b0c86da66 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast2300_irqs.h @@ -0,0 +1,92 @@ +/* + * arch/arm/plat-aspeed/include/plat/irqs.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST2300_IRQS_H_ +#define _AST2300_IRQS_H_ 1 + +#if defined(CONFIG_ARCH_AST1070) +//----------VIC + GPIO + CVIC chain-------------------------------------------------- +#define NR_IRQS (AST_VIC_NUM + ARCH_NR_GPIOS + AST_CVIC_NUM) +//--------------GPIO --------------------------------------------------------------- +#define ARCH_NR_GPIOS (GPIO_PORT_NUM*8) +#define IRQ_GPIO_CHAIN_START (AST_VIC_NUM) +//---------------CVIC--------------------------------------------------------------- +#define IRQ_C0_VIC_CHAIN IRQ_GPIOL1 +#define IRQ_C0_VIC_CHAIN_START (AST_VIC_NUM + ARCH_NR_GPIOS) +//------------------- --------------------------------------------------------------- +#else +#define NR_IRQS (AST_VIC_NUM + ARCH_NR_GPIOS) +//--------------GPIO --------------------------------------------------------------- +#define ARCH_NR_GPIOS (GPIO_PORT_NUM*8) +#define IRQ_GPIO_CHAIN_START AST_VIC_NUM + +#endif + + +#define AST_VIC_NUM 46 + +#define IRQ_SDRAM_ECC 0 +#define IRQ_MIC 1 +#define IRQ_MAC0 2 /* MAC 1 interrupt */ +#define IRQ_MAC1 3 /* MAC 2 interrupt */ +#define IRQ_CRYPTO 4 +#define IRQ_USB20_HUB 5 +#define IRQ_EHCI 5 +#define IRQ_XDMA 6 +#define IRQ_VIDEO 7 +#define IRQ_LPC 8 +#define IRQ_UART1 9 /* UART 1 interrupt */ +#define IRQ_UART0 10 /* UART 5 interrupt */ +//11 Reserved +#define IRQ_I2C 12 +#define IRQ_UDC11 13 +#define IRQ_UHCI 14 +#define IRQ_PECI 15 +#define IRQ_TIMER0 16 /* TIMER 1 interrupt */ +#define IRQ_TIMER1 17 /* TIMER 2 interrupt */ +#define IRQ_TIMER2 18 /* TIMER 3 interrupt */ +#define IRQ_SMC 19 +#define IRQ_GPIO 20 +#define IRQ_SCU 21 +#define IRQ_RTC 22 +//23 , 24 reserverd +#define IRQ_CRT 25 +#define IRQ_SDHC 26 +#define IRQ_WDT 27 +#define IRQ_TACHO 28 +#define IRQ_2D 29 +#define IRQ_SYS_WAKEUP 30 +#define IRQ_ADC 31 +#define IRQ_UART2 32 /* UART 2 interrupt */ +#define IRQ_UART3 33 /* UART 3 interrupt */ +#define IRQ_UART4 34 /* UART 4 interrupt */ +#define IRQ_TIMER3 35 /* TIMER 4 interrupt */ +#define IRQ_TIMER4 36 +#define IRQ_TIMER5 37 +#define IRQ_TIMER6 38 +#define IRQ_TIMER7 39 /* TIMER 8 interrupt */ +#define IRQ_SGPIO_MASTER 40 +#define IRQ_SGPIO_SLAVE 41 +#define IRQ_MCTP 42 +#define IRQ_JTAG 43 +//#define IRQ_RESERVED 44 +#define IRQ_CPU1 45 + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast2300_platform.h b/arch/arm/mach-aspeed/include/mach/ast2300_platform.h new file mode 100644 index 000000000000..4898856dabce --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast2300_platform.h @@ -0,0 +1,72 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST2300_PLATFORM_H_ +#define _AST2300_PLATFORM_H_ 1 + +#define AST_DRAM_BASE 0x40000000 +#define AST_SRAM_SIZE (SZ_16K) + +#define AST_OLD_SMC_BASE 0x10000000 /*Legacy BMC Static Memory */ +#define AST_OLD_SMC_CTRL_BASE 0x16000000 /*Legacy BMC Static Memory Ctrl*/ + +#define AST_AHB_CTRL_BASE 0x1E600000 /* AHB CONTROLLER */ + +#define AST_FMC_BASE 0x1E620000 /* NEW SMC CONTROLLER */ +#define AST_SPI_BASE 0x1E630000 /* SPI CONTROLLER */ +#define AST_MIC_BASE 0x1E640000 /* MIC CONTROLLER */ +#define AST_MAC0_BASE 0x1E660000 /* MAC1 */ +#define AST_MAC1_BASE 0x1E680000 /* MAC2 */ + +#define AST_USB20_BASE 0x1E6A0000 /* USB 2.0 VIRTUAL HUB CONTROLLER */ +#define AST_UHCI_BASE 0x1E6B0000 /* USB 1.1 HOST CONTROLLER */ +#define AST_VIC_BASE 0x1E6C0000 /* VIC */ +#define AST_SDMC_BASE 0x1E6E0000 /* SDRAM CTRL */ +#define AST_UDC11_BASE 0x1E6E1000 /* USB11 */ +#define AST_SCU_BASE 0x1E6E2000 /* SCU */ +#define AST_CRYPTO_BASE 0x1E6E3000 /* Crypto */ +#define AST_JTAG_BASE 0x1E6E4000 /* JTAG */ +#define AST_GRAPHIC_BASE 0x1E6E6000 /* Graphics */ +#define AST_XDMA_BASE 0x1E6E7000 /* XDMA */ +#define AST_MCTP_BASE 0x1E6E8000 /* MCTP */ +#define AST_ADC_BASE 0x1E6E9000 /* ADC */ + +#define AST_LPC_PLUS_BASE 0x1E6EC000 /* LPC+ Controller */ + +#define AST_VIDEO_BASE 0x1E700000 /* VIDEO ENGINE */ +#define AST_SRAM_BASE 0x1E720000 /* SRAM */ +#define AST_SDHC_BASE 0x1E740000 /* SDHC */ +#define AST_2D_BASE 0x1E760000 /* 2D */ +#define AST_GPIO_BASE 0x1E780000 /* GPIO */ +#define AST_RTC_BASE 0x1E781000 /* RTC */ +#define AST_TIMER_BASE 0x1E782000 /* TIMER #0~7*/ +#define AST_UART1_BASE 0x1E783000 /* UART1 */ +#define AST_UART0_BASE 0x1E784000 /* UART5 */ +#define AST_WDT_BASE 0x1E785000 /* WDT */ +#define AST_PWM_BASE 0x1E786000 /* PWM */ +#define AST_VUART0_BASE 0x1E787000 /* VUART1 */ +#define AST_PUART_BASE 0x1E788000 /* PUART */ +#define AST_LPC_BASE 0x1E789000 /* LPC */ +#define AST_MBX_BASE 0x1E789200 /* MailBox */ +#define AST_I2C_BASE 0x1E78A000 /* I2C */ +#define AST_PECI_BASE 0x1E78B000 /* PECI */ +#define AST_UART2_BASE 0x1E78D000 /* UART2 */ +#define AST_UART3_BASE 0x1E78E000 /* UART3 */ +#define AST_UART4_BASE 0x1E78F000 /* UART4 */ + +#define AST_LPC_BRIDGE 0x60000000 + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast2400_irqs.h b/arch/arm/mach-aspeed/include/mach/ast2400_irqs.h new file mode 100644 index 000000000000..17c59da16c0d --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast2400_irqs.h @@ -0,0 +1,96 @@ +/* + * arch/arm/plat-aspeed/include/plat/irqs.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST2400_IRQS_H_ +#define _AST2400_IRQS_H_ 1 + +#if defined(CONFIG_ARCH_AST1070) +#include <mach/ast1070_irqs.h> +#define MAX_AST1070_NR 2 +//----------VIC + CVIC + GPIO chain-------------------------------------------------- +#define NR_IRQS (AST_VIC_NUM + (AST_CVIC_NUM * MAX_AST1070_NR) + ARCH_NR_GPIOS) +//--------------GPIO --------------------------------------------------------------- +#define ARCH_NR_GPIOS (GPIO_PORT_NUM*8) +#define IRQ_GPIO_CHAIN_START (AST_VIC_NUM + (AST_CVIC_NUM * MAX_AST1070_NR)) +//------------------- --------------------------------------------------------------- +#else +//--------------GPIO --------------------------------------------------------------- +#define ARCH_NR_GPIOS (GPIO_PORT_NUM*8) +#define IRQ_GPIO_CHAIN_START (AST_VIC_NUM) +//------------------- --------------------------------------------------------------- +#define NR_IRQS (AST_VIC_NUM + ARCH_NR_GPIOS) + +#endif + +#define AST_VIC_NUM 51 + +#define IRQ_SDRAM_ECC 0 +#define IRQ_MIC 1 +#define IRQ_MAC0 2 /* MAC 1 interrupt */ +#define IRQ_MAC1 3 /* MAC 2 interrupt */ +#define IRQ_CRYPTO 4 +#define IRQ_USB20_HUB 5 +#define IRQ_EHCI 5 +#define IRQ_XDMA 6 +#define IRQ_VIDEO 7 +#define IRQ_LPC 8 +#define IRQ_UART1 9 /* UART 1 interrupt */ +#define IRQ_UART0 10 /* UART 5 interrupt */ +//11 Reserved +#define IRQ_I2C 12 +#define IRQ_UDC11 13 +#define IRQ_UHCI 14 +#define IRQ_PECI 15 +#define IRQ_TIMER0 16 /* TIMER 1 interrupt */ +#define IRQ_TIMER1 17 /* TIMER 2 interrupt */ +#define IRQ_TIMER2 18 /* TIMER 3 interrupt */ +#define IRQ_SMC 19 +#define IRQ_GPIO 20 +#define IRQ_SCU 21 +#define IRQ_RTC 22 +//23 , 24 reserverd +#define IRQ_CRT 25 +#define IRQ_SDHC 26 +#define IRQ_WDT 27 +#define IRQ_TACHO 28 +#define IRQ_2D 29 +#define IRQ_SYS_WAKEUP 30 +#define IRQ_ADC 31 +#define IRQ_UART2 32 /* UART 2 interrupt */ +#define IRQ_UART3 33 /* UART 3 interrupt */ +#define IRQ_UART4 34 /* UART 4 interrupt */ +#define IRQ_TIMER3 35 /* TIMER 4 interrupt */ +#define IRQ_TIMER4 36 +#define IRQ_TIMER5 37 +#define IRQ_TIMER6 38 +#define IRQ_TIMER7 39 /* TIMER 8 interrupt */ +#define IRQ_SGPIO_MASTER 40 +#define IRQ_SGPIO_SLAVE 41 +#define IRQ_MCTP 42 +#define IRQ_JTAG 43 +//#define IRQ_RESERVED 44 +#define IRQ_CPU1 45 +#define IRQ_MAILBOX 46 +#define IRQ_EXT0 47 +#define IRQ_EXT1 48 +#define IRQ_EXT2 49 +#define IRQ_EXT3 50 + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast2400_platform.h b/arch/arm/mach-aspeed/include/mach/ast2400_platform.h new file mode 100644 index 000000000000..e5079539279f --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast2400_platform.h @@ -0,0 +1,79 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST2400_PLATFORM_H_ +#define _AST2400_PLATFORM_H_ 1 + +#define AST_DRAM_BASE 0x40000000 + +#define AST_SRAM_SIZE (SZ_16K*2) + +#define AST_OLD_SMC_BASE 0x10000000 /*Legacy BMC Static Memory */ +#define AST_OLD_SMC_CTRL_BASE 0x16000000 /*Legacy BMC Static Memory Ctrl*/ + +#define AST_AHB_CTRL_BASE 0x1E600000 /* AHB CONTROLLER */ + +#define AST_FMC_BASE 0x1E620000 /* NEW SMC CONTROLLER */ +#define AST_SPI_BASE 0x1E630000 /* SPI CONTROLLER */ +#define AST_MIC_BASE 0x1E640000 /* MIC CONTROLLER */ +#define AST_MAC0_BASE 0x1E660000 /* MAC1 */ +#define AST_MAC1_BASE 0x1E680000 /* MAC2 */ + +#define AST_USB20_BASE 0x1E6A0000 /* USB 2.0 VIRTUAL HUB CONTROLLER */ +#define AST_EHCI_BASE 0x1E6A1000 /* USB 2.0 HOST CONTROLLER */ +#define AST_UHCI_BASE 0x1E6B0000 /* USB 1.1 HOST CONTROLLER */ +#define AST_VIC_BASE 0x1E6C0000 /* VIC */ +#define AST_SDMC_BASE 0x1E6E0000 /* SDRAM CTRL */ +#define AST_UDC11_BASE 0x1E6E1000 /* USB11 */ +#define AST_SCU_BASE 0x1E6E2000 /* SCU */ +#define AST_CRYPTO_BASE 0x1E6E3000 /* Crypto */ +#define AST_JTAG_BASE 0x1E6E4000 /* JTAG */ +#define AST_GRAPHIC_BASE 0x1E6E6000 /* Graphics */ +#define AST_XDMA_BASE 0x1E6E7000 /* XDMA */ +#define AST_MCTP_BASE 0x1E6E8000 /* MCTP */ +#define AST_ADC_BASE 0x1E6E9000 /* ADC */ + +#define AST_LPC_PLUS_BASE 0x1E6EC000 /* LPC+ Controller */ + +#define AST_VIDEO_BASE 0x1E700000 /* VIDEO ENGINE */ +#define AST_SRAM_BASE 0x1E720000 /* SRAM */ +#define AST_SDHC_BASE 0x1E740000 /* SDHC */ +#define AST_2D_BASE 0x1E760000 /* 2D */ +#define AST_GPIO_BASE 0x1E780000 /* GPIO */ +#define AST_RTC_BASE 0x1E781000 /* RTC */ +#define AST_TIMER_BASE 0x1E782000 /* TIMER #0~7*/ +#define AST_UART1_BASE 0x1E783000 /* UART1 */ +#define AST_UART0_BASE 0x1E784000 /* UART5 */ +#define AST_WDT_BASE 0x1E785000 /* WDT */ +#define AST_PWM_BASE 0x1E786000 /* PWM */ +#define AST_VUART0_BASE 0x1E787000 /* VUART1 */ +#define AST_PUART_BASE 0x1E788000 /* PUART */ +#define AST_LPC_BASE 0x1E789000 /* LPC */ +#define AST_MBX_BASE 0x1E789200 /* MailBox */ +#define AST_I2C_BASE 0x1E78A000 /* I2C */ +#define AST_PECI_BASE 0x1E78B000 /* PECI */ +#define AST_PCIARBITER_BASE 0x1E78C000 /* PCI ARBITER */ +#define AST_UART2_BASE 0x1E78D000 /* UART2 */ +#define AST_UART3_BASE 0x1E78E000 /* UART3 */ +#define AST_UART4_BASE 0x1E78F000 /* UART4 */ +#define AST_SPI0_MEM 0x30000000 + +#define AST_LPC_PLUS_BRIDGE 0x70000000 + +#define AST_LPC_BRIDGE 0x60000000 + + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast_gpio_irqs.h b/arch/arm/mach-aspeed/include/mach/ast_gpio_irqs.h new file mode 100644 index 000000000000..3bae742e064b --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast_gpio_irqs.h @@ -0,0 +1,272 @@ +/* + * file : gpio_irqs.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _GPIO_IRQS_H_ +#define _GPIO_IRQS_H_ 1 + +#if defined(CONFIG_ARCH_AST1010) +#define GPIO_PORT_NUM 19 +#elif defined(CONFIG_ARCH_AST2000) +#define GPIO_PORT_NUM 19 +#elif defined(CONFIG_ARCH_AST2100) +#define GPIO_PORT_NUM 19 +#elif defined(CONFIG_ARCH_AST2200) +#define GPIO_PORT_NUM 19 +#elif defined(CONFIG_ARCH_AST2300) +#define GPIO_PORT_NUM 19 +#elif defined(CONFIG_ARCH_AST2400) +#define GPIO_PORT_NUM 28 +#elif defined(CONFIG_ARCH_AST1520) +#define GPIO_PORT_NUM 28 +#else +#err "no define for gpio irqs.h" +#endif + + +#define IRQ_GPIOA0 (IRQ_GPIO_CHAIN_START + 0) +#define IRQ_GPIOA1 (IRQ_GPIO_CHAIN_START + 1) +#define IRQ_GPIOA2 (IRQ_GPIO_CHAIN_START + 2) +#define IRQ_GPIOA3 (IRQ_GPIO_CHAIN_START + 3) +#define IRQ_GPIOA4 (IRQ_GPIO_CHAIN_START + 4) +#define IRQ_GPIOA5 (IRQ_GPIO_CHAIN_START + 5) +#define IRQ_GPIOA6 (IRQ_GPIO_CHAIN_START + 6) +#define IRQ_GPIOA7 (IRQ_GPIO_CHAIN_START + 7) +#define IRQ_GPIOB0 (IRQ_GPIO_CHAIN_START + 8) +#define IRQ_GPIOB1 (IRQ_GPIO_CHAIN_START + 9) +#define IRQ_GPIOB2 (IRQ_GPIO_CHAIN_START + 10) +#define IRQ_GPIOB3 (IRQ_GPIO_CHAIN_START + 11) +#define IRQ_GPIOB4 (IRQ_GPIO_CHAIN_START + 12) +#define IRQ_GPIOB5 (IRQ_GPIO_CHAIN_START + 13) +#define IRQ_GPIOB6 (IRQ_GPIO_CHAIN_START + 14) +#define IRQ_GPIOB7 (IRQ_GPIO_CHAIN_START + 15) +#define IRQ_GPIOC0 (IRQ_GPIO_CHAIN_START + 16) +#define IRQ_GPIOC1 (IRQ_GPIO_CHAIN_START + 17) +#define IRQ_GPIOC2 (IRQ_GPIO_CHAIN_START + 18) +#define IRQ_GPIOC3 (IRQ_GPIO_CHAIN_START + 19) +#define IRQ_GPIOC4 (IRQ_GPIO_CHAIN_START + 20) +#define IRQ_GPIOC5 (IRQ_GPIO_CHAIN_START + 21) +#define IRQ_GPIOC6 (IRQ_GPIO_CHAIN_START + 22) +#define IRQ_GPIOC7 (IRQ_GPIO_CHAIN_START + 23) +#define IRQ_GPIOD0 (IRQ_GPIO_CHAIN_START + 24) +#define IRQ_GPIOD1 (IRQ_GPIO_CHAIN_START + 25) +#define IRQ_GPIOD2 (IRQ_GPIO_CHAIN_START + 26) +#define IRQ_GPIOD3 (IRQ_GPIO_CHAIN_START + 27) +#define IRQ_GPIOD4 (IRQ_GPIO_CHAIN_START + 28) +#define IRQ_GPIOD5 (IRQ_GPIO_CHAIN_START + 29) +#define IRQ_GPIOD6 (IRQ_GPIO_CHAIN_START + 30) +#define IRQ_GPIOD7 (IRQ_GPIO_CHAIN_START + 31) +#define IRQ_GPIOE0 (IRQ_GPIO_CHAIN_START + 32) +#define IRQ_GPIOE1 (IRQ_GPIO_CHAIN_START + 33) +#define IRQ_GPIOE2 (IRQ_GPIO_CHAIN_START + 34) +#define IRQ_GPIOE3 (IRQ_GPIO_CHAIN_START + 35) +#define IRQ_GPIOE4 (IRQ_GPIO_CHAIN_START + 36) +#define IRQ_GPIOE5 (IRQ_GPIO_CHAIN_START + 37) +#define IRQ_GPIOE6 (IRQ_GPIO_CHAIN_START + 38) +#define IRQ_GPIOE7 (IRQ_GPIO_CHAIN_START + 39) +#define IRQ_GPIOF0 (IRQ_GPIO_CHAIN_START + 40) +#define IRQ_GPIOF1 (IRQ_GPIO_CHAIN_START + 41) +#define IRQ_GPIOF2 (IRQ_GPIO_CHAIN_START + 42) +#define IRQ_GPIOF3 (IRQ_GPIO_CHAIN_START + 43) +#define IRQ_GPIOF4 (IRQ_GPIO_CHAIN_START + 44) +#define IRQ_GPIOF5 (IRQ_GPIO_CHAIN_START + 45) +#define IRQ_GPIOF6 (IRQ_GPIO_CHAIN_START + 46) +#define IRQ_GPIOF7 (IRQ_GPIO_CHAIN_START + 47) +#define IRQ_GPIOG0 (IRQ_GPIO_CHAIN_START + 48) +#define IRQ_GPIOG1 (IRQ_GPIO_CHAIN_START + 49) +#define IRQ_GPIOG2 (IRQ_GPIO_CHAIN_START + 50) +#define IRQ_GPIOG3 (IRQ_GPIO_CHAIN_START + 51) +#define IRQ_GPIOG4 (IRQ_GPIO_CHAIN_START + 52) +#define IRQ_GPIOG5 (IRQ_GPIO_CHAIN_START + 53) +#define IRQ_GPIOG6 (IRQ_GPIO_CHAIN_START + 54) +#define IRQ_GPIOG7 (IRQ_GPIO_CHAIN_START + 55) +#define IRQ_GPIOH0 (IRQ_GPIO_CHAIN_START + 56) +#define IRQ_GPIOH1 (IRQ_GPIO_CHAIN_START + 57) +#define IRQ_GPIOH2 (IRQ_GPIO_CHAIN_START + 58) +#define IRQ_GPIOH3 (IRQ_GPIO_CHAIN_START + 59) +#define IRQ_GPIOH4 (IRQ_GPIO_CHAIN_START + 60) +#define IRQ_GPIOH5 (IRQ_GPIO_CHAIN_START + 61) +#define IRQ_GPIOH6 (IRQ_GPIO_CHAIN_START + 62) +#define IRQ_GPIOH7 (IRQ_GPIO_CHAIN_START + 63) +#define IRQ_GPIOI0 (IRQ_GPIO_CHAIN_START + 64) +#define IRQ_GPIOI1 (IRQ_GPIO_CHAIN_START + 65) +#define IRQ_GPIOI2 (IRQ_GPIO_CHAIN_START + 66) +#define IRQ_GPIOI3 (IRQ_GPIO_CHAIN_START + 67) +#define IRQ_GPIOI4 (IRQ_GPIO_CHAIN_START + 68) +#define IRQ_GPIOI5 (IRQ_GPIO_CHAIN_START + 69) +#define IRQ_GPIOI6 (IRQ_GPIO_CHAIN_START + 70) +#define IRQ_GPIOI7 (IRQ_GPIO_CHAIN_START + 71) +#define IRQ_GPIOJ0 (IRQ_GPIO_CHAIN_START + 72) +#define IRQ_GPIOJ1 (IRQ_GPIO_CHAIN_START + 73) +#define IRQ_GPIOJ2 (IRQ_GPIO_CHAIN_START + 74) +#define IRQ_GPIOJ3 (IRQ_GPIO_CHAIN_START + 75) +#define IRQ_GPIOJ4 (IRQ_GPIO_CHAIN_START + 76) +#define IRQ_GPIOJ5 (IRQ_GPIO_CHAIN_START + 77) +#define IRQ_GPIOJ6 (IRQ_GPIO_CHAIN_START + 78) +#define IRQ_GPIOJ7 (IRQ_GPIO_CHAIN_START + 79) +#define IRQ_GPIOK0 (IRQ_GPIO_CHAIN_START + 80) +#define IRQ_GPIOK1 (IRQ_GPIO_CHAIN_START + 81) +#define IRQ_GPIOK2 (IRQ_GPIO_CHAIN_START + 82) +#define IRQ_GPIOK3 (IRQ_GPIO_CHAIN_START + 83) +#define IRQ_GPIOK4 (IRQ_GPIO_CHAIN_START + 84) +#define IRQ_GPIOK5 (IRQ_GPIO_CHAIN_START + 85) +#define IRQ_GPIOK6 (IRQ_GPIO_CHAIN_START + 86) +#define IRQ_GPIOK7 (IRQ_GPIO_CHAIN_START + 87) +#define IRQ_GPIOL0 (IRQ_GPIO_CHAIN_START + 88) +#define IRQ_GPIOL1 (IRQ_GPIO_CHAIN_START + 89) +#define IRQ_GPIOL2 (IRQ_GPIO_CHAIN_START + 90) +#define IRQ_GPIOL3 (IRQ_GPIO_CHAIN_START + 91) +#define IRQ_GPIOL4 (IRQ_GPIO_CHAIN_START + 92) +#define IRQ_GPIOL5 (IRQ_GPIO_CHAIN_START + 93) +#define IRQ_GPIOL6 (IRQ_GPIO_CHAIN_START + 94) +#define IRQ_GPIOL7 (IRQ_GPIO_CHAIN_START + 95) +#define IRQ_GPIOM0 (IRQ_GPIO_CHAIN_START + 96) +#define IRQ_GPIOM1 (IRQ_GPIO_CHAIN_START + 97) +#define IRQ_GPIOM2 (IRQ_GPIO_CHAIN_START + 98) +#define IRQ_GPIOM3 (IRQ_GPIO_CHAIN_START + 99) +#define IRQ_GPIOM4 (IRQ_GPIO_CHAIN_START + 100) +#define IRQ_GPIOM5 (IRQ_GPIO_CHAIN_START + 101) +#define IRQ_GPIOM6 (IRQ_GPIO_CHAIN_START + 102) +#define IRQ_GPIOM7 (IRQ_GPIO_CHAIN_START + 103) +#define IRQ_GPION0 (IRQ_GPIO_CHAIN_START + 104) +#define IRQ_GPION1 (IRQ_GPIO_CHAIN_START + 105) +#define IRQ_GPION2 (IRQ_GPIO_CHAIN_START + 106) +#define IRQ_GPION3 (IRQ_GPIO_CHAIN_START + 107) +#define IRQ_GPION4 (IRQ_GPIO_CHAIN_START + 108) +#define IRQ_GPION5 (IRQ_GPIO_CHAIN_START + 109) +#define IRQ_GPION6 (IRQ_GPIO_CHAIN_START + 110) +#define IRQ_GPION7 (IRQ_GPIO_CHAIN_START + 111) +#define IRQ_GPIOO0 (IRQ_GPIO_CHAIN_START + 112) +#define IRQ_GPIOO1 (IRQ_GPIO_CHAIN_START + 113) +#define IRQ_GPIOO2 (IRQ_GPIO_CHAIN_START + 114) +#define IRQ_GPIOO3 (IRQ_GPIO_CHAIN_START + 115) +#define IRQ_GPIOO4 (IRQ_GPIO_CHAIN_START + 116) +#define IRQ_GPIOO5 (IRQ_GPIO_CHAIN_START + 117) +#define IRQ_GPIOO6 (IRQ_GPIO_CHAIN_START + 118) +#define IRQ_GPIOO7 (IRQ_GPIO_CHAIN_START + 119) +#define IRQ_GPIOP0 (IRQ_GPIO_CHAIN_START + 120) +#define IRQ_GPIOP1 (IRQ_GPIO_CHAIN_START + 121) +#define IRQ_GPIOP2 (IRQ_GPIO_CHAIN_START + 122) +#define IRQ_GPIOP3 (IRQ_GPIO_CHAIN_START + 123) +#define IRQ_GPIOP4 (IRQ_GPIO_CHAIN_START + 124) +#define IRQ_GPIOP5 (IRQ_GPIO_CHAIN_START + 125) +#define IRQ_GPIOP6 (IRQ_GPIO_CHAIN_START + 126) +#define IRQ_GPIOP7 (IRQ_GPIO_CHAIN_START + 127) +#define IRQ_GPIOQ0 (IRQ_GPIO_CHAIN_START + 128) +#define IRQ_GPIOQ1 (IRQ_GPIO_CHAIN_START + 129) +#define IRQ_GPIOQ2 (IRQ_GPIO_CHAIN_START + 130) +#define IRQ_GPIOQ3 (IRQ_GPIO_CHAIN_START + 131) +#define IRQ_GPIOQ4 (IRQ_GPIO_CHAIN_START + 132) +#define IRQ_GPIOQ5 (IRQ_GPIO_CHAIN_START + 133) +#define IRQ_GPIOQ6 (IRQ_GPIO_CHAIN_START + 134) +#define IRQ_GPIOQ7 (IRQ_GPIO_CHAIN_START + 135) +#define IRQ_GPIOR0 (IRQ_GPIO_CHAIN_START + 136) +#define IRQ_GPIOR1 (IRQ_GPIO_CHAIN_START + 137) +#define IRQ_GPIOR2 (IRQ_GPIO_CHAIN_START + 138) +#define IRQ_GPIOR3 (IRQ_GPIO_CHAIN_START + 139) +#define IRQ_GPIOR4 (IRQ_GPIO_CHAIN_START + 140) +#define IRQ_GPIOR5 (IRQ_GPIO_CHAIN_START + 141) +#define IRQ_GPIOR6 (IRQ_GPIO_CHAIN_START + 142) +#define IRQ_GPIOR7 (IRQ_GPIO_CHAIN_START + 143) +#define IRQ_GPIOS0 (IRQ_GPIO_CHAIN_START + 144) +#define IRQ_GPIOS1 (IRQ_GPIO_CHAIN_START + 145) +#define IRQ_GPIOS2 (IRQ_GPIO_CHAIN_START + 146) +#define IRQ_GPIOS3 (IRQ_GPIO_CHAIN_START + 147) +#define IRQ_GPIOS4 (IRQ_GPIO_CHAIN_START + 148) +#define IRQ_GPIOS5 (IRQ_GPIO_CHAIN_START + 149) +#define IRQ_GPIOS6 (IRQ_GPIO_CHAIN_START + 150) +#define IRQ_GPIOS7 (IRQ_GPIO_CHAIN_START + 151) + +#if defined(CONFIG_ARCH_AST2400) || defined(CONFIG_ARCH_AST1520) + +#define IRQ_GPIOT0 (IRQ_GPIO_CHAIN_START + 152) +#define IRQ_GPIOT1 (IRQ_GPIO_CHAIN_START + 153) +#define IRQ_GPIOT2 (IRQ_GPIO_CHAIN_START + 154) +#define IRQ_GPIOT3 (IRQ_GPIO_CHAIN_START + 155) +#define IRQ_GPIOT4 (IRQ_GPIO_CHAIN_START + 156) +#define IRQ_GPIOT5 (IRQ_GPIO_CHAIN_START + 157) +#define IRQ_GPIOT6 (IRQ_GPIO_CHAIN_START + 158) +#define IRQ_GPIOT7 (IRQ_GPIO_CHAIN_START + 159) +#define IRQ_GPIOU0 (IRQ_GPIO_CHAIN_START + 161) +#define IRQ_GPIOU1 (IRQ_GPIO_CHAIN_START + 162) +#define IRQ_GPIOU2 (IRQ_GPIO_CHAIN_START + 163) +#define IRQ_GPIOU3 (IRQ_GPIO_CHAIN_START + 164) +#define IRQ_GPIOU4 (IRQ_GPIO_CHAIN_START + 165) +#define IRQ_GPIOU5 (IRQ_GPIO_CHAIN_START + 166) +#define IRQ_GPIOU6 (IRQ_GPIO_CHAIN_START + 167) +#define IRQ_GPIOU7 (IRQ_GPIO_CHAIN_START + 168) +#define IRQ_GPIOV0 (IRQ_GPIO_CHAIN_START + 169) +#define IRQ_GPIOV1 (IRQ_GPIO_CHAIN_START + 170) +#define IRQ_GPIOV2 (IRQ_GPIO_CHAIN_START + 171) +#define IRQ_GPIOV3 (IRQ_GPIO_CHAIN_START + 172) +#define IRQ_GPIOV4 (IRQ_GPIO_CHAIN_START + 173) +#define IRQ_GPIOV5 (IRQ_GPIO_CHAIN_START + 174) +#define IRQ_GPIOV6 (IRQ_GPIO_CHAIN_START + 175) +#define IRQ_GPIOV7 (IRQ_GPIO_CHAIN_START + 176) +#define IRQ_GPIOW0 (IRQ_GPIO_CHAIN_START + 177) +#define IRQ_GPIOW1 (IRQ_GPIO_CHAIN_START + 178) +#define IRQ_GPIOW2 (IRQ_GPIO_CHAIN_START + 179) +#define IRQ_GPIOW3 (IRQ_GPIO_CHAIN_START + 181) +#define IRQ_GPIOW4 (IRQ_GPIO_CHAIN_START + 182) +#define IRQ_GPIOW5 (IRQ_GPIO_CHAIN_START + 183) +#define IRQ_GPIOW6 (IRQ_GPIO_CHAIN_START + 184) +#define IRQ_GPIOW7 (IRQ_GPIO_CHAIN_START + 185) +#define IRQ_GPIOX0 (IRQ_GPIO_CHAIN_START + 186) +#define IRQ_GPIOX1 (IRQ_GPIO_CHAIN_START + 187) +#define IRQ_GPIOX2 (IRQ_GPIO_CHAIN_START + 188) +#define IRQ_GPIOX3 (IRQ_GPIO_CHAIN_START + 189) +#define IRQ_GPIOX4 (IRQ_GPIO_CHAIN_START + 190) +#define IRQ_GPIOX5 (IRQ_GPIO_CHAIN_START + 191) +#define IRQ_GPIOX6 (IRQ_GPIO_CHAIN_START + 192) +#define IRQ_GPIOX7 (IRQ_GPIO_CHAIN_START + 193) +#define IRQ_GPIOY0 (IRQ_GPIO_CHAIN_START + 194) +#define IRQ_GPIOY1 (IRQ_GPIO_CHAIN_START + 195) +#define IRQ_GPIOY2 (IRQ_GPIO_CHAIN_START + 196) +#define IRQ_GPIOY3 (IRQ_GPIO_CHAIN_START + 197) +#define IRQ_GPIOY4 (IRQ_GPIO_CHAIN_START + 198) +#define IRQ_GPIOY5 (IRQ_GPIO_CHAIN_START + 199) +#define IRQ_GPIOY6 (IRQ_GPIO_CHAIN_START + 200) +#define IRQ_GPIOY7 (IRQ_GPIO_CHAIN_START + 201) +#define IRQ_GPIOZ0 (IRQ_GPIO_CHAIN_START + 202) +#define IRQ_GPIOZ1 (IRQ_GPIO_CHAIN_START + 203) +#define IRQ_GPIOZ2 (IRQ_GPIO_CHAIN_START + 204) +#define IRQ_GPIOZ3 (IRQ_GPIO_CHAIN_START + 205) +#define IRQ_GPIOZ4 (IRQ_GPIO_CHAIN_START + 206) +#define IRQ_GPIOZ5 (IRQ_GPIO_CHAIN_START + 207) +#define IRQ_GPIOZ6 (IRQ_GPIO_CHAIN_START + 208) +#define IRQ_GPIOZ7 (IRQ_GPIO_CHAIN_START + 209) +#define IRQ_GPIOAA0 (IRQ_GPIO_CHAIN_START + 210) +#define IRQ_GPIOAA1 (IRQ_GPIO_CHAIN_START + 211) +#define IRQ_GPIOAA2 (IRQ_GPIO_CHAIN_START + 212) +#define IRQ_GPIOAA3 (IRQ_GPIO_CHAIN_START + 213) +#define IRQ_GPIOAA4 (IRQ_GPIO_CHAIN_START + 214) +#define IRQ_GPIOAA5 (IRQ_GPIO_CHAIN_START + 215) +#define IRQ_GPIOAA6 (IRQ_GPIO_CHAIN_START + 216) +#define IRQ_GPIOAA7 (IRQ_GPIO_CHAIN_START + 217) +#define IRQ_GPIOBB0 (IRQ_GPIO_CHAIN_START + 218) +#define IRQ_GPIOBB1 (IRQ_GPIO_CHAIN_START + 219) +#define IRQ_GPIOBB2 (IRQ_GPIO_CHAIN_START + 220) +#define IRQ_GPIOBB3 (IRQ_GPIO_CHAIN_START + 221) +#define IRQ_GPIOBB4 (IRQ_GPIO_CHAIN_START + 222) +#define IRQ_GPIOBB5 (IRQ_GPIO_CHAIN_START + 223) +#define IRQ_GPIOBB6 (IRQ_GPIO_CHAIN_START + 224) +#define IRQ_GPIOBB7 (IRQ_GPIO_CHAIN_START + 225) +#endif + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast_lcd.h b/arch/arm/mach-aspeed/include/mach/ast_lcd.h new file mode 100755 index 000000000000..20963ebf8dc8 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast_lcd.h @@ -0,0 +1,61 @@ + /******************************************************************************** +* File Name : drivers/video/ast_lcd.h +* Author : Ryan Chen +* Description : ASPEED LCD Panel Timing +* +* Copyright (C) ASPEED Tech. Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/12/27 Ryan Chen create this file +* +* +********************************************************************************/ +#include <linux/fb.h> + +//# Define IO __ for control +#define YUV_MODE 0x4630 +#define CHANGE_YUV_ADDR 0x4631 +#define CHANGE_ADDR 0x4632 +#define OVERSCAN 0x4634 + + +enum astfb_color_format { + ASTFB_COLOR_RGB565 = 0, + ASTFB_COLOR_RGB888, + ASTFB_COLOR_YUV444, + ASTFB_COLOR_YUV420, +}; + +struct aspeed_lcd_panel { + struct fb_videomode mode; + signed short width; /* width in mm */ + signed short height; /* height in mm */ +}; + +struct ast_monitor_info { + int status; //0: no data 1:get data + int type; //0:dvi 1:hdmi + struct fb_monspecs specs; + char edid[256]; +}; + +struct ast_fb_plat_data { + u32 (*get_clk)(void); +}; + +int ast_vga_get_info(struct fb_info *fb_info); +int ast_hdmi_get_info(struct fb_info *fb_info); +void ast_hdmi_enable(int en); +int vga_read_edid(void); + diff --git a/arch/arm/mach-aspeed/include/mach/ast_lpc_irqs.h b/arch/arm/mach-aspeed/include/mach/ast_lpc_irqs.h new file mode 100644 index 000000000000..bbb38789fb04 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast_lpc_irqs.h @@ -0,0 +1,34 @@ +/* + * arch/arm/plat-aspeed/include/plat/gpio_irqs.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _LPC_IRQS_H_ +#define _LPC_IRQS_H_ 1 + +#define AST_LPC_IRQ_NUM 7 + +#define IRQ_KCS0 (IRQ_LPC_CHAIN_START + 0) +#define IRQ_KCS1 (IRQ_LPC_CHAIN_START + 1) +#define IRQ_KCS2 (IRQ_LPC_CHAIN_START + 2) +#define IRQ_KCS3 (IRQ_LPC_CHAIN_START + 3) +#define IRQ_KCS4 (IRQ_LPC_CHAIN_START + 4) +#define IRQ_SNOOP0 (IRQ_LPC_CHAIN_START + 5) +#define IRQ_SNOOP1 (IRQ_LPC_CHAIN_START + 6) + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast_pwm_techo.h b/arch/arm/mach-aspeed/include/mach/ast_pwm_techo.h new file mode 100644 index 000000000000..51d4ae317cc2 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast_pwm_techo.h @@ -0,0 +1,13 @@ +/*
+ * ast_pwm_techo_h
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+struct ast_pwm_driver_data {
+ u32 (*get_pwm_clock)(void);
+};
+
diff --git a/arch/arm/mach-aspeed/include/mach/ast_spi.h b/arch/arm/mach-aspeed/include/mach/ast_spi.h new file mode 100755 index 000000000000..d612967c7eb5 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast_spi.h @@ -0,0 +1,14 @@ +/*
+ * ast_spi_h
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+struct ast_spi_driver_data {
+ u32 (*get_div)(u32 max_speed_hz);
+ u16 num_chipselect;
+};
diff --git a/arch/arm/mach-aspeed/include/mach/ast_video.h b/arch/arm/mach-aspeed/include/mach/ast_video.h new file mode 100644 index 000000000000..18f918916349 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast_video.h @@ -0,0 +1,89 @@ + /******************************************************************************** +* File Name : drivers/video/ast_video.h +* Author : Ryan Chen +* Description : ASPEED Video Engine +* +* Copyright (C) ASPEED Tech. Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/12/27 Ryan Chen create this file +* +* +********************************************************************************/ +typedef enum ast_video_mode { + VIDEO_SINGLE_MODE = 0, + VIDEO_FRAME_MODE, + VIDEO_STREAM_MODE, +} video_mode; + +//VR08[2] +typedef enum ast_video_source { + VIDEO_SOURCE_UNKNOW = 0, //maybe memory .. TODO ... + VIDEO_SOURCE_INTERNAL, + VIDEO_SOURCE_EXTERNAL, +} video_source; + +//VR08[5] +typedef enum ast_vga_mode { + VIDEO_VGA_DIRECT_MODE = 0, + VIDEO_VGA_CAPTURE_MODE, +} vga_mode; + +//VR08[4] +typedef enum ast_video_dis_en { + VIDEO_EXT_DE_SIGNAL = 0, + VIDEO_INT_DE_SIGNAL, +} display_enable; + +typedef enum video_compress_format { + VIDEO_YUV444 = 0, + VIDEO_YUV420, +} compress_formate; + +typedef enum video_color_format { + VIDEO_COLOR_RGB565 = 0, + VIDEO_COLOR_RGB888, + VIDEO_COLOR_YUV444, + VIDEO_COLOR_YUV420, +} color_formate; + +typedef enum vga_color_mode { + VGA_NO_SIGNAL = 0, + EGA_MODE, + VGA_MODE, + VGA_15BPP_MODE, + VGA_16BPP_MODE, + VGA_32BPP_MODE, +} color_mode; + +typedef enum video_stage { + NONE, + POLARITY, + RESOLUTION, + INIT, + RUN, +} stage; + +struct ast_video_plat_data { + u32 (*get_clk)(void); + void (*ctrl_reset)(void); + void (*vga_display)(u8 enable); + u32 (*get_vga_base)(void); + video_source input_source; + video_mode mode; + u8 rc4_enable; + u8 scaling; + compress_formate compress; +}; + diff --git a/arch/arm/mach-aspeed/include/mach/ast_wdt.h b/arch/arm/mach-aspeed/include/mach/ast_wdt.h new file mode 100755 index 000000000000..6d7d7f470b11 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast_wdt.h @@ -0,0 +1,11 @@ +/*
+ * ast_wdt_h
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+ extern void ast_soc_wdt_reset(void);
diff --git a/arch/arm/mach-aspeed/include/mach/debug-macro.S b/arch/arm/mach-aspeed/include/mach/debug-macro.S new file mode 100644 index 000000000000..0b7c9278b9b0 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/debug-macro.S @@ -0,0 +1,22 @@ +/* debug-macro.S + * + * Debugging macro include header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ +#include <mach/platform.h> +#include <mach/hardware.h> + + .macro addruart, rx, tmp + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =AST_UART0_BASE + ldrne \rx, =IO_ADDRESS(AST_UART0_BASE) + orr \rx, \rx, #0x00012000 + .endm + +#define UART_SHIFT 2 +#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-aspeed/include/mach/dma.h b/arch/arm/mach-aspeed/include/mach/dma.h new file mode 100644 index 000000000000..36c141d6c385 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/dma.h @@ -0,0 +1,25 @@ +/* + * dma.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#define MAX_DMA_ADDRESS 0xffffffff + +#define MAX_DMA_CHANNELS 0 + +#endif /* _ASM_ARCH_DMA_H */ diff --git a/arch/arm/mach-aspeed/include/mach/entry-macro.S b/arch/arm/mach-aspeed/include/mach/entry-macro.S new file mode 100644 index 000000000000..88b4417cbbb4 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/entry-macro.S @@ -0,0 +1,191 @@ +/* + * entry-macro.S + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include <mach/hardware.h> +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/regs-intr.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =IO_ADDRESS(AST_VIC_BASE) + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm +#if 1 + +#if defined(NEW_VIC) + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + ldr \tmp, =IO_ADDRESS(AST_SCU_BASE) + ldr \irqnr, [\tmp, #0x44] + + cmp \irqnr, #0 + beq 2000f + +1000: /* pass1 */ + cmp \irqnr, #32 + ble 1001f + ldr \tmp, =IO_ADDRESS(AST_VIC_BASE) + ldr \irqstat, [\tmp, #0x84] + sub \irqnr, \irqnr, #32 + mov \tmp, #32 + sub \tmp, \tmp, \irqnr + mov \irqstat, \irqstat, lsl \tmp /* mask uncompare parts */ + mov \irqstat, \irqstat, lsr \tmp + mov \irqnr, #63 + clz \tmp, \irqstat + cmp \tmp, #32 + bne 3000f + mov \irqnr, #32 +1001: + ldr \tmp, =IO_ADDRESS(AST_VIC_BASE) + ldr \irqstat, [\tmp, #0x00] + mov \tmp, #32 + sub \tmp, \tmp, \irqnr + mov \irqstat, \irqstat, lsl \tmp /* mask uncompare parts */ + mov \irqstat, \irqstat, lsr \tmp + mov \irqnr, #31 + clz \tmp, \irqstat + cmp \tmp, #32 + bne 3000f + +2000: /* pass 2 */ + ldr \tmp, =IO_ADDRESS(AST_VIC_BASE) + ldr \irqstat, [\tmp, #0x84] + mov \irqnr, #63 + clz \tmp, \irqstat + cmp \tmp, #32 + bne 3000f +2001: + ldr \tmp, =IO_ADDRESS(AST_VIC_BASE) + ldr \irqstat, [\tmp, #0x00] + mov \irqnr, #31 + clz \tmp, \irqstat + cmp \tmp, #32 + beq 4000f /* not find */ + +3000: /* find */ + sub \irqnr, \irqnr, \tmp + ldr \tmp, =IO_ADDRESS(AST_SCU_BASE) + str \irqnr, [\tmp, #0x44] + cmp \irqnr, #64 +4000: /* done */ + .endm +#else + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp +/* FIXME: should not be using soo many LDRs here */ + ldr \irqnr, =IO_ADDRESS(AST_VIC_BASE) + ldr \irqstat, [\irqnr, #ASPEED_VIC_STATUS_OFFSET] @ get masked status + + mov \irqnr, #0 +1001: tst \irqstat, #1 + bne 1002f + add \irqnr, \irqnr, #1 + mov \irqstat, \irqstat, lsr #1 + cmp \irqnr, #31 + bcc 1001b +1002: /* EQ will be set if we reach 31 */ + .endm + +#endif +#else + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + /*********************************************/ + /* load VIC (VIC1) status value into irqstat */ + /*********************************************/ + ldr \irqnr, =IO_ADDRESS(MVP2_VIC_BASE) + ldr \irqstat, [\irqnr, #MVP2_VIC_STATUS_OFFSET] + + + /**********************************************/ + /* check each status bit and start from bit 0 */ + /**********************************************/ + mov \irqnr, #0 +1000: tst \irqstat, #1 /* Check irqstat[irqnr] is 1 or not. */ + bne 1100f /* If irqstat[irqnr] is 1, service */ + /* this interrupt. */ +1001: + /* check next bit */ + add \irqnr, \irqnr, #1 + mov \irqstat, \irqstat, lsr #1 + + cmp \irqnr, #32 /* If irqnr is number 32, all bits on VIC1 */ + beq 1300f /* have been checked and leave this macro. */ + /* Note that the Zero bit should be 1. */ + + bne 1000b /* continue to check next bit */ + + + +1100: ldr \irqstat, =INT_VIC2IRQ /* interrupt from VIC2? */ + cmp \irqnr, \irqstat + + bne 1300f /* Interupt isn't from VIC2 (i.e. irqnr != INT_VIC2IRQ). */ + /* Leave this macro with irqnr isn't changed and keep Zero */ + /* flag not set */ + + + /***************************************/ + /* load VIC2 status value into irqstat */ + /***************************************/ +#if 0 + ldr \irqnr, =IO_ADDRESS(MVP2_VIC2_BASE) + ldr \irqstat, [\irqnr, #MVP2_VIC_STATUS_OFFSET] +#else + ldr \irqnr, =IO_ADDRESS(MVP2_VIC_BASE) + ldr \irqstat, =0x1000 + add \irqnr, \irqnr, \irqstat + ldr \irqstat, [\irqnr, #MVP2_VIC_STATUS_OFFSET] +#endif + + /***********************************************/ + /* Check each status bit and start from bit 0. */ + /* Note that bit 0 in VIC2 is IRQ number 32. */ + /***********************************************/ + mov \irqnr, #32 +1200: tst \irqstat, #1 + bne 1300f + + + /* check next bit */ + add \irqnr, \irqnr, #1 + mov \irqstat, \irqstat, lsr #1 + + cmp \irqnr, #64 /* If irqnr isn't reach 64 */ + bne 1200b /* continue check irqstat. */ + + + + /*************************************************************************/ + /* Examine all the other interrupt bits larger than INT_VIC2IRQ on VIC1. */ + /*************************************************************************/ + ldr \irqnr, =IO_ADDRESS(MVP2_VIC_BASE) + ldr \irqstat, [\irqnr, #MVP2_VIC_STATUS_OFFSET] + mov \irqnr, #INT_VIC2IRQ + mov \irqstat, \irqstat, lsr #INT_VIC2IRQ + b 1001b + + /* TODO : if needed */ + /* All interrupt bits on VIC2 have been checked and no bit with value */ + /* 1 is found. Write 1 to EdgeClearReg[INT_VIC2IRQ] to clear interrupt. */ + +1300: + .endm + +#endif + + + + .macro irq_prio_table + .endm + diff --git a/arch/arm/mach-aspeed/include/mach/ftgmac100_drv.h b/arch/arm/mach-aspeed/include/mach/ftgmac100_drv.h new file mode 100644 index 000000000000..40a59e3495e7 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ftgmac100_drv.h @@ -0,0 +1,18 @@ +/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+/* store this information for the driver.. */
+
+struct ftgmac100_eth_data
+{
+ unsigned char dev_addr[6]; //MAC address
+ unsigned char phy_addr; //Phy Address
+ unsigned char phy_id; //Phy ID
+ unsigned char DF_support; //Defragment support
+ unsigned long NCSI_support;
+ unsigned long INTEL_NCSI_EVA_support;
+};
diff --git a/arch/arm/mach-aspeed/include/mach/gpio.h b/arch/arm/mach-aspeed/include/mach/gpio.h new file mode 100644 index 000000000000..9ff38638641e --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/gpio.h @@ -0,0 +1,352 @@ +/* + * arch/arm/mach-aspeed/include/mach/gpio.h + * + * Support functions for ASPEED GPIO + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * Written by Ryan Chen <ryan_chen@aspeedtech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARCH_ASPEED_GPIO_H +#define __ASM_ARCH_ASPEED_GPIO_H + +#include <linux/kernel.h> +#include <mach/irqs.h> +#include <plat/aspeed.h> + +/*************************************************************/ +#define GPIO_PORTA 0x0 +#define GPIO_PORTB 0x1 +#define GPIO_PORTC 0x2 +#define GPIO_PORTD 0x3 +#define GPIO_PORTE 0x4 +#define GPIO_PORTF 0x5 +#define GPIO_PORTG 0x6 +#define GPIO_PORTH 0x7 +#define GPIO_PORTI 0x8 +#define GPIO_PORTJ 0x9 +#define GPIO_PORTK 0xa +#define GPIO_PORTL 0xb +#define GPIO_PORTM 0xc +#define GPIO_PORTN 0xd +#define GPIO_PORTO 0xe +#define GPIO_PORTP 0xf +#define GPIO_PORTQ 0x10 +#define GPIO_PORTR 0x11 +#define GPIO_PORTS 0x12 +//AST2300 didn't have PORT TT +#define GPIO_PORTT 0x13 +#if defined(AST_SOC_G4) || defined(CONFIG_AST2400_BMC) +#define GPIO_PORTU 0x14 +#define GPIO_PORTV 0x15 +#define GPIO_PORTW 0x16 +#define GPIO_PORTX 0x17 +#define GPIO_PORTY 0x18 +#define GPIO_PORTZ 0x19 +#define GPIO_PORTAA 0x1a +#define GPIO_PORTAB 0x1b +#endif + +#define GPIO_PER_PORT_PIN_NUM 8 + +#define GPIO_INPUT_MODE 0 +#define GPIO_OUTPUT_MODE 1 + +#define GPIO_RISING_EDGE 1 +#define GPIO_FALLING_EDGE 0 + +#define GPIO_LEVEL_HIGH 1 +#define GPIO_LEVEL_LOW 1 + +#define GPIO_EDGE_MODE 0 +#define GPIO_LEVEL_MODE 1 + +#define GPIO_EDGE_LEVEL_MODE 0 +#define GPIO_DUAL_EDGE_MODE 1 + +#define GPIO_NO_DEBOUNCE 0 +#define GPIO_DEBOUNCE_TIMER0 2 //GPIO 50 as debounce timer +#define GPIO_DEBOUNCE_TIMER1 1 //GPIO 54 as debounce timer +#define GPIO_DEBOUNCE_TIMER2 3 //GPIO 58 as debounce timer + +#define GPIO_CMD_ARM 0 +#define GPIO_CMD_LPC 1 +#define GPIO_CMD_COPROCESSOR 2 + +#define PIN_GPIOA0 (0) +#define PIN_GPIOA1 (1) +#define PIN_GPIOA2 (2) +#define PIN_GPIOA3 (3) +#define PIN_GPIOA4 (4) +#define PIN_GPIOA5 (5) +#define PIN_GPIOA6 (6) +#define PIN_GPIOA7 (7) +#define PIN_GPIOB0 (8) +#define PIN_GPIOB1 (9) +#define PIN_GPIOB2 (10) +#define PIN_GPIOB3 (11) +#define PIN_GPIOB4 (12) +#define PIN_GPIOB5 (13) +#define PIN_GPIOB6 (14) +#define PIN_GPIOB7 (15) +#define PIN_GPIOC0 (16) +#define PIN_GPIOC1 (17) +#define PIN_GPIOC2 (18) +#define PIN_GPIOC3 (19) +#define PIN_GPIOC4 (20) +#define PIN_GPIOC5 (21) +#define PIN_GPIOC6 (22) +#define PIN_GPIOC7 (23) +#define PIN_GPIOD0 (24) +#define PIN_GPIOD1 (25) +#define PIN_GPIOD2 (26) +#define PIN_GPIOD3 (27) +#define PIN_GPIOD4 (28) +#define PIN_GPIOD5 (29) +#define PIN_GPIOD6 (30) +#define PIN_GPIOD7 (31) +#define PIN_GPIOE0 (32) +#define PIN_GPIOE1 (33) +#define PIN_GPIOE2 (34) +#define PIN_GPIOE3 (35) +#define PIN_GPIOE4 (36) +#define PIN_GPIOE5 (37) +#define PIN_GPIOE6 (38) +#define PIN_GPIOE7 (39) +#define PIN_GPIOF0 (40) +#define PIN_GPIOF1 (41) +#define PIN_GPIOF2 (42) +#define PIN_GPIOF3 (43) +#define PIN_GPIOF4 (44) +#define PIN_GPIOF5 (45) +#define PIN_GPIOF6 (46) +#define PIN_GPIOF7 (47) +#define PIN_GPIOG0 (48) +#define PIN_GPIOG1 (49) +#define PIN_GPIOG2 (50) +#define PIN_GPIOG3 (51) +#define PIN_GPIOG4 (52) +#define PIN_GPIOG5 (53) +#define PIN_GPIOG6 (54) +#define PIN_GPIOG7 (55) +#define PIN_GPIOH0 (56) +#define PIN_GPIOH1 (57) +#define PIN_GPIOH2 (58) +#define PIN_GPIOH3 (59) +#define PIN_GPIOH4 (60) +#define PIN_GPIOH5 (61) +#define PIN_GPIOH6 (62) +#define PIN_GPIOH7 (63) +#define PIN_GPIOI0 (64) +#define PIN_GPIOI1 (65) +#define PIN_GPIOI2 (66) +#define PIN_GPIOI3 (67) +#define PIN_GPIOI4 (68) +#define PIN_GPIOI5 (69) +#define PIN_GPIOI6 (70) +#define PIN_GPIOI7 (71) +#define PIN_GPIOJ0 (72) +#define PIN_GPIOJ1 (73) +#define PIN_GPIOJ2 (74) +#define PIN_GPIOJ3 (75) +#define PIN_GPIOJ4 (76) +#define PIN_GPIOJ5 (77) +#define PIN_GPIOJ6 (78) +#define PIN_GPIOJ7 (79) +#define PIN_GPIOK0 (80) +#define PIN_GPIOK1 (81) +#define PIN_GPIOK2 (82) +#define PIN_GPIOK3 (83) +#define PIN_GPIOK4 (84) +#define PIN_GPIOK5 (85) +#define PIN_GPIOK6 (86) +#define PIN_GPIOK7 (87) +#define PIN_GPIOL0 (88) +#define PIN_GPIOL1 (89) +#define PIN_GPIOL2 (90) +#define PIN_GPIOL3 (91) +#define PIN_GPIOL4 (92) +#define PIN_GPIOL5 (93) +#define PIN_GPIOL6 (94) +#define PIN_GPIOL7 (95) +#define PIN_GPIOM0 (96) +#define PIN_GPIOM1 (97) +#define PIN_GPIOM2 (98) +#define PIN_GPIOM3 (99) +#define PIN_GPIOM4 (100) +#define PIN_GPIOM5 (101) +#define PIN_GPIOM6 (102) +#define PIN_GPIOM7 (103) +#define PIN_GPION0 (104) +#define PIN_GPION1 (105) +#define PIN_GPION2 (106) +#define PIN_GPION3 (107) +#define PIN_GPION4 (108) +#define PIN_GPION5 (109) +#define PIN_GPION6 (110) +#define PIN_GPION7 (111) +#define PIN_GPIOO0 (112) +#define PIN_GPIOO1 (113) +#define PIN_GPIOO2 (114) +#define PIN_GPIOO3 (115) +#define PIN_GPIOO4 (116) +#define PIN_GPIOO5 (117) +#define PIN_GPIOO6 (118) +#define PIN_GPIOO7 (119) +#define PIN_GPIOP0 (120) +#define PIN_GPIOP1 (121) +#define PIN_GPIOP2 (122) +#define PIN_GPIOP3 (123) +#define PIN_GPIOP4 (124) +#define PIN_GPIOP5 (125) +#define PIN_GPIOP6 (126) +#define PIN_GPIOP7 (127) +#define PIN_GPIOQ0 (128) +#define PIN_GPIOQ1 (129) +#define PIN_GPIOQ2 (130) +#define PIN_GPIOQ3 (131) +#define PIN_GPIOQ4 (132) +#define PIN_GPIOQ5 (133) +#define PIN_GPIOQ6 (134) +#define PIN_GPIOQ7 (135) +#define PIN_GPIOR0 (136) +#define PIN_GPIOR1 (137) +#define PIN_GPIOR2 (138) +#define PIN_GPIOR3 (139) +#define PIN_GPIOR4 (140) +#define PIN_GPIOR5 (141) +#define PIN_GPIOR6 (142) +#define PIN_GPIOR7 (143) +#define PIN_GPIOS0 (144) +#define PIN_GPIOS1 (145) +#define PIN_GPIOS2 (146) +#define PIN_GPIOS3 (147) +#define PIN_GPIOS4 (148) +#define PIN_GPIOS5 (149) +#define PIN_GPIOS6 (150) +#define PIN_GPIOS7 (151) +#if defined(AST_SOC_G4) || defined(CONFIG_AST2400_BMC) +#define PIN_GPIOT0 (152) +#define PIN_GPIOT1 (153) +#define PIN_GPIOT2 (154) +#define PIN_GPIOT3 (155) +#define PIN_GPIOT4 (156) +#define PIN_GPIOT5 (157) +#define PIN_GPIOT6 (158) +#define PIN_GPIOT7 (159) +#define PIN_GPIOU0 (161) +#define PIN_GPIOU1 (162) +#define PIN_GPIOU2 (163) +#define PIN_GPIOU3 (164) +#define PIN_GPIOU4 (165) +#define PIN_GPIOU5 (166) +#define PIN_GPIOU6 (167) +#define PIN_GPIOU7 (168) +#define PIN_GPIOV0 (169) +#define PIN_GPIOV1 (170) +#define PIN_GPIOV2 (171) +#define PIN_GPIOV3 (172) +#define PIN_GPIOV4 (173) +#define PIN_GPIOV5 (174) +#define PIN_GPIOV6 (175) +#define PIN_GPIOV7 (176) +#define PIN_GPIOW0 (177) +#define PIN_GPIOW1 (178) +#define PIN_GPIOW2 (179) +#define PIN_GPIOW3 (181) +#define PIN_GPIOW4 (182) +#define PIN_GPIOW5 (183) +#define PIN_GPIOW6 (184) +#define PIN_GPIOW7 (185) +#define PIN_GPIOX0 (186) +#define PIN_GPIOX1 (187) +#define PIN_GPIOX2 (188) +#define PIN_GPIOX3 (189) +#define PIN_GPIOX4 (190) +#define PIN_GPIOX5 (191) +#define PIN_GPIOX6 (192) +#define PIN_GPIOX7 (193) +#define PIN_GPIOY0 (194) +#define PIN_GPIOY1 (195) +#define PIN_GPIOY2 (196) +#define PIN_GPIOY3 (197) +#define PIN_GPIOY4 (198) +#define PIN_GPIOY5 (199) +#define PIN_GPIOY6 (200) +#define PIN_GPIOY7 (201) +#define PIN_GPIOZ0 (202) +#define PIN_GPIOZ1 (203) +#define PIN_GPIOZ2 (204) +#define PIN_GPIOZ3 (205) +#define PIN_GPIOZ4 (206) +#define PIN_GPIOZ5 (207) +#define PIN_GPIOZ6 (208) +#define PIN_GPIOZ7 (209) +#define PIN_GPIOAA0 (210) +#define PIN_GPIOAA1 (211) +#define PIN_GPIOAA2 (212) +#define PIN_GPIOAA3 (213) +#define PIN_GPIOAA4 (214) +#define PIN_GPIOAA5 (215) +#define PIN_GPIOAA6 (216) +#define PIN_GPIOAA7 (217) +#define PIN_GPIOBB0 (218) +#define PIN_GPIOBB1 (219) +#define PIN_GPIOBB2 (220) +#define PIN_GPIOBB3 (221) +#define PIN_GPIOBB4 (222) +#define PIN_GPIOBB5 (223) +#define PIN_GPIOBB6 (224) +#define PIN_GPIOBB7 (225) +#endif +/*************************************************************/ +#ifndef __ASSEMBLY__ + +/* callable at any time */ +extern int ast_set_gpio_value(unsigned gpio_pin, int value); +extern int ast_get_gpio_value(unsigned gpio_pin); + +/*-------------------------------------------------------------------------*/ + +/* wrappers for "new style" GPIO calls. the old AT91-specfic ones should + * eventually be removed (along with this errno.h inclusion), and the + * gpio request/free calls should probably be implemented. + */ + +//extern int gpio_direction_input(unsigned gpio); +//extern int gpio_direction_output(unsigned gpio, int value); + +static inline int gpio_get_value(unsigned gpio) +{ + return ast_get_gpio_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + ast_set_gpio_value(gpio, value); +} + +#include <asm-generic/gpio.h> /* cansleep wrappers */ + +#define gpio_to_irq(gpio) (IRQ_GPIO_CHAIN_START + (gpio)) +#define irq_to_gpio(irq) ((irq) - IRQ_GPIO_CHAIN_START) + +#endif /* __ASSEMBLY__ */ + + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/hardware.h b/arch/arm/mach-aspeed/include/mach/hardware.h new file mode 100644 index 000000000000..be3f23d22aa0 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/hardware.h @@ -0,0 +1,51 @@ +/* + * hardware.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <mach/platform.h> + +/* + * Where in virtual memory the IO devices (timers, system controllers + * and so on) + */ + +#define IO_BASE 0xF8000000 // VA of IO +/*#define IO_BASE2 0xE0000000 // VA of IO2 (AST1070) */ + +#ifdef CONFIG_AST_PCIE_EXT +#define ASPEED_IO_START2 AST_PCIE_WIN_BASE +#else +#define ASPEED_IO_START2 AST_LPC_BRIDGE +#endif + +/* macro to get at IO space when running virtually */ +//#define IO_ADDRESS(x) (((x) >> 4) + IO_BASE) +/*#define IO_ADDRESS(x) (x - 0x10000000 + IO_BASE) */ +#define IO_ADDRESS(x) (x - 0x1e600000 + IO_BASE) +/*#define IO_ADDRESS2(x) (x - ASPEED_IO_START2 + IO_BASE2) */ + +//PCIE +#ifdef CONFIG_AST_PCIE +#define PCIBIOS_MIN_IO 0x0 +#define PCIBIOS_MIN_MEM 0x0 +#define pcibios_assign_all_busses() 1 +#endif + +#endif /* __ASM_ARCH_HARDWARE_H END */ + diff --git a/arch/arm/mach-aspeed/include/mach/io.h b/arch/arm/mach-aspeed/include/mach/io.h new file mode 100644 index 000000000000..baf86d2dd677 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/io.h @@ -0,0 +1,28 @@ +/* + * io.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#include <mach/hardware.h> +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) ((void __iomem *)(a)) +#define __mem_pci(a) (a) +#define __mem_isa(a) (a) +#endif + diff --git a/arch/arm/mach-aspeed/include/mach/irqs.h b/arch/arm/mach-aspeed/include/mach/irqs.h new file mode 100644 index 000000000000..d13325143bf9 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/irqs.h @@ -0,0 +1,61 @@ +/* + * arch/arm/plat-aspeed/include/plat/irqs.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <plat/aspeed.h> + +#if defined(CONFIG_ARCH_AST1010) +#include <mach/ast1010_irqs.h> +#elif defined(CONFIG_ARCH_AST1510) +#include <mach/ast1510_irqs.h> +#elif defined(CONFIG_ARCH_AST1520) +#include <mach/ast1520_irqs.h> +#elif defined(CONFIG_ARCH_AST2000) +#include <mach/ast2000_irqs.h> +#elif defined(CONFIG_ARCH_AST2100) +#include <mach/ast2100_irqs.h> +#elif defined(CONFIG_ARCH_AST2200) +#include <mach/ast2200_irqs.h> +#elif defined(CONFIG_ARCH_AST2300) +#include <mach/ast2300_irqs.h> +#elif defined(CONFIG_ARCH_AST2400) +#include <mach/ast2400_irqs.h> +#elif defined(CONFIG_ARCH_AST2500) +#include <mach/ast2500_irqs.h> +#elif defined(CONFIG_ARCH_AST3100) +#include <mach/ast3100_irqs.h> +#elif defined(CONFIG_ARCH_AST3200) +#include <mach/ast3200_irqs.h> +#else +#err "no define for irqs.h" +#endif + +#include <mach/ast_gpio_irqs.h> +//#include <mach/ast_lpc_irqs.h> + +/*********************************************************************************/ +//CVIC +#if defined(CONFIG_ARCH_AST1070) +//Companion chip irq +#include <mach/ast1070_irqs.h> +#endif + +#if defined(CONFIG_AST2400_BMC) +#include <mach/ext_ast2400_irqs.h> +#endif diff --git a/arch/arm/mach-aspeed/include/mach/memory.h b/arch/arm/mach-aspeed/include/mach/memory.h new file mode 100644 index 000000000000..d9927b22f375 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/memory.h @@ -0,0 +1,48 @@ +/* + * memory.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <mach/platform.h> +#include <plat/aspeed.h> + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +/* + * Physical DRAM offset. + */ +#if defined(AST_SOC_G3) || defined(AST_SOC_G4) +#define PHYS_OFFSET UL(0x40000000) +#define BUS_OFFSET UL(0x40000000) +#elif defined(AST_SOC_G5) +#define PHYS_OFFSET UL(0x80000000) +#define BUS_OFFSET UL(0x80000000) +#else +#define PHYS_OFFSET UL(0x40000000) +#define BUS_OFFSET UL(0x40000000) +#endif + +/* + * Virtual view <-> DMA view memory address translations + * virt_to_bus: Used to translate the virtual address to an + * address suitable to be passed to set_dma_addr + * bus_to_virt: Used to convert an address for DMA operations + * to an address that the kernel can use. + */ +#define __virt_to_bus(x) (x - PAGE_OFFSET + BUS_OFFSET) +#define __bus_to_virt(x) (x - BUS_OFFSET + PAGE_OFFSET) + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/platform.h b/arch/arm/mach-aspeed/include/mach/platform.h new file mode 100644 index 000000000000..8951ffc47012 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/platform.h @@ -0,0 +1,66 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST_PLATFORM_H_ +#define _AST_PLATFORM_H_ 1 + +#define AST_PLL_25MHZ 25000000 +#define AST_PLL_24MHZ 24000000 +#define AST_PLL_12MHZ 12000000 + +#define AST_IO_START 0x1E600000 +#define AST_IO_SIZE 0x00200000 + +/*********************************************************************************/ +#if defined(CONFIG_ARCH_AST1520) +#include <mach/ast1520_platform.h> +#elif defined(CONFIG_ARCH_AST2000) +#include <mach/ast2000_platform.h> +#elif defined(CONFIG_ARCH_AST2100) +#include <mach/ast2100_platform.h> +#elif defined(CONFIG_ARCH_AST2200) +#include <mach/ast2200_platform.h> +#elif defined(CONFIG_ARCH_AST2300) +#include <mach/ast2300_platform.h> +#elif defined(CONFIG_ARCH_AST2400) +#include <mach/ast2400_platform.h> +#elif defined(CONFIG_ARCH_AST2500) +#include <mach/ast2500_platform.h> +#elif defined(CONFIG_ARCH_AST3200) +#include <mach/ast3200_platform.h> +#else +#err "No define for platform.h" +#endif +/*********************************************************************************/ +/* Companion Base Address */ +#if defined(CONFIG_ARCH_AST1070) +#include <mach/ast1070_platform.h> +#endif +/*********************************************************************************/ +#define AST_CS0_DEF_BASE 0x20000000 /* CS0 */ +#define AST_CS1_DEF_BASE 0x24000000 /* CS1 */ +#define AST_CS2_DEF_BASE 0x26000000 /* CS2 */ +#define AST_CS3_DEF_BASE 0x28000000 /* CS3 */ +#define AST_CS4_DEF_BASE 0x2a000000 /* CS4 */ + +#define AST_NOR_SIZE 0x01000000 /* AST2300 NOR size 16MB */ + +/* + * Watchdog + */ +#define AST_WDT_VA_BASE (IO_ADDRESS(AST_WDT_BASE)) + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/system.h b/arch/arm/mach-aspeed/include/mach/system.h new file mode 100644 index 000000000000..96e90dad52fc --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/system.h @@ -0,0 +1,44 @@ +/* + * system.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include <mach/hardware.h> +#include <asm/io.h> +#include <mach/ast_wdt.h> + +static inline void arch_idle(void) +{ + /* + * This should do all the clock switching + * and wait for interrupt tricks + */ + cpu_do_idle(); +} + +static inline void arch_reset(char mode) +{ + /* + * Use WDT to restart system + */ +#if defined(CONFIG_AST_WATCHDOG) || defined(CONFIG_AST_WATCHDOG_MODULE) + ast_soc_wdt_reset(); +#endif +} + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/time.h b/arch/arm/mach-aspeed/include/mach/time.h new file mode 100644 index 000000000000..973a0b004d7a --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/time.h @@ -0,0 +1,73 @@ +/* + * time.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <asm/system.h> +#include <asm/mach/time.h> +#include <asm/param.h> + +/* + * How long is the timer interval? + */ +#define TIMER_INTERVAL (ASPEED_TIMER_CLKRATE / HZ) +#define TIMER_RELOAD (TIMER_INTERVAL) +#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) + +/* + * Timer + */ +#define ASPEED_TIMER0_OFFSET 0x0000 /* Timer0 Offset */ +#define ASPEED_TIMER1_OFFSET 0x0010 /* Timer1 Offset */ +#define ASPEED_TIMER2_OFFSET 0x0020 /* Timer2 Offset */ +#define ASPEED_TIMERRC_OFFSET 0x0030 /* Timer RC Offset */ + +#define ASPEED_TIMER_CLKRATE (ASPEED_EXTCLK) +#define ASPEED_EXTCLK (1*1000*1000) /* 1M */ + +/* + * Ticks + */ +//#define TICKS_PER_uSEC 40 // IP Cam +//#define TICKS_PER_uSEC 24 // FPGA +#define TICKS_PER_uSEC 1 /* ASPEED_EXTCLK / 10 ^ 6 */ + +#define mSEC_1 1000 +#define mSEC_5 (mSEC_1 * 5) +#define mSEC_10 (mSEC_1 * 10) +#define mSEC_25 (mSEC_1 * 25) +#define SEC_1 (mSEC_1 * 1000) + +/* + * Timer Control + */ +#define TIMER0_ENABLE 0x0001 +#define TIMER1_ENABLE 0x0010 +#define TIMER2_ENABLE 0x0100 + +#define TIMER0_RefExt 0x0002 +#define TIMER1_RefExt 0x0020 +#define TIMER2_RefExt 0x0200 + +/* + * What does it look like? + */ +typedef struct TimerStruct { + unsigned long TimerValue; + unsigned long TimerLoad; + unsigned long TimerMatch1; + unsigned long TimerMatch2; +} TimerStruct_t; + diff --git a/arch/arm/mach-aspeed/include/mach/timex.h b/arch/arm/mach-aspeed/include/mach/timex.h new file mode 100644 index 000000000000..e907a3052ba0 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/timex.h @@ -0,0 +1,21 @@ +/* + * timex.h + * + * Integrator architecture timex specifications + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#define CLOCK_TICK_RATE (50000000 / 16) diff --git a/arch/arm/mach-aspeed/include/mach/uncompress.h b/arch/arm/mach-aspeed/include/mach/uncompress.h new file mode 100644 index 000000000000..896b8542a530 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/uncompress.h @@ -0,0 +1,38 @@ +/* + * uncompress.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_UNCOMPRESS_H +#define __ASM_ARCH_UNCOMPRESS_H + +#include <mach/platform.h> +#include <mach/aspeed_serial.h> + +#define UART_PUT_CHAR (*(volatile unsigned char *)(AST_UART0_BASE + UART_THR)) +#define UART_GET_LSR (*(volatile unsigned char *)(AST_UART0_BASE + UART_LSR)) + +static void putc(int c) +{ + + /* wait for space in the UART's transmitter */ + while (!(UART_GET_LSR & UART_LSR_THRE)) + barrier(); + + /* send the character out. */ + UART_PUT_CHAR = c; +} + +static inline void flush(void) +{ + while (UART_GET_LSR & (1 << 3)) + barrier(); +} + +#define arch_decomp_setup() +#define arch_decomp_wdog() + +#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-aspeed/include/mach/vmalloc.h b/arch/arm/mach-aspeed/include/mach/vmalloc.h new file mode 100644 index 000000000000..3706cf1f168e --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/vmalloc.h @@ -0,0 +1,29 @@ +/* + * vmalloc.h + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * Just any arbitrary offset to the start of the vmalloc VM area: the + * current 8MB value just means that there will be a 8MB "hole" after the + * physical memory until the kernel virtual memory starts. That means that + * any out-of-bounds memory accesses will hopefully be caught. + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + */ +#if 0 +#define VMALLOC_OFFSET (8*1024*1024) +#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) +#define VMALLOC_VMADDR(x) ((unsigned long)(x)) +#define VMALLOC_END (PAGE_OFFSET + 0x10000000) +#else +#define VMALLOC_END 0xf8000000UL +#endif
\ No newline at end of file diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index ab5f7a21350b..d7b499ac4410 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -180,7 +180,7 @@ config CPU_ARM925T # ARM926T config CPU_ARM926T bool "Support ARM926T processor" - depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || \ + depends on ARCH_ASPEED || ARCH_INTEGRATOR || ARCH_VERSATILE_PB || \ MACH_VERSATILE_AB || ARCH_OMAP730 || \ ARCH_OMAP16XX || MACH_REALVIEW_EB || \ ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \ @@ -188,7 +188,7 @@ config CPU_ARM926T ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \ ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \ ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MX2 - default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || \ + default y if ARCH_ASPEED || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || \ ARCH_OMAP730 || ARCH_OMAP16XX || \ ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \ ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \ diff --git a/arch/arm/plat-aspeed/Makefile b/arch/arm/plat-aspeed/Makefile new file mode 100644 index 000000000000..faba830357bd --- /dev/null +++ b/arch/arm/plat-aspeed/Makefile @@ -0,0 +1,35 @@ +# +# Makefile for the linux kernel. +# + +obj-y += irq.o timer.o devs.o ast-scu.o ast-sdmc.o + +obj-$(CONFIG_ARCH_AST1070) += ast1070_irq.o ast1070-scu.o ast1070-uart-dma.o dev-ci2c.o dev-cuart.o dev-clpc.o + +obj-$(CONFIG_AST_I2C_SLAVE_MODE) += i2c-slave-eeprom.o + +obj-$(CONFIG_AST2400_BMC) += ast2400-irq.o ast2400-scu.o dev-ast2400-uart.o #dev-ast2400-i2c.o + +#obj-n := dummy.o +#platform +obj-y += dev-uart.o dev-vuart.o dev-wdt.o dev-rtc.o dev-gpio.o dev-sgpio.o + +#Storage +obj-y += dev-nor.o dev-nand.o dev-sdhci.o + +#bus +obj-y += dev-i2c.o dev-spi.o dev-ehci.o dev-uhci.o dev-lpc.o dev-peci.o dev-kcs.o dev-mbx.o dev-snoop.o + +#dev +#obj-y += dev-udc11.o +#net +obj-y += dev-eth.o + +#hwmon +obj-y += dev-pwm-fan.o dev-adc.o + +#video +obj-y += dev-fb.o dev-video.o +#obj-m := +#obj-n := +#obj- := diff --git a/arch/arm/plat-aspeed/ast-scu.c b/arch/arm/plat-aspeed/ast-scu.c new file mode 100644 index 000000000000..1f1dde27608f --- /dev/null +++ b/arch/arm/plat-aspeed/ast-scu.c @@ -0,0 +1,1202 @@ +/******************************************************************************** +* File Name : arch/arm/plat-aspeed/ast-scu.c +* Author : Ryan Chen +* Description : AST SCU +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +CLK24M + | + |--> H-PLL -->HCLK + | + |--> M-PLL -xx->MCLK + | + |--> V-PLL1 -xx->DCLK + | + |--> V-PLL2 -xx->D2CLK + | + |--> USB2PHY -->UTMICLK + + +* History : +* 1. 2012/08/15 Ryan Chen Create +* +********************************************************************************/ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/delay.h> + +#include <mach/platform.h> +#include <asm/io.h> + +#include <mach/hardware.h> + +#include <plat/ast-scu.h> +#include <plat/regs-scu.h> + +//#define ASPEED_SCU_LOCK +//#define ASPEED_SCU_DEBUG + +#ifdef ASPEED_SCU_DEBUG +#define SCUDBUG(fmt, args...) printk("%s() " fmt, __FUNCTION__, ## args) +#else +#define SCUDBUG(fmt, args...) +#endif + +#define SCUMSG(fmt, args...) printk(fmt, ## args) + +static u32 ast_scu_base = IO_ADDRESS(AST_SCU_BASE); + +static inline u32 +ast_scu_read(u32 reg) +{ + u32 val; + + val = readl(ast_scu_base + reg); + + SCUDBUG("ast_scu_read : reg = 0x%08x, val = 0x%08x\n", reg, val); + + return val; +} + +static inline void +ast_scu_write(u32 val, u32 reg) +{ + SCUDBUG("ast_scu_write : reg = 0x%08x, val = 0x%08x\n", reg, val); +#ifdef CONFIG_AST_SCU_LOCK + //unlock + writel(SCU_PROTECT_UNLOCK, ast_scu_base); + writel(val, ast_scu_base + reg); + //lock + writel(0xaa,ast_scu_base); +#else + writel(val, ast_scu_base + reg); +#endif +} + +//SoC mapping Table +struct soc_id { + const char * name; + u32 rev_id; +}; + +static struct soc_id soc_map_table[] = { + [0] = { + .name = "AST1100/AST2050-A0", + .rev_id = 0x00000200, + }, + [1] = { + .name = "AST1100/AST2050-A1", + .rev_id = 0x00000201, + }, + [2] = { + .name = "AST1100/AST2050-A2,3/AST2150-A0,1", + .rev_id = 0x00000202, + }, + [3] = { + .name = "AST1510/AST2100-A0", + .rev_id = 0x00000300, + }, + [4] = { + .name = "AST1510/AST2100-A1", + .rev_id = 0x00000301, + }, + [5] = { + .name = "AST1510/AST2100-A2,3", + .rev_id = 0x00000302, + }, + [6] = { + .name = "AST2200-A0,1", + .rev_id = 0x00000102, + }, + [7] = { + .name = "AST2300-A0", + .rev_id = 0x01000003, + }, + [8] = { + .name = "AST2300-A1", + .rev_id = 0x01010303, + }, + [9] = { + .name = "AST1300-A1", + .rev_id = 0x01010003, + }, + [10] = { + .name = "AST1050-A1", + .rev_id = 0x01010203, + }, + [11] = { + .name = "AST2400-A0", + .rev_id = 0x02000303, + }, + [12] = { + .name = "AST2400-A1", + .rev_id = 0x02010303, + }, + [13] = { + .name = "AST1010-A0", + .rev_id = 0x03000003, + }, + [14] = { + .name = "AST1010-A1", + .rev_id = 0x03010003, + }, + [15] = { + .name = "AST1520-A0", + .rev_id = 0x03000003, + }, + [16] = { + .name = "AST3200-A0", + .rev_id = 0x03000003, + }, +}; + +//***********************************Initial control*********************************** +extern void +ast_scu_reset_video(void) +{ + ast_scu_write(ast_scu_read(AST_SCU_RESET) | SCU_RESET_VIDEO, AST_SCU_RESET); + udelay(100); + ast_scu_write(ast_scu_read(AST_SCU_RESET) & ~SCU_RESET_VIDEO, AST_SCU_RESET); +} + +EXPORT_SYMBOL(ast_scu_reset_video); + +extern void +ast_scu_init_video(u8 dynamic_en) +{ + //Video Engine Clock Enable and Reset + // Enable Clock & ECLK = inverse of (M-PLL / 2) + if(dynamic_en) + ast_scu_write((ast_scu_read(AST_SCU_CLK_SEL) & ~SCU_CLK_VIDEO_SLOW_MASK) | SCU_CLK_VIDEO_SLOW_EN | SCU_CLK_VIDEO_SLOW_SET(0), AST_SCU_CLK_SEL); + else + ast_scu_write((ast_scu_read(AST_SCU_CLK_SEL) & ~SCU_ECLK_SOURCE_MASK) | SCU_ECLK_SOURCE(2), AST_SCU_CLK_SEL); + + // Enable CLK + ast_scu_write(ast_scu_read(AST_SCU_CLK_STOP) & ~(SCU_ECLK_STOP_EN | SCU_VCLK_STOP_EN), AST_SCU_CLK_STOP); + mdelay(10); + ast_scu_write(ast_scu_read(AST_SCU_RESET) | SCU_RESET_VIDEO, AST_SCU_RESET); + udelay(100); + ast_scu_write(ast_scu_read(AST_SCU_RESET) & ~SCU_RESET_VIDEO, AST_SCU_RESET); +} + +EXPORT_SYMBOL(ast_scu_init_video); + +extern void +ast_scu_init_eth(u8 num) +{ + //AST2300 max clk to 125Mhz, AST2400 max clk to 198Mhz + if(ast_scu_read(AST_SCU_HW_STRAP1) && (SCU_HW_STRAP_MAC1_RGMII | SCU_HW_STRAP_MAC0_RGMII)) //RGMII --> H-PLL/6 + ast_scu_write((ast_scu_read(AST_SCU_CLK_SEL) & ~SCU_CLK_MAC_MASK) | SCU_CLK_MAC_DIV(2), AST_SCU_CLK_SEL); + else //RMII --> H-PLL/10 + ast_scu_write((ast_scu_read(AST_SCU_CLK_SEL) & ~SCU_CLK_MAC_MASK) | SCU_CLK_MAC_DIV(4), AST_SCU_CLK_SEL); + + //Set MAC delay Timing + ast_scu_write(0x2255, AST_SCU_MAC_CLK); + + switch(num) { + case 0: + ast_scu_write(ast_scu_read(AST_SCU_RESET) | SCU_RESET_MAC0, + AST_SCU_RESET); + udelay(100); + ast_scu_write(ast_scu_read(AST_SCU_CLK_STOP) & ~SCU_MAC0CLK_STOP_EN, + AST_SCU_CLK_STOP); + udelay(1000); + ast_scu_write(ast_scu_read(AST_SCU_RESET) & ~SCU_RESET_MAC0, + AST_SCU_RESET); + + break; + case 1: + ast_scu_write(ast_scu_read(AST_SCU_RESET) | SCU_RESET_MAC1, + AST_SCU_RESET); + udelay(100); + ast_scu_write(ast_scu_read(AST_SCU_CLK_STOP) & ~SCU_MAC1CLK_STOP_EN, + AST_SCU_CLK_STOP); + udelay(1000); + ast_scu_write(ast_scu_read(AST_SCU_RESET) & ~SCU_RESET_MAC1, + AST_SCU_RESET); + break; + + } +} + + +extern void +ast_scu_init_usb20(void) +{ + /* EHCI controller engine init. Process similar to VHub. */ + /* Following reset sequence can resolve "vhub dead on first power on" issue on V4 board. */ + //reset USB20 + ast_scu_write(ast_scu_read(AST_SCU_RESET) | SCU_RESET_USB20, AST_SCU_RESET); + + //enable USB20 clock + ast_scu_write(ast_scu_read(AST_SCU_CLK_STOP) | SCU_USB20_CLK_EN, AST_SCU_CLK_STOP); + mdelay(10); + + ast_scu_write(ast_scu_read(AST_SCU_RESET) & ~SCU_RESET_USB20, AST_SCU_RESET); + + udelay(500); + +// printk("%x \n",ast_scu_read(AST_SCU_RESET)); + + +} + +EXPORT_SYMBOL(ast_scu_init_usb20); + +extern void +ast_scu_init_uhci(void) +{ + //USB1.1 Host's Clock Enable and Reset + ast_scu_write(ast_scu_read(AST_SCU_CLK_STOP) & ~SCU_USB11CLK_STOP_EN, AST_SCU_CLK_STOP); + mdelay(10); + + ast_scu_write(ast_scu_read(AST_SCU_RESET) & ~SCU_RESET_USB11, AST_SCU_RESET); +} + +EXPORT_SYMBOL(ast_scu_init_uhci); + +extern void +ast_scu_init_udc11(void) +{ + //USB1.1 device Clock Enable and Reset + ast_scu_write(ast_scu_read(AST_SCU_CLK_STOP) & ~SCU_UCLK_STOP_EN, AST_SCU_CLK_STOP); + mdelay(10); + + ast_scu_write(ast_scu_read(AST_SCU_RESET) & ~SCU_RESET_USB11_HID, AST_SCU_RESET); +} + +EXPORT_SYMBOL(ast_scu_init_udc11); + +/// +extern void +ast_scu_init_sdhci(void) +{ + //SDHCI Host's Clock Enable and Reset + ast_scu_write(ast_scu_read(AST_SCU_RESET) | SCU_RESET_SD, AST_SCU_RESET); + + ast_scu_write(ast_scu_read(AST_SCU_CLK_STOP) & ~SCU_SDCLK_STOP_EN, AST_SCU_CLK_STOP); + mdelay(10); + + ast_scu_write(ast_scu_read(AST_SCU_CLK_SEL) | SCU_CLK_SD_EN, AST_SCU_CLK_SEL); + mdelay(10); + + // SDCLK = H-PLL / 4 + ast_scu_write((ast_scu_read(AST_SCU_CLK_SEL) & ~SCU_CLK_SD_MASK) | SCU_CLK_SD_DIV(1), + AST_SCU_CLK_SEL); + mdelay(10); + + ast_scu_write(ast_scu_read(AST_SCU_RESET) & ~SCU_RESET_SD, AST_SCU_RESET); +} + +EXPORT_SYMBOL(ast_scu_init_sdhci); + +extern void +ast_scu_init_i2c(void) +{ + ast_scu_write(ast_scu_read(AST_SCU_RESET) & ~SCU_RESET_I2C, AST_SCU_RESET); +} + +EXPORT_SYMBOL(ast_scu_init_i2c); + +extern void +ast_scu_init_pwm_tacho(void) +{ + ast_scu_write(ast_scu_read(AST_SCU_RESET) | SCU_RESET_PWM, AST_SCU_RESET); + ast_scu_write(ast_scu_read(AST_SCU_RESET) & ~SCU_RESET_PWM, AST_SCU_RESET); +} + +EXPORT_SYMBOL(ast_scu_init_pwm_tacho); + +extern void +ast_scu_init_adc(void) +{ + ast_scu_write(ast_scu_read(AST_SCU_RESET) | SCU_RESET_ADC, AST_SCU_RESET); + ast_scu_write(ast_scu_read(AST_SCU_RESET) & ~SCU_RESET_ADC, AST_SCU_RESET); +} + +EXPORT_SYMBOL(ast_scu_init_adc); + +extern void +ast_scu_init_peci(void) +{ + ast_scu_write(ast_scu_read(AST_SCU_RESET) | SCU_RESET_PECI, AST_SCU_RESET); + udelay(3); + ast_scu_write(ast_scu_read(AST_SCU_RESET) & ~SCU_RESET_PECI, AST_SCU_RESET); +} + +EXPORT_SYMBOL(ast_scu_init_peci); + +extern void +ast_scu_init_jtag(void) +{ + ast_scu_write(ast_scu_read(AST_SCU_RESET) | SCU_RESET_JTAG, AST_SCU_RESET); + udelay(3); + ast_scu_write(ast_scu_read(AST_SCU_RESET) & ~SCU_RESET_JTAG, AST_SCU_RESET); +} + +EXPORT_SYMBOL(ast_scu_init_jtag); + +extern void +ast_scu_init_lpc(void) +{ + //Note .. It have been enable in U-boot..... +// ast_scu_write(ast_scu_read(AST_SCU_RESET) | SCU_RESET_LPC, AST_SCU_RESET); + + //enable LPC clock LHCLK = H-PLL/8 + ast_scu_write(ast_scu_read(AST_SCU_CLK_STOP) | + SCU_SET_LHCLK_DIV(3) | + SCU_LHCLK_SOURCE_EN, + AST_SCU_CLK_STOP); + +} + +EXPORT_SYMBOL(ast_scu_init_lpc); + +//////1 : lpc plus modes +extern u8 +ast_scu_get_lpc_plus_enable(void) +{ + if(ast_scu_read(AST_SCU_FUN_PIN_CTRL5) & SCU_FUN_PIN_LPC_PLUS) + return 1; + else + return 0; +} + +EXPORT_SYMBOL(ast_scu_get_lpc_plus_enable); + +extern void +ast_scu_init_crt(void) +{ + //enable D2 pll , //enable DVO (bit18) is VGA , enable DAC (bit16) is CRT +#if defined(CONFIG_AST_DAC) || defined(CONFIG_AST_DVO) + ast_scu_write((ast_scu_read(AST_SCU_MISC1_CTRL) & ~(SCU_MISC_D2_PLL_DIS | SCU_MISC_DAC_MASK)) + | SCU_MISC_DAC_SOURCE_CRT | SCU_MISC_DVO_SOURCE_CRT | SCU_MISC_2D_CRT_EN , AST_SCU_MISC1_CTRL); +#elif defined(CONFIG_AST_DVO) + ast_scu_write((ast_scu_read(AST_SCU_MISC1_CTRL) & ~(SCU_MISC_D2_PLL_DIS)) | + SCU_MISC_DVO_SOURCE_CRT| SCU_MISC_2D_CRT_EN, AST_SCU_MISC1_CTRL); +#else //default(CONFIG_AST_DAC) + ast_scu_write((ast_scu_read(AST_SCU_MISC1_CTRL) & ~(SCU_MISC_D2_PLL_DIS | SCU_MISC_DAC_MASK)) + | SCU_MISC_DAC_SOURCE_CRT | SCU_MISC_2D_CRT_EN, AST_SCU_MISC1_CTRL); +#endif + /* Set Delay 5 Compensation TODO ...*/ + ast_scu_write((ast_scu_read(AST_SCU_CLK_SEL) & ~SCU_CLK_VIDEO_DELAY_MASK) | + SCU_CLK_VIDEO_DELAY(5), AST_SCU_CLK_SEL); + + /* Reset CRT */ + ast_scu_write(ast_scu_read(AST_SCU_RESET) | SCU_RESET_CRT, AST_SCU_RESET); + + //enable D2 CLK + ast_scu_write(ast_scu_read(AST_SCU_CLK_STOP) & ~SCU_D2CLK_STOP_EN , AST_SCU_CLK_STOP); + + udelay(10); + ast_scu_write(ast_scu_read(AST_SCU_RESET) & ~SCU_RESET_CRT, AST_SCU_RESET); + +} + +EXPORT_SYMBOL(ast_scu_init_crt); +//***********************************CLK control*********************************** +extern void +ast_scu_clk_stop(u32 clk_name,u8 stop_enable) +{ + switch(clk_name){ + default: + SCUMSG("ERRO clk_name :%d \n",clk_name); + break; + } +} + +EXPORT_SYMBOL(ast_scu_clk_stop); + + +//***********************************CLK Information*********************************** +extern u32 +ast_get_clk_source(void) +{ + if(ast_scu_read(AST_SCU_HW_STRAP1) & CLK_25M_IN) + return AST_PLL_25MHZ; + else + return AST_PLL_24MHZ; +} + +EXPORT_SYMBOL(ast_get_clk_source); + + +extern u32 +ast_get_h_pll_clk(void) +{ + u32 speed,clk=0; + u32 h_pll_set = ast_scu_read(AST_SCU_H_PLL); + + if(h_pll_set & SCU_H_PLL_OFF) + return 0; + + if(h_pll_set & SCU_H_PLL_PARAMETER) { + // Programming + clk = ast_get_clk_source(); + if(h_pll_set & SCU_H_PLL_BYPASS_EN) { + return clk; + } else { + //OD == SCU24[4] + //OD = SCU_H_PLL_GET_DIV(h_pll_set); + //Numerator == SCU24[10:5] + //num = SCU_H_PLL_GET_NUM(h_pll_set); + //Denumerator == SCU24[3:0] + //denum = SCU_H_PLL_GET_DENUM(h_pll_set); + + //hpll = 24MHz * (2-OD) * ((Numerator+2)/(Denumerator+1)) + clk = ((clk * (2-SCU_H_PLL_GET_DIV(h_pll_set)) * (SCU_H_PLL_GET_NUM(h_pll_set)+2))/(SCU_H_PLL_GET_DENUM(h_pll_set)+1)); + } + } else { + // HW Trap + speed = SCU_HW_STRAP_GET_H_PLL_CLK(ast_scu_read(AST_SCU_HW_STRAP1)); + switch (speed) { + case 0: + clk = 384000000; + break; + case 1: + clk = 360000000; + break; + case 2: + clk = 336000000; + break; + case 3: + clk = 408000000; + break; + default: + BUG(); + break; + } + } + SCUDBUG("h_pll = %d\n",clk); + return clk; +} + +EXPORT_SYMBOL(ast_get_h_pll_clk); + +extern u32 +ast_get_m_pll_clk(void) +{ + u32 clk=0; + u32 m_pll_set = ast_scu_read(AST_SCU_M_PLL); + + if(m_pll_set & SCU_M_PLL_OFF) + return 0; + + // Programming + clk = ast_get_clk_source(); + if(m_pll_set & SCU_M_PLL_BYPASS_EN) { + return clk; + } else { + //OD == SCU24[4] + //OD = SCU_M_PLL_GET_DIV(h_pll_set); + //Numerator == SCU24[10:5] + //num = SCU_M_PLL_GET_NUM(h_pll_set); + //Denumerator == SCU24[3:0] + //denum = SCU_M_PLL_GET_DENUM(h_pll_set); + + //hpll = 24MHz * (2-OD) * ((Numerator+2)/(Denumerator+1)) + clk = (clk * (2-SCU_M_PLL_GET_DIV(m_pll_set)) * ((SCU_M_PLL_GET_NUM(m_pll_set)+2)/(SCU_M_PLL_GET_DENUM(m_pll_set)+1))); + } + SCUDBUG("m_pll = %d\n",clk); + return clk; +} + +EXPORT_SYMBOL(ast_get_m_pll_clk); + +extern u32 +ast_get_ahbclk(void) +{ + unsigned int div, hpll; + + hpll = ast_get_h_pll_clk(); + div = SCU_HW_STRAP_GET_CPU_AHB_RATIO(ast_scu_read(AST_SCU_HW_STRAP1)); + switch(div) { + case 0: + div = 1; + break; + case 1: + div = 2; + break; + case 2: + div = 3; + break; + case 3: + div = 4; + break; + + } + + SCUDBUG("HPLL=%d, Div=%d, AHB CLK=%d\n", hpll, div, hpll/div); + return (hpll/div); + +} +EXPORT_SYMBOL(ast_get_ahbclk); + +extern u32 +ast_get_pclk(void) +{ + unsigned int div, hpll; + + hpll = ast_get_h_pll_clk(); + div = SCU_GET_PCLK_DIV(ast_scu_read(AST_SCU_CLK_SEL)); + div = (div+1) << 1; + + SCUDBUG("HPLL=%d, Div=%d, PCLK=%d\n", hpll, div, hpll/div); + return (hpll/div); + +} +EXPORT_SYMBOL(ast_get_pclk); + +extern u32 +ast_get_lhclk(void) +{ + unsigned int div, hpll; + u32 clk_sel = ast_scu_read(AST_SCU_CLK_SEL); +//FPGA AST1070 is default 100/2 Mhz input +// return 50000000; + hpll = ast_get_h_pll_clk(); + if(SCU_LHCLK_SOURCE_EN & clk_sel) { + div = SCU_GET_LHCLK_DIV(clk_sel); + switch(div) { + case 0: + div = 2; + break; + case 1: + div = 4; + break; + case 2: + div = 6; + break; + case 3: + div = 8; + break; + case 4: + div = 10; + break; + case 5: + div = 12; + break; + case 6: + div = 14; + break; + case 7: + div = 16; + break; + } + + SCUDBUG("HPLL=%d, Div=%d, LHCLK = %d\n", hpll, div, hpll/div); + return (hpll/div); + } else { + SCUMSG("LPC CLK not enable \n"); + return 0; + } + +} + +EXPORT_SYMBOL(ast_get_lhclk); + +extern u32 +ast_get_d2_pll_clk(void) +{ + u32 clk=0; + u32 d2_pll_set = ast_scu_read(AST_SCU_D2_PLL); + u32 OD,NUM,DENUM,PD,PD2; + + if(d2_pll_set & SCU_D2_PLL_OFF) + return 0; + + // Programming + clk = ast_get_clk_source(); + if(d2_pll_set & SCU_D2_PLL_BYPASS_EN) { + return clk; + } else { + NUM = SCU_D2_PLL_GET_NUM(d2_pll_set); + DENUM = SCU_D2_PLL_GET_DENUM(d2_pll_set); + OD = SCU_D2_PLL_GET_OD(d2_pll_set); + OD = (1 << (OD - 1)); + PD = SCU_D2_PLL_GET_PD(d2_pll_set); + switch(PD) { + case 0: + PD = 1; + break; + case 1: + PD = 2; + break; + case 2: + PD = 2; + break; + case 3: + PD = 4; + break; + } + PD2 = SCU_D2_PLL_GET_PD2(d2_pll_set); + PD2 = PD2+1; +// printk("clk %d ,num %d ,denum %d ,od %d ,pd %d ,pd2 %d \n",clk, NUM , DENUM, OD, PD, PD2); + //hpll = 24MHz * (Numerator * 2) / (Denumerator * OD * PD * PD2) + clk = (clk * NUM * 2) / (DENUM* OD * PD * PD2); + } + + SCUDBUG("d2_pll = %d\n",clk); + return clk; +} + +EXPORT_SYMBOL(ast_get_d2_pll_clk); + +//Because value 0 is not allowed in SDIO12C D[15:8]: Host Control Settings #1 Register, we have to increase the maximum +//host's clock in case that system will not ask host to set 1 in the sdhci_set_clock() function +/* +SCU7C: Silicon Revision ID Register +D[31:24]: Chip ID +0: AST2050/AST2100/AST2150/AST2200/AST3000 +1: AST2300 + +D[23:16] Silicon revision ID for AST2300 generation and later +0: A0 +1: A1 +2: A2 +. +. +. +FPGA revision starts from 0x80 + + +D[11:8] Bounding option + +D[7:0] Silicon revision ID for AST2050/AST2100 generation (for software compatible) +0: A0 +1: A1 +2: A2 +3: A3 +. +. +FPGA revision starts from 0x08, 8~10 means A0, 11+ means A1, AST2300 should be assigned to 3 +*/ + +extern u32 +ast_get_sd_clock_src(void) +{ + u32 clk=0, sd_div; + +#if defined(FPGA) + clk = 100000000; +#else + clk = ast_get_h_pll_clk(); + //get div + sd_div = SCU_CLK_SD_GET_DIV(ast_scu_read(AST_SCU_CLK_SEL)); + SCUDBUG("div %d, sdclk =%d \n",((sd_div + 1) * 2),clk/((sd_div + 1) * 2)); + clk /= ((sd_div + 1) * 2); + +#endif + return clk; +} + +EXPORT_SYMBOL(ast_get_sd_clock_src); + +extern void +ast_scu_show_system_info (void) +{ + u32 h_pll, div; + + h_pll = ast_get_h_pll_clk(); + + div = SCU_HW_STRAP_GET_CPU_AHB_RATIO(ast_scu_read(AST_SCU_HW_STRAP1)); + switch(div) { + case 0: + div = 1; + break; + case 1: + div = 2; + break; + case 2: + div = 3; + break; + case 3: + div = 4; + break; + + } + + SCUMSG("CPU = %d MHz ,AHB = %d MHz (%d:1) \n", h_pll/1000000, h_pll/div/1000000,div); + + return ; +} + +EXPORT_SYMBOL(ast_scu_show_system_info); + +//*********************************** Multi-function pin control *********************************** +extern void +ast_scu_multi_func_uart(u8 uart) +{ + switch(uart) { + case 1: + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) | + SCU_FUN_PIN_UART1_RXD | + SCU_FUN_PIN_UART1_TXD | + SCU_FUN_PIN_UART1_NRTS | + SCU_FUN_PIN_UART1_NDTR | + SCU_FUN_PIN_UART1_NRI | + SCU_FUN_PIN_UART1_NDSR | + SCU_FUN_PIN_UART1_NDCD | + SCU_FUN_PIN_UART1_NCTS, + AST_SCU_FUN_PIN_CTRL1); + break; + case 2: + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) | + SCU_FUN_PIN_UART2_RXD | + SCU_FUN_PIN_UART2_TXD | + SCU_FUN_PIN_UART2_NRTS | + SCU_FUN_PIN_UART2_NDTR | + SCU_FUN_PIN_UART2_NRI | + SCU_FUN_PIN_UART2_NDSR | + SCU_FUN_PIN_UART2_NDCD | + SCU_FUN_PIN_UART2_NCTS, + AST_SCU_FUN_PIN_CTRL1); + break; + case 3: + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) | + SCU_FUN_PIN_UART3_RXD | + SCU_FUN_PIN_UART3_TXD | + SCU_FUN_PIN_UART3_NRTS | + SCU_FUN_PIN_UART3_NDTR | + SCU_FUN_PIN_UART3_NRI | + SCU_FUN_PIN_UART3_NDSR | + SCU_FUN_PIN_UART3_NDCD | + SCU_FUN_PIN_UART3_NCTS, + AST_SCU_FUN_PIN_CTRL1); + break; + case 4: + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) | + SCU_FUN_PIN_UART4_RXD | + SCU_FUN_PIN_UART4_TXD | + SCU_FUN_PIN_UART4_NRTS | + SCU_FUN_PIN_UART4_NDTR | + SCU_FUN_PIN_UART4_NRI | + SCU_FUN_PIN_UART4_NDSR | + SCU_FUN_PIN_UART4_NDCD | + SCU_FUN_PIN_UART4_NCTS, + AST_SCU_FUN_PIN_CTRL1); + break; + } + + +} + +extern void +ast_scu_multi_func_video() +{ +#if defined(CONFIG_ARCH_2100) || defined(CONFIG_ARCH_2200) + ast_scu_write(ast_scu_read(AST_SCU_MULTI_FUNC_2) | + MULTI_FUNC_VIDEO_RGB18 | + MULTI_FUNC_VIDEO_SINGLE_EDGE, + AST_SCU_MULTI_FUNC_2); +#elif defined(CONFIG_ARCH_1100) || defined(CONFIG_ARCH_2050) + ast_scu_write(ast_scu_read(AST_SCU_MULTI_FUNC_2) | + MULTI_FUNC_VIDEO_RGB18 | + MULTI_FUNC_VIDEO_SINGLE_EDGE, + AST_SCU_MULTI_FUNC_2); +#else + +#endif +} + +extern void +ast_scu_multi_func_eth(u8 num) +{ + switch(num) { + case 0: + if(ast_scu_read(AST_SCU_HW_STRAP1) && SCU_HW_STRAP_MAC0_RGMII) { + SCUMSG("MAC0 : RGMII \n"); + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) | + SCU_FUN_PIN_MAC0_PHY_LINK, + AST_SCU_FUN_PIN_CTRL1); + } else { + SCUMSG("MAC0 : RMII/NCSI \n"); + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) & + ~SCU_FUN_PIN_MAC0_PHY_LINK, + AST_SCU_FUN_PIN_CTRL1); + } + + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL3) | + SCU_FUN_PIN_MAC0_MDIO | + SCU_FUN_PIN_MAC0_MDC, + AST_SCU_FUN_PIN_CTRL3); + + break; + case 1: + if(ast_scu_read(AST_SCU_HW_STRAP1) && SCU_HW_STRAP_MAC1_RGMII) { + SCUMSG("MAC1 : RGMII \n"); + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) | + SCU_FUN_PIN_MAC1_PHY_LINK, + AST_SCU_FUN_PIN_CTRL1); + } else { + SCUMSG("MAC1 : RMII/NCSI \n"); + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL1) & + ~SCU_FUN_PIN_MAC1_PHY_LINK, + AST_SCU_FUN_PIN_CTRL1); + } + + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL5) | + SCU_FUC_PIN_MAC1_MDIO, + AST_SCU_FUN_PIN_CTRL5); + + break; + } +} + +extern void +ast_scu_multi_func_nand(void) +{ + //enable NAND flash multipin FLBUSY and FLWP + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL2) | + SCU_FUN_PIN_NAND_FLBUSY | SCU_FUN_PIN_NAND_FLWP, + AST_SCU_FUN_PIN_CTRL2); + +} + +extern void +ast_scu_multi_func_nor(void) +{ + //Address + //ROMA2~17 + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL8) | + SCU_FUN_PIN_ROMA2 | SCU_FUN_PIN_ROMA3 | + SCU_FUN_PIN_ROMA4 | SCU_FUN_PIN_ROMA5 | + SCU_FUN_PIN_ROMA6 | SCU_FUN_PIN_ROMA7 | + SCU_FUN_PIN_ROMA8 | SCU_FUN_PIN_ROMA9 | + SCU_FUN_PIN_ROMA10 | SCU_FUN_PIN_ROMA11 | + SCU_FUN_PIN_ROMA12 | SCU_FUN_PIN_ROMA13 | + SCU_FUN_PIN_ROMA14 | SCU_FUN_PIN_ROMA15 | + SCU_FUN_PIN_ROMA16 | SCU_FUN_PIN_ROMA17, + AST_SCU_FUN_PIN_CTRL8); + + //ROMA18~21 + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL9) | + SCU_FUN_PIN_ROMA18 | SCU_FUN_PIN_ROMA19 | + SCU_FUN_PIN_ROMA20 | SCU_FUN_PIN_ROMA21, + AST_SCU_FUN_PIN_CTRL9); + + //ROMA22,23 + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL4) | SCU_FUN_PIN_ROMA22 | SCU_FUN_PIN_ROMA23, + AST_SCU_FUN_PIN_CTRL4); + + //ROMA24,25 + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL3) | SCU_FUN_PIN_ROMA24 | SCU_FUN_PIN_ROMA25, + AST_SCU_FUN_PIN_CTRL3); + + //SCU94 [1] = 0 + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL6) & SCU_VIDEO_OUT_MASK, + AST_SCU_FUN_PIN_CTRL6); + + + //data + //ROMD 4~7 //ROMWE#, OE# + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL4) | + SCU_FUN_PIN_ROMOE | SCU_FUN_PIN_ROMWE | + SCU_FUN_PIN_ROMD4 | SCU_FUN_PIN_ROMD5 | + SCU_FUN_PIN_ROMD6 | SCU_FUN_PIN_ROMD7, + AST_SCU_FUN_PIN_CTRL4); + + //ROMD 8~15 + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL5) | + SCU_FUC_PIN_ROM_16BIT, + AST_SCU_FUN_PIN_CTRL5); + +} + +extern void +ast_scu_multi_func_romcs(u8 num) +{ + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL3) | + SCU_FUN_PIN_ROMCS(num), + AST_SCU_FUN_PIN_CTRL3); +} + +extern void +ast_scu_multi_func_i2c(void) +{ + //TODO check ... //In AST2400 Due to share pin with SD , please not enable I2C 10 ~14 + // AST 2400 have 14 , AST 2300 9 ... +#ifdef CONFIG_MMC_AST + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL5) | + SCU_FUC_PIN_I2C3 | + SCU_FUC_PIN_I2C4 | + SCU_FUC_PIN_I2C5 | + SCU_FUC_PIN_I2C6 | + SCU_FUC_PIN_I2C7 | + SCU_FUC_PIN_I2C8 | + SCU_FUC_PIN_I2C9, + AST_SCU_FUN_PIN_CTRL5); +#else + ast_scu_write((ast_scu_read(AST_SCU_FUN_PIN_CTRL5) | + SCU_FUC_PIN_I2C3 | + SCU_FUC_PIN_I2C4 | + SCU_FUC_PIN_I2C5 | + SCU_FUC_PIN_I2C6 | + SCU_FUC_PIN_I2C7 | + SCU_FUC_PIN_I2C8 | + SCU_FUC_PIN_I2C9 | + SCU_FUC_PIN_I2C10 | + SCU_FUC_PIN_I2C11 | + SCU_FUC_PIN_I2C12 | + SCU_FUC_PIN_I2C13 | + SCU_FUC_PIN_I2C14) & + ~(SCU_FUC_PIN_SD1 | SCU_FUC_PIN_SD2), + AST_SCU_FUN_PIN_CTRL5); +#endif +} + +EXPORT_SYMBOL(ast_scu_multi_func_i2c); + +extern void +ast_scu_multi_func_pwm_tacho(void) +{ + //TODO check + u32 sts = ast_scu_read(AST_SCU_FUN_PIN_CTRL3) &~0xcfffff; + ast_scu_write(sts | 0xc000ff, AST_SCU_FUN_PIN_CTRL3); +} + +EXPORT_SYMBOL(ast_scu_multi_func_pwm_tacho); + +//0 : hub mode , 1: usb host mode +extern void +ast_scu_multi_func_usb20_host_hub(u8 mode) +{ + if(mode) + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL5) | SCU_FUC_PIN_USB20_HOST, + AST_SCU_FUN_PIN_CTRL5); + else + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL5) & ~SCU_FUC_PIN_USB20_HOST, + AST_SCU_FUN_PIN_CTRL5); +} + +EXPORT_SYMBOL(ast_scu_multi_func_usb20_host_hub); + +//0 : gpioQ6,7 mode , 1: usb1.1 host port 4 mode +extern void +ast_scu_multi_func_usb11_host_port4(u8 mode) +{ + if(mode) + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL5) | SCU_FUC_PIN_USB11_PORT4, + AST_SCU_FUN_PIN_CTRL5); + else + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL5) & ~SCU_FUC_PIN_USB11_PORT4, + AST_SCU_FUN_PIN_CTRL5); +} + +EXPORT_SYMBOL(ast_scu_multi_func_usb11_host_port4); + +//0 : USB 1.1 HID mode , 1: usb1.1 host port 2 mode +extern void +ast_scu_multi_func_usb11_host_port2(u8 mode) +{ + if(mode) + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL5) | SCU_FUC_PIN_USB11_PORT2, + AST_SCU_FUN_PIN_CTRL5); + else + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL5) & ~SCU_FUC_PIN_USB11_PORT2, + AST_SCU_FUN_PIN_CTRL5); +} + +EXPORT_SYMBOL(ast_scu_multi_func_usb11_host_port2); + +//0 : 1: SD1 function +extern void +ast_scu_multi_func_sdhc_slot1(u8 mode) +{ + if(mode) + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL5) | SCU_FUC_PIN_SD1, + AST_SCU_FUN_PIN_CTRL5); + else + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL5) & ~SCU_FUC_PIN_SD1, + AST_SCU_FUN_PIN_CTRL5); +} + +EXPORT_SYMBOL(ast_scu_multi_func_sdhc_slot1); + +extern void +ast_scu_multi_func_sdhc_slot2(u8 mode) +{ + if(mode) + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL5) | SCU_FUC_PIN_SD2, + AST_SCU_FUN_PIN_CTRL5); + else + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL5) & ~SCU_FUC_PIN_SD2, + AST_SCU_FUN_PIN_CTRL5); + +} + +EXPORT_SYMBOL(ast_scu_multi_func_sdhc_slot2); + +extern void +ast_scu_multi_func_crt(void) +{ + /* multi-pin for DVO */ + + //Digital vodeo input function pins : 00 disable, 10 24bits mode 888, + ast_scu_write((ast_scu_read(AST_SCU_FUN_PIN_CTRL5) & + ~SCU_FUC_PIN_DIGI_V_OUT_MASK) | + SCU_FUC_PIN_DIGI_V_OUT(VIDEO_24BITS),AST_SCU_FUN_PIN_CTRL5); + + //VPI input +#if 0 + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL2) | + SCU_FUN_PIN_VPIB9 | SCU_FUN_PIN_VPIB8 | + SCU_FUN_PIN_VPIB7 | SCU_FUN_PIN_VPIB6 | + SCU_FUN_PIN_VPIB5 | SCU_FUN_PIN_VPIB4 | + SCU_FUN_PIN_VPIB3 | SCU_FUN_PIN_VPIB2 | + SCU_FUN_PIN_VPIB1 | SCU_FUN_PIN_VPIB0 | + SCU_FUN_PIN_VPICLK | SCU_FUN_PIN_VPIVS | + SCU_FUN_PIN_VPIHS | SCU_FUN_PIN_VPIODD | + SCU_FUN_PIN_VPIDE ,AST_SCU_FUN_PIN_CTRL2); + + ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL3) | + SCU_FUN_PIN_VPIR9 | SCU_FUN_PIN_VPIR8 | + SCU_FUN_PIN_VPIR7 | SCU_FUN_PIN_VPIR6 | + SCU_FUN_PIN_VPIR5 | SCU_FUN_PIN_VPIR4 | + SCU_FUN_PIN_VPIR3 | SCU_FUN_PIN_VPIR2 | + SCU_FUN_PIN_VPIR1 | SCU_FUN_PIN_VPIR0 | + SCU_FUN_PIN_VPIG9 | SCU_FUN_PIN_VPIG8 | + SCU_FUN_PIN_VPIG7 | SCU_FUN_PIN_VPIG6 | + SCU_FUN_PIN_VPIG5 | SCU_FUN_PIN_VPIG4 | + SCU_FUN_PIN_VPIG3 | SCU_FUN_PIN_VPIG2 | + SCU_FUN_PIN_VPIG1 | SCU_FUN_PIN_VPIG0 ,AST_SCU_FUN_PIN_CTRL3); +#endif +} + +EXPORT_SYMBOL(ast_scu_multi_func_crt); +//***********************************Information *********************************** +extern u32 +ast_scu_revision_id(void) +{ + int i; + u32 rev_id = ast_scu_read(AST_SCU_REVISION_ID); + for(i=0;i<ARRAY_SIZE(soc_map_table);i++) { + if(rev_id == soc_map_table[i].rev_id) + break; + } + if(i == ARRAY_SIZE(soc_map_table)) + SCUMSG("UnKnow-SOC : %x \n",rev_id); + else + SCUMSG("SOC : %4s \n",soc_map_table[i].name); + + return rev_id; +} + +EXPORT_SYMBOL(ast_scu_revision_id); + +/* +* D[15:11] in 0x1E6E2040 is NCSI scratch from U-Boot. D[15:14] = MAC1, D[13:12] = MAC2 +* The meanings of the 2 bits are: +* 00(0): Dedicated PHY +* 01(1): ASPEED's EVA + INTEL's NC-SI PHY chip EVA +* 10(2): ASPEED's MAC is connected to NC-SI PHY chip directly +* 11: Reserved +*/ + +extern u32 +ast_scu_get_phy_config(u8 mac_num) +{ + u32 scatch = ast_scu_read(AST_SCU_SOC_SCRATCH0); + + switch(mac_num) { + case 0: + return (SCU_MAC0_GET_PHY_MODE(scatch)); + break; + case 1: + return (SCU_MAC1_GET_PHY_MODE(scatch)); + break; + default: + SCUMSG("error mac number \n"); + break; + } + return -1; +} +EXPORT_SYMBOL(ast_scu_get_phy_config); + +extern u32 +ast_scu_get_phy_interface(u8 mac_num) +{ + u32 trap1 = ast_scu_read(AST_SCU_HW_STRAP1); + + switch(mac_num) { + case 0: + if(SCU_HW_STRAP_MAC0_RGMII & trap1) + return 1; + else + return 0; + break; + case 1: + if(SCU_HW_STRAP_MAC1_RGMII & trap1) + return 1; + else + return 0; + break; + default: + SCUMSG("error mac number \n"); + break; + } + return -1; +} +EXPORT_SYMBOL(ast_scu_get_phy_interface); + +extern void +ast_scu_set_vga_display(u8 enable) +{ + if(enable) + printk("111111"); +} + +EXPORT_SYMBOL(ast_scu_set_vga_display); + +extern u32 +ast_scu_get_vga_memsize(void) +{ + u32 size=0; + + switch(SCU_HW_STRAP_VGA_SIZE_GET(ast_scu_read(AST_SCU_HW_STRAP1))) { + case 0: + size = 8*1024*1024; + break; + case 1: + size = 16*1024*1024; + break; + case 2: + size = 32*1024*1024; + break; + case 3: + size = 64*1024*1024; + break; + default: + SCUMSG("error vga size \n"); + break; + } + return size; +} + +EXPORT_SYMBOL(ast_scu_get_vga_memsize); + +extern void +ast_scu_get_who_init_dram(void) +{ + switch(SCU_VGA_DRAM_INIT_MASK(ast_scu_read(AST_SCU_VGA0))) { + case 0: + SCUMSG("VBIOS init \n"); + break; + case 1: + SCUMSG("SOC init \n"); + break; + default: + SCUMSG("error vga size \n"); + break; + } +} diff --git a/arch/arm/plat-aspeed/ast-sdmc.c b/arch/arm/plat-aspeed/ast-sdmc.c new file mode 100644 index 000000000000..238cf79ea6da --- /dev/null +++ b/arch/arm/plat-aspeed/ast-sdmc.c @@ -0,0 +1,100 @@ +/******************************************************************************** +* File Name : arch/arm/mach-aspeed/ast-sdmc.c +* Author : Ryan Chen +* Description : AST SDRAM Memory Ctrl +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +* History : +* 1. 2013/03/15 Ryan Chen Create +* +********************************************************************************/ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/delay.h> +#include <asm/io.h> + +#include <mach/platform.h> +#include <mach/hardware.h> + +#include <plat/ast-sdmc.h> +#include <plat/regs-sdmc.h> + +//#define AST_SDMC_LOCK +//#define AST_SDMC_DEBUG + +#ifdef AST_SDMC_DEBUG +#define SDMCDBUG(fmt, args...) printk("%s() " fmt, __FUNCTION__, ## args) +#else +#define SDMCDBUG(fmt, args...) +#endif + +#define SDMCMSG(fmt, args...) printk(fmt, ## args) + +static u32 ast_sdmc_base = IO_ADDRESS(AST_SDMC_BASE); + +static inline u32 +ast_sdmc_read(u32 reg) +{ + u32 val; + + val = readl(ast_sdmc_base + reg); + + SDMCDBUG("ast_sdmc_read : reg = 0x%08x, val = 0x%08x\n", reg, val); + + return val; +} + +static inline void +ast_sdmc_write(u32 val, u32 reg) +{ + SDMCDBUG("ast_sdmc_write : reg = 0x%08x, val = 0x%08x\n", reg, val); +#ifdef CONFIG_AST_SDMC_LOCK + //unlock + writel(SDMC_PROTECT_UNLOCK, ast_sdmc_base); + writel(val, ast_sdmc_base + reg); + //lock + writel(0xaa,ast_sdmc_base); +#else + writel(SDMC_PROTECT_UNLOCK, ast_sdmc_base); + + writel(val, ast_sdmc_base + reg); +#endif +} + +//***********************************Information *********************************** +extern u32 +ast_sdmc_get_mem_size(void) +{ + u32 size=0; + switch(SDMC_CONFIG_MEM_GET(ast_sdmc_read(AST_SDMC_CONFIG))) { + case 0: + size = 64*1024*1024; + break; + case 1: + size = 128*1024*1024; + break; + case 2: + size = 256*1024*1024; + break; + case 3: + size = 512*1024*1024; + break; + + default: + SDMCMSG("error ddr size \n"); + break; + } + return size; +} + diff --git a/arch/arm/plat-aspeed/ast1070-scu.c b/arch/arm/plat-aspeed/ast1070-scu.c new file mode 100644 index 000000000000..4ad12c74da28 --- /dev/null +++ b/arch/arm/plat-aspeed/ast1070-scu.c @@ -0,0 +1,178 @@ +/******************************************************************************** +* File Name : arch/arm/mach-aspeed/ast1070-scu.c +* Author : Ryan Chen +* Description : AST1070 SCU +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2013/05/15 Ryan Chen Create +* +********************************************************************************/ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/delay.h> + +#include <mach/platform.h> +#include <asm/io.h> + +#include <mach/hardware.h> + +#include <plat/ast1070-scu.h> +#include <plat/regs-ast1070-scu.h> + +#define CONFIG_AST1070_SCU_LOCK +//#define AST1070_SCU_DEBUG + +#ifdef AST1070_SCU_DEBUG +#define SCUDBUG(fmt, args...) printk("%s() " fmt, __FUNCTION__, ## args) +#else +#define SCUDBUG(fmt, args...) +#endif + +#define SCUMSG(fmt, args...) printk(fmt, ## args) + +static u32 ast1070_scu_base = IO_ADDRESS2(AST_C0_SCU_BASE); + +static inline u32 +ast1070_scu_read(u8 node, u32 reg) +{ + u32 val; + + val = readl(ast1070_scu_base + (node * 0x10000) + reg); + + SCUDBUG("ast1070_scu_read : reg = 0x%08x, val = 0x%08x\n", reg, val); + + return val; +} + +static inline void +ast1070_scu_write(u8 node, u32 val, u32 reg) +{ + SCUDBUG("ast1070_scu_write : reg = 0x%08x, val = 0x%08x\n", reg, val); +#ifdef CONFIG_AST1070_SCU_LOCK + //unlock + writel(AST1070_SCU_PROTECT_UNLOCK, ast1070_scu_base + (node * 0x10000)); + writel(val, ast1070_scu_base + (node * 0x10000) + reg); + //lock +// writel(0xaa,ast1070_scu_base + (node * 0x10000)); +#else + writel(val, ast1070_scu_base + (node * 0x10000) + reg); +#endif +} + +extern void +ast1070_scu_init_uart(u8 node) +{ + //SCU UART Reset + ast1070_scu_write(node, ast1070_scu_read(node, AST1070_SCU_RESET) & + ~(SCU_RESET_N1_UART | SCU_RESET_N2_UART | + SCU_RESET_N3_UART | SCU_RESET_N4_UART), + AST1070_SCU_RESET); +} + +EXPORT_SYMBOL(ast1070_scu_init_uart); + +extern void +ast1070_scu_init_i2c(u8 node) +{ + //SCU I2C Reset + ast1070_scu_write(node, ast1070_scu_read(node, AST1070_SCU_RESET) & ~SCU_RESET_I2C, AST1070_SCU_RESET); +} + +EXPORT_SYMBOL(ast1070_scu_init_i2c); + +extern void +ast1070_dma_init(u8 node) +{ + u32 val =0; + + //let the uart_dma engine leave the reset state + ast1070_scu_write(node, ast1070_scu_read(node, AST1070_SCU_RESET) & ~SCU_RESET_DMA, AST1070_SCU_RESET); + + val = ast1070_scu_read(node, AST1070_SCU_MISC_CTRL) & ~SCU_DMA_M_S_MASK; + + if(ast1070_scu_read(node, AST1070_SCU_TRAP) & TRAP_MULTI_MASTER) { + //AST1070 multi Initial DMA + if(ast1070_scu_read(node, AST1070_SCU_TRAP) & TRAP_DEVICE_SLAVE) + ast1070_scu_write(node, val | SCU_DMA_SLAVE_EN, AST1070_SCU_MISC_CTRL); + else + //Enable DMA master + ast1070_scu_write(node, val | SCU_DMA_MASTER_EN, AST1070_SCU_MISC_CTRL); + + } else { + //AST1070 single + ast1070_scu_write(node, val, AST1070_SCU_MISC_CTRL); + } +} +EXPORT_SYMBOL(ast1070_dma_init); + + +extern void +ast1070_scu_init_lpc(void) +{ + +} + +EXPORT_SYMBOL(ast1070_scu_init_lpc); + +//***********************************Multi-function pin control*********************************** + +extern void +ast1070_multi_func_uart(u8 node, u8 uart) +{ + ast1070_scu_write(node, (ast1070_scu_read(node, AST1070_SCU_UART_MUX) & + ~UART_MUX_MASK(uart)) | + SET_UART_IO_PAD(uart,PAD_FROM_BMC) | + SET_NODE_UART_CTRL(uart, NODE_UART_FROM_NONE) | + SET_BMC_UART_CTRL(uart, BMC_UART_FROM_PAD1), + AST1070_SCU_UART_MUX); + +} + +EXPORT_SYMBOL(ast1070_multi_func_uart); + + +//***********************************CLK control*********************************** + + +//***********************************CLK Information*********************************** +extern u32 +ast1070_get_clk_source(void) +{ + +} +EXPORT_SYMBOL(ast1070_get_clk_source); + +//***********************************Information *********************************** +extern void +ast1070_scu_revision_id(u8 node) +{ + u32 rev_id; + +#if 0 + if(gpio_get_value(PIN_GPIOI1)) + printk("Use LPC+ Bus Access \n"); + else + printk("Use LPC Bus Access \n"); +#endif + + rev_id = ast1070_scu_read(node, AST1070_SCU_CHIP_ID); + if (ast1070_scu_read(node, AST1070_SCU_TRAP) & TRAP_LPC_PLUS_MODE) { + printk("LPC+ : "); + } else + printk("LPC : "); + + printk("AST1070-[C%d] rev_id[%x] \n",node,rev_id); +} + +EXPORT_SYMBOL(ast1070_scu_revision_id); diff --git a/arch/arm/plat-aspeed/ast1070-uart-dma.c b/arch/arm/plat-aspeed/ast1070-uart-dma.c new file mode 100644 index 000000000000..9da401ead6fa --- /dev/null +++ b/arch/arm/plat-aspeed/ast1070-uart-dma.c @@ -0,0 +1,572 @@ +/* + * ast1070-uart-dma.c + * + * UART DMA for the AST1070 UART access. + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * History: + * 2012.05.26: Initial version [Ryan Chen] + */ + +#include <linux/sysdev.h> +#include <linux/dma-mapping.h> +#include <linux/interrupt.h> +#include <asm/io.h> +#include <mach/irqs.h> +#include <mach/hardware.h> +#include <mach/ast-uart-dma.h> +#include <plat/regs-uart-dma.h> + +//#define AST_UART_DMA_DEBUG + +#ifdef AST_UART_DMA_DEBUG +#define DMADUG(fmt, args...) printk("%s() " fmt, __FUNCTION__, ## args) +#else +#define DMADUG(fmt, args...) +#endif + +//#define AST1070_FPGA 1 + +struct ast1070_dma uart_dma[CONFIG_AST1070_NR]; + +static inline void +ast1070_uart_dma_write(struct ast1070_dma *dma, u32 val, u32 reg) +{ + //printk("uart dma write : val: %x , reg : %x \n",val,reg); + writel(val, dma->reg_base+ reg); +} + +static inline u32 +ast1070_uart_dma_read(struct ast1070_dma *dma, u32 reg) +{ +#if 0 + u32 val = readl(i2c_dev->reg_base + reg); + printk("R : reg %x , val: %x \n",reg, val); + return val; +#else + return readl(dma->reg_base + reg); +#endif +} + +/* *****************************************************************************/ +int ast_uart_rx_dma_enqueue(u8 node, u8 ch, dma_addr_t rx_buff, u16 len) +{ + unsigned long flags; + struct ast1070_dma *dma = &uart_dma[node]; + struct ast1070_dma_ch *dma_ch = &(dma->dma_rx_ch[ch]); + struct uart_dma_desc *rx_desc = dma_ch->desc; + + if(len > 4096) + printk("ERROR !!! Please Check ...\n"); + + local_irq_save(flags); + + //fill to rx desc --> + rx_desc->desc0 = DESC0_END | DESC0_INT_EN | DESC0_HW_OWN; + rx_desc->desc1 = DESC1_LEN(len); + rx_desc->desc2 = rx_buff; + rx_desc->desc3 = 0; + + DMADUG("[c%d]: ch = %d, rx buff = %x, len = %d \n",node, ch, rx_buff, len); + + //fill in tx descriptor base register + DMADUG("desc_addr : %x, reg offset %x \n",dma_ch->desc_dma_addr, dma_ch->desc_offset); + ast1070_uart_dma_write(dma, dma_ch->desc_dma_addr, dma_ch->desc_offset); + + local_irq_restore(flags); + + return 0; +} + +EXPORT_SYMBOL(ast_uart_rx_dma_enqueue); + +int ast_uart_tx_dma_enqueue(u8 node, u8 ch, dma_addr_t tx_buff, u16 len) +{ + unsigned long flags; + struct ast1070_dma *dma = &uart_dma[node]; + struct ast1070_dma_ch *dma_ch = &(dma->dma_tx_ch[ch]); + struct uart_dma_desc *tx_desc = dma_ch->desc; + + DMADUG("[c%d]: ch = %d, tx buff = %x, len = %d \n",node, ch, tx_buff, len); + + local_irq_save(flags); + + //fill to rx desc --> + tx_desc->desc0 = DESC0_END | DESC0_INT_EN | DESC0_HW_OWN; + tx_desc->desc1 = DESC1_LEN(len); + tx_desc->desc2 = tx_buff; + tx_desc->desc3 = 0; + +// DMADUG("desc vir = %x, tx desc = %x, %x, %x, %x ===\n",tx_desc, tx_desc->desc0 ,tx_desc->desc1,tx_desc->desc2,tx_desc->desc3); + //fill in tx descriptor base register + DMADUG("desc_addr : %x, in offset %x \n",dma_ch->desc_dma_addr, dma_ch->desc_offset); + ast1070_uart_dma_write(dma, dma_ch->desc_dma_addr, dma_ch->desc_offset); + + local_irq_restore(flags); + + return 0; +} + +EXPORT_SYMBOL(ast_uart_tx_dma_enqueue); + +int ast_uart_rx_dma_ctrl(u8 node, u8 ch, enum ast_uart_chan_op op) +{ + unsigned long flags; + struct ast1070_dma *dma = &uart_dma[node]; + struct ast1070_dma_ch *dma_ch = &(dma->dma_rx_ch[ch]); + DMADUG("[c%d]: ch = %d \n",node, ch); + + local_irq_save(flags); + + switch (op) { + case AST_UART_DMAOP_TRIGGER: + //trigger + DMADUG("Trigger \n"); + dma_ch->enable = 1; +// ast1070_uart_dma_write(dma, DMA_ENABLE, dma_ch->ctrl_offset); + ast1070_uart_dma_write(dma, DMA_TRIGGER | DMA_ENABLE, dma_ch->ctrl_offset); + break; + + case AST_UART_DMAOP_STOP: + //disable engine + DMADUG("Stop \n"); + dma_ch->enable = 0; + ast1070_uart_dma_write(dma, 0, dma_ch->ctrl_offset); + break; + } + + + return 0; +} +EXPORT_SYMBOL(ast_uart_rx_dma_ctrl); + +int ast_uart_tx_dma_ctrl(u8 node, u8 ch, enum ast_uart_chan_op op) +{ + unsigned long flags; + struct ast1070_dma *dma = &uart_dma[node]; + struct ast1070_dma_ch *dma_ch = &(dma->dma_tx_ch[ch]); + DMADUG("TX DMA CTRL [c%d]: ch = %d \n",node, ch); + + local_irq_save(flags); + + switch (op) { + case AST_UART_DMAOP_TRIGGER: + //trigger + DMADUG("Trigger \n"); + ast1070_uart_dma_write(dma, DMA_ENABLE, dma_ch->ctrl_offset); + ast1070_uart_dma_write(dma, DMA_TRIGGER | DMA_ENABLE, dma_ch->ctrl_offset); + break; + + case AST_UART_DMAOP_STOP: + //disable engine + DMADUG("STOP \n"); + ast1070_uart_dma_write(dma, 0, dma_ch->ctrl_offset); + break; + } + + + return 0; +} +EXPORT_SYMBOL(ast_uart_tx_dma_ctrl); + +int ast_uart_tx_dma_request(u8 node, u8 ch, ast_uart_dma_cbfn_t rtn, void *id) +{ + unsigned long flags; + struct ast1070_dma *dma = &uart_dma[node]; + struct ast1070_dma_ch *dma_ch = &(dma->dma_tx_ch[ch]); + + DMADUG("TX DMA REQUEST [c%d]: ch = %d \n",node, ch); + + local_irq_save(flags); + + if (dma_ch->enable) { + local_irq_restore(flags); + return -EBUSY; + } + + dma_ch->priv = id; + dma_ch->enable = 1; + dma_ch->callback_fn = rtn; + //DMA IRQ En + ast1070_uart_dma_write(dma, + ast1070_uart_dma_read(dma, UART_DMA_IER) | + (1 << ch) + , UART_DMA_IER); + + //enable engine +// ast1070_uart_dma_write(dma, DMA_ENABLE, dma_ch->ctrl_offset); + local_irq_restore(flags); + + return 0; + +} + +EXPORT_SYMBOL(ast_uart_tx_dma_request); + +int ast_uart_rx_dma_request(u8 node, u8 ch, ast_uart_dma_cbfn_t rtn, void *id) +{ + unsigned long flags; + struct ast1070_dma *dma = &uart_dma[node]; + struct ast1070_dma_ch *dma_ch = &(dma->dma_rx_ch[ch]); + + DMADUG("RX DMA REQUEST [c%d] : ch = %d \n",node, ch); + + local_irq_save(flags); + + if (dma->dma_rx_ch[ch].enable) { + local_irq_restore(flags); + return -EBUSY; + } + dma_ch->priv = id; +// dma_ch->enable = 1; + dma_ch->callback_fn = rtn; +// dma_ch->name + //DMA IRQ En + ast1070_uart_dma_write(dma, + ast1070_uart_dma_read(dma, UART_DMA_IER) | + (1 << (4+ch)) + , UART_DMA_IER); + + //enable engine +// ast1070_uart_dma_write(dma, DMA_ENABLE, dma_ch->ctrl_offset); + local_irq_restore(flags); + + return 0; + +} + +EXPORT_SYMBOL(ast_uart_rx_dma_request); +/* *****************************************************************************/ +static inline void ast_dma_bufffdone(struct ast1070_dma_ch *dma_ch) +{ + ////TODO desc -- remove ...... + //workaround : Issue RX dma can;t be stoped , close open close + if(dma_ch->enable == 0) { +// printk("workaround \n"); + return; + } + +// u32 sts = ast1070_uart_dma_read(dma, dma_ch->ctrl_offset); + DMADUG("dma dwn : ch[%d] : %s ,len : %d \n", dma_ch->ch_no, dma_ch->direction ? "tx" : "rx", DESC3_GET_LEN(dma_ch->desc->desc3)); + + DMADUG(" == desc = %x, %x, %x, %x ===\n",dma_ch->desc->desc0,dma_ch->desc->desc1,dma_ch->desc->desc2,dma_ch->desc->desc3); + + + if(dma_ch->desc->desc0 & DESC0_HW_OWN) + printk("ERROR ..... \n"); + + if (dma_ch->callback_fn != NULL) + (dma_ch->callback_fn)(dma_ch, dma_ch->priv, DESC3_GET_LEN(dma_ch->desc->desc3)); +} + + +static irqreturn_t +ast1070_c0_uart_dma_irq(int irq, void *dev_id) +{ +// struct ast1070_dma *dma = dev_id; + int i; + struct ast1070_dma *dma = &uart_dma[0]; + u32 sts = ast1070_uart_dma_read(dma, UART_DMA_ISR); + DMADUG("C0 int -- > \n"); + DMADUG("isr sts = %x\n", sts); + + for(i = 0;i < 17 ; i++) + DMADUG("offset : %x , val %x \n",i*4, ast1070_uart_dma_read(dma, i*4)); + + if (sts & UART_DMA3_RX_INT) { + ast1070_uart_dma_write(dma, UART_DMA3_RX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_rx_ch[3])); + } else if (sts & UART_DMA2_RX_INT) { + ast1070_uart_dma_write(dma, UART_DMA2_RX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_rx_ch[2])); + } else if (sts & UART_DMA1_RX_INT) { + ast1070_uart_dma_write(dma, UART_DMA1_RX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_rx_ch[1])); + } else if (sts & UART_DMA0_RX_INT) { + ast1070_uart_dma_write(dma, UART_DMA0_RX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_rx_ch[0])); + } else if (sts & UART_DMA3_TX_INT) { + ast1070_uart_dma_write(dma, UART_DMA3_TX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_tx_ch[3])); + } else if (sts & UART_DMA2_TX_INT) { + ast1070_uart_dma_write(dma, UART_DMA2_TX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_tx_ch[2])); + } else if (sts & UART_DMA1_TX_INT) { + ast1070_uart_dma_write(dma, UART_DMA1_TX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_tx_ch[1])); + } else if (sts & UART_DMA0_TX_INT) { + ast1070_uart_dma_write(dma, UART_DMA0_TX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_tx_ch[0])); + } else { + printk("No body .. !!! \n"); + } + + return IRQ_HANDLED; +} + +#if (CONFIG_AST1070_NR >=2) +static irqreturn_t +ast1070_c1_uart_dma_irq(int irq, void *dev_id) +{ +// struct ast1070_dma *dma = dev_id; + struct ast1070_dma *dma = &uart_dma[1]; + u32 sts = ast1070_uart_dma_read(dma, UART_DMA_ISR); + DMADUG("C1 int -- > \n"); + +// DMADUG("isr sts = %x\n", sts); + if (sts & UART_DMA3_RX_INT) { + ast1070_uart_dma_write(dma, UART_DMA3_RX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_rx_ch[3])); + } else if (sts & UART_DMA2_RX_INT) { + ast1070_uart_dma_write(dma, UART_DMA2_RX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_rx_ch[2])); + } else if (sts & UART_DMA1_RX_INT) { + ast1070_uart_dma_write(dma, UART_DMA1_RX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_rx_ch[1])); + } else if (sts & UART_DMA0_RX_INT) { + ast1070_uart_dma_write(dma, UART_DMA0_RX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_rx_ch[0])); + } else if (sts & UART_DMA3_TX_INT) { + ast1070_uart_dma_write(dma, UART_DMA3_TX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_tx_ch[3])); + } else if (sts & UART_DMA2_TX_INT) { + ast1070_uart_dma_write(dma, UART_DMA2_TX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_tx_ch[2])); + } else if (sts & UART_DMA1_TX_INT) { + ast1070_uart_dma_write(dma, UART_DMA1_TX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_tx_ch[1])); + } else if (sts & UART_DMA0_TX_INT) { + ast1070_uart_dma_write(dma, UART_DMA0_TX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_tx_ch[0])); + } else { + printk("No body .. !!! \n"); + } + + return IRQ_HANDLED; +} +#endif + +#if (CONFIG_AST1070_NR >=3) +static irqreturn_t +ast1070_c2_uart_dma_irq(int irq, void *dev_id) +{ + struct ast1070_dma *dma = dev_id; + u32 sts = ast1070_uart_dma_read(dma, UART_DMA_ISR); + +// DMADUG("isr sts = %x\n", sts); + if (sts & UART_DMA3_RX_INT) { + ast1070_uart_dma_write(dma, UART_DMA3_RX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_rx_ch[3])); + } else if (sts & UART_DMA2_RX_INT) { + ast1070_uart_dma_write(dma, UART_DMA2_RX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_rx_ch[2])); + } else if (sts & UART_DMA1_RX_INT) { + ast1070_uart_dma_write(dma, UART_DMA1_RX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_rx_ch[1])); + } else if (sts & UART_DMA0_RX_INT) { + ast1070_uart_dma_write(dma, UART_DMA0_RX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_rx_ch[0])); + } else if (sts & UART_DMA3_TX_INT) { + ast1070_uart_dma_write(dma, UART_DMA3_TX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_tx_ch[3])); + } else if (sts & UART_DMA2_TX_INT) { + ast1070_uart_dma_write(dma, UART_DMA2_TX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_tx_ch[2])); + } else if (sts & UART_DMA1_TX_INT) { + ast1070_uart_dma_write(dma, UART_DMA1_TX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_tx_ch[1])); + } else if (sts & UART_DMA0_TX_INT) { + ast1070_uart_dma_write(dma, UART_DMA0_TX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_tx_ch[0])); + } else { + printk("No body .. !!! \n"); + } + + return IRQ_HANDLED; +} +#endif + +#if (CONFIG_AST1070_NR >=4) +static irqreturn_t +ast1070_c3_uart_dma_irq(int irq, void *dev_id) +{ + struct ast1070_dma *dma = dev_id; + u32 sts = ast1070_uart_dma_read(dma, UART_DMA_ISR); + +// DMADUG("isr sts = %x\n", sts); + if (sts & UART_DMA3_RX_INT) { + ast1070_uart_dma_write(dma, UART_DMA3_RX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_rx_ch[3])); + } else if (sts & UART_DMA2_RX_INT) { + ast1070_uart_dma_write(dma, UART_DMA2_RX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_rx_ch[2])); + } else if (sts & UART_DMA1_RX_INT) { + ast1070_uart_dma_write(dma, UART_DMA1_RX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_rx_ch[1])); + } else if (sts & UART_DMA0_RX_INT) { + ast1070_uart_dma_write(dma, UART_DMA0_RX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_rx_ch[0])); + } else if (sts & UART_DMA3_TX_INT) { + ast1070_uart_dma_write(dma, UART_DMA3_TX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_tx_ch[3])); + } else if (sts & UART_DMA2_TX_INT) { + ast1070_uart_dma_write(dma, UART_DMA2_TX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_tx_ch[2])); + } else if (sts & UART_DMA1_TX_INT) { + ast1070_uart_dma_write(dma, UART_DMA1_TX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_tx_ch[1])); + } else if (sts & UART_DMA0_TX_INT) { + ast1070_uart_dma_write(dma, UART_DMA0_TX_INT, UART_DMA_ISR); + ast_dma_bufffdone(&(dma->dma_tx_ch[0])); + } else { + printk("No body .. !!! \n"); + } + + return IRQ_HANDLED; +} +#endif + +extern int +ast1070_uart_dma_init(u8 node) +{ + int ret,i; + struct ast1070_dma *dma = &uart_dma[node]; + + DMADUG("ast1070 uart_dma_init [c%d]\n", node); + + if(node == 0) { + dma->reg_base = ioremap(AST_C0_UART_DMA_BASE, 0x100); +#if (CONFIG_AST1070_NR >=2) + } else if (node == 1) { + dma->reg_base = ioremap(AST_C1_UART_DMA_BASE, 0x100); +#endif +#if (CONFIG_AST1070_NR >=3) + } else if (node == 2) { + dma->reg_base = ioremap(AST_C2_UART_DMA_BASE, 0x100); +#endif +#if (CONFIG_AST1070_NR >=4) + } else if (node == 3) { + dma->reg_base = ioremap(AST_C3_UART_DMA_BASE, 0x100); +#endif + } else { + printk("node out of range !! \n"); + return 1; + } + + if (!dma->reg_base) { + printk(KERN_ERR "%s: failed to ioremap()\n", __func__); + return -ENXIO; + } + + ast1070_uart_dma_write(dma, 0xff, UART_DMA_ISR); + ast1070_uart_dma_write(dma, 0, UART_DMA_IER); + + for(i=0;i<4;i++) { + //TX ------------------------ + dma->dma_tx_ch[i].enable = 0; + dma->dma_tx_ch[i].ch_no = i; + dma->dma_tx_ch[i].direction = 1; + //tx descriptor allocation + dma->dma_tx_ch[i].desc = dma_alloc_coherent(NULL, sizeof(struct uart_dma_desc), &(dma->dma_tx_ch[i].desc_dma_addr), GFP_KERNEL); + if (dma->dma_tx_ch[i].desc == NULL) { + DMADUG("Can't allocate tx descriptor\n"); + return 0; + } + memset(dma->dma_tx_ch[i].desc, 0, sizeof(struct uart_dma_desc)); + DMADUG("tx_desc [%d] virt = %x, dma = %x\n", i, (u32)dma->dma_tx_ch[i].desc, dma->dma_tx_ch[i].desc_dma_addr); + + ast1070_uart_dma_write(dma, 0, UART_DMA0_TX_CTRL + (i*8)); + dma->dma_tx_ch[i].ctrl_offset = UART_DMA0_TX_CTRL + (i*8); + dma->dma_tx_ch[i].desc_offset = UART_DMA0_TX_DESCPT + (i*8); + + //RX ------------------------ + dma->dma_rx_ch[i].enable = 0; + dma->dma_rx_ch[i].ch_no = i; + dma->dma_rx_ch[i].direction = 0; + //rx descriptor allocation + dma->dma_rx_ch[i].desc = dma_alloc_coherent(NULL, sizeof(struct uart_dma_desc), &(dma->dma_rx_ch[i].desc_dma_addr), GFP_KERNEL); + if (dma->dma_rx_ch[i].desc == NULL) { + DMADUG("Can't allocate tx descriptor\n"); + return 0; + } + memset(dma->dma_rx_ch[i].desc, 0, sizeof(struct uart_dma_desc)); + DMADUG("rx_desc [%d] virt = %x, dma = %x\n", i, (u32)dma->dma_rx_ch[i].desc, dma->dma_rx_ch[i].desc_dma_addr); + ast1070_uart_dma_write(dma, 0, UART_DMA0_RX_CTRL + (i*8)); + dma->dma_rx_ch[i].ctrl_offset = UART_DMA0_RX_CTRL + (i*8); + dma->dma_rx_ch[i].desc_offset = UART_DMA0_RX_DESCPT + (i*8); + } + + DMADUG("reg base = %x \n", (u32)dma->reg_base); + + if(node == 0) { + for(i=0;i<4;i++) { + ret = request_irq(IRQ_C0_N1_UART_DMA + i, + ast1070_c0_uart_dma_irq, IRQF_SHARED, + "ast1070_n1_uart_dma", dma); + if (ret) + printk ("Unable to get UART DMA IRQ !!!!!!!!!!!!!!!!!!!!\n"); + } +#if (CONFIG_AST1070_NR >=2) + } else if (node == 1) { + for(i=0;i<4;i++) { + ret = request_irq(IRQ_C1_N1_UART_DMA + i, + ast1070_c1_uart_dma_irq, IRQF_SHARED, + "ast1070_n1_uart_dma", dma); + if (ret) + printk ("Unable to get UART DMA IRQ !!!!!!!!!!!!!!!!!!!!\n"); + } +#endif +#if (CONFIG_AST1070_NR >=3) + } else if (node == 2) { + for(i=0;i<4;i++) { + ret = request_irq(IRQ_C2_N1_UART_DMA + i, + ast1070_c2_uart_dma_irq, IRQF_SHARED, + "ast1070_n1_uart_dma", dma); + if (ret) + printk ("Unable to get UART DMA IRQ !!!!!!!!!!!!!!!!!!!!\n"); + } +#endif +#if (CONFIG_AST1070_NR >=4) + } else if (node == 3) { + for(i=0;i<4;i++) { + ret = request_irq(IRQ_C3_N1_UART_DMA + i, + ast1070_c3_uart_dma_irq, IRQF_SHARED, + "ast1070_n1_uart_dma", dma); + if (ret) + printk ("Unable to get UART DMA IRQ !!!!!!!!!!!!!!!!!!!!\n"); + } +#endif + } else { + printk("ERROR !! \n"); + } + + //Limit : AST1070 4* SPI CLK < AST2400 HCLK + +#ifdef AST1070_FPGA + //Low SPI clk setting == PCLK/8 , set 11 + ast1070_uart_dma_write(dma, + (ast1070_uart_dma_read(dma, UART_DMA_CTRL) & ~SPI_CLK_MASK) | + SPI_CLK_SET(0x3) | + DMA_RX_TIMEOUT(0xfff) | + TXDESC_AUTO_POLLING | + RXDESC_AUTO_POLLING + , UART_DMA_CTRL); +#else + ast1070_uart_dma_write(dma, + (ast1070_uart_dma_read(dma, UART_DMA_CTRL) & + ~DMA_BURST_MASK) | + DMA_RX_TIMEOUT(0xfff) | + TXDESC_AUTO_POLLING | + RXDESC_AUTO_POLLING + , UART_DMA_CTRL); +#endif + + return 0; +} + +EXPORT_SYMBOL(ast1070_uart_dma_init); diff --git a/arch/arm/plat-aspeed/ast1070_irq.c b/arch/arm/plat-aspeed/ast1070_irq.c new file mode 100644 index 000000000000..e859cd17458a --- /dev/null +++ b/arch/arm/plat-aspeed/ast1070_irq.c @@ -0,0 +1,220 @@ +/* + * linux/arch/arm/plat-aspeed/ast1070_irq.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/init.h> +#include <linux/stddef.h> +#include <linux/list.h> +#include <linux/timer.h> + +#include <linux/device.h> +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> +#include <linux/sysdev.h> +#include <linux/interrupt.h> +#include <asm/system.h> +#include <linux/irq.h> + +#include <mach/hardware.h> +#include <asm/mach/irq.h> + +#include <asm/irq.h> +#include <asm/io.h> + +#include <plat/regs-ast1070-intc.h> + +#define irq_to_c0_vic(irq_no) (irq_no-IRQ_C0_VIC_CHAIN_START) + +static void ast1070_c0_mask_irq(unsigned int irq) +{ + u32 regVal; +// printk("ast_c0_mask_irq %d\n",irq); + irq = irq_to_c0_vic(irq); +// printk("ast_c0_mask_irq cvic %d\n",irq); + regVal = readl(AST_INTR_DIS(0)); + regVal |= (1 << irq); + writel(regVal, AST_INTR_DIS(0)); + +} + +static void ast1070_c0_unmask_irq(unsigned int irq) +{ + u32 regVal; +// printk("ast_c0_unmask_irq %d\n",irq); + irq = irq_to_c0_vic(irq); +// printk("ast_c0_unmask_irq cvic %d\n",irq); + regVal = readl(AST_INTR_EN(0)); + regVal |= (1 << irq); + writel(regVal, AST_INTR_EN(0)); +} + +static struct irq_chip ast1070_c0_irq_chip = { + .name = "ast1070_c0", + .ack = ast1070_c0_mask_irq, + .mask = ast1070_c0_mask_irq, + .unmask = ast1070_c0_unmask_irq, +}; + +static void +ast1070_c0_handle_irq(unsigned int irq, struct irq_desc *desc) +{ + int i,cvic_irq=0; + unsigned long sts = readl(AST_IRQ_STS(0)); + + if(irq != IRQ_C0_VIC_CHAIN) + BUG(); + + desc->chip->ack(IRQ_C0_VIC_CHAIN); + + if (sts == 0) { + do_bad_IRQ(irq, desc); + return; + } + + do { + for(i=0; i<AST_CVIC_NUM; i++) { + if((1<<i)& readl(AST_IRQ_STS(0))) { + cvic_irq =i; + break; + } + } + cvic_irq += IRQ_C0_VIC_CHAIN_START; + //dispatch IRQ +// printk("dispatch ast1070 IRQ %d\n",cvic_irq); + generic_handle_irq(cvic_irq); + + } while (readl(AST_IRQ_STS(0))); + + desc->chip->unmask(IRQ_C0_VIC_CHAIN); + +} + +static int __init ast1070_c0_init_irq(void) +{ + unsigned int i; +// printk("ast1070_c0_init_irq **==== Start ---------------\n"); + /* CVIC */ + writel(0, AST_INTR_EN(0)); + writel(0xFFFFFFFF, AST_INTR_DIS(0)); + + //AST1070 total IRQ# 25 + for (i = 0; i < AST_CVIC_NUM; i++) + { + IRQ_SET_HIGH_LEVEL(0,i); + IRQ_SET_LEVEL_TRIGGER(0,i); + set_irq_chip(i + IRQ_C0_VIC_CHAIN_START, &ast1070_c0_irq_chip); + set_irq_handler(i + IRQ_C0_VIC_CHAIN_START, handle_level_irq); + set_irq_flags(i + IRQ_C0_VIC_CHAIN_START, IRQF_VALID); + } + set_irq_chained_handler(IRQ_C0_VIC_CHAIN, ast1070_c0_handle_irq); +// printk("ast1070_init_irq **==== END ----------\n"); + return 0; +} + +arch_initcall(ast1070_c0_init_irq); + +#if (CONFIG_AST1070_NR >= 2) +#define irq_to_c1_vic(irq_no) (irq_no-IRQ_C1_VIC_CHAIN_START) + +static void ast1070_c1_mask_irq(unsigned int irq) +{ + u32 regVal; +// printk("ast_mask_irq %d\n",irq); + irq = irq_to_c1_vic(irq); +// printk("ast_mask_irq cvic %d\n",irq); + regVal = readl(AST_INTR_DIS(1)); + regVal |= (1 << irq); + writel(regVal, AST_INTR_DIS(1)); + +} + +static void ast1070_c1_unmask_irq(unsigned int irq) +{ + u32 regVal; +// printk("ast_unmask_irq %d\n",irq); + irq = irq_to_c1_vic(irq); +// printk("ast_unmask_irq cvic %d\n",irq); + regVal = readl(AST_INTR_EN(1)); + regVal |= (1 << irq); + writel(regVal, AST_INTR_EN(1)); +} + +static struct irq_chip ast1070_c1_irq_chip = { + .name = "ast1070_c1", + .ack = ast1070_c1_mask_irq, + .mask = ast1070_c1_mask_irq, + .unmask = ast1070_c1_unmask_irq, +}; + +static void +ast1070_c1_handle_irq(unsigned int irq, struct irq_desc *desc) +{ + int i,cvic_irq=0; + unsigned long sts = readl(AST_IRQ_STS(1)); + + if(irq != IRQ_C1_VIC_CHAIN) + BUG(); + + desc->chip->ack(IRQ_C1_VIC_CHAIN); + + if (sts == 0) { + do_bad_IRQ(irq, desc); + return; + } + + do { + for(i=0; i<AST_CVIC_NUM; i++) { + if((1<<i)& readl(AST_IRQ_STS(1))) { + cvic_irq =i; + break; + } + } + cvic_irq += IRQ_C1_VIC_CHAIN_START; + //dispatch IRQ +// printk("dispatch ast1070 IRQ %d\n",cvic_irq); + generic_handle_irq(cvic_irq); + + } while (readl(AST_IRQ_STS(1))); + + desc->chip->unmask(IRQ_C1_VIC_CHAIN); + +} + +static int __init ast1070_c1_init_irq(void) +{ + unsigned int i; +// printk("ast1070_c1_init_irq **==== Start ---------------\n"); + /* CVIC */ + writel(0, AST_INTR_EN(1)); + writel(0xFFFFFFFF, AST_INTR_DIS(1)); + + //AST1070 total IRQ# 25 + for (i = 0; i < AST_CVIC_NUM; i++) + { + IRQ_SET_HIGH_LEVEL(1,i); + IRQ_SET_LEVEL_TRIGGER(1,i); + set_irq_chip(i + IRQ_C1_VIC_CHAIN_START, &ast1070_c1_irq_chip); + set_irq_handler(i + IRQ_C1_VIC_CHAIN_START, handle_level_irq); + set_irq_flags(i + IRQ_C1_VIC_CHAIN_START, IRQF_VALID); + } + set_irq_chained_handler(IRQ_C1_VIC_CHAIN, ast1070_c1_handle_irq); +// printk("ast1070_init_irq **==== END ----------\n"); + return 0; +} + +arch_initcall(ast1070_c1_init_irq); + +#endif diff --git a/arch/arm/plat-aspeed/dev-adc.c b/arch/arm/plat-aspeed/dev-adc.c new file mode 100644 index 000000000000..e8d325aa303c --- /dev/null +++ b/arch/arm/plat-aspeed/dev-adc.c @@ -0,0 +1,76 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-adc.c +* Author : Ryan chen +* Description : ASPEED ADC Device +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/08/06 ryan chen create this file +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#if defined(CONFIG_COLDFIRE) +#include <asm/sizes.h> + +#include <asm/arch/irqs.h> +#include <asm/arch/platform.h> +#include <asm/arch/devs.h> +#include <asm/arch/ast-scu.h> +#else +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/devs.h> +#include <plat/ast-scu.h> +#endif + +/* -------------------------------------------------------------------- + * ADC + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_SENSORS_AST_ADC) || defined(CONFIG_SENSORS_AST_ADC_MODULE) || defined(CONFIG_SENSORS_AST1010_ADC) || defined(CONFIG_SENSORS_AST1010_ADC_MODULE) +static struct resource ast_adc_resources[] = { + [0] = { + .start = AST_ADC_BASE, + .end = AST_ADC_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_ADC, + .end = IRQ_ADC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_adc_device = { + .name = "ast_adc", + .id = 0, + .resource = ast_adc_resources, + .num_resources = ARRAY_SIZE(ast_adc_resources), +}; + +void __init ast_add_device_adc(void) +{ + //SCU ADC CTRL Reset + ast_scu_init_adc(); + + platform_device_register(&ast_adc_device); +} +#else +void __init ast_add_device_adc(void) {} +#endif diff --git a/arch/arm/plat-aspeed/dev-ci2c.c b/arch/arm/plat-aspeed/dev-ci2c.c new file mode 100644 index 000000000000..875639f601f7 --- /dev/null +++ b/arch/arm/plat-aspeed/dev-ci2c.c @@ -0,0 +1,521 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-ci2c.c +* Author : Ryan chen +* Description : ASPEED I2C Device +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/07/30 ryan chen create this file +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> +#include <linux/i2c.h> + +#include <asm/io.h> +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/ast_i2c.h> + +#include <plat/devs.h> +#include <plat/regs-iic.h> +#include <plat/ast-scu.h> +#include <plat/ast1070-scu.h> +/* -------------------------------------------------------------------- + * CI2C + * -------------------------------------------------------------------- */ +#if defined(CONFIG_I2C_AST1070) || defined(CONFIG_I2C_AST1070_MODULE) + +static struct ast_i2c_driver_data ast_ci2c_data = { + .bus_clk = 100000, //bus clock 100KHz + .master_dma = DMA_MODE, + .slave_dma = BYTE_MODE, +#ifdef CONFIG_AST_I2C_SLAVE_MODE + .slave_xfer = i2c_slave_xfer, + .slave_init = i2c_slave_init, +#endif +#ifdef CONFIG_AST_LPC_PLUS + //use lpc+ clock + .get_i2c_clock = ast_get_lhclk, +#else + .get_i2c_clock = ast_get_d2_pll_clk, +#endif +}; + +static u64 ast_i2c_dma_mask = 0xffffffffUL; +static struct resource ast_ci2c_dev1_resources[] = { + [0] = { + .start = AST_C0_I2C_BASE + AST_CI2C_DEVICE1, + .end = AST_C0_I2C_BASE + AST_CI2C_DEVICE1 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_C0_I2C, + .end = IRQ_C0_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_ci2c_dev1_device = { + .name = "ast-i2c", + .id = NUM_BUS + 0, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_ci2c_data, + }, + .resource = ast_ci2c_dev1_resources, + .num_resources = ARRAY_SIZE(ast_ci2c_dev1_resources), +}; + +static struct resource ast_ci2c_dev2_resources[] = { + [0] = { + .start = AST_C0_I2C_BASE + AST_CI2C_DEVICE2, + .end = AST_C0_I2C_BASE + AST_CI2C_DEVICE2 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_C0_I2C, + .end = IRQ_C0_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_ci2c_dev2_device = { + .name = "ast-i2c", + .id = NUM_BUS + 1, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_ci2c_data, + }, + .resource = ast_ci2c_dev2_resources, + .num_resources = ARRAY_SIZE(ast_ci2c_dev2_resources), +}; + +static struct resource ast_ci2c_dev3_resources[] = { + [0] = { + .start = AST_C0_I2C_BASE + AST_CI2C_DEVICE3, + .end = AST_C0_I2C_BASE + AST_CI2C_DEVICE3 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_C0_I2C, + .end = IRQ_C0_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_ci2c_dev3_device = { + .name = "ast-i2c", + .id = NUM_BUS + 2, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_ci2c_data, + }, + .resource = ast_ci2c_dev3_resources, + .num_resources = ARRAY_SIZE(ast_ci2c_dev3_resources), +}; + +static struct resource ast_ci2c_dev4_resources[] = { + [0] = { + .start = AST_C0_I2C_BASE + AST_CI2C_DEVICE4, + .end = AST_C0_I2C_BASE + AST_CI2C_DEVICE4 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_C0_I2C, + .end = IRQ_C0_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_ci2c_dev4_device = { + .name = "ast-i2c", + .id = NUM_BUS + 3, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_ci2c_data, + }, + .resource = ast_ci2c_dev4_resources, + .num_resources = ARRAY_SIZE(ast_ci2c_dev4_resources), +}; + +static struct resource ast_ci2c_dev5_resources[] = { + [0] = { + .start = AST_C0_I2C_BASE + AST_CI2C_DEVICE5, + .end = AST_C0_I2C_BASE + AST_CI2C_DEVICE5 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_C0_I2C, + .end = IRQ_C0_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_ci2c_dev5_device = { + .name = "ast-i2c", + .id = NUM_BUS + 4, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_ci2c_data, + }, + .resource = ast_ci2c_dev5_resources, + .num_resources = ARRAY_SIZE(ast_ci2c_dev5_resources), +}; + +static struct resource ast_ci2c_dev6_resources[] = { + [0] = { + .start = AST_C0_I2C_BASE + AST_CI2C_DEVICE6, + .end = AST_C0_I2C_BASE + AST_CI2C_DEVICE6 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_C0_I2C, + .end = IRQ_C0_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_ci2c_dev6_device = { + .name = "ast-i2c", + .id = NUM_BUS + 5, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_ci2c_data, + }, + .resource = ast_ci2c_dev6_resources, + .num_resources = ARRAY_SIZE(ast_ci2c_dev6_resources), +}; + +static struct resource ast_ci2c_dev7_resources[] = { + [0] = { + .start = AST_C0_I2C_BASE + AST_CI2C_DEVICE7, + .end = AST_C0_I2C_BASE + AST_CI2C_DEVICE7 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_C0_I2C, + .end = IRQ_C0_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_ci2c_dev7_device = { + .name = "ast-i2c", + .id = NUM_BUS + 6, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_ci2c_data, + }, + .resource = ast_ci2c_dev7_resources, + .num_resources = ARRAY_SIZE(ast_ci2c_dev7_resources), +}; + +static struct resource ast_ci2c_dev8_resources[] = { + [0] = { + .start = AST_C0_I2C_BASE + AST_CI2C_DEVICE8, + .end = AST_C0_I2C_BASE + AST_CI2C_DEVICE8 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_C0_I2C, + .end = IRQ_C0_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_ci2c_dev8_device = { + .name = "ast-i2c", + .id = NUM_BUS + 7, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_ci2c_data, + }, + .resource = ast_ci2c_dev8_resources, + .num_resources = ARRAY_SIZE(ast_ci2c_dev8_resources), +}; + +// +#if (CONFIG_AST1070_NR >= 2) + +static struct ast_i2c_driver_data ast_c1_i2c_data = { + .bus_clk = 100000, //bus clock 100KHz + .master_dma = DMA_MODE, + .slave_dma = BYTE_MODE, +#ifdef CONFIG_AST_I2C_SLAVE_MODE + .slave_xfer = i2c_slave_xfer, + .slave_init = i2c_slave_init, +#endif +#ifdef CONFIG_ARCH_AST2300 + .get_i2c_clock = ast_get_d2_pll_clk, +#else //AST2400 use lpc+ clock + .get_i2c_clock = ast_get_lhclk, +#endif +}; + +static struct resource ast_c1_i2c_dev1_resources[] = { + [0] = { + .start = AST_C1_I2C_BASE + AST_CI2C_DEVICE1, + .end = AST_C1_I2C_BASE + AST_CI2C_DEVICE1 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_C1_I2C, + .end = IRQ_C1_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_c1_i2c_dev1_device = { + .name = "ast-i2c", + .id = NUM_BUS + 8 + 0, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_c1_i2c_data, + }, + .resource = ast_c1_i2c_dev1_resources, + .num_resources = ARRAY_SIZE(ast_c1_i2c_dev1_resources), +}; + +static struct resource ast_c1_i2c_dev2_resources[] = { + [0] = { + .start = AST_C1_I2C_BASE + AST_CI2C_DEVICE2, + .end = AST_C1_I2C_BASE + AST_CI2C_DEVICE2 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_C1_I2C, + .end = IRQ_C1_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_c1_i2c_dev2_device = { + .name = "ast-i2c", + .id = NUM_BUS + 8 + 1, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_c1_i2c_data, + }, + .resource = ast_c1_i2c_dev2_resources, + .num_resources = ARRAY_SIZE(ast_c1_i2c_dev2_resources), +}; + +static struct resource ast_c1_i2c_dev3_resources[] = { + [0] = { + .start = AST_C1_I2C_BASE + AST_CI2C_DEVICE3, + .end = AST_C1_I2C_BASE + AST_CI2C_DEVICE3 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_C1_I2C, + .end = IRQ_C1_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_c1_i2c_dev3_device = { + .name = "ast-i2c", + .id = NUM_BUS + 8 + 2, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_c1_i2c_data, + }, + .resource = ast_c1_i2c_dev3_resources, + .num_resources = ARRAY_SIZE(ast_c1_i2c_dev3_resources), +}; + +static struct resource ast_c1_i2c_dev4_resources[] = { + [0] = { + .start = AST_C1_I2C_BASE + AST_CI2C_DEVICE4, + .end = AST_C1_I2C_BASE + AST_CI2C_DEVICE4 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_C1_I2C, + .end = IRQ_C1_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_c1_i2c_dev4_device = { + .name = "ast-i2c", + .id = NUM_BUS + 8 + 3, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_c1_i2c_data, + }, + .resource = ast_c1_i2c_dev4_resources, + .num_resources = ARRAY_SIZE(ast_c1_i2c_dev4_resources), +}; + +static struct resource ast_c1_i2c_dev5_resources[] = { + [0] = { + .start = AST_C1_I2C_BASE + AST_CI2C_DEVICE5, + .end = AST_C1_I2C_BASE + AST_CI2C_DEVICE5 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_C1_I2C, + .end = IRQ_C1_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_c1_i2c_dev5_device = { + .name = "ast-i2c", + .id = NUM_BUS + 8 + 4, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_c1_i2c_data, + }, + .resource = ast_c1_i2c_dev5_resources, + .num_resources = ARRAY_SIZE(ast_c1_i2c_dev5_resources), +}; + +static struct resource ast_c1_i2c_dev6_resources[] = { + [0] = { + .start = AST_C1_I2C_BASE + AST_CI2C_DEVICE6, + .end = AST_C1_I2C_BASE + AST_CI2C_DEVICE6 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_C1_I2C, + .end = IRQ_C1_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_c1_i2c_dev6_device = { + .name = "ast-i2c", + .id = NUM_BUS + 8 + 5, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_c1_i2c_data, + }, + .resource = ast_c1_i2c_dev6_resources, + .num_resources = ARRAY_SIZE(ast_c1_i2c_dev6_resources), +}; + +static struct resource ast_c1_i2c_dev7_resources[] = { + [0] = { + .start = AST_C1_I2C_BASE + AST_CI2C_DEVICE7, + .end = AST_C1_I2C_BASE + AST_CI2C_DEVICE7 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_C1_I2C, + .end = IRQ_C1_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_c1_i2c_dev7_device = { + .name = "ast-i2c", + .id = NUM_BUS + 8 + 6, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_c1_i2c_data, + }, + .resource = ast_c1_i2c_dev7_resources, + .num_resources = ARRAY_SIZE(ast_c1_i2c_dev7_resources), +}; + +static struct resource ast_c1_i2c_dev8_resources[] = { + [0] = { + .start = AST_C1_I2C_BASE + AST_CI2C_DEVICE8, + .end = AST_C1_I2C_BASE + AST_CI2C_DEVICE8 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_C1_I2C, + .end = IRQ_C1_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_c1_i2c_dev8_device = { + .name = "ast-i2c", + .id = NUM_BUS + 8 + 7, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_c1_i2c_data, + }, + .resource = ast_c1_i2c_dev8_resources, + .num_resources = ARRAY_SIZE(ast_c1_i2c_dev8_resources), +}; +#endif +// +/*-------------------------------------*/ +void __init ast_add_device_ci2c(void) +{ + ast1070_scu_init_i2c(0); + + ast_ci2c_data.reg_gr = IO_ADDRESS2(AST_C0_I2C_BASE); + if (!ast_ci2c_data.reg_gr) { + printk("ast_add_device_i2c ERROR \n"); + return; + } + platform_device_register(&ast_ci2c_dev1_device); + platform_device_register(&ast_ci2c_dev2_device); + platform_device_register(&ast_ci2c_dev3_device); + platform_device_register(&ast_ci2c_dev4_device); + platform_device_register(&ast_ci2c_dev5_device); + platform_device_register(&ast_ci2c_dev6_device); + platform_device_register(&ast_ci2c_dev7_device); + platform_device_register(&ast_ci2c_dev8_device); + + +#if (CONFIG_AST1070_NR >= 2) + + ast1070_scu_init_i2c(1); + + ast_c1_i2c_data.reg_gr = IO_ADDRESS2(AST_C1_I2C_BASE); + if (!ast_c1_i2c_data.reg_gr) { + printk("ast_add_device_i2c ERROR \n"); + return; + } + platform_device_register(&ast_c1_i2c_dev1_device); + platform_device_register(&ast_c1_i2c_dev2_device); + platform_device_register(&ast_c1_i2c_dev3_device); + platform_device_register(&ast_c1_i2c_dev4_device); + platform_device_register(&ast_c1_i2c_dev5_device); + platform_device_register(&ast_c1_i2c_dev6_device); + platform_device_register(&ast_c1_i2c_dev7_device); + platform_device_register(&ast_c1_i2c_dev8_device); +#endif + +} +#else +void __init ast_add_device_ci2c(void) {} +#endif diff --git a/arch/arm/plat-aspeed/dev-clpc.c b/arch/arm/plat-aspeed/dev-clpc.c new file mode 100644 index 000000000000..d9fde7a76aba --- /dev/null +++ b/arch/arm/plat-aspeed/dev-clpc.c @@ -0,0 +1,240 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-clpc.c +* Author : Ryan chen +* Description : ASPEED LPC Controller +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/11/29 ryan chen create this file +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/devs.h> +#include <plat/ast-scu.h> + + + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/devs.h> +#include <plat/ast-scu.h> + + +/* -------------------------------------------------------------------- + * LPC + * -------------------------------------------------------------------- */ +#if defined(CONFIG_CLPC) || defined(CONFIG_CLPC_MODULE) +static u64 aspeed_lpc_dma_mask = 0xffffffffUL; + +static struct resource aspeed_clpc0_resource[] = { + [0] = { + .start = AST_CLPC1_BASE, + .end = AST_CLPC1_BASE + SZ_4K, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_N1_KCS, + .end = IRQ_N1_KCS, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_N1_UART, + .end = IRQ_N1_UART, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_N1_MAILBOX, + .end = IRQ_N1_MAILBOX, + .flags = IORESOURCE_IRQ, + }, + [4] = { + .start = IRQ_N1_PORT80, + .end = IRQ_N1_PORT80, + .flags = IORESOURCE_IRQ, + }, + [4] = { + .start = IRQ_N1_RESET, + .end = IRQ_N1_RESET, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device aspeed_clpc0_device = { + .name = "aspeed_lpc", + .id = 0, + .dev = { + .dma_mask = &aspeed_lpc_dma_mask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = aspeed_clpc0_resource, + .num_resources = ARRAY_SIZE(aspeed_clpc0_resource), +}; + +static struct resource aspeed_clpc1_resource[] = { + [0] = { + .start = AST_CLPC2_BASE, + .end = AST_CLPC2_BASE + SZ_4K, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_N2_KCS, + .end = IRQ_N2_KCS, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_N2_UART, + .end = IRQ_N2_UART, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_N2_MAILBOX, + .end = IRQ_N2_MAILBOX, + .flags = IORESOURCE_IRQ, + }, + [4] = { + .start = IRQ_N2_PORT80, + .end = IRQ_N2_PORT80, + .flags = IORESOURCE_IRQ, + }, + [4] = { + .start = IRQ_N2_RESET, + .end = IRQ_N2_RESET, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device aspeed_clpc1_device = { + .name = "aspeed_lpc", + .id = 1, + .dev = { + .dma_mask = &aspeed_lpc_dma_mask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = aspeed_clpc1_resource, + .num_resources = ARRAY_SIZE(aspeed_clpc1_resource), +}; + +static struct resource aspeed_clpc2_resource[] = { + [0] = { + .start = AST_CLPC3_BASE, + .end = AST_CLPC3_BASE + SZ_4K, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_N3_KCS, + .end = IRQ_N3_KCS, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_N3_UART, + .end = IRQ_N3_UART, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_N3_MAILBOX, + .end = IRQ_N3_MAILBOX, + .flags = IORESOURCE_IRQ, + }, + [4] = { + .start = IRQ_N3_PORT80, + .end = IRQ_N3_PORT80, + .flags = IORESOURCE_IRQ, + }, + [4] = { + .start = IRQ_N3_RESET, + .end = IRQ_N3_RESET, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device aspeed_clpc2_device = { + .name = "aspeed_lpc", + .id = 2, + .dev = { + .dma_mask = &aspeed_lpc_dma_mask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = aspeed_clpc2_resource, + .num_resources = ARRAY_SIZE(aspeed_clpc2_resource), +}; + +static struct resource aspeed_clpc3_resource[] = { + [0] = { + .start = AST_CLPC4_BASE, + .end = AST_CLPC4_BASE + SZ_4K, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_N4_KCS, + .end = IRQ_N4_KCS, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_N4_UART, + .end = IRQ_N4_UART, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_N4_MAILBOX, + .end = IRQ_N4_MAILBOX, + .flags = IORESOURCE_IRQ, + }, + [4] = { + .start = IRQ_N4_PORT80, + .end = IRQ_N4_PORT80, + .flags = IORESOURCE_IRQ, + }, + [4] = { + .start = IRQ_N4_RESET, + .end = IRQ_N4_RESET, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device aspeed_clpc3_device = { + .name = "aspeed_lpc", + .id = 3, + .dev = { + .dma_mask = &aspeed_lpc_dma_mask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = aspeed_clpc3_resource, + .num_resources = ARRAY_SIZE(aspeed_clpc3_resource), +}; + +void __init aspeed_add_device_clpc(void) +{ +// it should enable at u-boot +// aspeed_scu_init_lpc(); + + platform_device_register(&aspeed_clpc0_device); + platform_device_register(&aspeed_clpc1_device); + platform_device_register(&aspeed_clpc2_device); + platform_device_register(&aspeed_clpc3_device); +} +#else +void __init aspeed_add_device_clpc(void) {} +#endif + diff --git a/arch/arm/plat-aspeed/dev-cuart.c b/arch/arm/plat-aspeed/dev-cuart.c new file mode 100644 index 000000000000..8731f7c27e33 --- /dev/null +++ b/arch/arm/plat-aspeed/dev-cuart.c @@ -0,0 +1,197 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-cuart.c +* Author : Ryan chen +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/09/15 ryan chen create this file +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> +#include <linux/serial.h> +#include <linux/tty.h> +#include <linux/serial_8250.h> + +#include <mach/irqs.h> +#include <mach/platform.h> +#include <mach/hardware.h> +#include <mach/ast-uart-dma.h> + +#include <plat/ast1070-devs.h> +#include <plat/ast1070-scu.h> + +/* -------------------------------------------------------------------- + * UART + * -------------------------------------------------------------------- */ +#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_ARCH_AST1070) +static struct ast_uart_dma_data c0_uart0_dma_data = { + .chip_no = 0, + .dma_ch = 0, +}; + +static struct ast_uart_dma_data c0_uart1_dma_data = { + .chip_no = 0, + .dma_ch = 1, +}; + +static struct ast_uart_dma_data c0_uart2_dma_data = { + .chip_no = 0, + .dma_ch = 2, +}; + +static struct ast_uart_dma_data c0_uart3_dma_data = { + .chip_no = 0, + .dma_ch = 3, +}; + +#if (CONFIG_AST1070_NR >=2) +static struct ast_uart_dma_data c1_uart0_dma_data = { + .chip_no = 1, + .dma_ch = 0, +}; + +static struct ast_uart_dma_data c1_uart1_dma_data = { + .chip_no = 1, + .dma_ch = 1, +}; + +static struct ast_uart_dma_data c1_uart2_dma_data = { + .chip_no = 1, + .dma_ch = 2, +}; + +static struct ast_uart_dma_data c1_uart3_dma_data = { + .chip_no = 1, + .dma_ch = 3, +}; +#endif + +static struct plat_serial8250_port ast1070_c_uart_data[] = { + { + .mapbase = AST_C0_UART0_BASE, + .membase = (char*)(IO_ADDRESS2(AST_C0_UART0_BASE)), + .irq = IRQ_C0_N1_UART, + .uartclk = (24*1000000L), + .regshift = 2, + .iotype = UPIO_MEM, + .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .private_data = &c0_uart0_dma_data, + }, + { + .mapbase = AST_C0_UART1_BASE, + .membase = (char*)(IO_ADDRESS2(AST_C0_UART1_BASE)), + .irq = IRQ_C0_N2_UART, + .uartclk = (24*1000000L), + .regshift = 2, + .iotype = UPIO_MEM, + .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .private_data = &c0_uart1_dma_data, + }, + { + .mapbase = AST_C0_UART2_BASE, + .membase = (char*)(IO_ADDRESS2(AST_C0_UART2_BASE)), + .irq = IRQ_C0_N3_UART, + .uartclk = (24*1000000L), + .regshift = 2, + .iotype = UPIO_MEM, + .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .private_data = &c0_uart2_dma_data, + }, + { + .mapbase = AST_C0_UART3_BASE, + .membase = (char*)(IO_ADDRESS2(AST_C0_UART3_BASE)), + .irq = IRQ_C0_N4_UART, + .uartclk = (24*1000000L), + .regshift = 2, + .iotype = UPIO_MEM, + .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .private_data = &c0_uart3_dma_data, + }, +#if (CONFIG_AST1070_NR >=2) + { + .mapbase = AST_C1_UART0_BASE, + .membase = (char*)(IO_ADDRESS2(AST_C1_UART0_BASE)), + .irq = IRQ_C1_N1_UART, + .uartclk = (24*1000000L), + .regshift = 2, + .iotype = UPIO_MEM, + .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .private_data = &c1_uart0_dma_data, + }, + { + .mapbase = AST_C1_UART1_BASE, + .membase = (char*)(IO_ADDRESS2(AST_C1_UART1_BASE)), + .irq = IRQ_C1_N2_UART, + .uartclk = (24*1000000L), + .regshift = 2, + .iotype = UPIO_MEM, + .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .private_data = &c1_uart1_dma_data, + }, + { + .mapbase = AST_C1_UART2_BASE, + .membase = (char*)(IO_ADDRESS2(AST_C1_UART2_BASE)), + .irq = IRQ_C1_N3_UART, + .uartclk = (24*1000000L), + .regshift = 2, + .iotype = UPIO_MEM, + .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .private_data = &c1_uart2_dma_data, + }, + { + .mapbase = AST_C1_UART3_BASE, + .membase = (char*)(IO_ADDRESS2(AST_C1_UART3_BASE)), + .irq = IRQ_C1_N4_UART, + .uartclk = (24*1000000L), + .regshift = 2, + .iotype = UPIO_MEM, + .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .private_data = &c1_uart3_dma_data, + }, +#endif + { }, +}; + +struct platform_device ast1070_c_uart_device = { +#ifdef CONFIG_SERIAL_AST_DMA_UART + .name = "ast-uart-dma", +#else + .name = "serial8250", +#endif + .id = PLAT8250_DEV_PLATFORM1, + .dev = { + .platform_data = ast1070_c_uart_data, + }, +}; + +void __init ast_add_device_cuart(void) +{ + int i;//j; + for(i=0;i<CONFIG_AST1070_NR;i++) { + //reset 4 UART + ast1070_scu_init_uart(i); + //Please don't enable : Feature remove +// for(j=0;j<4;j++) +// ast1070_multi_func_uart(i, j); + } + + platform_device_register(&ast1070_c_uart_device); +} +#else +void __init ast_add_device_cuart(void) {} +#endif diff --git a/arch/arm/plat-aspeed/dev-ehci.c b/arch/arm/plat-aspeed/dev-ehci.c new file mode 100644 index 000000000000..8c34a6335142 --- /dev/null +++ b/arch/arm/plat-aspeed/dev-ehci.c @@ -0,0 +1,73 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-ehci.c +* Author : Ryan chen +* Description : ASPEED EHCI Device +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/07/30 ryan chen create this file +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/devs.h> +#include <plat/ast-scu.h> + + +/* -------------------------------------------------------------------- + * EHCI + * -------------------------------------------------------------------- */ +#if defined(CONFIG_USB_EHCI_AST) || defined(CONFIG_USB_EHCI_AST_MODULE) +static struct resource ast_echi_resource[] = { + [0] = { + .start = AST_EHCI_BASE, + .end = AST_EHCI_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_EHCI, + .end = IRQ_EHCI, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ast_ehci_dma_mask = 0xffffffffUL; + +static struct platform_device ast_ehci_device = { + .name = "ehci-ast", + .id = 0, + .dev = { + .dma_mask = &ast_ehci_dma_mask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = ast_echi_resource, + .num_resources = ARRAY_SIZE(ast_echi_resource), +}; + +void __init ast_add_device_ehci(void) +{ + ast_scu_multi_func_usb20_host_hub(1); + ast_scu_init_usb20(); + + platform_device_register(&ast_ehci_device); +} +#else +void __init ast_add_device_ehci(void) {} +#endif diff --git a/arch/arm/plat-aspeed/dev-eth.c b/arch/arm/plat-aspeed/dev-eth.c new file mode 100644 index 000000000000..5d33e3364810 --- /dev/null +++ b/arch/arm/plat-aspeed/dev-eth.c @@ -0,0 +1,201 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-eth.c +* Author : Ryan Chen +* Description : Aspeed Ethernet Device +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/08/24 Ryan Chen initial +* +********************************************************************************/ +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/platform.h> +#include <mach/ftgmac100_drv.h> + +#include <plat/devs.h> +#include <plat/ast-scu.h> + +/* -------------------------------------------------------------------- + * Ethernet + * -------------------------------------------------------------------- */ +#if defined(CONFIG_ASPEEDMAC) || defined(CONFIG_ASPEEDMAC_MODULE) +#ifdef AST_MAC0_BASE +static struct ftgmac100_eth_data ast_eth0_data = { + .dev_addr = { 0x00, 0x84, 0x14, 0xA0, 0xB0, 0x22}, + .phy_id = 1, +}; + +static u64 ast_eth_dmamask = 0xffffffffUL; +static struct resource ast_mac0_resources[] = { + [0] = { + .start = AST_MAC0_BASE, + .end = AST_MAC0_BASE + SZ_128K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_MAC0, + .end = IRQ_MAC0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ast_eth0_device = { + .name = "ast_gmac", + .id = 0, + .dev = { + .dma_mask = &ast_eth_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_eth0_data, + }, + .resource = ast_mac0_resources, + .num_resources = ARRAY_SIZE(ast_mac0_resources), +}; +#endif +#ifdef AST_MAC1_BASE +static struct ftgmac100_eth_data ast_eth1_data = { + .dev_addr = { 0x00, 0x84, 0x14, 0xA0, 0xB0, 0x23}, + .phy_id = 1, +}; + +static struct resource ast_mac1_resources[] = { + [0] = { + .start = AST_MAC1_BASE, + .end = AST_MAC1_BASE + SZ_128K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_MAC1, + .end = IRQ_MAC1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ast_eth1_device = { + .name = "ast_gmac", + .id = 1, + .dev = { + .dma_mask = &ast_eth_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_eth1_data, + }, + .resource = ast_mac1_resources, + .num_resources = ARRAY_SIZE(ast_mac1_resources), +}; +#endif + +/* + * MAC1 always has MII MDC+MDIO pins to access PHY registers. We assume MAC1 + * always has a PHY chip, if MAC1 is enabled. + * U-Boot can enable MAC2 MDC+MDIO pins for a 2nd PHY, or MAC2 might be + * disabled (only one port), or it's sideband-RMII which has no PHY chip. + * + * Return miiPhyId==0 if the MAC cannot be accessed. + * Return miiPhyId==1 if the MAC registers are OK but it cannot carry traffic. + * Return miiPhyId==2 if the MAC can send/receive but it has no PHY chip. + * Else return the PHY 22-bit vendor ID, 6-bit model and 4-bit revision. + */ + +void __init ast_add_device_gmac(void) +{ + + u8 phy_mode,phy_inter; + u32 isRevA0; + u32 rev_id; + + rev_id = ast_scu_revision_id() & 0xff; + + + if (rev_id >= 0x08 && rev_id <= 0x0f) { + // AST2100 FPGA board: up to 10 means rev.A0, 11 means rev.A1 + isRevA0 = (rev_id < 11); + } else { + // Real silicon: rev.A0 has 0x00 in bits[7:0]. rev A2 = 0x02 in bits[7:0] + isRevA0 = 0; //((regVal & 0x00ff) == 0x00); +// out->isRevA2 = 1; //((regVal & 0x00ff) == 0x02); + } + + ast_eth0_data.DF_support = !isRevA0; + + ast_scu_init_eth(0); + ast_scu_multi_func_eth(0); + + + /* + * D[15:11] in 0x1E6E2040 is NCSI scratch from U-Boot. D[15:14] = MAC1, D[13:12] = MAC2 + * The meanings of the 2 bits are: + * 00(0): Dedicated PHY + * 01(1): ASPEED's EVA + INTEL's NC-SI PHY chip EVA + * 10(2): ASPEED's MAC is connected to NC-SI PHY chip directly + * 11: Reserved + */ + + phy_mode = ast_scu_get_phy_config(0); + switch(phy_mode) { + case 0: + ast_eth0_data.INTEL_NCSI_EVA_support = 0; + ast_eth0_data.NCSI_support = 0; + break; + case 1: + ast_eth0_data.NCSI_support = 1; + break; + case 2: + ast_eth0_data.INTEL_NCSI_EVA_support = 1; + break; + + } + + phy_inter = ast_scu_get_phy_interface(0); + + // We assume the Clock Stop register does not disable the MAC1 or MAC2 clock + // unless Reset Control also holds the MAC in reset. + + + platform_device_register(&ast_eth0_device); + +#ifdef AST_MAC1_BASE + ast_scu_init_eth(1); + ast_scu_multi_func_eth(1); + + ast_eth1_data.DF_support = !isRevA0; + + phy_mode = ast_scu_get_phy_config(1); + switch(phy_mode) { + case 0: + ast_eth1_data.INTEL_NCSI_EVA_support = 0; + ast_eth1_data.NCSI_support = 0; + break; + case 1: + ast_eth1_data.NCSI_support = 1; + break; + case 2: + ast_eth1_data.INTEL_NCSI_EVA_support = 1; + break; + + } + phy_inter = ast_scu_get_phy_interface(1); + + platform_device_register(&ast_eth1_device); + +#endif + +} +#else +void __init ast_add_device_gmac(void) {} +#endif + diff --git a/arch/arm/plat-aspeed/dev-fb.c b/arch/arm/plat-aspeed/dev-fb.c new file mode 100644 index 000000000000..3673160db44e --- /dev/null +++ b/arch/arm/plat-aspeed/dev-fb.c @@ -0,0 +1,80 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-fb.c +* Author : Ryan Chen +* Description : ASPEED Frambuffer Driver +* +* Copyright (C) ASPEED Tech. Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/12/15 Ryan Chen initial +* +********************************************************************************/ +#include <linux/kernel.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/platform.h> + +#include <plat/devs.h> +#include <plat/ast-scu.h> + +#include <mach/ast_lcd.h> + +/* -------------------------------------------------------------------- + * ASPEED FB + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_FB_AST) || defined(CONFIG_FB_AST_MODULE) +static struct ast_fb_plat_data fb_plat_data = { + .get_clk = ast_get_d2_pll_clk, +}; + + +static struct resource ast_fb_resources[] = { + [0] = { + .start = AST_GRAPHIC_BASE, + .end = AST_GRAPHIC_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_CRT, + .end = IRQ_CRT, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ast_device_fb_dmamask = 0xffffffffUL; +struct platform_device ast_fb_device = { + .name = "ast-fb", + .id = 0, + .dev = { + .dma_mask = &ast_device_fb_dmamask, + .coherent_dma_mask = 0xffffffffUL, + .platform_data= &fb_plat_data, + }, + .resource = ast_fb_resources, + .num_resources = ARRAY_SIZE(ast_fb_resources), +}; + +void __init ast_add_device_fb(void) +{ + ast_scu_multi_func_crt(); + + ast_scu_init_crt(); + + platform_device_register(&ast_fb_device); +} +#else +void __init ast_add_device_fb(void) {} +#endif diff --git a/arch/arm/plat-aspeed/dev-gpio.c b/arch/arm/plat-aspeed/dev-gpio.c new file mode 100644 index 000000000000..356fd5396a0a --- /dev/null +++ b/arch/arm/plat-aspeed/dev-gpio.c @@ -0,0 +1,68 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-rtc.c +* Author : Ryan chen +* Description : Socle Real Time Clock Device (RTC) +* +* Copyright (C) Socle Tech. Corp. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2010/09/15 ryan chen create this file +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/regs-gpio.h> + +#include <plat/devs.h> + +/* -------------------------------------------------------------------- + * ASPEED GPIO + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_GPIO_AST) || defined(CONFIG_GPIO_AST_MODULE) +static struct resource ast_gpio_resource[] = { + [0] = { + .start = AST_GPIO_BASE, + .end = AST_GPIO_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_GPIO, + .end = IRQ_GPIO, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ast_device_gpio = { + .name = "ast-gpio", + .id = 0, + .num_resources = ARRAY_SIZE(ast_gpio_resource), + .resource = ast_gpio_resource, +}; + +extern void __init +ast_add_device_gpio(void) +{ + platform_device_register(&ast_device_gpio); +} + +#else +extern void __init ast_add_device_gpio(void) {} +#endif + diff --git a/arch/arm/plat-aspeed/dev-i2c.c b/arch/arm/plat-aspeed/dev-i2c.c new file mode 100644 index 000000000000..47cd15249b10 --- /dev/null +++ b/arch/arm/plat-aspeed/dev-i2c.c @@ -0,0 +1,669 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-i2c.c +* Author : Ryan chen +* Description : ASPEED I2C Device +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/07/30 ryan chen create this file +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> +#include <linux/i2c.h> +#include <asm/io.h> +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/ast_i2c.h> +#include <plat/devs.h> +#include <plat/regs-iic.h> +#include <plat/ast-scu.h> + +/* -------------------------------------------------------------------- + * I2C + * -------------------------------------------------------------------- */ +#ifdef AST_I2C_DEBUG +#define I2CDBUG(fmt, args...) printk("%s() " fmt, __FUNCTION__, ## args) +#else +#define I2CDBUG(fmt, args...) +#endif + +#if defined(CONFIG_I2C_AST) || defined(CONFIG_I2C_AST_MODULE) + +#if defined (CONFIG_ARCH_AST2400) +#define I2C_PAGE_SIZE 8 +struct buf_page page_info[I2C_PAGE_SIZE] = +{ + [0] = { + .flag = 0, + .page_no = 0, + .page_size = 256, + .page_addr_point = 0, + }, + [1] = { + .flag = 0, + .page_no = 1, + .page_size = 256, + .page_addr_point = 0, + }, + [2] = { + .flag = 0, + .page_no = 2, + .page_size = 256, + .page_addr_point = 0, + }, + [3] = { + .flag = 0, + .page_no = 3, + .page_size = 256, + .page_addr_point = 0, + }, + [4] = { + .flag = 0, + .page_no = 4, + .page_size = 256, + .page_addr_point = 0, + }, + [5] = { + .flag = 0, + .page_no = 5, + .page_size = 256, + .page_addr_point = 0, + }, + [6] = { + .flag = 0, + .page_no = 6, + .page_size = 256, + .page_addr_point = 0, + }, + [7] = { + .flag = 0, + .page_no = 7, + .page_size = 256, + .page_addr_point = 0, + }, +}; + +static void pool_buff_page_init(u32 buf_pool_addr) +{ + u32 offset; + int i ,j; + + for(i=0;i<I2C_PAGE_SIZE;i++) { + offset = 0; + for(j=0;j<i;j++) + offset += page_info[i].page_size; + + page_info[i].page_addr = buf_pool_addr + offset; +// I2CDBUG( "page[%d],addr :%x \n", i, page_info[i].page_addr); + } + +} + +static u8 request_pool_buff_page(struct buf_page **req_page) +{ + int i; + //TODO + spinlock_t lock; + spin_lock(&lock); + for(i=0;i<I2C_PAGE_SIZE;i++) { + if(page_info[i].flag ==0) { + page_info[i].flag = 1; + *req_page = &page_info[i]; +// I2CDBUG( "request page addr %x \n", page_info[i].page_addr); + break; + } + } + spin_unlock(&lock); + return 0; +} + +static void free_pool_buff_page(struct buf_page *req_page) +{ + req_page->flag = 0; +// I2CDBUG( "free page addr %x \n", req_page->page_addr); + req_page = NULL; +} + +#elif defined (CONFIG_ARCH_AST2300) +#define I2C_PAGE_SIZE 5 + +struct buf_page page_info[I2C_PAGE_SIZE] = +{ + [0] = { + .flag = 0, + .page_size = 128, + }, + [1] = { + .flag = 0, + .page_size = 32, + }, + [2] = { + .flag = 0, + .page_size = 32, + }, + [3] = { + .flag = 0, + .page_size = 32, + }, + [4] = { + .flag = 0, + .page_size = 32, + }, +}; + +static void pool_buff_page_init(u32 buf_pool_addr) +{ + + u32 offset; + int i ,j; + + for(i=0;i<I2C_PAGE_SIZE;i++) { + offset = 0; + for(j=0;j<i;j++) + offset += page_info[i].page_size; + + page_info[i].page_addr = buf_pool_addr + offset; + page_info[i].page_addr_point = page_info[i].page_addr/4; +// printk("page[%d],addr :%x , point : %d\n", i, page_info[i].page_addr, page_info[i].page_addr_point); + } +} + +static u8 request_pool_buff_page(struct buf_page **req_page) +{ + int i; + //TODO + spinlock_t lock; + spin_lock(&lock); + for(i=0;i<I2C_PAGE_SIZE;i++) { + if(page_info[i].flag ==0) { + page_info[i].flag = 1; + *req_page = &page_info[i]; + spin_unlock(&lock); + return 1; + } + } + spin_unlock(&lock); + return 0; + +} + +//TODO check free ? +static void free_pool_buff_page(struct buf_page *req_page) +{ + req_page->flag = 0; + req_page = NULL; +} + +#else +//DO nothing +static void pool_buff_page_init(void) {} +static u8 request_pool_buff_page(struct buf_page **req_page) {return 0;} +static void free_pool_buff_page(struct buf_page *req_page) {} +#endif + +static struct ast_i2c_driver_data ast_i2c_data = { + .bus_clk = 100000, //bus clock 100KHz + .master_dma = BUFF_MODE, + .slave_dma = BYTE_MODE, + .request_pool_buff_page = request_pool_buff_page, + .free_pool_buff_page = free_pool_buff_page, +#ifdef CONFIG_AST_I2C_SLAVE_MODE + .slave_xfer = i2c_slave_xfer, + .slave_init = i2c_slave_init, +#endif + .get_i2c_clock = ast_get_pclk, +}; + +static u64 ast_i2c_dma_mask = 0xffffffffUL; +static struct resource ast_i2c_dev1_resources[] = { + [0] = { + .start = AST_I2C_BASE + AST_I2C_DEVICE1, + .end = AST_I2C_BASE + AST_I2C_DEVICE1 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C, + .end = IRQ_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_i2c_dev1_device = { + .name = "ast-i2c", + .id = 0, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_i2c_data, + }, + .resource = ast_i2c_dev1_resources, + .num_resources = ARRAY_SIZE(ast_i2c_dev1_resources), +}; + +static struct resource ast_i2c_dev2_resources[] = { + [0] = { + .start = AST_I2C_BASE + AST_I2C_DEVICE2, + .end = AST_I2C_BASE + AST_I2C_DEVICE2 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C, + .end = IRQ_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_i2c_dev2_device = { + .name = "ast-i2c", + .id = 1, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_i2c_data, + }, + .resource = ast_i2c_dev2_resources, + .num_resources = ARRAY_SIZE(ast_i2c_dev2_resources), +}; + +static struct resource ast_i2c_dev3_resources[] = { + [0] = { + .start = AST_I2C_BASE + AST_I2C_DEVICE3, + .end = AST_I2C_BASE + AST_I2C_DEVICE3 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C, + .end = IRQ_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_i2c_dev3_device = { + .name = "ast-i2c", + .id = 2, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_i2c_data, + }, + .resource = ast_i2c_dev3_resources, + .num_resources = ARRAY_SIZE(ast_i2c_dev3_resources), +}; + +static struct resource ast_i2c_dev4_resources[] = { + [0] = { + .start = AST_I2C_BASE + AST_I2C_DEVICE4, + .end = AST_I2C_BASE + AST_I2C_DEVICE4 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C, + .end = IRQ_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_i2c_dev4_device = { + .name = "ast-i2c", + .id = 3, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_i2c_data, + }, + .resource = ast_i2c_dev4_resources, + .num_resources = ARRAY_SIZE(ast_i2c_dev4_resources), +}; + +static struct resource ast_i2c_dev5_resources[] = { + [0] = { + .start = AST_I2C_BASE + AST_I2C_DEVICE5, + .end = AST_I2C_BASE + AST_I2C_DEVICE5 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C, + .end = IRQ_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_i2c_dev5_device = { + .name = "ast-i2c", + .id = 4, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_i2c_data, + }, + .resource = ast_i2c_dev5_resources, + .num_resources = ARRAY_SIZE(ast_i2c_dev5_resources), +}; + +static struct resource ast_i2c_dev6_resources[] = { + [0] = { + .start = AST_I2C_BASE + AST_I2C_DEVICE6, + .end = AST_I2C_BASE + AST_I2C_DEVICE6 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C, + .end = IRQ_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_i2c_dev6_device = { + .name = "ast-i2c", + .id = 5, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_i2c_data, + }, + .resource = ast_i2c_dev6_resources, + .num_resources = ARRAY_SIZE(ast_i2c_dev6_resources), +}; + +static struct resource ast_i2c_dev7_resources[] = { + [0] = { + .start = AST_I2C_BASE + AST_I2C_DEVICE7, + .end = AST_I2C_BASE + AST_I2C_DEVICE7 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C, + .end = IRQ_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_i2c_dev7_device = { + .name = "ast-i2c", + .id = 6, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_i2c_data, + }, + .resource = ast_i2c_dev7_resources, + .num_resources = ARRAY_SIZE(ast_i2c_dev7_resources), +}; + +static struct resource ast_i2c_dev8_resources[] = { + [0] = { + .start = AST_I2C_BASE + AST_I2C_DEVICE8, + .end = AST_I2C_BASE + AST_I2C_DEVICE8 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C, + .end = IRQ_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_i2c_dev8_device = { + .name = "ast-i2c", + .id = 7, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_i2c_data, + }, + .resource = ast_i2c_dev8_resources, + .num_resources = ARRAY_SIZE(ast_i2c_dev8_resources), +}; + +static struct resource ast_i2c_dev9_resources[] = { + [0] = { + .start = AST_I2C_BASE + AST_I2C_DEVICE9, + .end = AST_I2C_BASE + AST_I2C_DEVICE9 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C, + .end = IRQ_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_i2c_dev9_device = { + .name = "ast-i2c", + .id = 8, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_i2c_data, + }, + .resource = ast_i2c_dev9_resources, + .num_resources = ARRAY_SIZE(ast_i2c_dev9_resources), +}; + +#if defined(CONFIG_ARCH_AST2400) +static struct resource ast_i2c_dev10_resources[] = { + [0] = { + .start = AST_I2C_BASE + AST_I2C_DEVICE10, + .end = AST_I2C_BASE + AST_I2C_DEVICE10 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C, + .end = IRQ_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_i2c_dev10_device = { + .name = "ast-i2c", + .id = 9, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_i2c_data, + }, + .resource = ast_i2c_dev10_resources, + .num_resources = ARRAY_SIZE(ast_i2c_dev10_resources), +}; + +static struct resource ast_i2c_dev11_resources[] = { + [0] = { + .start = AST_I2C_BASE + AST_I2C_DEVICE11, + .end = AST_I2C_BASE + AST_I2C_DEVICE11 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C, + .end = IRQ_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_i2c_dev11_device = { + .name = "ast-i2c", + .id = 10, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_i2c_data, + }, + .resource = ast_i2c_dev11_resources, + .num_resources = ARRAY_SIZE(ast_i2c_dev11_resources), +}; + +static struct resource ast_i2c_dev12_resources[] = { + [0] = { + .start = AST_I2C_BASE + AST_I2C_DEVICE12, + .end = AST_I2C_BASE + AST_I2C_DEVICE12 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C, + .end = IRQ_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_i2c_dev12_device = { + .name = "ast-i2c", + .id = 11, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_i2c_data, + }, + .resource = ast_i2c_dev12_resources, + .num_resources = ARRAY_SIZE(ast_i2c_dev12_resources), +}; + +static struct resource ast_i2c_dev13_resources[] = { + [0] = { + .start = AST_I2C_BASE + AST_I2C_DEVICE13, + .end = AST_I2C_BASE + AST_I2C_DEVICE13 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C, + .end = IRQ_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_i2c_dev13_device = { + .name = "ast-i2c", + .id = 12, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_i2c_data, + }, + .resource = ast_i2c_dev13_resources, + .num_resources = ARRAY_SIZE(ast_i2c_dev13_resources), +}; + +static struct resource ast_i2c_dev14_resources[] = { + [0] = { + .start = AST_I2C_BASE + AST_I2C_DEVICE14, + .end = AST_I2C_BASE + AST_I2C_DEVICE14 + 4*SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C, + .end = IRQ_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_i2c_dev14_device = { + .name = "ast-i2c", + .id = 13, + .dev = { + .dma_mask = &ast_i2c_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_i2c_data, + }, + .resource = ast_i2c_dev14_resources, + .num_resources = ARRAY_SIZE(ast_i2c_dev14_resources), +}; +#endif + +/*--------- I2C Board devices ------------*/ +//ASPEED AST2300 EVB I2C Device +#if defined(CONFIG_ARCH_AST2300) || defined(CONFIG_ARCH_AST2400) +//Under I2C Dev 1 +static struct i2c_board_info __initdata ast_i2c_board_info_1[] = { + { + I2C_BOARD_INFO("cat9883", 0x4d), + } +}; + +//Under I2C Dev 4 +static struct i2c_board_info __initdata ast_i2c_board_info_4[] = { + { + I2C_BOARD_INFO("24c128", 0x50), + + + } +}; +//Under I2C Dev 8 +static struct i2c_board_info __initdata ast_i2c_board_info_8[] = { + { + I2C_BOARD_INFO("lm75b", 0x4a), + } +}; + +#endif + +/*-------------------------------------*/ +void __init ast_add_device_i2c(void) +{ + //I2C Multi-Pin + ast_scu_multi_func_i2c(); + + //SCU I2C Reset + ast_scu_init_i2c(); + + ast_i2c_data.reg_gr = ioremap(AST_I2C_BASE, 4*SZ_16); + if (!ast_i2c_data.reg_gr) { + printk("ast_add_device_i2c ERROR \n"); + return; + } + +#if defined (CONFIG_ARCH_AST2400) + ast_i2c_data.buf_pool= ioremap(AST_I2C_BASE+0x800, 2048); + if (!ast_i2c_data.buf_pool) { + printk("ast_add_device_i2c ERROR \n"); + return; + } +#else + ast_i2c_data.buf_pool = ioremap(AST_I2C_BASE+0x200, 256); + if (!ast_i2c_data.buf_pool) { + printk("ast_add_device_i2c ERROR \n"); + return; + } +#endif + //TODO + pool_buff_page_init(ast_i2c_data.buf_pool); + platform_device_register(&ast_i2c_dev1_device); + i2c_register_board_info(0, ast_i2c_board_info_1, ARRAY_SIZE(ast_i2c_board_info_1)); + platform_device_register(&ast_i2c_dev2_device); + platform_device_register(&ast_i2c_dev3_device); + platform_device_register(&ast_i2c_dev4_device); + i2c_register_board_info(3, ast_i2c_board_info_4, ARRAY_SIZE(ast_i2c_board_info_4)); + platform_device_register(&ast_i2c_dev5_device); + platform_device_register(&ast_i2c_dev6_device); + platform_device_register(&ast_i2c_dev7_device); + platform_device_register(&ast_i2c_dev8_device); + i2c_register_board_info(7, ast_i2c_board_info_8, ARRAY_SIZE(ast_i2c_board_info_8)); + platform_device_register(&ast_i2c_dev9_device); + +#if defined(CONFIG_ARCH_AST2400) + platform_device_register(&ast_i2c_dev10_device); +#if defined(CONFIG_MMC_AST) + //Due to share pin with SD +#else + platform_device_register(&ast_i2c_dev11_device); + platform_device_register(&ast_i2c_dev12_device); + platform_device_register(&ast_i2c_dev13_device); + platform_device_register(&ast_i2c_dev14_device); +#endif +#endif +} +#else +void __init ast_add_device_i2c(void) {} +#endif diff --git a/arch/arm/plat-aspeed/dev-kcs.c b/arch/arm/plat-aspeed/dev-kcs.c new file mode 100644 index 000000000000..726dbf7551fc --- /dev/null +++ b/arch/arm/plat-aspeed/dev-kcs.c @@ -0,0 +1,129 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-kcs.c +* Author : Ryan chen +* Description : ASPEED KCS +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/11/29 ryan chen create this file +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/devs.h> +#include <plat/ast-scu.h> + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/devs.h> +#include <plat/ast-scu.h> + +/* -------------------------------------------------------------------- + * KCS + * -------------------------------------------------------------------- */ +#if defined(CONFIG_AST_KCS) || defined(CONFIG_AST_KCS_MODULE) +static u64 ast_kcs_dma_mask = 0xffffffffUL; + +static struct resource ast_kcs0_resource[] = { + [0] = { + .start = AST_LPC_BASE, + .end = AST_LPC_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_LPC, + .end = IRQ_LPC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ast_kcs0_device = { + .name = "ast-kcs", + .id = 0, + .dev = { + .dma_mask = &ast_kcs_dma_mask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = ast_kcs0_resource, + .num_resources = ARRAY_SIZE(ast_kcs0_resource), +}; + +static struct resource ast_kcs1_resource[] = { + [0] = { + .start = AST_LPC_BASE, + .end = AST_LPC_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_LPC, + .end = IRQ_LPC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ast_kcs1_device = { + .name = "ast-kcs", + .id = 1, + .dev = { + .dma_mask = &ast_kcs_dma_mask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = ast_kcs1_resource, + .num_resources = ARRAY_SIZE(ast_kcs1_resource), +}; + +static struct resource ast_kcs2_resource[] = { + [0] = { + .start = AST_LPC_BASE, + .end = AST_LPC_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_LPC, + .end = IRQ_LPC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ast_kcs2_device = { + .name = "ast-kcs", + .id = 2, + .dev = { + .dma_mask = &ast_kcs_dma_mask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = ast_kcs2_resource, + .num_resources = ARRAY_SIZE(ast_kcs2_resource), +}; + +void __init ast_add_device_kcs(void) +{ +// platform_device_register(&ast_kcs0_device); +// platform_device_register(&ast_kcs1_device); + platform_device_register(&ast_kcs2_device); +} +#else +void __init ast_add_device_kcs(void) {} +#endif + diff --git a/arch/arm/plat-aspeed/dev-lpc.c b/arch/arm/plat-aspeed/dev-lpc.c new file mode 100644 index 000000000000..50eb4e6b9a03 --- /dev/null +++ b/arch/arm/plat-aspeed/dev-lpc.c @@ -0,0 +1,105 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-lpc.c +* Author : Ryan chen +* Description : ASPEED LPC Controller +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/11/29 ryan chen create this file +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/devs.h> +#include <plat/ast-scu.h> + + + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/devs.h> +#include <plat/ast-scu.h> + + +/* -------------------------------------------------------------------- + * LPC + * -------------------------------------------------------------------- */ +#if defined(CONFIG_LPC) || defined(CONFIG_LPC_MODULE) +static struct resource ast_lpc_resource[] = { + [0] = { + .start = AST_LPC_BASE, + .end = AST_LPC_BASE + SZ_4K, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_LPC, + .end = IRQ_LPC, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ast_lpc_dma_mask = 0xffffffffUL; + +static struct platform_device ast_lpc_device = { + .name = "ast_lpc", + .id = 0, + .dev = { + .dma_mask = &ast_lpc_dma_mask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = ast_lpc_resource, + .num_resources = ARRAY_SIZE(ast_lpc_resource), +}; + +static struct resource ast_lpc_plus_resource[] = { + [0] = { + .start = AST_LPC_PLUS_BASE, + .end = AST_LPC_PLUS_BASE + SZ_4K, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ast_lpc_plus_device = { + .name = "ast_lpc_plus", + .id = 1, + .dev = { + .dma_mask = &ast_lpc_dma_mask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = ast_lpc_plus_resource, + .num_resources = ARRAY_SIZE(ast_lpc_plus_resource), +}; + +void __init ast_add_device_lpc(void) +{ +// it should enable at u-boot +// ast_scu_init_lpc(); + + platform_device_register(&ast_lpc_device); + platform_device_register(&ast_lpc_plus_device); +} +#else +void __init ast_add_device_lpc(void) {} +#endif + diff --git a/arch/arm/plat-aspeed/dev-mbx.c b/arch/arm/plat-aspeed/dev-mbx.c new file mode 100644 index 000000000000..75baf87b62ec --- /dev/null +++ b/arch/arm/plat-aspeed/dev-mbx.c @@ -0,0 +1,79 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-mbx.c +* Author : Ryan chen +* Description : ASPEED MailBox Controller +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/11/29 ryan chen create this file +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/devs.h> +#include <plat/ast-scu.h> + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/devs.h> +#include <plat/ast-scu.h> + +/* -------------------------------------------------------------------- + * MailBox + * -------------------------------------------------------------------- */ +#if defined(CONFIG_AST_MBX) || defined(CONFIG_AST_MBX_MODULE) +static struct resource ast_mbx_resource[] = { + [0] = { + .start = AST_MBX_BASE, + .end = AST_MBX_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_MAILBOX, + .end = IRQ_MAILBOX, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ast_mbx_dma_mask = 0xffffffffUL; + +static struct platform_device ast_mbx_device = { + .name = "ast-mailbox", + .id = 0, + .dev = { + .dma_mask = &ast_mbx_dma_mask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = ast_mbx_resource, + .num_resources = ARRAY_SIZE(ast_mbx_resource), +}; + +void __init ast_add_device_mailbox(void) +{ + platform_device_register(&ast_mbx_device); +} +#else +void __init ast_add_device_mailbox(void) {} +#endif + diff --git a/arch/arm/plat-aspeed/dev-nand.c b/arch/arm/plat-aspeed/dev-nand.c new file mode 100644 index 000000000000..f11ff3147f39 --- /dev/null +++ b/arch/arm/plat-aspeed/dev-nand.c @@ -0,0 +1,331 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-nand.c +* Author : Ryan chen +* Description : ASPEED NAND Device +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/10/15 ryan chen create this file +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <asm/mach/flash.h> + +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/devs.h> +#include <plat/regs-fmc.h> +#include <asm/io.h> + +#include <linux/mtd/nand.h> + +#include <plat/ast-scu.h> +#include <linux/mtd/mtd.h> + + + +/* -------------------------------------------------------------------- + * NAND Flash + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_MTD_NAND_AST) || defined(CONFIG_MTD_NAND_AST_MODULE) +static void __iomem *fmc_regs; + +/* returns 0 if the nand is busy, returns 1 if the nand is ready */ +static int +ast_nand_dev_ready(struct mtd_info *mtd) +{ + int status; + status = (readl(fmc_regs + FMC_MISC_CTRL1) & READ_BUSY_PIN_STS) >> 3; + return status; +} + +/* We use 2 256bytes as ECC's data length in sample code */ +static void +ast_enable_hwecc(struct mtd_info *mtd, int cmd) +{ + writel(NAND_ECC_DATA_BLK_256 | NAND_ECC_ENABLE , fmc_regs + FMC_NAND_ECC); + + writel(NAND_ECC_RESET , fmc_regs + FMC_NAND_ECC); + + writel(NAND_ECC_DATA_BLK_256 | NAND_ECC_ENABLE , fmc_regs + FMC_NAND_ECC); +} + +static int +ast_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) +{ + uint32_t ecc_1, ecc_2, ecc_3; + + ecc_1 = readl(fmc_regs + FMC_NAND_ECC_GEN1); + ecc_2 = readl(fmc_regs + FMC_NAND_ECC_GEN2); + ecc_3 = readl(fmc_regs + FMC_NAND_ECC_GEN3); + + ecc_code[0] = ecc_1; + ecc_code[1] = ecc_1 >> 8; + ecc_code[2] = ecc_1 >> 16; + ecc_code[3] = ecc_1 >> 24; + ecc_code[4] = ecc_2; + ecc_code[5] = (((ecc_2 >> 8) & 0x0F) | 0xF0); //Becase flash's data value will be 0xff after flash is erased. The 256bytes mode will use 44bits to do ECC, the software needs to add 0xF0 for the last 4 bits. + + return 0; +} + +static int +ast_nand_correct_data(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *calc_ecc) +{ + unsigned int dw_read_data[3], dw_calc_data[3]; + unsigned int data1_check_status, data2_check_status; + unsigned int i, ecc_position, ecc_bit; + + for (i = 0; i < 3; i++) { + dw_read_data[i] = 0; + dw_calc_data[i] = 0; + } + memcpy (dw_read_data, read_ecc, 6); + memcpy (dw_calc_data, calc_ecc, 6); + for (i = 0; i < 2; i++) { + writel(dw_read_data[i], fmc_regs + FMC_NAND_ECC_CK1 + (i*4)); + writel(dw_calc_data[i], fmc_regs + FMC_NAND_ECC_GEN1 + (i*4)); + } + + data1_check_status = readl(fmc_regs + FMC_NAND_ECC_CK_R1) & 0xffff; + data2_check_status = (readl(fmc_regs + FMC_NAND_ECC_CK_R1) & 0xffff0000) >> 16; + + if ((data1_check_status & 0x1000) && (data2_check_status & 0x1000)) { + return 0; + } + + if ((data1_check_status & 0x8000) || (data2_check_status & 0x8000)) { + printk(KERN_ERR "uncorrectable error : "); + return -1; + } + + if ((data1_check_status & 0x4000) || (data2_check_status & 0x4000)) { + printk ("error in ecc data\n"); + return 1; /* error in ecc data; no action needed */ + } + +//Correctable + if (data1_check_status & 0x2000) { + printk ("correctable in data area 1\n"); + ecc_position = (data1_check_status & 0xff8) >> 3; + ecc_bit = (data1_check_status & 0x07); + dat[ecc_position] ^= (1 << ecc_bit); + } + if (data2_check_status & 0x2000) { + printk ("correctable in data area 2\n"); + ecc_position = (data2_check_status & 0xff8) >> 3; + ecc_bit = (data2_check_status & 0x07); + dat[128 + ecc_position] ^= (1 << ecc_bit); + } + + return 1; +} + +/*--------------------------------------------------------- + * AST2300 1 NAND * 128MB + *--------------------------------------------------------*/ + +static struct mtd_partition ast_nand_partition_info[] = { + [0] = { + .name = "ASPEED NAND Flash 0", + .offset = 0, + .size = SZ_64M, + }, + [1] = { + .name = "ASPEED NAND Flash 1", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL + }, +}; + +static const char *ast_nand_part_probes[] = { "cmdlinepart", NULL }; + +struct platform_nand_data ast_nand_platdata = { + .chip = { + .nr_chips = 1, + .chip_offset = 0, + .nr_partitions = ARRAY_SIZE(ast_nand_partition_info), + .partitions = ast_nand_partition_info, + /* 50 us command delay time */ + .chip_delay = 50, + .options = NAND_NO_AUTOINCR, + .part_probe_types = ast_nand_part_probes, + }, + .ctrl = { + .hwcontrol = ast_enable_hwecc, + .dev_ready = ast_nand_dev_ready, + .select_chip = 0, + .calculate = ast_calculate_ecc, + .correct = ast_nand_correct_data, + }, +}; + +#if defined(CONFIG_AST_CS0_NAND) +static struct resource ast_nand_resource0[] = { + { + .start = AST_CS0_DEF_BASE, + .end = AST_CS0_DEF_BASE + 0x10000, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ast_nand_device0 = { + .name = "ast-nand", + .id = 0, + .dev = { + .platform_data = &ast_nand_platdata, + }, + .num_resources = ARRAY_SIZE(ast_nand_resource0), + .resource = ast_nand_resource0, +}; +#endif + +#if defined(CONFIG_AST_CS1_NAND) +static struct resource ast_nand_resource1[] = { + { + .start = AST_CS1_DEF_BASE, + .end = AST_CS1_DEF_BASE + 0x10000, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ast_nand_device1 = { + .name = "ast-nand", + .id = 1, + .dev = { + .platform_data = &ast_nand_platdata, + }, + .num_resources = ARRAY_SIZE(ast_nand_resource1), + .resource = ast_nand_resource1, +}; +#endif + +#if defined(CONFIG_AST_CS2_NAND) +static struct resource ast_nand_resource2[] = { + { + .start = AST_CS2_DEF_BASE, + .end = AST_CS2_DEF_BASE + 0x10000, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ast_nand_device2 = { + .name = "ast-nand", + .id = 2, + .dev = { + .platform_data = &ast_nand_platdata, + }, + .num_resources = ARRAY_SIZE(ast_nand_resource2), + .resource = ast_nand_resource2, +}; +#endif + +#if defined(CONFIG_AST_CS3_NAND) +static struct resource ast_nand_resource3[] = { + { + .start = AST_CS3_DEF_BASE, + .end = AST_CS3_DEF_BASE + 0x10000, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ast_nand_device3 = { + .name = "ast-nand", + .id = 3, + .dev = { + .platform_data = &ast_nand_platdata, + }, + .num_resources = ARRAY_SIZE(ast_nand_resource3), + .resource = ast_nand_resource3, +}; +#endif + +#if defined(CONFIG_AST_CS4_NAND) +static struct resource ast_nand_resource4[] = { + { + .start = AST_CS4_DEF_BASE, + .end = AST_CS4_DEF_BASE + 0x10000, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ast_nand_device4 = { + .name = "ast-nand", + .id = 4, + .dev = { + .platform_data = &ast_nand_platdata, + }, + .num_resources = ARRAY_SIZE(ast_nand_resource4), + .resource = ast_nand_resource4, +}; +#endif + +/*-------------------------------------*/ +void __init ast_add_device_nand(void) +{ + u32 tmp; + fmc_regs = ioremap(AST_FMC_BASE, 4*SZ_16); + + ast_scu_multi_func_nand(); + writel(0x31 , fmc_regs + FMC_MISC_CTRL1); + +#if defined(CONFIG_AST_CS0_NAND) + platform_device_register(&ast_nand_device0); + tmp = (readl(fmc_regs) | FMC_SET_WRITE_CS(0)) & FMC_MASK_TYPE_CS(0); + writel( tmp | FMC_SET_TYPE_NAND_CS(0), fmc_regs); + writel(0x9 , fmc_regs + FMC_CE0_CTRL); +#endif + +#if defined(CONFIG_AST_CS1_NAND) + ast_scu_multi_func_romcs(1); + tmp = (readl(fmc_regs) | FMC_SET_WRITE_CS(1)) & FMC_MASK_TYPE_CS(1); + writel( tmp | FMC_SET_TYPE_NAND_CS(1), fmc_regs); + writel(0x9 , fmc_regs + FMC_CE1_CTRL); + platform_device_register(&ast_nand_device1); +#endif +#if defined(CONFIG_AST_CS2_NAND) + ast_scu_multi_func_romcs(2); + tmp = (readl(fmc_regs) | FMC_SET_WRITE_CS(2)) & FMC_MASK_TYPE_CS(2); + writel( tmp | FMC_SET_TYPE_NAND_CS(2), fmc_regs); + writel(0x9 , fmc_regs + FMC_CE2_CTRL); + platform_device_register(&ast_nand_device2); +#endif +#if defined(CONFIG_AST_CS3_NAND) + ast_scu_multi_func_romcs(3); + tmp = (readl(fmc_regs) | FMC_SET_WRITE_CS(3)) & FMC_MASK_TYPE_CS(3); + writel( tmp | FMC_SET_TYPE_NAND_CS(3), fmc_regs); + writel(0x9 , fmc_regs + FMC_CE3_CTRL); + platform_device_register(&ast_nand_device3); +#endif +#if defined(CONFIG_AST_CS4_NAND) + ast_scu_multi_func_romcs(4); + tmp = (readl(fmc_regs) | FMC_SET_WRITE_CS(4)) & FMC_MASK_TYPE_CS(4); + writel( tmp | FMC_SET_TYPE_NAND_CS(4), fmc_regs); + writel(0x9 , fmc_regs + FMC_CE4_CTRL); + platform_device_register(&ast_nand_device4); +#endif + iounmap(fmc_regs); + +} +#else +void __init ast_add_device_nand(void) {} +#endif diff --git a/arch/arm/plat-aspeed/dev-nor.c b/arch/arm/plat-aspeed/dev-nor.c new file mode 100644 index 000000000000..abf49c0df827 --- /dev/null +++ b/arch/arm/plat-aspeed/dev-nor.c @@ -0,0 +1,219 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-nor.c +* Author : Ryan chen +* Description : ASPEED NOR Device +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/08/01 ryan chen create this file +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <asm/mach/flash.h> + +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/devs.h> +#include <plat/regs-fmc.h> +#include <asm/io.h> +#include <plat/ast-scu.h> + + +/* -------------------------------------------------------------------- + * NOR Flash + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_MTD_AST) || defined(CONFIG_MTD_AST_MODULE) +/*--------------------------------------------------------- + * AST2300 1 NOR * 16MB + *--------------------------------------------------------*/ +static struct mtd_partition nor_partitions[] = { + /* bootloader (U-Boot, etc) in first sector */ + { + .name = "u-boot", + .offset = 0, + .size = 0x80000, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + /* kernel */ + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = 0x300000, + }, + /* file system */ + { + .name = "ramdisk", + .offset = MTDPART_OFS_APPEND, + .size = 0x500000, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; + +static struct flash_platform_data ast_nor_data = { + .map_name = "cfi_probe", + .width = 2, + .parts = nor_partitions, + .nr_parts = ARRAY_SIZE(nor_partitions), +}; + +#if defined(CONFIG_AST_CS0_NOR) +static struct resource ast_nor_resource0[] = { + { + .start = AST_CS0_DEF_BASE, + .end = AST_CS0_DEF_BASE + AST_NOR_SIZE- 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ast_nor_device0 = { + .name = "ast-nor", + .id = 0, + .dev = { + .platform_data = &ast_nor_data, + }, + .num_resources = ARRAY_SIZE(ast_nor_resource0), + .resource = ast_nor_resource0, +}; +#endif + +#if defined(CONFIG_AST_CS1_NOR) +static struct resource ast_nor_resource1[] = { + { + .start = AST_CS1_DEF_BASE, + .end = AST_CS1_DEF_BASE + AST_NOR_SIZE- 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ast_nor_device1 = { + .name = "ast-nor", + .id = 1, + .dev = { + .platform_data = &ast_nor_data, + }, + .num_resources = ARRAY_SIZE(ast_nor_resource1), + .resource = ast_nor_resource1, +}; +#endif + +#if defined(CONFIG_AST_CS2_NOR) +static struct resource ast_nor_resource2[] = { + { + .start = AST_CS2_DEF_BASE, + .end = AST_CS2_DEF_BASE + AST_NOR_SIZE- 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ast_nor_device2 = { + .name = "ast-nor", + .id = 2, + .dev = { + .platform_data = &ast_nor_data, + }, + .num_resources = ARRAY_SIZE(ast_nor_resource2), + .resource = ast_nor_resource2, +}; +#endif + +#if defined(CONFIG_AST_CS3_NOR) +static struct resource ast_nor_resource3[] = { + { + .start = AST_CS3_DEF_BASE, + .end = AST_CS3_DEF_BASE + AST_NOR_SIZE- 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ast_nor_device3 = { + .name = "ast-nor", + .id = 3, + .dev = { + .platform_data = &ast_nor_data, + }, + .num_resources = ARRAY_SIZE(ast_nor_resource3), + .resource = ast_nor_resource3, +}; +#endif + +#if defined(CONFIG_AST_CS4_NOR) +static struct resource ast_nor_resource4[] = { + { + .start = AST_CS4_DEF_BASE, + .end = AST_CS4_DEF_BASE + AST_NOR_SIZE- 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ast_nor_device4 = { + .name = "ast-nor", + .id = 4, + .dev = { + .platform_data = &ast_nor_data, + }, + .num_resources = ARRAY_SIZE(ast_nor_resource4), + .resource = ast_nor_resource4, +}; +#endif + +/*-------------------------------------*/ +void __init ast_add_device_flash(void) +{ + void __iomem *fmc_regs = ioremap(AST_FMC_BASE, 4*SZ_16); + + ast_scu_multi_func_nor(); + +#if defined(CONFIG_AST_CS0_NOR) + //Enable NOR ACK + ast_scu_multi_func_romcs(0); + platform_device_register(&ast_nor_device0); + writel((readl(fmc_regs) | FMC_SET_WRITE_CS(0)) & FMC_MASK_TYPE_CS(0), fmc_regs); +#endif +#if defined(CONFIG_AST_CS1_NOR) + ast_scu_multi_func_romcs(1); + writel((readl(fmc_regs) | FMC_SET_WRITE_CS(1)) & FMC_MASK_TYPE_CS(1), fmc_regs); + platform_device_register(&ast_nor_device1); +#endif +#if defined(CONFIG_AST_CS2_NOR) + ast_scu_multi_func_romcs(2); + writel((readl(fmc_regs) | FMC_SET_WRITE_CS(2)) & FMC_MASK_TYPE_CS(2), fmc_regs); + platform_device_register(&ast_nor_device2); +#endif +#if defined(CONFIG_AST_CS3_NOR) + ast_scu_multi_func_romcs(3); + writel((readl(fmc_regs) | FMC_SET_WRITE_CS(3)) & FMC_MASK_TYPE_CS(3), fmc_regs); + platform_device_register(&ast_nor_device3); +#endif +#if defined(CONFIG_AST_CS4_NOR) + ast_scu_multi_func_romcs(4); + writel((readl(fmc_regs) | FMC_SET_WRITE_CS(4)) & FMC_MASK_TYPE_CS(4), fmc_regs); + platform_device_register(&ast_nor_device4); +#endif + iounmap(fmc_regs); + +} +#else +void __init ast_add_device_flash(void) {} +#endif diff --git a/arch/arm/plat-aspeed/dev-peci.c b/arch/arm/plat-aspeed/dev-peci.c new file mode 100644 index 000000000000..28ad1a5f119d --- /dev/null +++ b/arch/arm/plat-aspeed/dev-peci.c @@ -0,0 +1,68 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-peci.c +* Author : Ryan chen +* Description : ASPEED PECI Device +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/08/06 ryan chen create this file +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/devs.h> +#include <plat/ast-scu.h> + + +/* -------------------------------------------------------------------- + * PECI + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_AST_PECI) || defined(CONFIG_AST_PECI_MODULE) +static struct resource ast_peci_resources[] = { + [0] = { + .start = AST_PECI_BASE, + .end = AST_PECI_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_PECI, + .end = IRQ_PECI, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ast_peci_device = { + .name = "ast_peci", + .id = 0, + .resource = ast_peci_resources, + .num_resources = ARRAY_SIZE(ast_peci_resources), +}; + +void __init ast_add_device_peci(void) +{ + //SCU PECI CTRL Reset + ast_scu_init_peci(); + + platform_device_register(&ast_peci_device); +} +#else +void __init ast_add_device_peci(void) {} +#endif diff --git a/arch/arm/plat-aspeed/dev-pwm-fan.c b/arch/arm/plat-aspeed/dev-pwm-fan.c new file mode 100644 index 000000000000..85570bb6196c --- /dev/null +++ b/arch/arm/plat-aspeed/dev-pwm-fan.c @@ -0,0 +1,80 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-pwm-fan.c +* Author : Ryan chen +* Description : ASPEED PWM-FAN Device +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/08/06 ryan chen create this file +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/devs.h> +#include <plat/ast-scu.h> +#include <mach/ast_pwm_techo.h> + +/* -------------------------------------------------------------------- + * PWM-FAN + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_SENSORS_AST_PWM_FAN) || defined(CONFIG_SENSORS_AST_PWM_FAN_MODULE) +static struct resource ast_pwm_fan_resources[] = { + [0] = { + .start = AST_PWM_BASE, + .end = AST_PWM_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TACHO, + .end = IRQ_TACHO, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct ast_pwm_driver_data ast_pwm_data = { + .get_pwm_clock = ast_get_h_pll_clk, +}; + +struct platform_device ast_pwm_fan_device = { + .name = "ast_pwm_tacho", + .id = 0, + .dev = { + .platform_data = &ast_pwm_data, + }, + .resource = ast_pwm_fan_resources, + .num_resources = ARRAY_SIZE(ast_pwm_fan_resources), +}; + +void __init ast_add_device_pwm_fan(void) +{ + //SCU Initial + + //SCU Pin-MUX //PWM & TACHO + ast_scu_multi_func_pwm_tacho(); + + //SCU PWM CTRL Reset + ast_scu_init_pwm_tacho(); + + platform_device_register(&ast_pwm_fan_device); +} +#else +void __init ast_add_device_pwm_fan(void) {} +#endif diff --git a/arch/arm/plat-aspeed/dev-rtc.c b/arch/arm/plat-aspeed/dev-rtc.c new file mode 100644 index 000000000000..214aa686dcd5 --- /dev/null +++ b/arch/arm/plat-aspeed/dev-rtc.c @@ -0,0 +1,65 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-wdt.c +* Author : Ryan Chen +* Description : AST WDT Device +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/09/15 Ryan Chen initial +* +********************************************************************************/ +#include <linux/kernel.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/platform.h> + +#include <plat/devs.h> + + +/* -------------------------------------------------------------------- + * Watchdog + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_RTC_DRV_AST) || defined(CONFIG_RTC_DRV_AST_MODULE) + +static struct resource ast_rtc_resource[] = { + [0] = { + .start = AST_RTC_BASE, + .end = AST_RTC_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_RTC, + .end = IRQ_RTC, + .flags = IORESOURCE_IRQ, + }, + +}; + +static struct platform_device ast_device_rtc = { + .name = "ast_rtc", + .id = -1, + .resource = ast_rtc_resource, + .num_resources = ARRAY_SIZE(ast_rtc_resource), +}; + +void __init ast_add_device_rtc(void) +{ + platform_device_register(&ast_device_rtc); +} +#else +void __init ast_add_device_rtc(void) {} +#endif diff --git a/arch/arm/plat-aspeed/dev-sdhci.c b/arch/arm/plat-aspeed/dev-sdhci.c new file mode 100644 index 000000000000..bcc8cce49a93 --- /dev/null +++ b/arch/arm/plat-aspeed/dev-sdhci.c @@ -0,0 +1,110 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-sdhc.c +* Author : Ryan chen +* Description : ASPEED SDHC Device +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/07/30 ryan chen create this file +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/devs.h> +#include <plat/ast_sdhci.h> +#include <plat/ast-scu.h> + + +/* -------------------------------------------------------------------- + * SDHC + * -------------------------------------------------------------------- */ +#if defined(CONFIG_MMC_AST) || defined(CONFIG_MMC_AST_MODULE) +static struct ast_sdhc_platform_data ast_sdhc_info = { + .sd_clock_src_get = ast_get_sd_clock_src, +}; + +static struct resource ast_sdhci0_resource[] = { + [0] = { + .start = AST_SDHC_BASE + 0x100, + .end = AST_SDHC_BASE + 0x100 + 0xFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_SDHC, + .end = IRQ_SDHC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource ast_sdhci1_resource[] = { + [0] = { + .start = AST_SDHC_BASE + 0x200, + .end = AST_SDHC_BASE + 0x200 + 0xFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_SDHC, + .end = IRQ_SDHC, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ast_sdhc_dma_mask = 0xffffffffUL; + +static struct platform_device ast_sdhci_device0 = { + .name = "ast_sdhci", + .id = 0, + .dev = { + .dma_mask = &ast_sdhc_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_sdhc_info, + }, + .resource = ast_sdhci0_resource, + .num_resources = ARRAY_SIZE(ast_sdhci0_resource), +}; + +static struct platform_device ast_sdhci_device1 = { + .name = "ast_sdhci", + .id = 1, + .dev = { + .dma_mask = &ast_sdhc_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ast_sdhc_info, + }, + .resource = ast_sdhci1_resource, + .num_resources = ARRAY_SIZE(ast_sdhci1_resource), +}; + +void __init ast_add_device_sdhci(void) +{ + ast_scu_init_sdhci(); + //multipin. Remind: AST2300FPGA only supports one port at a time + + ast_scu_multi_func_sdhc_slot1(1); + + platform_device_register(&ast_sdhci_device0); + + ast_scu_multi_func_sdhc_slot2(1); + + platform_device_register(&ast_sdhci_device1); +} +#else +void __init ast_add_device_sdhci(void) {} +#endif diff --git a/arch/arm/plat-aspeed/dev-sgpio.c b/arch/arm/plat-aspeed/dev-sgpio.c new file mode 100644 index 000000000000..c6ca2c44c1f4 --- /dev/null +++ b/arch/arm/plat-aspeed/dev-sgpio.c @@ -0,0 +1,68 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-rtc.c +* Author : Ryan chen +* Description : Socle Real Time Clock Device (RTC) +* +* Copyright (C) Socle Tech. Corp. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2010/09/15 ryan chen create this file +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/platform.h> +//#include <plat/regs-sgpio.h> + +#include <plat/devs.h> + +/* -------------------------------------------------------------------- + * ASPEED SGPIO + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_SGPIO_AST) || defined(CONFIG_SGPIO_AST_MODULE) +static struct resource ast_sgpio_resource[] = { + [0] = { + .start = AST_SGPIO_BASE, + .end = AST_SGPIO_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_SGPIO, + .end = IRQ_SGPIO, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ast_device_sgpio = { + .name = "ast-sgpio", + .id = 0, + .num_resources = ARRAY_SIZE(ast_sgpio_resource), + .resource = ast_sgpio_resource, +}; + +extern void __init +ast_add_device_sgpio(void) +{ + platform_device_register(&ast_device_sgpio); +} + +#else +extern void __init ast_add_device_sgpio(void) {} +#endif + diff --git a/arch/arm/plat-aspeed/dev-snoop.c b/arch/arm/plat-aspeed/dev-snoop.c new file mode 100644 index 000000000000..9e286bc3f899 --- /dev/null +++ b/arch/arm/plat-aspeed/dev-snoop.c @@ -0,0 +1,94 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-snoop.c +* Author : Ryan chen +* Description : ASPEED SNOOP Device +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/11/29 ryan chen create this file +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/devs.h> +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/platform.h> +#include <plat/devs.h> +#include <plat/ast-snoop.h> + +/* -------------------------------------------------------------------- + * AST SNOOP -- DMA or 80Port SNOOP + * -------------------------------------------------------------------- */ +#if defined(CONFIG_SNOOP_AST) || defined(CONFIG_SNOOP_AST_MODULE) +static u64 ast_snoop_dma_mask = 0xffffffffUL; + +static struct ast_snoop_channel snoop_ch0 = { + .snoop_ch = 0, + .snoop_port = 0x80, +}; + +static struct ast_snoop_channel snoop_ch1 = { + .snoop_ch = 1, + .snoop_port = 0x81, +}; + +static struct ast_snoop snoop = { + .snoop_ch0 = &snoop_ch0, + .snoop_ch1 = &snoop_ch1, +}; + +static struct platform_device ast_snoop_device = { + .name = "ast_snoop", + .id = 0, + .dev = { + .dma_mask = &ast_snoop_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &snoop, + }, +}; + +struct ast_snoop_dma_channel snoop_dma_ch0 = { + .snoop_ch = 0, + .snoop_port = 0x3f8, + .snoop_mask = 7, +}; + +static struct platform_device ast_snoop_dma_device = { + .name = "ast_snoop_dma", + .id = 0, + .dev = { + .dma_mask = &ast_snoop_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &snoop_dma_ch0, + }, +}; + +void __init ast_add_device_snoop(void) +{ + platform_device_register(&ast_snoop_device); + platform_device_register(&ast_snoop_dma_device); +} +#else +void __init ast_add_device_snoop(void) {} +#endif + diff --git a/arch/arm/plat-aspeed/dev-spi.c b/arch/arm/plat-aspeed/dev-spi.c new file mode 100644 index 000000000000..7ddd2e437212 --- /dev/null +++ b/arch/arm/plat-aspeed/dev-spi.c @@ -0,0 +1,448 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-spi.c +* Author : Ryan chen +* Description : ASPEED SPI device +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/08/01 ryan chen create this file +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/spi/flash.h> + +#include <linux/spi/spi.h> + + +#include <asm/io.h> +#if defined(CONFIG_COLDFIRE) +#include <asm/sizes.h> +#include <asm/arch/ast_spi.h> +#include <asm/arch/ast-scu.h> +#include <asm/arch/irqs.h> +#include <asm/arch/platform.h> +#include <asm/arch/devs.h> +#else +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/devs.h> +#include <plat/regs-fmc.h> +#include <plat/ast-scu.h> +#include <mach/ast_spi.h> +#endif + +/* -------------------------------------------------------------------- + * SPI Ctrl, (AST SPI + FMC SPI) + * -------------------------------------------------------------------- */ +#if defined(CONFIG_SPI_FMC) || defined(CONFIG_SPI_FMC_MODULE) || defined(CONFIG_SPI_AST) || defined(CONFIG_SPI_AST_MODULE) +static u32 ast_spi_calculate_divisor(u32 max_speed_hz) +{ + // [0] ->15 : HCLK , HCLK/16 + u8 SPI_DIV[16] = {16, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0}; + u32 i, hclk, spi_cdvr=0; + + hclk = ast_get_h_pll_clk(); + for(i=1;i<17;i++) { + if(max_speed_hz >= (hclk/i)) { + spi_cdvr = SPI_DIV[i-1]; + break; + } + } + +// printk("hclk is %d, divisor is %d, target :%d , cal speed %d\n", hclk, spi_cdvr, spi->max_speed_hz, hclk/i); + return spi_cdvr; +} +#endif + +#if defined(CONFIG_SPI_FMC) || defined(CONFIG_SPI_FMC_MODULE) +static struct ast_spi_driver_data fmc_spi_data = { + .get_div = ast_spi_calculate_divisor, + .num_chipselect = 1, +}; + +#if defined(CONFIG_AST_CS0_SPI) +static struct resource ast_fmc_spi_resource0[] = { + { + .start = AST_FMC_BASE + 0x10, + .end = AST_FMC_BASE + 0x10 + SZ_16, + .flags = IORESOURCE_MEM, + }, + { + .start = AST_CS0_DEF_BASE, + .end = AST_CS0_DEF_BASE + SZ_16, + .flags = IORESOURCE_IO, + }, +}; +static struct platform_device ast_fmc_spi_device0 = { + .name = "fmc-spi", + .id = 0, + .dev = { + .platform_data = &fmc_spi_data, + }, + .num_resources = ARRAY_SIZE(ast_fmc_spi_resource0), + .resource = ast_fmc_spi_resource0, +}; +#endif + +#if defined(CONFIG_AST_CS1_SPI) +static struct resource ast_fmc_spi_resource1[] = { + { + .start = AST_FMC_BASE + 0x14, + .end = AST_FMC_BASE + 0x14 + SZ_16, + .flags = IORESOURCE_MEM, + }, + { + .start = AST_CS1_DEF_BASE, + .end = AST_CS1_DEF_BASE + SZ_16, + .flags = IORESOURCE_IO, + }, +}; +static struct platform_device ast_fmc_spi_device1 = { + .name = "fmc-spi", + .id = 1, + .dev = { + .platform_data = &fmc_spi_data, + }, + .num_resources = ARRAY_SIZE(ast_fmc_spi_resource1), + .resource = ast_fmc_spi_resource1, +}; +#endif + +#if defined(CONFIG_AST_CS2_SPI) +static struct resource ast_fmc_spi_resource2[] = { + { + .start = AST_FMC_BASE + 0x18, + .end = AST_FMC_BASE + 0x18 + SZ_16, + .flags = IORESOURCE_MEM, + }, + { + .start = AST_CS2_DEF_BASE, + .end = AST_CS2_DEF_BASE + SZ_16, + .flags = IORESOURCE_IO, + }, +}; + +static struct platform_device ast_fmc_spi_device2 = { + .name = "fmc-spi", + .id = 2, + .dev = { + .platform_data = &fmc_spi_data, + }, + .num_resources = ARRAY_SIZE(ast_fmc_spi_resource2), + .resource = ast_fmc_spi_resource2, +}; +#endif + +#if defined(CONFIG_AST_CS3_SPI) +static struct resource ast_fmc_spi_resource3[] = { + { + .start = AST_FMC_BASE + 0x1c, + .end = AST_FMC_BASE + 0x1c + SZ_16, + .flags = IORESOURCE_MEM, + }, + { + .start = AST_CS3_DEF_BASE, + .end = AST_CS3_DEF_BASE + SZ_16, + .flags = IORESOURCE_IO, + }, +}; + +static struct platform_device ast_fmc_spi_device3 = { + .name = "fmc-spi", + .id = 3, + .dev = { + .platform_data = &fmc_spi_data, + }, + .num_resources = ARRAY_SIZE(ast_fmc_spi_resource3), + .resource = ast_fmc_spi_resource3, +}; +#endif + +#if defined(CONFIG_AST_CS4_SPI) +static struct resource ast_fmc_spi_resource4[] = { + { + .start = AST_FMC_BASE + 0x20, + .end = AST_FMC_BASE + 0x20 + SZ_16, + .flags = IORESOURCE_MEM, + }, + { + .start = AST_CS4_DEF_BASE, + .end = AST_CS4_DEF_BASE + SZ_16, + .flags = IORESOURCE_IO, + }, +}; + +static struct platform_device ast_fmc_spi_device4 = { + .name = "fmc-spi", + .id = 4, + .dev = { + .platform_data = &fmc_spi_data, + }, + .num_resources = ARRAY_SIZE(ast_fmc_spi_resource4), + .resource = ast_fmc_spi_resource4, +}; +#endif + +#endif //CONFIG_SPI_FMC + +#if defined(CONFIG_SPI_AST) || defined(CONFIG_SPI_AST_MODULE) +static struct ast_spi_driver_data ast_spi0_data = { + .get_div = ast_spi_calculate_divisor, + .num_chipselect = 1, +}; + +static struct resource ast_spi_resource0[] = { + { + .start = AST_SPI0_BASE, + .end = AST_SPI0_BASE + SZ_16, + .flags = IORESOURCE_MEM, + }, + { + .start = AST_SPI0_MEM + 0x04, + .end = AST_SPI0_MEM + SZ_16, + .flags = IORESOURCE_IO, + }, +}; + +static struct platform_device ast_spi_device0 = { + .name = "ast-spi", +#if defined(CONFIG_ARCH_AST1010) + .id = 0, +#else + .id = 5, +#endif + .dev = { + .platform_data = &ast_spi0_data, + }, + .num_resources = ARRAY_SIZE(ast_spi_resource0), + .resource = ast_spi_resource0, +}; + +#if defined(AST_SPI1_BASE) +static struct ast_spi_driver_data ast_spi1_data = { + .get_div = ast_spi_calculate_divisor, + .num_chipselect = 1, +}; + +static struct resource aspeed_spi1_resource[] = { + { + .start = AST_SPI1_BASE, + .end = AST_SPI1_BASE + SZ_16, + .flags = IORESOURCE_MEM, + }, + { + .start = AST_SPI1_MEM, + .end = AST_SPI1_MEM + SZ_16, + .flags = IORESOURCE_IO, + }, +}; + +static struct platform_device aspeed_spi_device1 = { + .name = "ast-spi", + .id = 1, + .dev = { + .platform_data = &ast_spi1_data, + }, + .num_resources = ARRAY_SIZE(aspeed_spi1_resource), + .resource = aspeed_spi1_resource, +}; + +#endif + +#endif //CONFIG_SPI_AST + +#if defined(CONFIG_ARCH_AST1010) +static struct mtd_partition ast_spi_flash_partitions[] = { + { + .name = "uboot", + .offset = 0, + .size = 0x00030000, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "uboot-env", + .offset = MTDPART_OFS_APPEND, + .size = 0x00010000, +// .mask_flags = MTD_WRITEABLE, + }, + { + .name = "uCLinux", + .offset = MTDPART_OFS_APPEND, + .size = 0x003c0000, +// .mask_flags = MTD_CAP_NORFLASH, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, +// .mask_flags = MTD_CAP_NORFLASH, + } +}; +#else +static struct mtd_partition ast_spi_flash_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x80000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = 0x80000, + .size = 0x200000, + }, { + .name = "rootfs", + .offset = 0x300000, + .size = 0x4F0000, + }, { + .name = "env", + .offset = 0x7f0000, + .size = 0x10000, + }, { + .name = "data0", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; +#endif + +static struct flash_platform_data ast_spi_flash_data = { +#if defined(CONFIG_ARCH_AST2400) + .type = "mx25l25635e", //AST2400 A1 +#elif defined(CONFIG_ARCH_AST1010) + .type = "mx25l6405d", +#else + .type = "mx25l12805d", //old AST2300 +#endif + .nr_parts = ARRAY_SIZE(ast_spi_flash_partitions), + .parts = ast_spi_flash_partitions, +}; + +static struct spi_board_info ast_spi_devices[] = { + { + .modalias = "m25p80", + .platform_data = &ast_spi_flash_data, + .chip_select = 0, //.chip_select This tells your device driver which chipselect to use. + .max_speed_hz = 50 * 1000 * 1000, + .bus_num = 0, // This chooses if SPI0 or SPI1 of the SoC is used. + .mode = SPI_MODE_0, + }, + { + .modalias = "spidev", + .chip_select = 0, + .max_speed_hz = 30 * 1000 * 1000, + .bus_num = 1, + .mode = SPI_MODE_0, + }, +}; + +#if defined(AST_SPI1_BASE) +static struct mtd_partition ast_spi_flash1_partitions[] = { + { + .name = "bios", + .offset = 0, + .size = MTDPART_SIZ_FULL, + } +}; + +static struct flash_platform_data ast_spi_flash1_data = { + .type = "mx25l6405d", +// .type = "w25q64", + .nr_parts = ARRAY_SIZE(ast_spi_flash1_partitions), + .parts = ast_spi_flash1_partitions, +}; + + +static struct spi_board_info ast_spi1_devices[] = { + { + .modalias = "m25p80", + .platform_data = &ast_spi_flash1_data, + .chip_select = 0, //.chip_select This tells your device driver which chipselect to use. + .max_speed_hz = 100 * 1000 * 1000, + .bus_num = 1, // This chooses if SPI0 or SPI1 of the SoC is used. + .mode = SPI_MODE_0, + }, +}; +#endif + +#if defined(CONFIG_SPI_FMC) || defined(CONFIG_SPI_FMC_MODULE) || defined(CONFIG_SPI_AST) || defined(CONFIG_SPI_AST_MODULE) + +/*-------------------------------------*/ +void __init ast_add_device_spi(void) +{ +#if defined(CONFIG_SPI_FMC) || defined(CONFIG_SPI_FMC_MODULE) + void __iomem *fmc_regs = ioremap(AST_FMC_BASE, 4*SZ_16); + u32 tmp = 0; + +#if defined(CONFIG_AST_CS0_SPI) + platform_device_register(&ast_fmc_spi_device0); + tmp = (readl(fmc_regs) | FMC_SET_WRITE_CS(0)) & FMC_MASK_TYPE_CS(0); + writel( tmp | FMC_SET_TYPE_SPI_CS(0), fmc_regs); +#endif + +#if defined(CONFIG_AST_CS1_SPI) + ast_scu_multi_func_romcs(1); + tmp = (readl(fmc_regs) | FMC_SET_WRITE_CS(1)) & FMC_MASK_TYPE_CS(1); + writel( tmp | FMC_SET_TYPE_SPI_CS(1), fmc_regs); + platform_device_register(&ast_fmc_spi_device1); +#endif + +#if defined(CONFIG_AST_CS2_SPI) + ast_scu_multi_func_romcs(2); + tmp = (readl(fmc_regs) | FMC_SET_WRITE_CS(2)) & FMC_MASK_TYPE_CS(2); + writel( tmp | FMC_SET_TYPE_SPI_CS(2), fmc_regs); + platform_device_register(&ast_fmc_spi_device2); +#endif +#if defined(CONFIG_AST_CS3_SPI) + ast_scu_multi_func_romcs(3); + tmp = (readl(fmc_regs) | FMC_SET_WRITE_CS(3)) & FMC_MASK_TYPE_CS(3); + writel( tmp | FMC_SET_TYPE_SPI_CS(3), fmc_regs); + platform_device_register(&ast_fmc_spi_device3); +#endif +#if defined(CONFIG_AST_CS4_SPI) + ast_scu_multi_func_romcs(4); + tmp = (readl(fmc_regs) | FMC_SET_WRITE_CS(4)) & FMC_MASK_TYPE_CS(4); + writel( tmp | FMC_SET_TYPE_SPI_CS(4), fmc_regs); + platform_device_register(&ast_fmc_spi_device4); +#endif + + iounmap(fmc_regs); + +#endif + +#if defined(CONFIG_SPI_AST) || defined(CONFIG_SPI_AST_MODULE) + //pin switch by trap[13:12] + platform_device_register(&ast_spi_device0); +#endif + + spi_register_board_info(ast_spi_devices, ARRAY_SIZE(ast_spi_devices)); + +#if defined(AST_SPI1_BASE) + //AST1010 SCU CONFIG TODO ....... + writel(readl(AST_SCU_BASE + 0x70) | 0x10,AST_SCU_BASE + 0x70); + platform_device_register(&aspeed_spi_device1); + spi_register_board_info(ast_spi1_devices, ARRAY_SIZE(ast_spi1_devices)); +#endif + +} +#else +void __init ast_add_device_spi(void) {} +#endif + + diff --git a/arch/arm/plat-aspeed/dev-uart.c b/arch/arm/plat-aspeed/dev-uart.c new file mode 100644 index 000000000000..592ef4fdadd5 --- /dev/null +++ b/arch/arm/plat-aspeed/dev-uart.c @@ -0,0 +1,144 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-uart.c +* Author : Ryan chen +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/09/15 ryan chen create this file +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> +#include <linux/serial.h> +#include <linux/tty.h> +#include <linux/serial_8250.h> + +#if defined(CONFIG_COLDFIRE) +#include <asm/sizes.h> +#include <asm/arch/devs.h> +#include <asm/arch/platform.h> +#include <asm/arch/irqs.h> +#else +#include <mach/irqs.h> +#include <mach/platform.h> +#include <mach/hardware.h> +#include <plat/ast-scu.h> +#include <plat/devs.h> +#endif + +/* -------------------------------------------------------------------- + * UART + * -------------------------------------------------------------------- */ +#ifdef CONFIG_SERIAL_8250 +static struct plat_serial8250_port ast_uart_data[] = { + { + .mapbase = AST_UART0_BASE, + .irq = IRQ_UART0, + .uartclk = (24*1000000L), + .regshift = 2, +#if defined(CONFIG_COLDFIRE) + .iotype = UPIO_MEM32, +#else + .iotype = UPIO_MEM, +#endif + .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + }, +#if defined(CONFIG_ARCH_AST1010) + { + .mapbase = AST_UART1_BASE, + .irq = IRQ_UART1, + .uartclk = (24*1000000L), + .regshift = 2, + .iotype = UPIO_MEM32, + .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + }, + { + .mapbase = AST_UART2_BASE, + .irq = IRQ_UART2, + .uartclk = (24*1000000L), + .regshift = 2, + .iotype = UPIO_MEM32, + .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + }, +#else +//BMC UART 1 ,2 default to LPC +#ifdef CONFIG_ARCH_AST1070 +#ifdef AST_UART1_BASE + { + .mapbase = AST_UART1_BASE, + .irq = IRQ_UART1, + .uartclk = (24*1000000L), + .regshift = 2, + .iotype = UPIO_MEM, + .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + }, +#endif +#ifdef AST_UART2_BASE + { + .mapbase = AST_UART2_BASE, + .irq = IRQ_UART2, + .uartclk = (24*1000000L), + .regshift = 2, + .iotype = UPIO_MEM, + .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + }, +#endif +#endif +#ifdef AST_UART3_BASE + { + .mapbase = AST_UART3_BASE, + .irq = IRQ_UART3, + .uartclk = (24*1000000L), + .regshift = 2, + .iotype = UPIO_MEM, + .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + }, +#endif +#ifdef AST_UART4_BASE + { + .mapbase = AST_UART4_BASE, + .irq = IRQ_UART4, + .uartclk = (24*1000000L), + .regshift = 2, + .iotype = UPIO_MEM, + .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + }, +#endif +#endif + { }, +}; + +struct platform_device ast_uart_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = ast_uart_data, + }, +}; + +void __init ast_add_device_uart(void) +{ +#if defined(CONFIG_ARCH_AST1010) +#else + ast_scu_multi_func_uart(3); + ast_scu_multi_func_uart(4); +#endif + platform_device_register(&ast_uart_device); +} +#else +void __init ast_add_device_uart(void) {} +#endif diff --git a/arch/arm/plat-aspeed/dev-uhci.c b/arch/arm/plat-aspeed/dev-uhci.c new file mode 100644 index 000000000000..961ec9b19ee5 --- /dev/null +++ b/arch/arm/plat-aspeed/dev-uhci.c @@ -0,0 +1,82 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-uhci.c +* Author : Ryan chen +* Description : ASPEED EHCI Device +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/07/30 ryan chen create this file +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/devs.h> +#include <plat/ast-scu.h> + +/* -------------------------------------------------------------------- + * UHCI + * -------------------------------------------------------------------- */ +#if defined(CONFIG_AST_USB_UHCI_HCD) || defined(CONFIG_AST_USB_UHCI_HCD_MODULE) +static struct resource ast_uchi_resource[] = { + [0] = { + .start = AST_UHCI_BASE, + .end = AST_UHCI_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_UHCI, + .end = IRQ_UHCI, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ast_uhci_dma_mask = 0xffffffffUL; + +static struct platform_device ast_uhci_device = { + .name = "ast_uhci", + .id = 0, + .dev = { + .dma_mask = &ast_uhci_dma_mask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = ast_uchi_resource, + .num_resources = ARRAY_SIZE(ast_uchi_resource), +}; + +void __init ast_add_device_uhci(void) +{ + +#if defined (CONFIG_AST_USB_UHCI_MULTIPORT_2) + ast_scu_multi_func_usb11_host_port2(1); +#elif defined (CONFIG_AST_USB_UHCI_MULTIPORT_4) + ast_scu_multi_func_usb11_host_port2(1); + ast_scu_multi_func_usb11_host_port4(1); +#else + ast_scu_multi_func_usb11_host_port2(0); + ast_scu_multi_func_usb11_host_port4(0); +#endif + + ast_scu_init_uhci(); + + platform_device_register(&ast_uhci_device); +} +#else +void __init ast_add_device_uhci(void) {} +#endif diff --git a/arch/arm/plat-aspeed/dev-video.c b/arch/arm/plat-aspeed/dev-video.c new file mode 100644 index 000000000000..3d66effb307f --- /dev/null +++ b/arch/arm/plat-aspeed/dev-video.c @@ -0,0 +1,102 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-video.c +* Author : Ryan Chen +* Description : ASPEED Video Driver +* +* Copyright (C) ASPEED Tech. Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2013/04/15 Ryan Chen initial +* +********************************************************************************/ +#include <linux/kernel.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/platform.h> + +#include <plat/devs.h> +#include <plat/ast-scu.h> +#include <plat/ast-sdmc.h> + +#include <mach/ast_video.h> + +/* -------------------------------------------------------------------- + * AST VIDEO + * -------------------------------------------------------------------- */ +#if defined(CONFIG_AST_VIDEO) || defined(CONFIG_AST_VIDEO_MODULE) + +#define ASR_VIDEO_MEM AST_DRAM_BASE + SZ_8M*10 +static u32 get_vga_mem_base(void) +{ + u32 vga_mem_size, mem_size; + mem_size = ast_sdmc_get_mem_size(); + vga_mem_size = ast_scu_get_vga_memsize(); + printk("VGA Info : MEM Size %d, VGA Mem Size %d \n",mem_size, vga_mem_size); + return (mem_size - vga_mem_size); +} + +static struct ast_video_plat_data video_plat_data = { + .get_clk = ast_get_m_pll_clk, + .ctrl_reset = ast_scu_reset_video, + .vga_display = ast_scu_set_vga_display, + .get_vga_base = get_vga_mem_base, + .input_source = VIDEO_SOURCE_INTERNAL, + .mode = VIDEO_FRAME_MODE, + .rc4_enable = 0, + .compress = VIDEO_YUV444, + .scaling = 0, +}; + + +static struct resource ast_video_resources[] = { + [0] = { + .start = AST_VIDEO_BASE, + .end = AST_VIDEO_BASE + SZ_1K*2 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_VIDEO, + .end = IRQ_VIDEO, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = ASR_VIDEO_MEM, + .end = ASR_VIDEO_MEM + SZ_32M, + .flags = IORESOURCE_DMA, + }, +}; + +static u64 ast_device_video_dmamask = 0xffffffffUL; +struct platform_device ast_video_device = { + .name = "ast-video", + .id = 0, + .dev = { + .dma_mask = &ast_device_video_dmamask, + .coherent_dma_mask = 0xffffffffUL, + .platform_data= &video_plat_data, + }, + .resource = ast_video_resources, + .num_resources = ARRAY_SIZE(ast_video_resources), +}; + +void __init ast_add_device_video(void) +{ + ast_scu_init_video(0); + ast_scu_multi_func_video(); + platform_device_register(&ast_video_device); +} +#else +void __init ast_add_device_video(void) {} +#endif diff --git a/arch/arm/plat-aspeed/dev-vuart.c b/arch/arm/plat-aspeed/dev-vuart.c new file mode 100644 index 000000000000..0e2ab8a1bb7e --- /dev/null +++ b/arch/arm/plat-aspeed/dev-vuart.c @@ -0,0 +1,100 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-uart.c +* Author : Ryan chen +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/09/15 ryan chen create this file +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> +#include <linux/serial.h> +#include <linux/tty.h> +#include <linux/serial_8250.h> + +#include <mach/irqs.h> +#include <mach/platform.h> +#include <mach/hardware.h> +#include <asm/io.h> + +#include <plat/ast-scu.h> +#include <plat/devs.h> + +#include <plat/regs-vuart.h> + +#define AST_COM_PORT PORT_3F8 +#define AST_SIRQ SIRQ4 + +#define PORT_2F8 0x2f8 +#define PORT_3F8 0x3f8 + +typedef enum SIO_serial_irq { + SIRQ0 = 0, + SIRQ1, + SIRQ2, + SIRQ3, + SIRQ4, + SIRQ5, + SIRQ6, + SIRQ7, + SIRQ8, + SIRQ9, +}; + +/* -------------------------------------------------------------------- + * UART + * -------------------------------------------------------------------- */ +#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_AST_VUART) +static struct plat_serial8250_port ast_vuart_data[] = { + { + .mapbase = AST_VUART0_BASE, + .membase = (char*)(IO_ADDRESS(AST_VUART0_BASE)), + .irq = IRQ_LPC, + .uartclk = (24*1000000L), + .regshift = 2, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ, + }, + { }, +}; + +struct platform_device ast_vuart_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM1, + .dev = { + .platform_data = ast_vuart_data, + }, +}; + +void __init ast_add_device_vuart(void) +{ + u32 vuart_base = ioremap(AST_VUART0_BASE, SZ_256); + + writel(0x0, vuart_base + AST_VUART_CTRLA); + writel(SET_SIRQ_NUM(AST_SIRQ) |0x3, vuart_base + AST_VUART_CTRLB); + writel(AST_COM_PORT & 0xff, vuart_base + AST_VUART_ADDRL); + writel(AST_COM_PORT >> 8, vuart_base + AST_VUART_ADDRH); + writel(0x0, vuart_base + AST_VUART_CTRLF); + writel(VUART_ENABLE | VUART_SIRQ_POLARITY | VUART_DISABLE_H_TX_DISCARD, vuart_base + AST_VUART_CTRLA); + + iounmap(vuart_base); + platform_device_register(&ast_vuart_device); +} +#else +void __init ast_add_device_vuart(void) {} +#endif diff --git a/arch/arm/plat-aspeed/dev-wdt.c b/arch/arm/plat-aspeed/dev-wdt.c new file mode 100644 index 000000000000..079d1a904a9e --- /dev/null +++ b/arch/arm/plat-aspeed/dev-wdt.c @@ -0,0 +1,76 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/dev-wdt.c +* Author : Ryan Chen +* Description : AST WDT Device +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/09/15 Ryan Chen initial +* +********************************************************************************/ +#include <linux/kernel.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/platform.h> + +#include <plat/devs.h> + +/* -------------------------------------------------------------------- + * Watchdog + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_AST_WATCHDOG) || defined(CONFIG_AST_WATCHDOG_MODULE) + +static struct resource ast_wdt_resource0[] = { + [0] = { + .start = AST_WDT_BASE, + .end = AST_WDT_BASE + (SZ_16*2) - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_WDT, + .end = IRQ_WDT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource ast_wdt_resource1[] = { + [0] = { + .start = AST_WDT_BASE + (SZ_16*2), + .end = AST_WDT_BASE + (SZ_16*4) - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_WDT, + .end = IRQ_WDT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ast_device_wdt = { + .name = "ast-wdt", + .id = -1, + .resource = ast_wdt_resource0, + .num_resources = ARRAY_SIZE(ast_wdt_resource0), +}; + +void __init ast_add_device_watchdog(void) +{ + platform_device_register(&ast_device_wdt); +} +#else +void __init ast_add_device_watchdog(void) {} +#endif diff --git a/arch/arm/plat-aspeed/devs.c b/arch/arm/plat-aspeed/devs.c new file mode 100644 index 000000000000..7906b9cbbce8 --- /dev/null +++ b/arch/arm/plat-aspeed/devs.c @@ -0,0 +1,69 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/devs.c +* Author : Ryan chen +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/08/10 create this file [Ryan Chen] +* +********************************************************************************/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/platform.h> + +#include <plat/devs.h> + +typedef void (init_fnc_t) (void); + +init_fnc_t __initdata *init_all_device[] = { + ast_add_device_uart, + ast_add_device_vuart, + ast_add_device_watchdog, + ast_add_device_rtc, + ast_add_device_i2c, + ast_add_device_spi, + ast_add_device_ehci, + ast_add_device_nand, + ast_add_device_flash, + ast_add_device_pwm_fan, + ast_add_device_adc, + ast_add_device_gpio, + ast_add_device_sgpio, + ast_add_device_peci, + ast_add_device_fb, + ast_add_device_sdhci, + ast_add_device_uhci, + ast_add_device_video, + ast_add_device_kcs, + ast_add_device_mailbox, + ast_add_device_snoop, + ast_add_device_gmac, +// ast_add_device_nand, + NULL, +}; + +void __init ast_add_all_devices(void) +{ + init_fnc_t **init_fnc_ptr; + + for (init_fnc_ptr = init_all_device; *init_fnc_ptr; ++init_fnc_ptr) { + (*init_fnc_ptr)(); + } + + return; +} diff --git a/arch/arm/plat-aspeed/i2c-slave-eeprom.c b/arch/arm/plat-aspeed/i2c-slave-eeprom.c new file mode 100644 index 000000000000..fd53f1a664ae --- /dev/null +++ b/arch/arm/plat-aspeed/i2c-slave-eeprom.c @@ -0,0 +1,141 @@ +/******************************************************************************** +* File Name : linux/arch/arm/plat-aspeed/i2c-slave-eeprom.c +* Author : Ryan chen +* Description : ASPEED I2C Device +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2013/05/30 ryan chen create this file +* +********************************************************************************/ +#include <linux/i2c.h> +#if defined(CONFIG_COLDFIRE) +#include <asm/arch/ast_i2c.h> +#else +#include <plat/ast_i2c.h> +#endif + +#ifdef I2C_EEPROM +#define EEPROM_DBUG(fmt, args...) printk("%s() " fmt, __FUNCTION__, ## args) +#else +#define EEPROM_DBUG(fmt, args...) +#endif + +static u8 cmd_buf[1] = {0}; +static struct i2c_msg cmd_msg = { + .addr = 0x04, + .len = 1, + .buf = cmd_buf, +}; + +//Note 10 byte data memory share for all bus slave device ........... +#define BUF_SIZE 10 + +static u8 store_memory[BUF_SIZE] = {0x03,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09}; + // RO, RW, ................. +static struct i2c_msg data_msg = { + .addr = 0x04, + .len = BUF_SIZE, + .buf = store_memory, +}; +static u8 mem_index = 0; +static u8 slave_stage = INIT_STAGE; + +extern void i2c_slave_init(struct i2c_msg **msgs) +{ + *msgs = &cmd_msg; +} + +extern void i2c_slave_xfer(i2c_slave_event_t event, struct i2c_msg **msgs) +{ + EEPROM_DBUG("[event %d] \n",event); + switch(event) { + case I2C_SLAVE_EVENT_START_READ: + cmd_msg.flags = I2C_M_RD; + data_msg.flags = I2C_M_RD; + if(slave_stage == INIT_STAGE) { + EEPROM_DBUG("Rt DATA_MSG [%x]\n",data_msg.buf[0]); + slave_stage = DATA_STAGE; + *msgs = &data_msg; + } else { + //CMD_STAGE + if(cmd_msg.buf[0] != ((cmd_msg.addr << 1)|1)) + printk("START READ ADDR Error %x\n",cmd_msg.buf[0]); + + EEPROM_DBUG("Rt CMD_DATA_MSG data [%x]\n",store_memory[mem_index]); + cmd_msg.buf[0] = store_memory[mem_index]; + mem_index++; + mem_index %=BUF_SIZE; + slave_stage = CMD_DATA_STAGE; + *msgs = &cmd_msg; + } + break; + case I2C_SLAVE_EVENT_START_WRITE: + EEPROM_DBUG("Rt CMD_MSG START_WRITE %x\n",cmd_msg.buf[0]); + cmd_msg.flags = 0; + if(cmd_msg.buf[0] != cmd_msg.addr <<1) + printk("ERROR ADDRESS Match [%x] \n", cmd_msg.buf[0]); + slave_stage = CMD_STAGE; + + *msgs = &cmd_msg; + + break; + + case I2C_SLAVE_EVENT_WRITE: + cmd_msg.flags = 0; + if(slave_stage == CMD_STAGE) { + EEPROM_DBUG("w CMD = [index %x] \n",cmd_msg.buf[0]); + mem_index = cmd_msg.buf[0]; + mem_index %= BUF_SIZE; + slave_stage = CMD_DATA_STAGE; + *msgs = &cmd_msg; + } else { + EEPROM_DBUG("w index %d CMD_DATA [%x] \n",mem_index, cmd_msg.buf[0]); + if(mem_index !=0) + store_memory[mem_index] = cmd_msg.buf[0]; + mem_index++; + mem_index %=BUF_SIZE; + EEPROM_DBUG("Rt CMD_DATA_MSG \n"); + *msgs = &cmd_msg; + } + break; + case I2C_SLAVE_EVENT_READ: + cmd_msg.flags = I2C_M_RD; + if(slave_stage == CMD_DATA_STAGE) { + cmd_msg.buf[0] = store_memory[mem_index]; + mem_index++; + mem_index %=BUF_SIZE; + EEPROM_DBUG("Rt CMD_DATA_MSG [%x]\n",cmd_msg.buf[0]); + *msgs = &cmd_msg; + } else { + EEPROM_DBUG("Rt DATA_MSG [%x]\n",data_msg.buf[0]); + *msgs = &data_msg; + } + break; + case I2C_SLAVE_EVENT_NACK: + cmd_msg.flags = I2C_M_RD; + slave_stage = INIT_STAGE; + *msgs = &cmd_msg; + + break; + + case I2C_SLAVE_EVENT_STOP: + cmd_msg.flags = I2C_M_RD; + slave_stage = INIT_STAGE; + *msgs = &cmd_msg; + break; + } + +} diff --git a/arch/arm/plat-aspeed/include/plat/aspeed.h b/arch/arm/plat-aspeed/include/plat/aspeed.h new file mode 100644 index 000000000000..4f7c2400d0ce --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/aspeed.h @@ -0,0 +1,44 @@ +/* + * arch/arm/plat-aspeed/include/plat/aspeed.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#if defined(CONFIG_ARCH_AST3200) || defined(CONFIG_ARCH_AST2500) || defined(CONFIG_ARCH_AST1520) +#define AST_SOC_G5 +#define NEW_VIC +#define SRAM_SIZE SZ_32K +#elif defined(CONFIG_ARCH_AST1400) || defined(CONFIG_ARCH_AST2400) || defined(CONFIG_ARCH_AST3100) +#define AST_SOC_G4 +#define NEW_VIC +#define SRAM_SIZE SZ_32K +#elif defined(CONFIG_ARCH_AST1300) || defined(CONFIG_ARCH_AST2300) || defined(CONFIG_ARCH_AST1510) +#define AST_SOC_G3 +#define NEW_VIC +#define SRAM_SIZE SZ_16K +#elif defined(CONFIG_ARCH_AST2150) || defined(CONFIG_ARCH_AST2200) +#define AST_SOC_G2_5 +#elif defined(CONFIG_ARCH_AST1100) || defined(CONFIG_ARCH_AST2050) || defined(CONFIG_ARCH_AST2100) +#define AST_SOC_G2 +#elif defined(CONFIG_ARCH_AST2000) || defined(CONFIG_ARCH_AST1000) +#define AST_SOC_G1 +#else +#error "Not define SoC generation" +#endif + + + diff --git a/arch/arm/plat-aspeed/include/plat/ast-lpc.h b/arch/arm/plat-aspeed/include/plat/ast-lpc.h new file mode 100644 index 000000000000..1bf2befcf2fc --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/ast-lpc.h @@ -0,0 +1,34 @@ +/*
+ * Platform data for AST LPC .
+ *
+ * Copyright (C) ASPEED Technology Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+struct ast_lpc_bus_info
+{
+ u8 lpc_dev_mode; /* 0: host mode , 1: dev mode*/
+ u8 bus_scan;
+ u8 scan_node;
+ u8 lpc_mode; /* 0: lpc , 1: lpc+ */
+ u32 bridge_phy_addr;
+};
+
+struct ast_lpc_driver_data
+{
+ struct platform_device *pdev;
+ void __iomem *reg_base; /* virtual */
+ int irq; //I2C IRQ number
+ u32 bus_id; //for i2c dev# IRQ number check
+ struct ast_lpc_bus_info *bus_info;
+};
+
+extern struct ast_lpc_info *ast_get_lpc_info(void);
diff --git a/arch/arm/plat-aspeed/include/plat/ast-pcie.h b/arch/arm/plat-aspeed/include/plat/ast-pcie.h new file mode 100644 index 000000000000..d099c577ff72 --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/ast-pcie.h @@ -0,0 +1,28 @@ +/*
+ * Platform data for AST PCIe Root Complex module.
+ *
+ * Copyright (C) ASPEED Technology Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __AST_PCIE_H_
+#define __AST_PCIE_H_
+
+struct ast_pcie_data {
+ int msi_irq_base;
+ int msi_irq_num;
+ int force_x1;
+ int msi_inv; /* 1 = MSI ack requires "write 0 to clear" */
+ unsigned short int device_id;
+};
+
+#endif
+
diff --git a/arch/arm/plat-aspeed/include/plat/ast-scu.h b/arch/arm/plat-aspeed/include/plat/ast-scu.h new file mode 100644 index 000000000000..77169ee3279c --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/ast-scu.h @@ -0,0 +1,92 @@ +/******************************************************************************** +* File Name : arch/arm/mach-aspeed/include/plat/ast-scu.h +* Author : Ryan Chen +* Description : AST SCU Service Header +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/08/03 Ryan Chen create this file +* +********************************************************************************/ + +#ifndef __AST_SCU_H_INCLUDED +#define __AST_SCU_H_INCLUDED + +//information +extern void ast_scu_show_system_info (void); +extern u32 ast_scu_revision_id(void); +extern u32 ast_scu_get_phy_interface(u8 mac_num); +extern u32 ast_scu_get_phy_config(u8 mac_num); + + +//CLK +extern u32 ast_get_clk_source(void); +extern u32 ast_get_h_pll_clk(void); +extern u32 ast_get_m_pll_clk(void); +extern u32 ast_get_pclk(void); +extern u32 ast_get_sd_clock_src(void); +extern u32 ast_get_d2_pll_clk(void); +extern u32 ast_get_lhclk(void); + +extern void ast_scu_set_vga_display(u8 enable); +extern u32 ast_scu_get_vga_memsize(void); + +//Ctrl Initial +extern void ast_scu_init_video(u8 dynamic_en); +extern void ast_scu_reset_video(void); +extern void ast_scu_init_eth(u8 num); +extern void ast_scu_init_lpc(void); +extern u8 ast_scu_get_lpc_plus_enable(void); +extern void ast_scu_init_udc11(void); +extern void ast_scu_init_usb20(void); +extern void ast_scu_init_uhci(void); +extern void ast_scu_init_sdhci(void); +extern void ast_scu_init_i2c(void); +extern void ast_scu_init_pwm_tacho(void); +extern void ast_scu_init_adc(void); +extern void ast_scu_init_peci(void); +extern void ast_scu_init_jtag(void); +extern void ast_scu_init_crt(void); + + + +//Share pin +extern void ast_scu_multi_func_uart(u8 uart); +extern void ast_scu_multi_func_video(void); + +extern void ast_scu_multi_func_eth(u8 num); + +extern void ast_scu_multi_func_nand(void); + +extern void ast_scu_multi_func_nor(void); + +extern void ast_scu_multi_func_romcs(u8 num); + +extern void ast_scu_multi_func_i2c(void); +extern void ast_scu_multi_func_pwm_tacho(void); +//0 : hub mode , 1: usb host mode +extern void ast_scu_multi_func_usb20_host_hub(u8 mode); +//0 : gpioQ6,7 mode , 1: usb1.1 host port 4 mode +extern void ast_scu_multi_func_usb11_host_port4(u8 mode); +//0 : USB 1.1 HID mode , 1: usb1.1 host port 2 mode +extern void ast_scu_multi_func_usb11_host_port2(u8 mode); + +extern void ast_scu_multi_func_sdhc_slot1(u8 mode); +extern void ast_scu_multi_func_sdhc_slot2(u8 mode); +extern void ast_scu_multi_func_crt(void); + + + + + +#endif diff --git a/arch/arm/plat-aspeed/include/plat/ast-sdmc.h b/arch/arm/plat-aspeed/include/plat/ast-sdmc.h new file mode 100644 index 000000000000..72d8d724363a --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/ast-sdmc.h @@ -0,0 +1,26 @@ +/******************************************************************************** +* File Name : arch/arm/mach-aspeed/include/plat/ast-scu.h +* Author : Ryan Chen +* Description : AST SCU Service Header +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/08/03 Ryan Chen create this file +* +********************************************************************************/ + +#ifndef __AST_SDMC_H_INCLUDED +#define __AST_SDMC_H_INCLUDED + +extern u32 ast_sdmc_get_mem_size(void); +#endif diff --git a/arch/arm/plat-aspeed/include/plat/ast-snoop.h b/arch/arm/plat-aspeed/include/plat/ast-snoop.h new file mode 100644 index 000000000000..76ea76110da8 --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/ast-snoop.h @@ -0,0 +1,37 @@ +/*
+ * ast-snoop_h
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+struct ast_snoop_channel {
+ u8 snoop_ch;
+ u8 snoop_port;
+ u8 snoop_data;
+};
+
+struct ast_snoop {
+ struct ast_snoop_channel *snoop_ch0;
+ struct ast_snoop_channel *snoop_ch1;
+};
+
+struct ast_snoop_dma_channel {
+ u8 snoop_ch;
+ u8 snoop_port;
+ u8 snoop_mask;
+ u8 snoop_mode;
+ u8 snoop_index;
+ u32 dma_virt;
+ dma_addr_t dma_addr;
+ u16 dma_size;
+};
+
+extern int ast_snoop_init(struct ast_snoop *snoop);
+extern void ast_snoop_dma_init(struct ast_snoop_dma_channel *ast_dma_ch);
+
+
+
diff --git a/arch/arm/plat-aspeed/include/plat/ast1070-devs.h b/arch/arm/plat-aspeed/include/plat/ast1070-devs.h new file mode 100644 index 000000000000..b3aa799f4b14 --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/ast1070-devs.h @@ -0,0 +1,25 @@ +/******************************************************************************** +* arch/arm/plat-aspeed/include/plat/devs.h +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +********************************************************************************/ +#ifndef __ASM_PLAT_AST1070_H +#define __ASM_PLAT_AST1070_H + +//ast1070 +extern void __init ast_add_device_cuart(u8 chip, u32 lpc_base); +extern void __init ast_add_device_clpc(u8 chip, u32 lpc_base); +extern void __init ast_add_device_ci2c(u8 chip, u32 lpc_base); + +#endif diff --git a/arch/arm/plat-aspeed/include/plat/ast1070-scu.h b/arch/arm/plat-aspeed/include/plat/ast1070-scu.h new file mode 100644 index 000000000000..70c63e24888f --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/ast1070-scu.h @@ -0,0 +1,34 @@ +/******************************************************************************** +* File Name : arch/arm/mach-aspeed/include/plat/ast1070-scu.h +* Author : Ryan Chen +* Description : AST1070 SCU Service Header +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2013/05/03 Ryan Chen create this file +* +********************************************************************************/ + +#ifndef __AST1070_SCU_H_INCLUDED +#define __AST1070_SCU_H_INCLUDED + +extern void ast1070_scu_init_i2c(u8 node); +extern void ast1070_scu_init_uart(u8 node); +extern void ast1070_scu_revision_id(u8 node); +extern void ast1070_dma_init(u8 node); +extern void ast1070_multi_func_uart(u8 node, u8 uart); + + + + +#endif diff --git a/arch/arm/plat-aspeed/include/plat/ast1070-uart-dma.h b/arch/arm/plat-aspeed/include/plat/ast1070-uart-dma.h new file mode 100644 index 000000000000..c4edd7528dc0 --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/ast1070-uart-dma.h @@ -0,0 +1,27 @@ +/******************************************************************************** +* File Name : arch/arm/mach-aspeed/include/plat/ast1070-scu.h +* Author : Ryan Chen +* Description : AST1070 SCU Service Header +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2013/05/03 Ryan Chen create this file +* +********************************************************************************/ + +#ifndef __AST1070_UART_DMA_H_INCLUDED +#define __AST1070_UART_DMA_H_INCLUDED + +extern void ast1070_uart_dma_init(u8 node); + +#endif diff --git a/arch/arm/plat-aspeed/include/plat/ast_i2c.h b/arch/arm/plat-aspeed/include/plat/ast_i2c.h new file mode 100644 index 000000000000..b0ff995c2b24 --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/ast_i2c.h @@ -0,0 +1,64 @@ +/*
+ * ast_i2c_h
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+//I2C MEMORY Device state machine
+typedef enum i2c_slave_stage {
+ INIT_STAGE,
+ CMD_STAGE,
+ CMD_DATA_STAGE,
+ DATA_STAGE
+} stage;
+
+typedef enum i2c_xfer_mode {
+ BYTE_XFER,
+ BUFF_XFER,
+ DMA_XFER
+} i2c_xfer_mode_t;
+
+//1. usage flag , 2 size, 3. request address
+struct buf_page
+{
+ u8 flag; //0:free to usage, 1: used
+ u8 page_no; //for AST2400 usage
+ u16 page_size;
+ u32 page_addr;
+ u32 page_addr_point;
+};
+
+typedef enum i2c_slave_event_e {
+ I2C_SLAVE_EVENT_START_READ,
+ I2C_SLAVE_EVENT_READ,
+ I2C_SLAVE_EVENT_START_WRITE,
+ I2C_SLAVE_EVENT_WRITE,
+ I2C_SLAVE_EVENT_NACK,
+ I2C_SLAVE_EVENT_STOP
+} i2c_slave_event_t;
+
+#define BYTE_MODE 0
+#define BUFF_MODE 1
+#define DMA_MODE 2
+
+struct ast_i2c_driver_data {
+ void __iomem *reg_gr;
+ u32 bus_clk;
+ u8 master_dma; //0,byte mode 1,Buffer pool mode 256 , or 2048 , 2: DMA mode
+ u8 slave_dma; //0,byte mode 1,Buffer pool mode 256 , or 2048 , 2: DMA mode
+ u8 (*request_pool_buff_page)(struct buf_page **page);
+ void (*free_pool_buff_page)(struct buf_page *page);
+ unsigned char *buf_pool;
+ void (*slave_xfer)(i2c_slave_event_t event, struct i2c_msg **msgs);
+ void (*slave_init)(struct i2c_msg **msgs);
+ u32 (*get_i2c_clock)(void);
+};
+
+#ifdef CONFIG_AST_I2C_SLAVE_MODE
+extern void i2c_slave_init(struct i2c_msg **msgs);
+extern void i2c_slave_xfer(i2c_slave_event_t event, struct i2c_msg **msgs);
+#endif
\ No newline at end of file diff --git a/arch/arm/plat-aspeed/include/plat/ast_mctp.h b/arch/arm/plat-aspeed/include/plat/ast_mctp.h new file mode 100644 index 000000000000..51396ff4d0ab --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/ast_mctp.h @@ -0,0 +1,31 @@ +/******************************************************************************** +* File Name : arch/arm/mach-aspeed/include/plat/ast-scu.h +* Author : Ryan Chen +* Description : AST SCU Service Header +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/08/03 Ryan Chen create this file +* +********************************************************************************/ + +#ifndef __AST_P2X_H_INCLUDED +#define __AST_P2X_H_INCLUDED + +extern void ast_pcie_cfg_read(u8 type, u32 bdf_offset, u32 *value); +//extern void ast_pcie_cfg_write(u8 type, u32 bdf_offset, u32 data); +extern void ast_pcie_cfg_write(u8 type, u8 byte_en, u32 bdf_offset, u32 data); +extern void ast_mctp_addr_map(u32 mask, u32 addr); + +#endif + diff --git a/arch/arm/plat-aspeed/include/plat/ast_sdhci.h b/arch/arm/plat-aspeed/include/plat/ast_sdhci.h new file mode 100644 index 000000000000..13547af85f91 --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/ast_sdhci.h @@ -0,0 +1,290 @@ +/*
+ * sdhci.h - Secure Digital Host Controller Interface driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+#include <linux/scatterlist.h>
+#include <linux/leds.h>
+#include <linux/interrupt.h>
+
+
+/*
+ * Controller registers
+ */
+
+#define SDHCI_DMA_ADDRESS 0x00
+
+#define SDHCI_BLOCK_SIZE 0x04
+#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
+
+#define SDHCI_BLOCK_COUNT 0x06
+
+#define SDHCI_ARGUMENT 0x08
+
+#define SDHCI_TRANSFER_MODE 0x0C
+#define SDHCI_TRNS_DMA 0x01
+#define SDHCI_TRNS_BLK_CNT_EN 0x02
+#define SDHCI_TRNS_ACMD12 0x04
+#define SDHCI_TRNS_READ 0x10
+#define SDHCI_TRNS_MULTI 0x20
+
+#define SDHCI_COMMAND 0x0E
+#define SDHCI_CMD_RESP_MASK 0x03
+#define SDHCI_CMD_CRC 0x08
+#define SDHCI_CMD_INDEX 0x10
+#define SDHCI_CMD_DATA 0x20
+
+#define SDHCI_CMD_RESP_NONE 0x00
+#define SDHCI_CMD_RESP_LONG 0x01
+#define SDHCI_CMD_RESP_SHORT 0x02
+#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
+
+#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
+
+#define SDHCI_RESPONSE 0x10
+
+#define SDHCI_BUFFER 0x20
+
+#define SDHCI_PRESENT_STATE 0x24
+#define SDHCI_CMD_INHIBIT 0x00000001
+#define SDHCI_DATA_INHIBIT 0x00000002
+#define SDHCI_DOING_WRITE 0x00000100
+#define SDHCI_DOING_READ 0x00000200
+#define SDHCI_SPACE_AVAILABLE 0x00000400
+#define SDHCI_DATA_AVAILABLE 0x00000800
+#define SDHCI_CARD_PRESENT 0x00010000
+#define SDHCI_WRITE_PROTECT 0x00080000
+
+#define SDHCI_HOST_CONTROL 0x28
+#define SDHCI_CTRL_LED 0x01
+#define SDHCI_CTRL_4BITBUS 0x02
+#define SDHCI_CTRL_HISPD 0x04
+#define SDHCI_CTRL_DMA_MASK 0x18
+#define SDHCI_CTRL_SDMA 0x00
+#define SDHCI_CTRL_ADMA1 0x08
+#define SDHCI_CTRL_ADMA32 0x10
+#define SDHCI_CTRL_ADMA64 0x18
+
+#define SDHCI_POWER_CONTROL 0x29
+#define SDHCI_POWER_ON 0x01
+#define SDHCI_POWER_180 0x0A
+#define SDHCI_POWER_300 0x0C
+#define SDHCI_POWER_330 0x0E
+
+#define SDHCI_BLOCK_GAP_CONTROL 0x2A
+
+#define SDHCI_WAKE_UP_CONTROL 0x2B
+
+#define SDHCI_CLOCK_CONTROL 0x2C
+#define SDHCI_DIVIDER_SHIFT 8
+#define SDHCI_CLOCK_CARD_EN 0x0004
+#define SDHCI_CLOCK_INT_STABLE 0x0002
+#define SDHCI_CLOCK_INT_EN 0x0001
+
+#define SDHCI_TIMEOUT_CONTROL 0x2E
+
+#define SDHCI_SOFTWARE_RESET 0x2F
+#define SDHCI_RESET_ALL 0x01
+#define SDHCI_RESET_CMD 0x02
+#define SDHCI_RESET_DATA 0x04
+
+#define SDHCI_INT_STATUS 0x30
+#define SDHCI_INT_ENABLE 0x34
+#define SDHCI_SIGNAL_ENABLE 0x38
+#define SDHCI_INT_RESPONSE 0x00000001
+#define SDHCI_INT_DATA_END 0x00000002
+#define SDHCI_INT_DMA_END 0x00000008
+#define SDHCI_INT_SPACE_AVAIL 0x00000010
+#define SDHCI_INT_DATA_AVAIL 0x00000020
+#define SDHCI_INT_CARD_INSERT 0x00000040
+#define SDHCI_INT_CARD_REMOVE 0x00000080
+#define SDHCI_INT_CARD_INT 0x00000100
+#define SDHCI_INT_ERROR 0x00008000
+#define SDHCI_INT_TIMEOUT 0x00010000
+#define SDHCI_INT_CRC 0x00020000
+#define SDHCI_INT_END_BIT 0x00040000
+#define SDHCI_INT_INDEX 0x00080000
+#define SDHCI_INT_DATA_TIMEOUT 0x00100000
+#define SDHCI_INT_DATA_CRC 0x00200000
+#define SDHCI_INT_DATA_END_BIT 0x00400000
+#define SDHCI_INT_BUS_POWER 0x00800000
+#define SDHCI_INT_ACMD12ERR 0x01000000
+#define SDHCI_INT_ADMA_ERROR 0x02000000
+
+#define SDHCI_INT_NORMAL_MASK 0x00007FFF
+#define SDHCI_INT_ERROR_MASK 0xFFFF8000
+
+#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
+ SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
+#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
+ SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
+ SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
+ SDHCI_INT_DATA_END_BIT)
+
+#define SDHCI_ACMD12_ERR 0x3C
+
+/* 3E-3F reserved */
+
+#define SDHCI_CAPABILITIES 0x40
+#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
+#define SDHCI_TIMEOUT_CLK_SHIFT 0
+#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
+#define SDHCI_CLOCK_BASE_MASK 0x00003F00
+#define SDHCI_CLOCK_BASE_SHIFT 8
+#define SDHCI_MAX_BLOCK_MASK 0x00030000
+#define SDHCI_MAX_BLOCK_SHIFT 16
+#define SDHCI_CAN_DO_ADMA2 0x00080000
+#define SDHCI_CAN_DO_ADMA1 0x00100000
+#define SDHCI_CAN_DO_HISPD 0x00200000
+#define SDHCI_CAN_DO_DMA 0x00400000
+#define SDHCI_CAN_VDD_330 0x01000000
+#define SDHCI_CAN_VDD_300 0x02000000
+#define SDHCI_CAN_VDD_180 0x04000000
+#define SDHCI_CAN_64BIT 0x10000000
+
+/* 44-47 reserved for more caps */
+
+#define SDHCI_MAX_CURRENT 0x48
+
+/* 4C-4F reserved for more max current */
+
+#define SDHCI_SET_ACMD12_ERROR 0x50
+#define SDHCI_SET_INT_ERROR 0x52
+
+#define SDHCI_ADMA_ERROR 0x54
+
+/* 55-57 reserved */
+
+#define SDHCI_ADMA_ADDRESS 0x58
+
+/* 60-FB reserved */
+
+#define SDHCI_SLOT_INT_STATUS 0xFC
+
+#define SDHCI_HOST_VERSION 0xFE
+#define SDHCI_VENDOR_VER_MASK 0xFF00
+#define SDHCI_VENDOR_VER_SHIFT 8
+#define SDHCI_SPEC_VER_MASK 0x00FF
+#define SDHCI_SPEC_VER_SHIFT 0
+#define SDHCI_SPEC_100 0
+#define SDHCI_SPEC_200 1
+
+struct sdhci_ops;
+
+struct sdhci_host {
+ /* Data set by hardware interface driver */
+ const char *hw_name; /* Hardware bus name */
+
+ unsigned int quirks; /* Deviations from spec. */
+
+/* Controller doesn't honor resets unless we touch the clock register */
+#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
+/* Controller has bad caps bits, but really supports DMA */
+#define SDHCI_QUIRK_FORCE_DMA (1<<1)
+/* Controller doesn't like to be reset when there is no card inserted. */
+#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
+/* Controller doesn't like clearing the power reg before a change */
+#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
+/* Controller has flaky internal state so reset it on each ios change */
+#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
+/* Controller has an unusable DMA engine */
+#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
+/* Controller has an unusable ADMA engine */
+#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
+/* Controller can only DMA from 32-bit aligned addresses */
+#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
+/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
+#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
+/* Controller can only ADMA chunks that are a multiple of 32 bits */
+#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
+/* Controller needs to be reset after each request to stay stable */
+#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
+/* Controller needs voltage and power writes to happen separately */
+#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
+/* Controller provides an incorrect timeout value for transfers */
+#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
+/* Controller has an issue with buffer bits for small transfers */
+#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
+/* Controller supports high speed but doesn't have the caps bit set */
+#define SDHCI_QUIRK_FORCE_HIGHSPEED (1<<14)
+/* Controller does not provide transfer-complete interrupt when not busy */
+#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<15)
+
+ int irq; /* Device IRQ */
+ void __iomem * ioaddr; /* Mapped address */
+
+ const struct sdhci_ops *ops; /* Low level hw interface */
+
+ /* Internal data */
+ struct mmc_host *mmc; /* MMC structure */
+ u64 dma_mask; /* custom DMA mask */
+
+#ifdef CONFIG_LEDS_CLASS
+ struct led_classdev led; /* LED control */
+ char led_name[32];
+#endif
+
+ spinlock_t lock; /* Mutex */
+
+ int flags; /* Host attributes */
+#define SDHCI_USE_DMA (1<<0) /* Host is DMA capable */
+#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
+#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
+#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
+
+ unsigned int version; /* SDHCI spec. version */
+
+ unsigned int max_clk; /* Max possible freq (MHz) */
+ unsigned int timeout_clk; /* Timeout freq (KHz) */
+
+ unsigned int clock; /* Current clock (MHz) */
+ unsigned short power; /* Current voltage */
+
+ struct mmc_request *mrq; /* Current request */
+ struct mmc_command *cmd; /* Current command */
+ struct mmc_data *data; /* Current data request */
+ unsigned int data_early:1; /* Data finished before cmd */
+
+ struct sg_mapping_iter sg_miter; /* SG state for PIO */
+ unsigned int blocks; /* remaining PIO blocks */
+
+ int sg_count; /* Mapped sg entries */
+
+ u8 *adma_desc; /* ADMA descriptor table */
+ u8 *align_buffer; /* Bounce buffer */
+
+ dma_addr_t adma_addr; /* Mapped ADMA descr. table */
+ dma_addr_t align_addr; /* Mapped bounce buffer */
+
+ struct tasklet_struct card_tasklet; /* Tasklet structures */
+ struct tasklet_struct finish_tasklet;
+
+ struct timer_list timer; /* Timer for timeouts */
+
+ unsigned long private[0] ____cacheline_aligned;
+};
+
+struct ast_sdhc_platform_data {
+ u32 (*sd_clock_src_get)(void);
+};
+
+extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
+ size_t priv_size);
+extern void sdhci_free_host(struct sdhci_host *host);
+
+static inline void *sdhci_priv(struct sdhci_host *host)
+{
+ return (void *)host->private;
+}
+
+extern int sdhci_add_host(struct sdhci_host *host);
+extern void sdhci_remove_host(struct sdhci_host *host, int dead);
+
+#ifdef CONFIG_PM
+extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
+extern int sdhci_resume_host(struct sdhci_host *host);
+#endif
diff --git a/arch/arm/plat-aspeed/include/plat/devs.h b/arch/arm/plat-aspeed/include/plat/devs.h new file mode 100644 index 000000000000..41cbea934421 --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/devs.h @@ -0,0 +1,65 @@ +/******************************************************************************** +* arch/arm/plat-aspeed/include/plat/devs.h +* +* Copyright (C) ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +********************************************************************************/ +#ifndef __ASM_PLAT_ASPEED_H +#define __ASM_PLAT_ASPEED_H + +extern void __init ast_add_all_devices(void); + +//platform +extern void __init ast_add_device_uart(void); +extern void __init ast_add_device_vuart(void); +extern void __init ast_add_device_watchdog(void); +extern void __init ast_add_device_rtc(void); +extern void __init ast_add_device_gpio(void); +extern void __init ast_add_device_sgpio(void); + +//ADC + +//Bus +extern void __init ast_add_device_lpc(void); +extern void __init ast_add_device_snoop(void); +extern void __init ast_add_device_kcs(void); +extern void __init ast_add_device_mailbox(void); +extern void __init ast_add_device_i2c(void); +extern void __init ast_add_device_spi(void); +extern void __init ast_add_device_ehci(void); +extern void __init ast_add_device_uhci(void); +extern void __init ast_add_device_gmac(void); +extern void __init ast_add_device_udc11(void); +extern void __init ast_add_device_hid(void); + +extern void __init ast_add_device_pcie(void); + +extern void __init ast_add_device_peci(void); +extern void __init ast_add_device_jtag(void); + +//hwmon +extern void __init ast_add_device_pwm_fan(void); +extern void __init ast_add_device_adc(void); + + +//Storage +extern void __init ast_add_device_nand(void); +extern void __init ast_add_device_flash(void); +extern void __init ast_add_device_sdhci(void); +extern void __init ast_add_device_nand(void); + +//video +extern void __init ast_add_device_fb(void); +extern void __init ast_add_device_video(void); + +#endif diff --git a/arch/arm/plat-aspeed/include/plat/regs-1070_lpc.h b/arch/arm/plat-aspeed/include/plat/regs-1070_lpc.h new file mode 100644 index 000000000000..ef8cd8c04973 --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-1070_lpc.h @@ -0,0 +1,32 @@ +/* arch/arm/plat-aspeed/include/mach/regs-1070_lpc.h + * + * Copyright (c) 2012 ASPEED Technology Inc. <ryan_chen@aspeedtech.com> + * http://www.aspeedtech.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ASPEED AST1070 LPC Controller +*/ + +#ifndef __ASM_ARCH_REGS_LPC_H +#define __ASM_ARCH_REGS_LPC_H __FILE__ + +#define AST1070_LPC_HICR0 0x00 +#define AST1070_LPC_HICR1 0x04 +#define AST1070_LPC_HICR2 0x08 +#define AST1070_LPC_HICR3 0x0c +#define AST1070_LPC_HICR4 0x10 + +//for snoop driver +#define AST1070_LPC_L_80H_ADDR 0x220 +#define AST1070_LPC_H_80H_ADDR 0x224 +#define AST1070_LPC_80H_DATA 0x228 +#define AST1070_LPC_80H_CTRL 0x22c + + +#define AST1070_LPC_80H_CLR (0x1 << 4) + +#define AST1070_LPC_80H_EN 0x1 +#endif /* __ASM_ARCH_REGS_LPC_H */ diff --git a/arch/arm/plat-aspeed/include/plat/regs-adc.h b/arch/arm/plat-aspeed/include/plat/regs-adc.h new file mode 100644 index 000000000000..97f5919036be --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-adc.h @@ -0,0 +1,191 @@ +/* arch/arm/plat-aspeed/include/mach/regs-adc.h + * + * Copyright (c) 2012 ASPEED Technology Inc. <ryan_chen@aspeedtech.com> + * http://www.aspeedtech.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ASPEED ADC Controller +*/ + +#ifndef __ASM_ARCH_REGS_ADC_H +#define __ASM_ARCH_REGS_ADC_H __FILE__ + +#if defined(CONFIG_ARCH_AST2300) +#define MAX_CH_NO 12 +#elif defined(CONFIG_ARCH_AST2400) || defined(CONFIG_ARCH_AST2500) +#define MAX_CH_NO 16 +#elif defined(CONFIG_ARCH_AST1010) +#define MAX_CH_NO 8 +#else +#err "ADC NO define MAX CHANNEL NO" +#endif + +#if defined(CONFIG_ARCH_AST2500) +#define TEMPER_CH_NO 2 +#endif + +/*AST ADC Register Definition */ +#define AST_ADC_CTRL 0x00 +#define AST_ADC_IER 0x04 +#define AST_ADC_VGA 0x08 +#if defined(CONFIG_ARCH_AST1010) +#define AST_ADC_TRIM 0x08 +#endif +#define AST_ADC_CLK 0x0c +#define AST_ADC_CH0_1 0x10 +#define AST_ADC_CH2_3 0x14 +#define AST_ADC_CH4_5 0x18 +#define AST_ADC_CH6_7 0x1c +#define AST_ADC_CH8_9 0x20 +#define AST_ADC_CH10_11 0x24 +#define AST_ADC_CH12_13 0x28 +#define AST_ADC_CH14_15 0x2c +#define AST_ADC_BOUND0 0x30 +#define AST_ADC_BOUND1 0x34 +#define AST_ADC_BOUND2 0x38 +#define AST_ADC_BOUND3 0x3c +#define AST_ADC_BOUND4 0x40 +#define AST_ADC_BOUND5 0x44 +#define AST_ADC_BOUND6 0x48 +#define AST_ADC_BOUND7 0x4c +#define AST_ADC_BOUND8 0x50 +#define AST_ADC_BOUND9 0x54 +#define AST_ADC_BOUND10 0x58 +#define AST_ADC_BOUND11 0x5c +#define AST_ADC_BOUND12 0x60 +#define AST_ADC_BOUND13 0x64 +#define AST_ADC_BOUND14 0x68 +#define AST_ADC_BOUND15 0x6c +#define AST_ADC_HYSTER0 0x70 +#define AST_ADC_HYSTER1 0x74 +#define AST_ADC_HYSTER2 0x78 +#define AST_ADC_HYSTER3 0x7c +#define AST_ADC_HYSTER4 0x80 +#define AST_ADC_HYSTER5 0x84 +#define AST_ADC_HYSTER6 0x88 +#define AST_ADC_HYSTER7 0x8c +#define AST_ADC_HYSTER8 0x90 +#define AST_ADC_HYSTER9 0x94 +#define AST_ADC_HYSTER10 0x98 +#define AST_ADC_HYSTER11 0x9c +#define AST_ADC_HYSTER12 0xa0 +#define AST_ADC_HYSTER13 0xa4 +#define AST_ADC_HYSTER14 0xa8 +#define AST_ADC_HYSTER15 0xac +#define AST_ADC_INTR_SEL 0xC0 +#if defined(CONFIG_ARCH_AST2500) +#define AST_ADC_CH16 0xD0 +#define AST_ADC_CH17 0xD4 +#endif + + +#define AST_ADC_TRIM 0xC4 + +// AST_ADC_CTRL:0x00 - ADC Engine Control Register +#define AST_ADC_CTRL_CH15_EN (0x1 << 31) +#define AST_ADC_CTRL_CH14_EN (0x1 << 30) +#define AST_ADC_CTRL_CH13_EN (0x1 << 29) +#define AST_ADC_CTRL_CH12_EN (0x1 << 28) +#define AST_ADC_CTRL_CH11_EN (0x1 << 27) +#define AST_ADC_CTRL_CH10_EN (0x1 << 26) +#define AST_ADC_CTRL_CH9_EN (0x1 << 25) +#define AST_ADC_CTRL_CH8_EN (0x1 << 24) +#define AST_ADC_CTRL_CH7_EN (0x1 << 23) +#define AST_ADC_CTRL_CH6_EN (0x1 << 22) +#define AST_ADC_CTRL_CH5_EN (0x1 << 21) +#define AST_ADC_CTRL_CH4_EN (0x1 << 20) +#define AST_ADC_CTRL_CH3_EN (0x1 << 19) +#define AST_ADC_CTRL_CH2_EN (0x1 << 18) +#define AST_ADC_CTRL_CH1_EN (0x1 << 17) +#define AST_ADC_CTRL_CH0_EN (0x1 << 16) + +#if defined(CONFIG_ARCH_AST2300) +#define AST_ADC_CTRL_COMPEN_CLR (0x1 << 6) +#define AST_ADC_CTRL_COMPEN (0x1 << 5) +#elif defined(CONFIG_ARCH_AST2400) +#define AST_ADC_CTRL_COMPEN (0x1 << 4) +#elif defined(CONFIG_ARCH_AST2500) +#define AST_ADC_CTRL_INIT_RDY (0x1 << 8) +#define AST_ADC_CTRL_COMPEN (0x1 << 5) +#else +#err "ERROR define COMPEN ADC" +#endif + +#if defined(CONFIG_ARCH_AST1010) +#define AST_ADC_CTRL_OTP (0x1 << 3) +#define AST_ADC_CTRL_PWR_DWN (0x1 << 2) +#define AST_ADC_CTRL_TEST (0x1 << 1) +#endif + +#define AST_ADC_CTRL_NORMAL (0x7 << 1) + +#define AST_ADC_CTRL_EN (0x1) + + +/* AST_ADC_IER : 0x04 - Interrupt Enable and Interrupt status */ +#define AST_ADC_IER_CH15 (0x1 << 31) +#define AST_ADC_IER_CH14 (0x1 << 30) +#define AST_ADC_IER_CH13 (0x1 << 29) +#define AST_ADC_IER_CH12 (0x1 << 28) +#define AST_ADC_IER_CH11 (0x1 << 27) +#define AST_ADC_IER_CH10 (0x1 << 26) +#define AST_ADC_IER_CH9 (0x1 << 25) +#define AST_ADC_IER_CH8 (0x1 << 24) +#define AST_ADC_IER_CH7 (0x1 << 23) +#define AST_ADC_IER_CH6 (0x1 << 22) +#define AST_ADC_IER_CH5 (0x1 << 21) +#define AST_ADC_IER_CH4 (0x1 << 20) +#define AST_ADC_IER_CH3 (0x1 << 19) +#define AST_ADC_IER_CH2 (0x1 << 18) +#define AST_ADC_IER_CH1 (0x1 << 17) +#define AST_ADC_IER_CH0 (0x1 << 16) +#define AST_ADC_STS_CH15 (0x1 << 15) +#define AST_ADC_STS_CH14 (0x1 << 14) +#define AST_ADC_STS_CH13 (0x1 << 13) +#define AST_ADC_STS_CH12 (0x1 << 12) +#define AST_ADC_STS_CH11 (0x1 << 11) +#define AST_ADC_STS_CH10 (0x1 << 10) +#define AST_ADC_STS_CH9 (0x1 << 9) +#define AST_ADC_STS_CH8 (0x1 << 8) +#define AST_ADC_STS_CH7 (0x1 << 7) +#define AST_ADC_STS_CH6 (0x1 << 6) +#define AST_ADC_STS_CH5 (0x1 << 5) +#define AST_ADC_STS_CH4 (0x1 << 4) +#define AST_ADC_STS_CH3 (0x1 << 3) +#define AST_ADC_STS_CH2 (0x1 << 2) +#define AST_ADC_STS_CH1 (0x1 << 1) +#define AST_ADC_STS_CH0 (0x1) + +/* AST_ADC_VGA : 0x08 - VGA Detect Control */ +#define AST_ADC_VGA_EN (0x1 << 16) +#define AST_ADC_VGA_DIV_MASK (0x3ff) + +/* AST_ADC_CLK : 0x0c - ADC CLK Control */ +#define AST_ADC_CLK_PRE_DIV_MASK (0x7fff << 17) +#define AST_ADC_CLK_PRE_DIV (0x1 << 17) +#define AST_ADC_CLK_INVERT (0x1 << 16) //only for ast2300 +#define AST_ADC_CLK_DIV_MASK (0x3ff) + +#define AST_ADC_H_CH_MASK (0x3ff << 16) +#define AST_ADC_L_CH_MASK (0x3ff) + +#define AST_ADC_H_BOUND (0x3ff << 16) +#define AST_ADC_L_BOUND (0x3ff) + +#define AST_ADC_HYSTER_EN (0x1 << 31) + +#if defined(CONFIG_ARCH_AST2500) +/* AST_ADC_CH16 : 0xD0 - */ +/* AST_ADC_CH17 : 0xD4 - */ +#define AST_TEMP_CH_RDY (0x1 << 31) +#define AST_GET_TEMP_A_MASK(x) ((x >>16) & 0xfff) +#define AST_TEMP_CH_EN (0x1 << 15) +#define AST_GET_TEMP_B_MASK(x) (x & 0xfff) + + +#endif + +#endif /* __ASM_ARCH_REGS_ADC_H */ diff --git a/arch/arm/plat-aspeed/include/plat/regs-ast1070-intc.h b/arch/arm/plat-aspeed/include/plat/regs-ast1070-intc.h new file mode 100644 index 000000000000..00dd1cba2c9f --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-ast1070-intc.h @@ -0,0 +1,42 @@ +/* arch/arm/mach-aspeed/include/mach/regs-intr.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * History : + * 1. 2012/08/15 Ryan Chen Create + * +********************************************************************************/ +#ifndef __ASPEED_AST1070_INTR_H +#define __ASPEED_AST1070_INTR_H 1 + +#include <asm/io.h> +#include <mach/platform.h> +#include <mach/irqs.h> + +/* + * VIC Register (VA) + */ + +#define VIC_BASE_VA(x) IO_ADDRESS2(AST_C0_VIC_BASE + (0x10000*x)) + +#define AST_IRQ_STS(x) (VIC_BASE_VA(x) + 0x00) +#define AST_RAW_STS(x) (VIC_BASE_VA(x) + 0x08) +#define AST_INTR_EN(x) (VIC_BASE_VA(x) + 0x10) +#define AST_INTR_DIS(x) (VIC_BASE_VA(x) + 0x14) +#define AST_INTR_SENSE(x) (VIC_BASE_VA(x) + 0x24) +#define AST_INTR_BOTH_EDGE(x) (VIC_BASE_VA(x) + 0x28) +#define AST_INTR_EVENT(x) (VIC_BASE_VA(x) + 0x2C) + +#define IRQ_SET_LEVEL_TRIGGER(x,irq_no) *((volatile unsigned long*)AST_INTR_SENSE(x)) |= 1 << (irq_no) +#define IRQ_SET_EDGE_TRIGGER(x,irq_no) *((volatile unsigned long*)AST_INTR_SENSE(x)) &= ~(1 << (irq_no)) +#define IRQ_SET_RISING_EDGE(x,irq_no) *((volatile unsigned long*)AST_INTR_EVENT(x)) |= 1 << (irq_no) +#define IRQ_SET_FALLING_EDGE(x,irq_no) *((volatile unsigned long*)AST_INTR_EVENT(x)) &= ~(1 << (irq_no)) +#define IRQ_SET_HIGH_LEVEL(x,irq_no) *((volatile unsigned long*)AST_INTR_EVENT(x)) |= 1 << (irq_no) +#define IRQ_SET_LOW_LEVEL(x,irq_no) *((volatile unsigned long*)AST_INTR_EVENT(x)) &= ~(1 << (irq_no)) + + +#endif diff --git a/arch/arm/plat-aspeed/include/plat/regs-ast1070-lpc.h b/arch/arm/plat-aspeed/include/plat/regs-ast1070-lpc.h new file mode 100644 index 000000000000..22f84756d5eb --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-ast1070-lpc.h @@ -0,0 +1,117 @@ +/* arch/arm/plat-aspeed/include/mach/regs-lpc.h + * + * Copyright (c) 2012 ASPEED Technology Inc. <ryan_chen@aspeedtech.com> + * http://www.aspeedtech.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ASPEED LPC Controller +*/ + +#ifndef __AST1070_LPC_H_ +#define __AST1070_LPC_H_ + +#define AST_LPC_HICR0 0x000 +#define AST_LPC_HICR1 0x004 +#define AST_LPC_HICR2 0x008 +#define AST_LPC_HICR3 0x00C +#define AST_LPC_HICR4 0x010 +#define AST_LPC_LADR3H 0x014 +#define AST_LPC_LADR3L 0x018 +#define AST_LPC_LADR12H 0x01C +#define AST_LPC_LADR12L 0x020 +#define AST_LPC_IDR1 0x024 +#define AST_LPC_IDR2 0x028 +#define AST_LPC_IDR3 0x02C +#define AST_LPC_ODR1 0x030 +#define AST_LPC_ODR2 0x034 +#define AST_LPC_ODR3 0x038 +#define AST_LPC_STR1 0x03C +#define AST_LPC_STR2 0x040 +#define AST_LPC_STR3 0x044 +//// +#define AST_LPC_SIRQCR0 0x048 +#define AST_LPC_SIRQCR1 0x04C +#define AST_LPC_SIRQCR2 0x050 +#define AST_LPC_SIRQCR3 0x06C +//// +#define AST_LPC_ADR1 0x070 +#define AST_LPC_IRQ1 0x074 +#define AST_LPC_ADR2 0x078 +#define AST_LPC_IRQ2 0x07C +#define AST_LPC_ADR3 0x080 +#define AST_LPC_IRQ3 0x084 + +#define AST_LPC_DEV_ADDRM0 0x100 +#define AST_LPC_DEV_ADDRM1 0x104 +#define AST_LPC_DEV_ADDRM2 0x108 +#define AST_LPC_DEV_ADDRM3 0x10C +#define AST_LPC_DEV_ADDR0 0x110 +#define AST_LPC_DEV_ADDR1 0x114 +#define AST_LPC_DEV_ADDR2 0x118 +#define AST_LPC_DEV_ADDR3 0x11C +#define AST_LPC_DEC_ADDR0 0x120 +#define AST_LPC_DEC_ADDR1 0x124 +#define AST_LPC_DEC_RANGE0 0x128 +#define AST_LPC_DEC_RANGE1 0x12C + +#define AST_LPC_MBXDAT0 0x180 +#define AST_LPC_MBXDAT1 0x184 +#define AST_LPC_MBXDAT2 0x188 +#define AST_LPC_MBXDAT3 0x18C +#define AST_LPC_MBXDAT4 0x190 +#define AST_LPC_MBXDAT5 0x194 +#define AST_LPC_MBXDAT6 0x198 +#define AST_LPC_MBXDAT7 0x19C +#define AST_LPC_MBXDAT8 0x1A0 +#define AST_LPC_MBXDAT9 0x1A4 +#define AST_LPC_MBXDATA 0x1A8 +#define AST_LPC_MBXDATB 0x1AC +#define AST_LPC_MBXDATC 0x1B0 +#define AST_LPC_MBXDATD 0x1B4 +#define AST_LPC_MBXDATE 0x1B8 +#define AST_LPC_MBXDATF 0x1BC + +#define AST_LPC_MBXSTS0 0x1C0 +#define AST_LPC_MBXSTS1 0x1C4 + +#define AST_LPC_MBXBICR 0x1C8 +#define AST_LPC_MBXHICR 0x1CC +#define AST_LPC_MBXBIE0 0x1D0 +#define AST_LPC_MBXBIE1 0x1D4 +#define AST_LPC_MBXHIE0 0x1D8 +#define AST_LPC_MBXHIE1 0x1DC + +#define AST_LPC_PIN_MON 0x200 +#define AST_LPC_SIRQ_CTRL 0x208 +#define AST_LPC_INT_STS 0x20C +#define AST_LPC_CTRL_STS 0x210 +#define AST_LPC_PME 0x218 +#define AST_LPC_SMI 0x21C +#define AST_LPC_80H_ADDR0 0x220 +#define AST_LPC_80H_ADDR1 0x224 +#define AST_LPC_80H_DATA 0x228 +#define AST_LPC_80H_CTRL 0x22C + +#define AST_LPC_CHIP_VER 0x240 +#define AST_LPC_CHIP_REVER 0x244 +#define AST_LPC_BMC_SCH0 0x248 +#define AST_LPC_BMC_SCH1 0x24C +#define AST_LPC_NODE_SCH0 0x250 +#define AST_LPC_NODE_SCH1 0x254 +#define AST_LPC_NODE_SCH2 0x258 +#define AST_LPC_NODE_SCH3 0x25C + + + + + + + + + + + +#endif diff --git a/arch/arm/plat-aspeed/include/plat/regs-ast1070-scu.h b/arch/arm/plat-aspeed/include/plat/regs-ast1070-scu.h new file mode 100644 index 000000000000..a5a4f95eaf25 --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-ast1070-scu.h @@ -0,0 +1,95 @@ +/* arch/arm/mach-aspeed/include/mach/regs-ast1070-scu.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * History : + * 1. 2013/05/15 Ryan Chen Create + * +********************************************************************************/ +#ifndef __AST1070_SCU_H +#define __AST1070_SCU_H 1 + +/* + * Register for SCU + * */ +#define AST1070_SCU_PROTECT 0x00 /* protection key register */ +#define AST1070_SCU_RESET 0x04 /* system reset control register */ +#define AST1070_SCU_MISC_CTRL 0x08 /* misc control register */ +#define AST1070_SCU_UART_MUX 0x0C /* UART Mux control register */ +#define AST1070_SCU_SPI_USB_MUX 0x10 /* SPI/USB Mux control register */ +#define AST1070_SCU_IO_DRIVING 0x14 /* I/O Driving Strength control register */ +#define AST1070_SCU_IO_PULL 0x18 /* I/O Internal Pull control register */ +#define AST1070_SCU_IO_SLEW 0x1C /* I/O Slew Rate control register */ +#define AST1070_SCU_IO_SCHMITT 0x20 /* I/O Schmitt Trigger Control register */ +#define AST1070_SCU_IO_SELECT 0x24 /* I/O Port Selection register */ +#define AST1070_SCU_TRAP 0x30 /* HW TRAPPING register */ +#define AST1070_SCU_CHIP_ID 0x34 /* CHIP ID register */ + + +/* AST1070_SCU_PROTECT: 0x00 - protection key register */ +#define AST1070_SCU_PROTECT_UNLOCK 0x16881A78 + +/* AST1070_SCU_RESET :0x04 - system reset control register */ +#define SCU_RESET_DMA (0x1 << 11) +#define SCU_RESET_SPI_M (0x1 << 10) +#define SCU_RESET_SPI_S (0x1 << 9) +#define SCU_RESET_N4_LPC (0x1 << 8) +#define SCU_RESET_N3_LPC (0x1 << 7) +#define SCU_RESET_N2_LPC (0x1 << 6) +#define SCU_RESET_N1_LPC (0x1 << 5) +#define SCU_RESET_I2C (0x1 << 4) +#define SCU_RESET_N4_UART (0x1 << 3) +#define SCU_RESET_N3_UART (0x1 << 2) +#define SCU_RESET_N2_UART (0x1 << 1) +#define SCU_RESET_N1_UART (0x1 << 0) + +/* AST1070_SCU_MISC_CTRL 0x08 misc control register */ +#define SCU_DMA_M_S_MASK (0x3 << 9) + +#define SCU_DMA_SLAVE_EN (0x1 << 10) +#define SCU_DMA_MASTER_EN (0x1 << 9) + +/* AST1070_SCU_UART_MUX 0x0C UART Mux control register */ +#define UART_MUX_MASK(x) (0xff << (x*8)) + +#define BMC_UART_CTRL(x) (6 + (x*8)) +#define BMC_UART_CTRL_MASK(x) (0x3 << (6 + (x*8))) +#define SET_BMC_UART_CTRL(x,v) ((v) << (6 + (x*8))) +#define BMC_UART_FROM_N1 0 +#define BMC_UART_FROM_PAD1 1 +#define BMC_UART_FROM_NONE 2 + +#define NODE_UART_CTRL(x) (3 + (x*8)) +#define NODE_UART_CTRL_MASK(x) (0x7 << (3 + (x*8))) +#define SET_NODE_UART_CTRL(x,v) ((v) << (3 + (x*8))) +#define NODE_UART_FROM_BMC 0 +#define NODE_UART_FROM_PAD1 1 +#define NODE_UART_FROM_PAD2 2 +#define NODE_UART_FROM_PAD3 3 +#define NODE_UART_FROM_PAD4 4 +#define NODE_UART_FROM_NONE 5 +#define NODE_UART_FROM_N2 6 +#define NODE_UART_FROM_N3 7 + + +#define SCU_UART_IO_PAD(x) (x*8) +#define UART_IO_PAD_MASK(x) (0x7 << (x*8)) +#define SET_UART_IO_PAD(x,v) ((v) << (x*8)) +#define PAD_FROM_NONE 0 +#define PAD_FROM_N1_UART 1 +#define PAD_FROM_N2_UART 2 +#define PAD_FROM_N3_UART 3 +#define PAD_FROM_N4_UART 4 +#define PAD_FROM_BMC 5 + +/* AST1070_SCU_TRAP 0x30 HW TRAPPING register */ +#define TRAP_DEVICE_SLAVE (0x1 << 2) +#define TRAP_MULTI_MASTER (0x1 << 1) +#define TRAP_LPC_PLUS_MODE (0x1 << 0) + +#endif + diff --git a/arch/arm/plat-aspeed/include/plat/regs-crt.h b/arch/arm/plat-aspeed/include/plat/regs-crt.h new file mode 100644 index 000000000000..674928500766 --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-crt.h @@ -0,0 +1,183 @@ +/* linux/include/asm-arm/arch-aspeed/regs-crt.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef ___ASM_ARCH_REGS_CRT_H +#define ___ASM_ARCH_REGS_CRT_H + +/* CRT control registers */ + + +////////////////////////////////////////////////////////////////// +#define AST3000_VGA1_CTLREG 0x00 +#define AST3000_VGA1_CTLREG2 0x04 +#define AST3000_VGA1_STATUSREG 0x08 +#define AST3000_VGA1_PLL 0x0C +#define AST3000_VGA1_HTREG 0x10 +#define AST3000_VGA1_HRREG 0x14 +#define AST3000_VGA1_VTREG 0x18 +#define AST3000_VGA1_VRREG 0x1C +#define AST3000_VGA1_STARTADDR 0x20 +#define AST3000_VGA1_OFFSETREG 0x24 +#define AST3000_VGA1_THRESHOLD 0x28 + +#define AST3000_VGA2_CTLREG 0x60 +#define AST3000_VGA2_CTLREG2 0x64 +#define AST3000_VGA2_STATUSREG 0x68 +#define AST3000_VGA2_PLL 0x6C +#define AST3000_VGA2_HTREG 0x70 +#define AST3000_VGA2_HRREG 0x74 +#define AST3000_VGA2_VTREG 0x78 +#define AST3000_VGA2_VRREG 0x7C +#define AST3000_VGA2_STARTADDR 0x80 +#define AST3000_VGA2_OFFSETREG 0x84 +#define AST3000_VGA2_THRESHOLD 0x88 +////////////////////////////////////////////////////////////////// + +//0x00 ~ 0x5F Reserved - FB0 +//0x60 ~ 90 FB1 +#define AST_CRT_CTRL1 0x60 +#define AST_CRT_CTRL2 0x64 +#define AST_CRT_STS 0x68 +#define AST_CRT_PLL 0x6C +#define AST_CRT_HORIZ0 0x70 +#define AST_CRT_HORIZ1 0x74 +#define AST_CRT_VERTI0 0x78 +#define AST_CRT_VERTI1 0x7C +#define AST_CRT_ADDR 0x80 +#define AST_CRT_OFFSET 0x84 +#define AST_CRT_THROD 0x88 +#define AST_CRT_XSCALING 0x8C +//0x8c Reserved +//0x90 ~ Cursor +#define AST_CRT_CURSOR0 0x90 +#define AST_CRT_CURSOR1 0x94 +#define AST_CRT_CURSOR2 0x98 +#define AST_CRT_UADDR 0x9C +//0x9c Reserved +//0xA0 ~ OSD +#define AST_CRT_OSDH 0xA0 +#define AST_CRT_OSDV 0xA4 +#define AST_CRT_OSDADDR 0xA8 +#define AST_CRT_OSDDISP 0xAC +#define AST_CRT_OSDTHROD 0xB0 +#define AST_CRT_VADDR 0xB4 + +//0xb4 Reserved +#define AST_CRT_STS_V 0xB8 +#define AST_CRT_SCRATCH 0xBC +#define AST_CRT_X 0xC0 +//0xC4 +#define AST_CRT_OSD_COLOR 0xE0 + +/* AST_CRT_CTRL1 - 0x60 : CRT Control Register I */ +#define CRT_CTRL_VERTICAL_INTR_STS (0x1 << 31) +#define CRT_CTRL_VERTICAL_INTR_EN (0x1 << 30) +//24~28 reserved +#define CRT_CTRL_DESK_OFF (0x1 << 23) +#define CRT_CTRL_FSYNC_OFF (0x1 << 22) +#define CRT_CTRL_FSYNC_POLARITY (0x1 << 21) +#define CRT_CTRL_SCREEN_OFF (0x1 << 20) +#define CRT_CTRL_VSYNC_OFF (0x1 << 19) +#define CRT_CTRL_HSYNC_OFF (0x1 << 18) +#define CRT_CTRL_VSYNC_POLARITY (0x1 << 17) +#define CRT_CTRL_HSYNC_POLARITY (0x1 << 16) +#define CRT_CTRL_TILE_EN (0x1 << 15) +#define CRT_CTRL_HDTVYUV_EN (0x1 << 14) +#define CRT_CTRL_YUV_FORMAT(x) (x << 12) +#define YUV_MODE0 0 +#define YUV_MODE1 1 +#define YUV_MODE2 2 +// bit 11 reserved +#define CRT_CTRL_HW_CURSOR_FORMAT (0x1 << 10) // 0: XRGB4444, 1:ARGB4444 +#define CRT_CTRL_FORMAT_MASK (0x7 << 7) +#define CRT_CTRL_FORMAT(x) (x << 7) +#define COLOR_RGB565 (0) +#define COLOR_YUV444 (1) +#define COLOR_XRGB8888 (2) +#define COLOR_YUV444_2RGB (5) +#define CRT_CTRL_ENVEFLIP (0x1 << 6) +//bit 5 +#define CRT_CTRL_SCALING_X (0x1 << 4) +#define CRT_CTRL_INTER_TIMING (0x1 << 3) +#define CRT_CTRL_OSD_EN (0x1 << 2) +#define CRT_CTRL_HW_CURSOR_EN (0x1 << 1) +#define CRT_CTRL_GRAPHIC_EN (0x1) + +/*AST_CRT_CTRL2 - 0x64 : CRT Control Register II */ +#define CRT_CTRL_VLINE_NUM_MASK (0xfff << 20) +#define CRT_CTRL_VLINE_NUM(x) (x << 20) +#define CRT_CTRL_TESTDVO_MASK (0xfff << 8) +#define CRT_CTRL_TESTDVO(x) (x << 8) +#define CRT_CTRL_DVO_EN (0x1 << 7) +#define CRT_CTRL_DVO_DUAL (0x1 << 6) +#define CRT_CTRL_FIFO_FULL (0x1 << 5) +#define CRT_CTRL_TEST_EN (0x1 << 4) +#define CRT_CTRL_SIGN_DON (0x1 << 3) +#define CRT_CTRL_SIGN_TRIGGER (0x1 << 2) +#define CRT_CTRL_DAC_TEST_EN (0x1 << 1) +#define CRT_CTRL_DAC_PWR_EN (0x1) + +/* AST_CRT_STS - 0x68 : CRT Status Register */ +#define CRT_STS_RED_RB(x) (x << 24) +#define CRT_STS_GREEN_RB(x) (x << 16) +#define CRT_STS_BLUE_RB(x) (x << 8) +#define CRT_STS_DAC_SENSE_EN (0x1 << 7) +//6 reserved +#define CRT_STS_ODDFIELD_SYNC (0x1 << 5) +#define CRT_STS_ODDFIELD (0x1 << 4) +#define CRT_STS_HDISPLAY_RB (0x1 << 3) +#define CRT_STS_HRETRACE_RB (0x1 << 2) +#define CRT_STS_VDISPLAY_RB (0x1 << 1) +#define CRT_STS_VRETRACE_RB (0x1) + +/* AST_CRT_PLL - 0x6C : CRT Video PLL Setting Register */ +#define CRT_PLL_DAC_MODE_SENSE(x) (x << 30) +#define CRT_PLL_DAC_SENSE(x) (x << 28) +#define CRT_PLL_BYPASS (0x1 << 17) +#define CRT_PLL_PWR_DWN (0x1 << 16) +#define CRT_PLL_POST_DIVIDER(x) (((x & 0x3) << 13) | (((x >> 2) & 0xf) << 18) | (((x >> 6) & 0x1) << 23) | (((x >> 7) & 0x1) << 22)) +#define CRT_PLL_DENUM(x) (x << 8) +#define CRT_PLL_NUM(x) (x) + +/* AST_CRT_HORIZ0 - 0x70 : CRT Horizontal Total & Display Enable End Register */ +#define CRT_H_TOTAL(x) (x) +#define CRT_H_DE(x) (x << 16) + +/* AST_ 0x74 : CRT Horizontal Retrace Start & End Register */ +#define CRT_H_RS_START(x) (x) +#define CRT_H_RS_END(x) (x << 16) + +/* AST_CRT_ - 0x78 : CRT Horizontal Total & Display Enable End Register */ +#define CRT_V_TOTAL(x) (x) +#define CRT_V_DE(x) (x << 16) + +/* AST_ 0x7C : CRT Horizontal Retrace Start & End Register */ +#define CRT_V_RS_START(x) (x) +#define CRT_V_RS_END(x) (x << 16) + +/* AST_CRT_OFFSET - 0x84 : CRT Display Offset & Terminal Count Register */ +#define CRT_DISP_OFFSET(x) (x) +#define CRT_TERM_COUNT(x) (x << 16) + +/* AST_CRT_THROD - 0x88 : CRT Threadhold Register */ +#define CRT_THROD_LOW(x) (x) +#define CRT_THROD_HIGH(x) (x << 8) +#define CRT_THROD_X_SCALING(x) (x << 16) +#define CRT_THROD_CRT2Y (0x1 << 20) + +/* AST_CRT_XSCALING - 0x8C : CRT X Scaling-up Factor Register */ + + +/* AST_CRT_CURSOR0 : 0x90 - CRT Hardware Cursor X & Y Offset Register */ +#define CRT_HW_CURSOR_X_OFFSET(x) (x) +#define CRT_HW_CURSOR_Y_OFFSET(x) (x << 16) + +/* AST_CRT_CURSOR1 : 0x94 - CRT Hardware Cursor X & Y Position Register */ +#define CRT_HW_CURSOR_X_POSITION(x) (x) +#define CRT_HW_CURSOR_Y_POSITION(x) (x << 16) + +#endif /* ___ASM_ARCH_REGS_CRT_H */ diff --git a/arch/arm/plat-aspeed/include/plat/regs-fmc.h b/arch/arm/plat-aspeed/include/plat/regs-fmc.h new file mode 100644 index 000000000000..25c3046fe064 --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-fmc.h @@ -0,0 +1,112 @@ +/* arch/arm/plat-aspeed/include/mach/regs-smc.h + * + * Copyright (c) 2012 ASPEED Technology Inc. <ryan_chen@aspeedtech.com> + * http://www.aspeedtech.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ASPEED Static memory ctrol +*/ + +#ifndef __ASM_ARCH_REGS_FMC_H +#define __ASM_ARCH_REGS_FMC_H __FILE__ + +#define FMC_CE_TYPE 0x00 +#define FMC_CE_CTRL 0x04 +#define FMC_INTR_CTRL 0x08 +#define FMC_CE0_CTRL 0x10 +#define FMC_CE1_CTRL 0x14 +#define FMC_CE2_CTRL 0x18 +#define FMC_CE3_CTRL 0x1c +#define FMC_CE4_CTRL 0x20 + +#define FMC_CE0_ADDR 0x30 +#define FMC_CE1_ADDR 0x34 +#define FMC_CE2_ADDR 0x38 +#define FMC_CE3_ADDR 0x3c +#define FMC_CE4_ADDR 0x40 + +#define FMC_MISC_CTRL1 0x50 +#define FMC_MISC_CTRL2 0x54 +#define FMC_NAND_CTRL 0x58 +#define FMC_NAND_ECC 0x5c +#define FMC_NAND_ECC_CK1 0x60 +#define FMC_NAND_ECC_CK2 0x64 +#define FMC_NAND_ECC_CK3 0x68 +#define FMC_NAND_ECC_GEN1 0x6c +#define FMC_NAND_ECC_GEN2 0x70 +#define FMC_NAND_ECC_GEN3 0x74 +#define FMC_NAND_ECC_CK_R1 0x78 +#define FMC_NAND_ECC_CK_R2 0x7c +#define FMC_DMA_CTRL 0x80 +#define FMC_DMA_FLASH_ADDR 0x84 +#define FMC_DMA_DRAM_ADDR 0x88 +#define FMC_DMA_LEN 0x8C +#define FMC_CHECK_SUM 0x90 +#define FMC_SPI_TIMING 0x94 + +/* FMC_CE_TYPE 0x00 */ +#define FMC_SET_WRITE_CS(x) (0x1 << (x+16)) +#define FMC_MASK_TYPE_CS(x) (~(0x3 << (2*x))) +#define FMC_SET_TYPE_NAND_CS(x) (0x1 << (2*x)) +#define FMC_SET_TYPE_SPI_CS(x) (0x2 << (2*x)) + +#define FMC_TYPE_NOR 0 +#define FMC_TYPE_NAND 1 +#define FMC_TYPE_SPI 2 + + +/* FMC_CE0_CTRL for NAND 0x10, 0x14, 0x18, 0x1c, 0x20 */ +#define NAND_T_WEH(x) (x << 28) +#define NAND_T_WEL(x) (x << 24) +#define NAND_T_REH(x) (x << 20) +#define NAND_T_REL(x) (x << 16) +#define NAND_T_CESH(x) (x << 12) +#define NAND_T_WTR(x) (x << 10) +#define NAND_T_R(x) (x << 4) +#define NAND_ADDR_CYCLE (1 << 3) +#define NAND_CE_ACTIVE (1 << 2) +#define NAND_OP_MODE (1 << 0) + +/* FMC_CE0_CTRL for SPI 0x10, 0x14, 0x18, 0x1c, 0x20 */ +#define SPI_IO_MODE(x) (x << 28) +#define SPI_CE_WIDTH(x) (x << 24) +#define SPI_CMD_DATA(x) (x << 16) +#define SPI_DUMMY_CMD (1 << 15) +#define SPI_DUMMY_HIGH (1 << 14) +#define SPI_CLK_DIV (1 << 13) +#define SPI_ADDR_CYCLE (1 << 13) +#define SPI_CMD_MERGE_DIS (1 << 12) +#define SPI_T_CLK (x << 8) +#define SPI_DUMMY_LOW (x << 6) +#define SPI_LSB_FIRST_CTRL (1 << 5) +#define SPI_CPOL_1 (1 << 4) +#define SPI_DUAL_DATA (1 << 3) +#define SPI_CE_INACTIVE (1 << 2) +#define SPI_CMD_MODE (x) +#define SPI_CMD_NOR_R_MODE 0 +#define SPI_CMD_FAST_R_MODE 1 +#define SPI_CMD_NOR_W_MODE 2 +#define SPI_CMD_USER_MODE 3 + + +/* FMC_CE0_ADDR 0x30 0x34 0x38 0x3c 0x40*/ +#define FMC_END_ADDR(x) (x << 24) +#define FMC_START_ADDR(x) (x << 16) + + +/* FMC_MISC_CTRL1 0x50 */ +#define READ_BUSY_PIN_STS (1 << 3) + +/* FMC_NAND_ECC 0x5c */ +#define NAND_ECC_RESET (1 << 3) +#define NAND_ECC_ENABLE (1 << 2) +#define NAND_ECC_DATA_BLK_512 2 +#define NAND_ECC_DATA_BLK_256 1 +#define NAND_ECC_DATA_BLK_128 0 + + + +#endif /* __ASM_ARCH_REGS_FMC_H */ diff --git a/arch/arm/plat-aspeed/include/plat/regs-gpio.h b/arch/arm/plat-aspeed/include/plat/regs-gpio.h new file mode 100644 index 000000000000..d6e7de02c19d --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-gpio.h @@ -0,0 +1,338 @@ +/* arch/arm/plat-aspeed/include/mach/regs-gpio.h + * + * Copyright (c) 2012 ASPEED Technology Inc. <ryan_chen@aspeedtech.com> + * http://www.aspeedtech.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ASPEED I2C Controller +*/ + +#ifndef __ASM_ARCH_REGS_GPIO_H +#define __ASM_ARCH_REGS_GPIO_H __FILE__ + +/*AST GPIO Register Definition */ +#define AST_GPIO_DATA 0x000 +#define AST_GPIO_DIR 0x004 +#define AST_GPIO_INT_EN 0x008 +#define AST_GPIO_INT_SEN_T0 0x00c +#define AST_GPIO_INT_SEN_T1 0x010 +#define AST_GPIO_INT_SEN_T2 0x014 +#define AST_GPIO_INT_STS 0x018 +#define AST_GPIO_RST_TOR 0x01c +#define AST_EXT_GPIO_DATA 0x020 +#define AST_EXT_GPIO_DIR 0x024 +#define AST_EXT_GPIO_INT_EN 0x028 +#define AST_EXT_GPIO_INT_SEN_T0 0x02c +#define AST_EXT_GPIO_INT_SEN_T1 0x030 +#define AST_EXT_GPIO_INT_SEN_T2 0x034 +#define AST_EXT_GPIO_INT_STS 0x038 +#define AST_EXT_GPIO_RST_TOR 0x03c +#define AST_GPIO_DEBOUNCE_SET1 0x040 //A/B/C/D +#define AST_GPIO_DEBOUNCE_SET2 0x044 //A/B/C/D +#define AST_EXT_GPIO_DEBOUNCE_SET1 0x048 //E/F/G/H +#define AST_EXT_GPIO_DEBOUNCE_SET2 0x04C //E/F/G/H +#define AST_DEBOUNCE_TIME_SET1 0x050 +#define AST_DEBOUNCE_TIME_SET2 0x054 +#define AST_DEBOUNCE_TIME_SET3 0x058 +#define AST_GPIO_CMD_S0 0x060 +#define AST_GPIO_CMD_S1 0x064 +#define AST_EXT_GPIO_CMD_S0 0x068 +#define AST_EXT_GPIO_CMD_S1 0x06C +#define AST_SIMPLE_GPIO_DATA0 0x070 +#define AST_SIMPLE_GPIO_DIR0 0x074 +#define AST_SIMPLE_GPIO_DATA1 0x078 +#define AST_SIMPLE_GPIO_DIR1 0x07C +#define AST_SIMPLE_GPIO_DATA2 0x080 +#define AST_SIMPLE_GPIO_DIR2 0x084 +#define AST_SIMPLE_GPIO_DATA3 0x088 +#define AST_SIMPLE_GPIO_DIR3 0x08C +#define AST_SIMPLE_GPIO0_CMD_S0 0x090 +#define AST_SIMPLE_GPIO0_CMD_S1 0x094 +#define AST_SIMPLE_GPIO0_INT_EN 0x098 +#define AST_SIMPLE_GPIO0_INT_SEN_T0 0x09c +#define AST_SIMPLE_GPIO0_INT_SEN_T1 0x0a0 +#define AST_SIMPLE_GPIO0_INT_SEN_T2 0x0a4 +#define AST_SIMPLE_GPIO0_INT_STS 0x0a8 +#define AST_SIMPLE_GPIO0_RST_TOR 0x0ac +#define AST_SIMPLE_GPIO0_DEBOUNCE_SET1 0x0b0 +#define AST_SIMPLE_GPIO0_DEBOUNCE_SET2 0x0b4 +#define AST_SIMPLE_GPIO0_INT_MASK 0x0b8 +#define AST_GPIO_DATA_READ 0x0c0 +#define AST_EXT_GPIO_DATA_READ 0x0c4 +#define AST_SIMPLE_GPIO0_DATA_READ 0x0c8 +#define AST_SIMPLE_GPIO1_DATA_READ 0x0cc +#define AST_SIMPLE_GPIO2_DATA_READ 0x0d0 +#define AST_SIMPLE_GPIO3_DATA_READ 0x0d4 +#define AST_SIMPLE_GPIO4_DATA_READ 0x0d8 +#define AST_SIMPLE_GPIO1_CMD_S0 0x0e0 +#define AST_SIMPLE_GPIO1_CMD_S1 0x0e4 +#define AST_SIMPLE_GPIO1_INT_EN 0x0e8 +#define AST_SIMPLE_GPIO1_INT_SEN_T0 0x0ec +#define AST_SIMPLE_GPIO1_INT_SEN_T1 0x0f0 +#define AST_SIMPLE_GPIO1_INT_SEN_T2 0x0f4 +#define AST_SIMPLE_GPIO1_INT_STS 0x0f8 +#define AST_SIMPLE_GPIO1_RST_TOR 0x0fc +#define AST_SIMPLE_GPIO1_DEBOUNCE_SET1 0x100 +#define AST_SIMPLE_GPIO1_DEBOUNCE_SET2 0x104 +#define AST_SIMPLE_GPIO1_INT_MASK 0x108 +#define AST_SIMPLE_GPIO2_CMD_S0 0x110 +#define AST_SIMPLE_GPIO2_CMD_S1 0x114 +#define AST_SIMPLE_GPIO2_INT_EN 0x118 +#define AST_SIMPLE_GPIO2_INT_SEN_T0 0x11c +#define AST_SIMPLE_GPIO2_INT_SEN_T1 0x120 +#define AST_SIMPLE_GPIO2_INT_SEN_T2 0x124 +#define AST_SIMPLE_GPIO2_INT_STS 0x128 +#define AST_SIMPLE_GPIO2_RST_TOR 0x12c +#define AST_SIMPLE_GPIO2_DEBOUNCE_SET1 0x130 +#define AST_SIMPLE_GPIO2_DEBOUNCE_SET2 0x134 +#define AST_SIMPLE_GPIO2_INT_MASK 0x138 +#define AST_SIMPLE_GPIO3_CMD_S0 0x140 +#define AST_SIMPLE_GPIO3_CMD_S1 0x144 +#define AST_SIMPLE_GPIO3_INT_EN 0x148 +#define AST_SIMPLE_GPIO3_INT_SEN_T0 0x14c +#define AST_SIMPLE_GPIO3_INT_SEN_T1 0x150 +#define AST_SIMPLE_GPIO3_INT_SEN_T2 0x154 +#define AST_SIMPLE_GPIO3_INT_STS 0x158 +#define AST_SIMPLE_GPIO3_RST_TOR 0x15c +#define AST_SIMPLE_GPIO3_DEBOUNCE_SET1 0x160 +#define AST_SIMPLE_GPIO3_DEBOUNCE_SET2 0x164 +#define AST_SIMPLE_GPIO3_INT_MASK 0x168 +#define AST_SIMPLE_GPIO4_CMD_S0 0x170 +#define AST_SIMPLE_GPIO4_CMD_S1 0x174 +#define AST_SIMPLE_GPIO4_INT_EN 0x178 +#define AST_SIMPLE_GPIO4_INT_SEN_T0 0x17c +#define AST_SIMPLE_GPIO4_INT_SEN_T1 0x180 +#define AST_SIMPLE_GPIO4_INT_SEN_T2 0x184 +#define AST_SIMPLE_GPIO4_INT_STS 0x188 +#define AST_SIMPLE_GPIO4_RST_TOR 0x18c +#define AST_SIMPLE_GPIO4_DEBOUNCE_SET1 0x190 +#define AST_SIMPLE_GPIO4_DEBOUNCE_SET2 0x194 +#define AST_SIMPLE_GPIO4_INT_MASK 0x198 +#define AST_GPIO_INT_MASK 0x1d0 +#define AST_EXT_GPIO_INT_MASK 0x1d4 +#ifdef CONFIG_ARCH_AST1010 +#else +#define AST_SIMPLE_GPIO_DATA4 0x1e0 +#define AST_SIMPLE_GPIO_DIR4 0x1e4 +#endif + +//Serial GPIO +#define AST_SGPIO_DATA 0x200 +#define AST_SGPIO_INT_EN 0x204 +#define AST_SGPIO_INT_SEN_T0 0x208 +#define AST_SGPIO_INT_SEN_T1 0x20c +#define AST_SGPIO_INT_SEN_T2 0x210 +#define AST_SGPIO_INT_STS 0x214 +#define AST_SGPIO_RST_TOR 0x218 +#define AST_EXT_SGPIO_DATA 0x21c +#define AST_EXT_SGPIO_INT_EN 0x220 +#define AST_EXT_SGPIO_INT_SEN_T0 0x224 +#define AST_EXT_SGPIO_INT_SEN_T1 0x228 +#define AST_EXT_SGPIO_INT_SEN_T2 0x22c +#define AST_EXT_SGPIO_INT_STS 0x230 +#define AST_EXT_SGPIO_RST_TOR 0x234 +#define AST_SGPIO_CTRL 0x254 +#define AST_SGPIO_DATA_READ 0x270 +#define AST_EXT_SGPIO_DAT 0x274 + +//Serial GPIO Slave Monitor +#define AST_SGPIO_SLAVE_DATA_INIT 0x300 +#define AST_SGPIO_SLAVE_DATA_TARGET 0x304 +#define AST_SGPIO_SLAVE_DATA_LOAD 0x308 +#define AST_SGPIO_SLAVE_INT_EN0 0x30c +#define AST_SGPIO_SLAVE_INT_EN1 0x310 +#define AST_SGPIO_SLAVE_INT_EN2 0x314 +#define AST_SGPIO_SLAVE_INT_STS0 0x318 +#define AST_SGPIO_SLAVE_INT_STS1 0x31c +#define AST_SGPIO_SLAVE_INT_STS2 0x320 + +/**********************************************************************************/ +/* AST_GPIO_DATA - 0x000 : A/B/C/D Data Vale */ +#define GET_GPIOD_DATA(x) ((x&0xff000000) >> 24) +#define SET_GPIOD_DATA(x) (x << 24) +#define GET_GPIOD_PIN_DATA(x,pin) ((x >> (pin + 24)) & 1) +#define SET_GPIOD_PIN_DATA(pin) (1<<(pin + 24)) +#define GET_GPIOC_DATA(x) ((x&0xff0000) >> 16) +#define SET_GPIOC_DATA(x) (x << 16) +#define GET_GPIOC_PIN_DATA(x,pin) ((x >> (pin + 16)) & 1) +#define SET_GPIOC_PIN_DATA(pin) (1<<(pin + 16)) +#define GET_GPIOB_DATA(x) ((x&0xff00) >> 8) +#define SET_GPIOB_DATA(x) (x << 8) +#define GET_GPIOB_PIN_DATA(x,pin) ((x >> (pin + 8)) & 1) +#define SET_GPIOB_PIN_DATA(pin) (1<<(pin + 8)) +#define GET_GPIOA_DATA(x) (x&0xff) +#define SET_GPIOA_DATA(x) (x) +#define GET_GPIOA_PIN_DATA(x,pin) ((x >> pin) & 1) +#define SET_GPIOA_PIN_DATA(pin) (1<<pin) + +/* AST_GPIO_DIR - 0x004 : Direction */ +#define GET_GPIOD_DIR(x) ((x&0xff000000) >> 24) +#define SET_GPIOD_DIR(x) (x << 24) +#define GET_GPIOD_PIN_DIR(x,pin) ((x >> (pin + 24)) & 1) +#define SET_GPIOD_PIN_DIR(pin) (1<<(pin + 24)) +#define GET_GPIOC_DIR(x) ((x&0xff0000) >> 16) +#define SET_GPIOC_DIR(x) (x << 16) +#define GET_GPIOC_PIN_DIR(x,pin) ((x >> (pin + 16)) & 1) +#define SET_GPIOC_PIN_DIR(pin) (1<<(pin + 16)) +#define GET_GPIOB_DIR(x) ((x&0xff00) >> 8) +#define SET_GPIOB_DIR(x) (x << 8) +#define GET_GPIOB_PIN_DIR(x,pin) ((x >> (pin + 8)) & 1) +#define SET_GPIOB_PIN_DIR(pin) (1<<(pin + 8)) +#define GET_GPIOA_DIR(x) (x&0xff) +#define SET_GPIOA_DIR(x) (x) +#define GET_GPIOA_PIN_DIR(x,pin) ((x >> pin) & 1) +#define SET_GPIOA_PIN_DIR(pin) (1<<pin) + +/* AST_GPIO_INT_EN - 0x008 : Interrupt Enable */ +#define GET_GPIOD_INT_EN(x) ((x&0xff000000) >> 24) +#define SET_GPIOD_INT_EN(x) (x << 24) +#define GET_GPIOD_PIN_INT_EN(x,pin) ((x >> (pin + 24)) & 1) +#define SET_GPIOD_PIN_INT_EN(pin) (1<<(pin + 24)) +#define GET_GPIOC_INT_EN(x) ((x&0xff0000) >> 16) +#define SET_GPIOC_INT_EN(x) (x << 16) +#define GET_GPIOC_PIN_INT_EN(x,pin) ((x >> (pin + 16)) & 1) +#define SET_GPIOC_PIN_INT_EN(pin) (1<<(pin + 16)) +#define GET_GPIOB_INT_EN(x) ((x&0xff00) >> 8) +#define SET_GPIOB_INT_EN(x) (x << 8) +#define GET_GPIOB_PIN_INT_EN(x,pin) ((x >> (pin + 8)) & 1) +#define SET_GPIOB_PIN_INT_EN(pin) (1<<(pin + 8)) +#define GET_GPIOA_INT_EN(x) (x&0xff) +#define SET_GPIOA_INT_EN(x) (x) +#define GET_GPIOA_PIN_INT_EN(x,pin) ((x >> pin) & 1) +#define SET_GPIOA_PIN_INT_EN(pin) (1<<pin) + +/* AST_GPIO_INT_SEN_T0/1/2 - 0x00c/0x010/0x014 : Interrupt Sensitivity Type 0/1/2 */ +#define GET_GPIOD_INT_MODE(x) ((x&0xff000000) >> 24) +#define SET_GPIOD_INT_MODE(x) (x << 24) +#define GET_GPIOD_PIN_INT_MODE(x,pin) ((x >> (pin + 24)) & 1) +#define SET_GPIOD_PIN_INT_MODE(pin) (1<<(pin + 24)) +#define GET_GPIOC_INT_MODE(x) ((x&0xff0000) >> 16) +#define SET_GPIOC_INT_MODE(x) (x << 16) +#define GET_GPIOC_PIN_INT_MODE(x,pin) ((x >> (pin + 16)) & 1) +#define SET_GPIOC_PIN_INT_MODE(pin) (1<<(pin + 16)) +#define GET_GPIOB_INT_MODE(x) ((x&0xff00) >> 8) +#define SET_GPIOB_INT_MODE(x) (x << 16) +#define GET_GPIOB_PIN_INT_MODE(x,pin) ((x >> (pin + 8)) & 1) +#define SET_GPIOB_PIN_INT_MODE(pin) (1<<(pin + 8)) +#define GET_GPIOA_INT_MODE(x) (x&0xff) +#define SET_GPIOA_INT_MODE(x) (x) +#define GET_GPIOA_PIN_INT_MODE(x,pin) ((x >> pin) & 1) +#define SET_GPIOA_PIN_INT_MODE(pin) (1 << pin) + +/* AST_GPIO_INT_STS - 0x018 : Interrupt Status */ +#define GET_GPIOD_INT_STS(x) ((x&0xff000000) >> 24) +#define SET_GPIOD_INT_STS(x) (x << 24) +#define GET_GPIOD_PIN_INT_STS(x,pin) ((x >> (pin + 24)) & 1) +#define SET_GPIOD_PIN_INT_STS(pin) (1<<(pin + 24)) +#define GET_GPIOC_INT_STS(x) ((x&0xff0000) >> 16) +#define SET_GPIOC_INT_STS(x) (x << 16) +#define GET_GPIOC_PIN_INT_STS(x,pin) ((x >> (pin + 16)) & 1) +#define SET_GPIOC_PIN_INT_STS(pin) (1<<(pin + 16)) +#define GET_GPIOB_INT_STS(x) ((x&0xff00) >> 8) +#define SET_GPIOB_INT_STS(x) (x << 16) +#define GET_GPIOB_PIN_INT_STS(x,pin) ((x >> (pin + 8)) & 1) +#define SET_GPIOB_PIN_INT_STS(pin) (1<<(pin + 8)) +#define GET_GPIOA_INT_STS(x) (x&0xff) +#define SET_GPIOA_INT_STS(x) (x) +#define GET_GPIOA_PIN_INT_STS(x,pin) ((x >> pin) & 1) +#define SET_GPIOA_PIN_INT_STS(pin) (1 << pin) + +/* AST_GPIO_RST_TOR - 0x01c : Reset Tolerant */ +#define GET_GPIOD_RST_EN(x) ((x&0xff000000) >> 24) +#define SET_GPIOD_RST_EN(x) (x << 24) +#define GET_GPIOD_PIN_RST_EN(x,pin) ((x >> (pin + 24)) & 1) +#define SET_GPIOD_PIN_RST_EN(pin) (1<<(pin + 24)) +#define GET_GPIOC_RST_EN(x) ((x&0xff0000) >> 16) +#define SET_GPIOC_RST_EN(x) (x << 16) +#define GET_GPIOC_PIN_RST_EN(x,pin) ((x >> (pin + 16)) & 1) +#define SET_GPIOC_PIN_RST_EN(pin) (1<<(pin + 16)) +#define GET_GPIOB_RST_EN(x) ((x&0xff00) >> 8) +#define SET_GPIOB_RST_EN(x) (x << 16) +#define GET_GPIOB_PIN_RST_EN(x,pin) ((x >> (pin + 8)) & 1) +#define SET_GPIOB_PIN_RST_EN(pin) (1<<(pin + 8)) +#define GET_GPIOA_RST_EN(x) (x&0xff) +#define SET_GPIOA_RST_EN(x) (x) +#define GET_GPIOA_PIN_RST_EN(x,pin) ((x >> pin) & 1) +#define SET_GPIOA_PIN_RST_EN(pin) (1 << pin) + +/* AST_EXT_GPIO_DATA - 0x020 : E/F/G/H Data Vale */ +#define GET_GPIOH_DATA(x) ((x&0xff000000) >> 24) +#define SET_GPIOH_DATA(x) (x << 24) +#define GET_GPIOH_PIN_DATA(x,pin) ((x >> (pin + 24)) & 1) +#define SET_GPIOH_PIN_DATA(pin) (1<<(pin + 24)) +#define GET_GPIOG_DATA(x) ((x&0xff0000) >> 16) +#define SET_GPIOG_DATA(x) (x << 16) +#define GET_GPIOG_PIN_DATA(x,pin) ((x >> (pin + 16)) & 1) +#define SET_GPIOG_PIN_DATA(pin) (1<<(pin + 16)) +#define GET_GPIOF_DATA(x) ((x&0xff00) >> 8) +#define SET_GPIOF_DATA(x) (x << 8) +#define GET_GPIOF_PIN_DATA(x,pin) ((x >> (pin + 8)) & 1) +#define SET_GPIOF_PIN_DATA(pin) (1<<(pin + 8)) +#define GET_GPIOE_DATA(x) (x&0xff) +#define SET_GPIOE_DATA(x) (x) +#define GET_GPIOE_PIN_DATA(x,pin) ((x >> pin) & 1) +#define SET_GPIOE_PIN_DATA(pin) (1<<pin) + +/* AST_EXT_GPIO_DIR - 0x024 : */ +#define GET_GPIOH_DIR(x) ((x&0xff000000) >> 24) +#define SET_GPIOH_DIR(x) (x << 24) +#define GET_GPIOH_PIN_DIR(x,pin) ((x >> (pin + 24)) & 1) +#define SET_GPIOH_PIN_DIR(pin) (1<<(pin + 24)) +#define GET_GPIOG_DIR(x) ((x&0xff0000) >> 16) +#define SET_GPIOG_DIR(x) (x << 16) +#define GET_GPIOG_PIN_DIR(x,pin) ((x >> (pin + 16)) & 1) +#define SET_GPIOG_PIN_DIR(pin) (1<<(pin + 16)) +#define GET_GPIOF_DIR(x) ((x&0xff00) >> 8) +#define SET_GPIOF_DIR(x) (x << 8) +#define GET_GPIOF_PIN_DIR(x,pin) ((x >> (pin + 8)) & 1) +#define SET_GPIOF_PIN_DIR(pin) (1<<(pin + 8)) +#define GET_GPIOE_DIR(x) (x&0xff) +#define SET_GPIOE_DIR(x) (x) +#define GET_GPIOE_PIN_DIR(x,pin) ((x >> pin) & 1) +#define SET_GPIOE_PIN_DIR(pin) (1<<pin) + +/* AST_EXT_GPIO_INT_EN - 0x028 */ +#define GET_GPIOH_INT_EN(x) ((x&0xff000000) >> 24) +#define SET_GPIOH_INT_EN(x) (x << 24) +#define GET_GPIOH_PIN_INT_EN(x,pin) ((x >> (pin + 24)) & 1) +#define SET_GPIOH_PIN_INT_EN(pin) (1<<(pin + 24)) +#define GET_GPIOG_INT_EN(x) ((x&0xff0000) >> 16) +#define SET_GPIOG_INT_EN(x) (x << 16) +#define GET_GPIOG_PIN_INT_EN(x,pin) ((x >> (pin + 16)) & 1) +#define SET_GPIOG_PIN_INT_EN(pin) (1<<(pin + 16)) +#define GET_GPIOF_INT_EN(x) ((x&0xff00) >> 8) +#define SET_GPIOF_INT_EN(x) (x << 8) +#define GET_GPIOF_PIN_INT_EN(x,pin) ((x >> (pin + 8)) & 1) +#define SET_GPIOF_PIN_INT_EN(pin) (1<<(pin + 8)) +#define GET_GPIOE_INT_EN(x) (x&0xff) +#define SET_GPIOE_INT_EN(x) (x) +#define GET_GPIOE_PIN_INT_EN(x,pin) ((x >> pin) & 1) +#define SET_GPIOE_PIN_INT_EN(pin) (1<<pin) + +/* AST_EXT_GPIO_INT_SEN_T0/1/2 - 0x02c/0x30/0x34 : */ +/* AST_EXT_GPIO_INT_STS 0x038 */ +/* AST_EXT_GPIO_RST_TOR 0x03c */ + +/* AST_GPIO_DEBOUNCE_SET1 - 0x040 : Debounce Setting #1 */ +#define GET_GPIO3_DEBOUNCE(x) ((x&0xff000000) >> 24) +#define SET_GPIO3_DEBOUNCE(x) (x << 24) +#define GET_GPIO3_PIN_DEBOUNCE(x,pin) ((x >> (pin + 24)) & 1) +#define SET_GPIO3_PIN_DEBOUNCE(pin) (1<<(pin + 24)) +#define GET_GPIO2_DEBOUNCE(x) ((x&0xff0000) >> 16) +#define SET_GPIO2_DEBOUNCE(x) (x << 16) +#define GET_GPIO2_PIN_DEBOUNCE(x,pin) ((x >> (pin + 16)) & 1) +#define SET_GPIO2_PIN_DEBOUNCE(pin) (1<<(pin + 16)) +#define GET_GPIO1_DEBOUNCE(x) ((x&0xff00) >> 8) +#define SET_GPIO1_DEBOUNCE(x) (x << 8) +#define GET_GPIO1_PIN_DEBOUNCE(x,pin) ((x >> (pin + 8)) & 1) +#define SET_GPIO1_PIN_DEBOUNCE(pin) (1<<(pin + 8)) +#define GET_GPIO0_DEBOUNCE(x) (x&0xff) +#define SET_GPIO0_DEBOUNCE(x) (x) +#define GET_GPIO0_PIN_DEBOUNCE(x,pin) ((x >> pin) & 1) +#define SET_GPIO0_PIN_DEBOUNCE(pin) (1<<pin) + + +#endif /* __ASM_ARCH_REGS_GPIO_H */
\ No newline at end of file diff --git a/arch/arm/plat-aspeed/include/plat/regs-iic.h b/arch/arm/plat-aspeed/include/plat/regs-iic.h new file mode 100644 index 000000000000..14db73ca177b --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-iic.h @@ -0,0 +1,286 @@ +/* arch/arm/plat-aspeed/include/mach/regs-iic.h + * + * Copyright (c) 2012 ASPEED Technology Inc. <ryan_chen@aspeedtech.com> + * http://www.aspeedtech.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ASPEED I2C Controller +*/ + +#ifndef __ASM_ARCH_REGS_IIC_H +#define __ASM_ARCH_REGS_IIC_H __FILE__ + +#ifdef CONFIG_ARCH_AST1010 +#define AST_I2C_DMA_SIZE 512 +#else +#define AST_I2C_DMA_SIZE 4096 +#endif + +#define AST_I2C_PAGE_SIZE 256 + +#if defined(CONFIG_ARCH_AST2300) +#define MASTER_XFER_MODE BUFF_MODE +#define SLAVE_XFER_MODE BYTE_MODE +#define NUM_BUS 9 +#elif defined(CONFIG_ARCH_AST2400) +#define MASTER_XFER_MODE BUFF_MODE +#define SLAVE_XFER_MODE BYTE_MODE +#define NUM_BUS 14 +#elif defined(CONFIG_ARCH_AST1010) +#define MASTER_XFER_MODE BYTE_MODE +#define SLAVE_XFER_MODE BYTE_MODE +#define NUM_BUS 15 +#elif defined(CONFIG_ARCH_AST1520) || defined(CONFIG_ARCH_AST3200) || defined(CONFIG_ARCH_AST2500) +#define MASTER_XFER_MODE BYTE_MODE +#define SLAVE_XFER_MODE BYTE_MODE +#define NUM_BUS 4 +#else +#err "NO define NUM_BUS" +#endif + +#if defined(CONFIG_ARCH_AST1070) +#define AST_CI2C_GLOBAL_REG 0x00 +#define AST_CI2C_DEVICE1 0x40 +#define AST_CI2C_DEVICE2 0x80 +#define AST_CI2C_DEVICE3 0xc0 +#define AST_CI2C_DEVICE4 0x100 +#define AST_CI2C_DEVICE5 0x140 +#define AST_CI2C_DEVICE6 0x180 +#define AST_CI2C_DEVICE7 0x1c0 +#define AST_CI2C_DEVICE8 0x200 +#endif + +/*AST I2C Register Definition */ +#if defined(CONFIG_ARCH_AST2400) || defined(CONFIG_AST2400_BMC) +#define AST_I2C_POOL_BUFF_2048 +#define AST_I2C_GLOBAL_REG 0x00 +#define AST_I2C_DEVICE1 0x40 +#define AST_I2C_DEVICE2 0x80 +#define AST_I2C_DEVICE3 0xc0 +#define AST_I2C_DEVICE4 0x100 +#define AST_I2C_DEVICE5 0x140 +#define AST_I2C_DEVICE6 0x180 +#define AST_I2C_DEVICE7 0x1c0 +#define AST_I2C_BUFFER_POOL2 0x200 +#define AST_I2C_DEVICE8 0x300 +#define AST_I2C_DEVICE9 0x340 +#define AST_I2C_DEVICE10 0x380 +#define AST_I2C_DEVICE11 0x3c0 +#define AST_I2C_DEVICE12 0x400 +#define AST_I2C_DEVICE13 0x440 +#define AST_I2C_DEVICE14 0x480 +#define AST_I2C_BUFFER_POOL1 0x800 + +#elif defined(CONFIG_ARCH_AST2300) +#define AST_I2C_POOL_BUFF_256 +#define AST_I2C_GLOBAL_REG 0x00 +#define AST_I2C_DEVICE1 0x40 +#define AST_I2C_DEVICE2 0x80 +#define AST_I2C_DEVICE3 0xc0 +#define AST_I2C_DEVICE4 0x100 +#define AST_I2C_DEVICE5 0x140 +#define AST_I2C_DEVICE6 0x180 +#define AST_I2C_DEVICE7 0x1c0 +#define AST_I2C_BUFFER_POOL2 0x200 +#define AST_I2C_DEVICE8 0x300 +#define AST_I2C_DEVICE9 0x340 +#elif defined(CONFIG_ARCH_AST1010) +#define AST_I2C_GLOBAL_REG 0x00 +#define AST_I2C_DEVICE1 0x40 +#define AST_I2C_DEVICE2 0x80 +#define AST_I2C_DEVICE3 0xc0 +#define AST_I2C_DEVICE4 0x100 +#define AST_I2C_DEVICE5 0x140 +#define AST_I2C_DEVICE6 0x180 +#define AST_I2C_DEVICE7 0x1c0 +#define AST_I2C_DEVICE8 0x200 +#define AST_I2C_DEVICE9 0x240 +#define AST_I2C_DEVICE10 0x280 +#define AST_I2C_DEVICE11 0x2c0 +#define AST_I2C_DEVICE12 0x300 +#define AST_I2C_DEVICE13 0x340 +#define AST_I2C_DEVICE14 0x380 +#define AST_I2C_DEVICE15 0x3c0 +#elif defined(CONFIG_ARCH_AST1520) || defined(CONFIG_ARCH_AST3200) || defined(CONFIG_ARCH_AST2500) +#define AST_I2C_GLOBAL_REG 0x00 +#define AST_I2C_DEVICE1 0x40 +#define AST_I2C_DEVICE2 0x80 +#define AST_I2C_DEVICE3 0xc0 +#define AST_I2C_DEVICE4 0x100 +#else +#err "NO define for I2C" +#endif + + + +/* I2C Register */ +#define I2C_FUN_CTRL_REG 0x00 +#define I2C_AC_TIMING_REG1 0x04 +#define I2C_AC_TIMING_REG2 0x08 +#define I2C_INTR_CTRL_REG 0x0c +#define I2C_INTR_STS_REG 0x10 +#define I2C_CMD_REG 0x14 +#define I2C_DEV_ADDR_REG 0x18 +#define I2C_BUF_CTRL_REG 0x1c +#define I2C_BYTE_BUF_REG 0x20 +#define I2C_DMA_BASE_REG 0x24 +#define I2C_DMA_LEN_REG 0x28 + + +/* Gloable Register Definition */ +/* 0x00 : I2C Interrupt Status Register */ +/* 0x08 : I2C Interrupt Target Assignment */ +#if defined(CONFIG_ARCH_AST2400) +#define AST_I2CG_INTR14 (0x1 << 13) +#define AST_I2CG_INTR13 (0x1 << 12) +#define AST_I2CG_INTR12 (0x1 << 11) +#define AST_I2CG_INTR11 (0x1 << 10) +#define AST_I2CG_INTR10 (0x1 << 9) +#elif defined(CONFIG_ARCH_AST1010) +#define AST_I2CG_INTR14 (0x1 << 13) +#define AST_I2CG_INTR13 (0x1 << 12) +#define AST_I2CG_INTR12 (0x1 << 11) +#define AST_I2CG_INTR11 (0x1 << 10) +#define AST_I2CG_INTR10 (0x1 << 9) +#endif +#define AST_I2CG_INTR09 (0x1 << 8) +#define AST_I2CG_INTR08 (0x1 << 7) +#define AST_I2CG_INTR07 (0x1 << 6) +#define AST_I2CG_INTR06 (0x1 << 5) +#define AST_I2CG_INTR05 (0x1 << 4) +#define AST_I2CG_INTR04 (0x1 << 3) +#define AST_I2CG_INTR03 (0x1 << 2) +#define AST_I2CG_INTR02 (0x1 << 1) +#define AST_I2CG_INTR01 (0x1 ) + +/* Device Register Definition */ +/* 0x00 : I2CD Function Control Register */ +#define AST_I2CD_BUFF_SEL_MASK (0x7 << 20) +#define AST_I2CD_BUFF_SEL(x) (x << 20) // page 0 ~ 7 +#define AST_I2CD_M_SDA_LOCK_EN (0x1 << 16) +#define AST_I2CD_MULTI_MASTER_DIS (0x1 << 15) +#define AST_I2CD_M_SCL_DRIVE_EN (0x1 << 14) +#define AST_I2CD_MSB_STS (0x1 << 9) +#define AST_I2CD_SDA_DRIVE_1T_EN (0x1 << 8) +#define AST_I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7) +#define AST_I2CD_M_HIGH_SPEED_EN (0x1 << 6) +#define AST_I2CD_DEF_ADDR_EN (0x1 << 5) +#define AST_I2CD_DEF_ALERT_EN (0x1 << 4) +#define AST_I2CD_DEF_ARP_EN (0x1 << 3) +#define AST_I2CD_DEF_GCALL_EN (0x1 << 2) +#define AST_I2CD_SLAVE_EN (0x1 << 1) +#define AST_I2CD_MASTER_EN (0x1 ) + +/* 0x04 : I2CD Clock and AC Timing Control Register #1 */ +#define AST_I2CD_tBUF (0x1 << 28) // 0~7 +#define AST_I2CD_tHDSTA (0x1 << 24) // 0~7 +#define AST_I2CD_tACST (0x1 << 20) // 0~7 +#define AST_I2CD_tCKHIGH (0x1 << 16) // 0~7 +#define AST_I2CD_tCKLOW (0x1 << 12) // 0~7 +#define AST_I2CD_tHDDAT (0x1 << 10) // 0~7 +#define AST_I2CD_CLK_TO_BASE_DIV (0x1 << 8) // 0~3 +#define AST_I2CD_CLK_BASE_DIV (0x1 ) // 0~0xf + +/* 0x08 : I2CD Clock and AC Timing Control Register #2 */ +#define AST_I2CD_tTIMEOUT (0x1 ) // 0~7 +#define AST_NO_TIMEOUT_CTRL 0x0 + + +/* 0x0c : I2CD Interrupt Control Register */ +#define AST_I2CD_SDA_DL_TO_INTR_EN (0x1 << 14) +#define AST_I2CD_BUS_RECOVER_INTR_EN (0x1 << 13) +#define AST_I2CD_SMBUS_ALT_INTR_EN (0x1 << 12) +#define AST_I2CD_SLAVE_MATCH_INTR_EN (0x1 << 7) +#define AST_I2CD_SCL_TO_INTR_EN (0x1 << 6) +#define AST_I2CD_ABNORMAL_INTR_EN (0x1 << 5) +#define AST_I2CD_NORMAL_STOP_INTR_EN (0x1 << 4) +#define AST_I2CD_ARBIT_LOSS_INTR_EN (0x1 << 3) +#define AST_I2CD_RX_DOWN_INTR_EN (0x1 << 2) +#define AST_I2CD_TX_NAK_INTR_EN (0x1 << 1) +#define AST_I2CD_TX_ACK_INTR_EN (0x1 ) + +/* 0x10 : I2CD Interrupt Status Register : WC */ +#define AST_I2CD_INTR_STS_SDA_DL_TO (0x1 << 14) +#define AST_I2CD_INTR_STS_BUS_RECOVER (0x1 << 13) +#define AST_I2CD_INTR_STS_SMBUS_ALT (0x1 << 12) +#define AST_I2CD_INTR_STS_SMBUS_ARP_ADDR (0x1 << 11) +#define AST_I2CD_INTR_STS_SMBUS_DEV_ALT (0x1 << 10) +#define AST_I2CD_INTR_STS_SMBUS_DEF_ADDR (0x1 << 9) +#define AST_I2CD_INTR_STS_GCALL_ADDR (0x1 << 8) +#define AST_I2CD_INTR_STS_SLAVE_MATCH (0x1 << 7) +#define AST_I2CD_INTR_STS_SCL_TO (0x1 << 6) +#define AST_I2CD_INTR_STS_ABNORMAL (0x1 << 5) +#define AST_I2CD_INTR_STS_NORMAL_STOP (0x1 << 4) +#define AST_I2CD_INTR_STS_ARBIT_LOSS (0x1 << 3) +#define AST_I2CD_INTR_STS_RX_DOWN (0x1 << 2) +#define AST_I2CD_INTR_STS_TX_NAK (0x1 << 1) +#define AST_I2CD_INTR_STS_TX_ACK (0x1 ) + +/* 0x14 : I2CD Command/Status Register */ +#define AST_I2CD_SDA_OE (0x1 << 28) +#define AST_I2CD_SDA_O (0x1 << 27) +#define AST_I2CD_SCL_OE (0x1 << 26) +#define AST_I2CD_SCL_O (0x1 << 25) +#define AST_I2CD_TX_TIMING (0x1 << 24) // 0 ~3 +#define AST_I2CD_TX_STATUS (0x1 << 23) +// Tx State Machine +#define AST_I2CD_IDLE 0x0 +#define AST_I2CD_MACTIVE 0x8 +#define AST_I2CD_MSTART 0x9 +#define AST_I2CD_MSTARTR 0xa +#define AST_I2CD_MSTOP 0xb +#define AST_I2CD_MTXD 0xc +#define AST_I2CD_MRXACK 0xd +#define AST_I2CD_MRXD 0xe +#define AST_I2CD_MTXACK 0xf +#define AST_I2CD_SWAIT 0x1 +#define AST_I2CD_SRXD 0x4 +#define AST_I2CD_STXACK 0x5 +#define AST_I2CD_STXD 0x6 +#define AST_I2CD_SRXACK 0x7 +#define AST_I2CD_RECOVER 0x3 + +#define AST_I2CD_SCL_LINE_STS (0x1 << 18) +#define AST_I2CD_SDA_LINE_STS (0x1 << 17) +#define AST_I2CD_BUS_BUSY_STS (0x1 << 16) +#define AST_I2CD_SDA_OE_OUT_DIR (0x1 << 15) +#define AST_I2CD_SDA_O_OUT_DIR (0x1 << 14) +#define AST_I2CD_SCL_OE_OUT_DIR (0x1 << 13) +#define AST_I2CD_SCL_O_OUT_DIR (0x1 << 12) +#define AST_I2CD_BUS_RECOVER_CMD_EN (0x1 << 11) +#define AST_I2CD_S_ALT_EN (0x1 << 10) +// 0 : DMA Buffer, 1: Pool Buffer +//AST1070 DMA register +#define AST_I2CD_RX_DMA_ENABLE (0x1 << 9) +#define AST_I2CD_TX_DMA_ENABLE (0x1 << 8) + +/* Command Bit */ +#define AST_I2CD_RX_BUFF_ENABLE (0x1 << 7) +#define AST_I2CD_TX_BUFF_ENABLE (0x1 << 6) +#define AST_I2CD_M_STOP_CMD (0x1 << 5) +#define AST_I2CD_M_S_RX_CMD_LAST (0x1 << 4) +#define AST_I2CD_M_RX_CMD (0x1 << 3) +#define AST_I2CD_S_TX_CMD (0x1 << 2) +#define AST_I2CD_M_TX_CMD (0x1 << 1) +#define AST_I2CD_M_START_CMD (0x1 ) + +/* 0x18 : I2CD Slave Device Address Register */ + +/* 0x1C : I2CD Pool Buffer Control Register */ +#define AST_I2CD_RX_BUF_ADDR_GET(x) ((x>> 24)& 0xff) +#define AST_I2CD_RX_BUF_END_ADDR_SET(x) (x << 16) +#define AST_I2CD_TX_DATA_BUF_END_SET(x) ((x&0xff) << 8) +#define AST_I2CD_TX_DATA_BUF_GET(x) ((x >>8) & 0xff) +#define AST_I2CD_BUF_BASE_ADDR_SET(x) (x & 0x3f) + +/* 0x20 : I2CD Transmit/Receive Byte Buffer Register */ +#define AST_I2CD_GET_MODE(x) ((x >> 8) & 0x1) + +#define AST_I2CD_RX_BYTE_BUFFER (0xff << 8) +#define AST_I2CD_TX_BYTE_BUFFER (0xff ) + + +#endif /* __ASM_ARCH_REGS_IIC_H */ diff --git a/arch/arm/plat-aspeed/include/plat/regs-intr.h b/arch/arm/plat-aspeed/include/plat/regs-intr.h new file mode 100644 index 000000000000..cea0132d08f6 --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-intr.h @@ -0,0 +1,74 @@ +/* arch/arm/mach-aspeed/include/mach/regs-intr.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * History : + * 1. 2012/08/15 Ryan Chen Create + * +********************************************************************************/ +#ifndef __ASPEED_AST_INTR_H +#define __ASPEED_AST_INTR_H 1 + +#ifndef __ASSEMBLY__ +#include <asm/io.h> +#endif +//============== INTERRUPT======================================== +#include <mach/platform.h> +#include <mach/irqs.h> +#include <plat/aspeed.h> + +/* + * VIC Register (VA) + */ + +#define VIC_BASE_VA IO_ADDRESS(AST_VIC_BASE) + +#if defined(NEW_VIC) +//New Mappling + +#define AST_IRQ_STS(x) (VIC_BASE_VA + 0x80 + (x*0x04)) +#define AST_FIQ_STS(x) (VIC_BASE_VA + 0x88 + (x*0x04)) +#define AST_RAW_STS(x) (VIC_BASE_VA + 0x90 + (x*0x04)) +#define AST_INTR_SEL(x) (VIC_BASE_VA + 0x98 + (x*0x04)) +#define AST_INTR_EN(x) (VIC_BASE_VA + 0xA0 + (x*0x04)) +#define AST_INTR_DIS(x) (VIC_BASE_VA + 0xA8 + (x*0x04)) +#define AST_INTR_SW_EN(x) (VIC_BASE_VA + 0xB0 + (x*0x04)) +#define AST_INTR_SW_CLR(x) (VIC_BASE_VA + 0xB8 + (x*0x04)) +#define AST_INTR_SENSE(x) (VIC_BASE_VA + 0xC0 + (x*0x04)) +#define AST_INTR_BOTH_EDGE(x) (VIC_BASE_VA + 0xC8 + (x*0x04)) +#define AST_INTR_EVENT(x) (VIC_BASE_VA + 0xD0 + (x*0x04)) +#define AST_INTR_EDGE_CLR(x) (VIC_BASE_VA + 0xD8 + (x*0x04)) +#define AST_INTR_EDGE_STS(x) (VIC_BASE_VA + 0xE0 + (x*0x04)) + +#else + +//Legacy Maping + +#define AST_IRQ_STS(x) (VIC_BASE_VA + 0x00) +#define AST_FIQ_STS(x) (VIC_BASE_VA + 0x04) +#define AST_RAW_STS(x) (VIC_BASE_VA + 0x08) +#define AST_INTR_SEL(x) (VIC_BASE_VA + 0x0C) +#define AST_INTR_EN(x) (VIC_BASE_VA + 0x10) +#define AST_INTR_DIS(x) (VIC_BASE_VA + 0x14) +#define AST_INTR_SW_EN(x) (VIC_BASE_VA + 0x18) +#define AST_INTR_SW_CLR(x) (VIC_BASE_VA + 0x1C) +#define AST_INTR_SENSE(x) (VIC_BASE_VA + 0x24) +#define AST_INTR_BOTH_EDGE(x) (VIC_BASE_VA + 0x28) +#define AST_INTR_EVENT(x) (VIC_BASE_VA + 0x2C) +#define AST_INTR_EDGE_CLR(x) (VIC_BASE_VA + 0x38) +#endif + +#define IRQ_SET_LEVEL_TRIGGER(x, irq_no) *((volatile unsigned long*)AST_INTR_SENSE(x)) |= 1 << (irq_no) +#define IRQ_SET_EDGE_TRIGGER(x, irq_no) *((volatile unsigned long*)AST_INTR_SENSE(x)) &= ~(1 << (irq_no)) +#define IRQ_SET_RISING_EDGE(x, irq_no) *((volatile unsigned long*)AST_INTR_EVENT(x)) |= 1 << (irq_no) +#define IRQ_SET_FALLING_EDGE(x, irq_no) *((volatile unsigned long*)AST_INTR_EVENT(x)) &= ~(1 << (irq_no)) +#define IRQ_SET_HIGH_LEVEL(x,irq_no) *((volatile unsigned long*)AST_INTR_EVENT(x)) |= 1 << (irq_no) +#define IRQ_SET_LOW_LEVEL(x, irq_no) *((volatile unsigned long*)AST_INTR_EVENT(x)) &= ~(1 << (irq_no)) +#define IRQ_EDGE_CLEAR(x, irq_no) *((volatile unsigned long*)AST_INTR_EDGE_CLR(x)) |= 1 << (irq_no) + +#endif + diff --git a/arch/arm/plat-aspeed/include/plat/regs-jtag.h b/arch/arm/plat-aspeed/include/plat/regs-jtag.h new file mode 100644 index 000000000000..7df385d18512 --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-jtag.h @@ -0,0 +1,65 @@ +/* arch/arm/plat-aspeed/include/mach/regs-jtag.h + * + * Copyright (c) 2012 ASPEED Technology Inc. <ryan_chen@aspeedtech.com> + * http://www.aspeedtech.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ASPEED JTAG Controller +*/ + +#define AST_JTAG_DATA 0x00 +#define AST_JTAG_INST 0x04 +#define AST_JTAG_CTRL 0x08 +#define AST_JTAG_ISR 0x0C +#define AST_JTAG_SW 0x10 +#define AST_JTAG_TCK 0x14 +#define AST_JTAG_IDLE 0x18 + +/* AST_JTAG_CTRL - 0x08 : Engine Control */ +#define JTAG_ENG_EN (0x1 << 31) +#define JTAG_ENG_OUT_EN (0x1 << 30) +#define JTAG_FORCE_TMS (0x1 << 29) + +#define JTAG_IR_UPDATE (0x1 << 26) //AST2500 only +#define JTAG_INST_LEN_MASK (0x3f << 20) +#define JTAG_SET_INST_LEN(x) (x << 20) +#define JTAG_SET_INST_MSB (0x1 << 19) +#define JTAG_TERMINATE_INST (0x1 << 18) +#define JTAG_LAST_INST (0x1 << 17) +#define JTAG_INST_EN (0x1 << 16) +#define JTAG_DATA_LEN_MASK (0x3f << 4) + +#define JTAG_DR_UPDATE (0x1 << 10) //AST2500 only +#define JTAG_DATA_LEN(x) (x << 4) +#define JTAG_SET_DATA_MSB (0x1 << 3) +#define JTAG_TERMINATE_DATA (0x1 << 2) +#define JTAG_LAST_DATA (0x1 << 1) +#define JTAG_DATA_EN (0x1) + +/* AST_JTAG_ISR - 0x0C : INterrupt status and enable */ +#define JTAG_INST_PAUSE (0x1 << 19) +#define JTAG_INST_COMPLETE (0x1 << 18) +#define JTAG_DATA_PAUSE (0x1 << 17) +#define JTAG_DATA_COMPLETE (0x1 << 16) + +#define JTAG_INST_PAUSE_EN (0x1 << 3) +#define JTAG_INST_COMPLETE_EN (0x1 << 2) +#define JTAG_DATA_PAUSE_EN (0x1 << 1) +#define JTAG_DATA_COMPLETE_EN (0x1) + + +/* AST_JTAG_SW - 0x10 : Software Mode and Status */ +#define JTAG_SW_MODE_EN (0x1 << 19) +#define JTAG_SW_MODE_TCK (0x1 << 18) +#define JTAG_SW_MODE_TMS (0x1 << 17) +#define JTAG_SW_MODE_TDIO (0x1 << 16) +// +#define JTAG_STS_INST_PAUSE (0x1 << 2) +#define JTAG_STS_DATA_PAUSE (0x1 << 1) +#define JTAG_STS_ENG_IDLE (0x1) + +/* AST_JTAG_IDLE - 0x18 : Ctroller set for go to IDLE */ +#define JTAG_GO_IDLE (0x1) diff --git a/arch/arm/plat-aspeed/include/plat/regs-lpc.h b/arch/arm/plat-aspeed/include/plat/regs-lpc.h new file mode 100644 index 000000000000..f4523d7eaeb0 --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-lpc.h @@ -0,0 +1,215 @@ +/* arch/arm/plat-aspeed/include/mach/regs-lpc.h + * + * Copyright (c) 2012 ASPEED Technology Inc. <ryan_chen@aspeedtech.com> + * http://www.aspeedtech.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ASPEED LPC Controller +*/ + +#ifndef __AST_LPC_H_ +#define __AST_LPC_H_ + +#define AST_LPC_HICR0 0x000 +#define AST_LPC_HICR1 0x004 +#define AST_LPC_HICR2 0x008 /* Host Interface Control Register 2 */ +#define AST_LPC_HICR3 0x00C +#define AST_LPC_HICR4 0x010 +#define AST_LPC_LADR3H 0x014 +#define AST_LPC_LADR3L 0x018 +#define AST_LPC_LADR12H 0x01C +#define AST_LPC_LADR12L 0x020 +#define AST_LPC_IDR1 0x024 +#define AST_LPC_IDR2 0x028 +#define AST_LPC_IDR3 0x02C +#define AST_LPC_ODR1 0x030 +#define AST_LPC_ODR2 0x034 +#define AST_LPC_ODR3 0x038 +#define AST_LPC_STR1 0x03C +#define AST_LPC_STR2 0x040 +#define AST_LPC_STR3 0x044 +#define AST_LPC_BTR0 0x048 +#define AST_LPC_BTR1 0x04C +#define AST_LPC_BTCSR0 0x050 +#define AST_LPC_BTCSR1 0x054 +#define AST_LPC_BTCR 0x058 +#define AST_LPC_BTDTR 0x05C +#define AST_LPC_BTIMSR 0x060 +#define AST_LPC_BTFVSR0 0x064 +#define AST_LPC_BTFVSR1 0x068 +#define AST_LPC_SIRQCR0 0x06C +#define AST_LPC_SIRQCR1 0x070 +#define AST_LPC_SIRQCR2 0x074 +#define AST_LPC_SIRQCR3 0x078 + +////// +#define AST_LPC_HICR5 0x080 /* LPC Host interface Control Register 5 */ +#define AST_LPC_HICR6 0x084 /* LPC Host Interface Control Register 6 */ +#define AST_LPC_HICR7 0x088 +#define AST_LPC_HICR8 0x08C +#define AST_LPC_SNPWADR 0x090 /* LPC Snoop Address Register */ +#define AST_LPC_SNPWDR 0x094 /* LPC SNoop Data Register */ +#define AST_LPC_HICR9 0x098 +#define AST_LPC_HICRA 0x09C +#define AST_LPC_LHCR0 0x0A0 +#define AST_LPC_LHCR1 0x0A4 +#define AST_LPC_LHCR2 0x0A8 +#define AST_LPC_LHCR3 0x0AC +#define AST_LPC_LHCR4 0x0B0 +#define AST_LPC_LHCR5 0x0B4 +#define AST_LPC_LHCR6 0x0B8 +#define AST_LPC_LHCR7 0x0BC +#define AST_LPC_LHCR8 0x0C0 +#define AST_LPC_PCCR6 0x0C4 +#define AST_LPC_LHCRA 0x0C8 +#define AST_LPC_LHCRB 0x0CC + + +#define AST_LPC_PCCR4 0x0D0 /* Post Code Control Regiter 4 */ +#define AST_LPC_PCCR5 0x0D4 /* Post Code Control Regiter 5 */ + +#define AST_LPC_HICRB 0x0D8 +#define AST_LPC_HICRC 0x0DC +#define AST_LPC_HISR0 0x0E0 +#define AST_LPC_HISR1 0x0E4 +#define AST_LPC_LADR4 0x0E8 +#define AST_LPC_IDR4 0x0EC +#define AST_LPC_ODR4 0x0F0 +#define AST_LPC_STR4 0x0F4 +#define AST_LPC_LSADR12 0x0F8 +#define AST_LPC_IDR5 0x0FC +#define AST_LPC_ODR5 0x100 +#define AST_LPC_STR5 0x104 + + + +#define AST_LPC_PCCR0 0x130 /*Post Code Contol Register 0 */ +#define AST_LPC_PCCR1 0x134 /*Post Code Contol Register 1 */ +#define AST_LPC_PCCR2 0x138 /*Post Code Contol Register 2 */ +#define AST_LPC_PCCR3 0x13C /*Post Code Contol Register 3 */ + + +#define AST_LPC_IBTCR0 0x140 +#define AST_LPC_IBTCR1 0x144 +#define AST_LPC_IBTCR2 0x148 +#define AST_LPC_IBTCR3 0x14C +#define AST_LPC_IBTCR4 0x150 +#define AST_LPC_IBTCR5 0x154 +#define AST_LPC_IBTCR6 0x158 +#define AST_LPC_SRUART1 0x15C +#define AST_LPC_SRUART2 0x160 +#define AST_LPC_SRUART3 0x164 +#define AST_LPC_SRUART4 0x168 +#define AST_LPC_SCR0SIO 0x16C +#define AST_LPC_SCR0SI1 0x170 +#define AST_LPC_SCR0SI2 0x174 +#define AST_LPC_SCR0SI3 0x17C + +#define AST_LPC_SWCR0300 0x180 +#define AST_LPC_SWCR0704 0x184 +#define AST_LPC_SWCR0B08 0x188 +#define AST_LPC_SWCR0F0C 0x18C +#define AST_LPC_SWCR1310 0x190 +#define AST_LPC_SWCR1714 0x194 +#define AST_LPC_SWCR1B18 0x198 +#define AST_LPC_SWCR1F1C 0x19C +#define AST_LPC_ACPIE3E0 0x1A0 +#define AST_LPC_ACPIC1C0 0x1A4 +#define AST_LPC_ACPIB3B0 0x1A8 +#define AST_LPC_ACPIB7B4 0x1AC + +/* AST_LPC_HICR0 0x000 */ +#define LPC_LPC3_EN (1 << 7) +#define LPC_LPC2_EN (1 << 6) +#define LPC_LPC1_EN (1 << 5) + +#define LPC_SDWNE (1 << 3) +#define LPC_PMEE (1 << 2) + +/* AST_LPC_HICR2 0x008 */ +#define LPC_LRST (1 << 6) +#define LPC_SDWN (1 << 5) +#define LPC_ABRT (1 << 4) +#define LPC_IBFIF3 (1 << 3) +#define LPC_IBFIF2 (1 << 2) +#define LPC_IBFIF1 (1 << 1) +#define LPC_EERIE (1) + + + + + + + +/* AST_LPC_HICR4 0x010 */ +#define LPC_HICS_LADR12AS (1 << 7) +#define LPC_HICS_CLRINTLRSTR (1 << 6) +#define LPC_HICS_STSINTLRSTR (1 << 5) +#define LPC_HICS_ENINTLRSTR (1 << 4) +/* bit 3 reserved */ +#define LPC_HICS_KCSENBL (1 << 2) +/* bit 1 reserved */ +#define LPC_HICS_BTENBL (1) + + +/* AST_LPC_STR1 0: 0x03C, 1: 0x40, 2 : 0x44, 3: 4: */ +#define LPC_STR_DBU4 (1 << 7) +#define LPC_STR_DBU3 (1 << 6) +#define LPC_STR_DBU2 (1 << 5) +#define LPC_STR_DBU1 (1 << 4) +#define LPC_STR_CMD_DAT (1 << 3) +#define LPC_STR_DBU0 (1 << 2) +#define LPC_STR_IBF (1 << 1) +#define LPC_STR_OBF (1) + + +/* AST_LPC_HICR5 0x080 - LPC Host interface Control Register */ +#define LPC_HICR5_SNP1INT_EN (1 << 3) +#define LPC_HICR5_SNP1W_EN (1 << 2) +#define LPC_HICR5_SNP0INT_EN (1 << 1) +#define LPC_HICR5_SNP0W_EN (1) + +/* AST_LPC_HICR6 0x084 - LPC Host Interface Control Register 6 */ +#define LPC_HICR6_STR_BAUD (1 << 3) +#define LPC_HICR6_STR_PME (1 << 2) +#define LPC_HICR6_STR_SNP1W (1 << 1) +#define LPC_HICR6_STR_SNP0W (1) + +/* AST_LPC_SNPWADR 0x090 - LPC Snoop Address Register*/ +#define LPC_SNOOP_ADDR1_MASK (0xffff << 16) +#define LPC_SNOOP_ADDR0_MASK (0xffff) + +/* AST_LPC_SNPWDR 0x094 - LPC SNoop Data Register */ +#define GET_LPC_SNPD1(x) ((x >> 7) & 0xff) +#define GET_LPC_SNPD0(x) (x & 0xff) + +/*AST_LPC_PCCR0 0x130 - Post Code Contol Register 0 */ +#define LPC_POST_DMA_INT_EN (1 << 31) +#define LPC_POST_DMA_MODE_EN (1 << 14) +#define LPC_RX_FIFO_CLR (1 << 7) +#define LPC_POST_ +#define LPC_POST_CODE_MODE_MASK (0x3 << 4) +#define LPC_POST_CODE_MODE(x) (x << 4) +#define BYTE_MODE 0 +#define WORD_MODE 1 +#define DWORD_MODE 2 +#define FULL_MODE 3 + +#define LPC_POST_CODE_RXOVR (1 << 3) +#define LPC_POST_CODE_RXTO (1 << 2) +#define LPC_POST_CODE_RXAVA (1 << 1) +#define LPC_POST_CODE_EN (1) + +/*AST_LPC_PCCR1 0x134 Post Code Contol Register 1 */ +#define LPC_POST_ADDR_MASK 0x3fffff +#define LPC_CAPTURE_ADDR_MASK(x) (x << 16) +#define LPC_CAPTURE_BASE_ADDR(x) (x) + +/*AST_LPC_PCCR2 0x138 Post Code Contol Register 2 */ +#define LPC_POST_CODE_DMA_RDY (1 << 4) +#define LPC_POST_CODE_STS (1) + +#endif diff --git a/arch/arm/plat-aspeed/include/plat/regs-mbx.h b/arch/arm/plat-aspeed/include/plat/regs-mbx.h new file mode 100644 index 000000000000..636207fb91dd --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-mbx.h @@ -0,0 +1,48 @@ +/* arch/arm/plat-aspeed/include/mach/regs-lpc.h + * + * Copyright (c) 2012 ASPEED Technology Inc. <ryan_chen@aspeedtech.com> + * http://www.aspeedtech.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ASPEED LPC Controller +*/ + +#ifndef __AST_MBX_H_ +#define __AST_MBX_H_ + +#define AST_MBX_DAT0 0x00 +#define AST_MBX_DAT1 0x04 +#define AST_MBX_DAT2 0x08 +#define AST_MBX_DAT3 0x0C +#define AST_MBX_DAT4 0x10 +#define AST_MBX_DAT5 0x14 +#define AST_MBX_DAT6 0x18 +#define AST_MBX_DAT7 0x1C +#define AST_MBX_DAT8 0x20 +#define AST_MBX_DAT9 0x24 +#define AST_MBX_DATA 0x28 +#define AST_MBX_DATB 0x2C +#define AST_MBX_DATC 0x30 +#define AST_MBX_DATD 0x34 +#define AST_MBX_DATE 0x38 +#define AST_MBX_DATF 0x3C +#define AST_MBX_STS0 0x40 +#define AST_MBX_STS1 0x44 +#define AST_MBX_BCR 0x48 +#define AST_MBX_HCR 0x4C +#define AST_MBX_BIE0 0x50 +#define AST_MBX_BIE1 0x54 +#define AST_MBX_HIE0 0x58 +#define AST_MBX_HIE1 0x5C + +/* AST_MBX_BCR 0x48 */ +#define MBHIST (1 << 7) +#define MBHMK (1 << 1) +#define MBBINT (1) + + + +#endif diff --git a/arch/arm/plat-aspeed/include/plat/regs-mctp.h b/arch/arm/plat-aspeed/include/plat/regs-mctp.h new file mode 100644 index 000000000000..2237cfebd0ab --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-mctp.h @@ -0,0 +1,47 @@ +/* arch/arm/mach-aspeed/include/mach/regs-ast1010-scu.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * History : + * 1. 2012/12/29 Ryan Chen Create + * +********************************************************************************/ +#ifndef __AST_MCTP_H +#define __AST_MCTP_H 1 + +/* + * Register for MCTP + * */ +#define AST_MCTP_CTRL 0x00 /* Engine Status and Engine Control */ +#define AST_MCTP_INT 0x04 /* Interrupt Enable and Status Register */ +#define AST_MCTP_ID 0x08 /* Target ID and Mask */ +#define AST_MCTP_TX_DESC3 0x10 /* Sending Descriptor [127:96] */ +#define AST_MCTP_TX_DESC2 0x14 /* Sending Descriptor [95:64] */ +#define AST_MCTP_TX_DESC1 0x18 /* Sending Descriptor [63:32] */ +#define AST_MCTP_TX_DESC0 0x1C /* Sending Descriptor [31:0] */ +#define AST_MCTP_TX_DATA 0x20 /* Sending Data Port */ +#define AST_MCTP_RX_DESC3 0x40 /* Received Descriptor [127:96] */ +#define AST_MCTP_RX_DESC2 0x44 /* Received Descriptor [95:64] */ +#define AST_MCTP_RX_DESC1 0x48 /* Received Descriptor [63:32] */ +#define AST_MCTP_RX_DESC0 0x4C /* Received Descriptor [31:0] */ +#define AST_MCTP_RX_DATA 0x50 /* Received Data Port */ + +#define AST_MCTP_DEC_ADDR 0x80 /* ADDR */ +#define AST_MCTP_DEC_MASK 0x84 /* MASK */ +#define AST_MCTP_DEC_TAG 0x88 /* TAG */ + +/* AST_MCTP_CTRL 0x00 Engine Status and Engine Control */ + +/* AST_MCTP_INT 0x04 Interrupt Enable and Status Register */ +#define MCTP_RX_INT_EN (1 << 17) +#define MCTP_TX_INT_EN (1 << 16) + +#define MCTP_RX_COMPLETE (1 << 1) +#define MCTP_TX_COMPLETE (1) + +#endif + diff --git a/arch/arm/plat-aspeed/include/plat/regs-pcie.h b/arch/arm/plat-aspeed/include/plat/regs-pcie.h new file mode 100644 index 000000000000..bd699fc82f5a --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-pcie.h @@ -0,0 +1,68 @@ +/* arch/arm/mach-aspeed/include/mach/regs-ast1010-scu.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * History : + * 1. 2012/12/29 Ryan Chen Create + * +********************************************************************************/ +#ifndef __AST_PCIE_H +#define __AST_PCIE_H 1 + +/* + * Register for PCIE + * */ +#define AST_PCIE_CFG2 0x04 +#define AST_PCIE_SSID 0x28 +#define AST_PCIE_GLOBAL 0x30 +#define AST_PCIE_LOCK 0x7C + +#define AST_PCIE_LINK 0xC0 +#define AST_PCIE_INT 0xC4 + +/* AST_PCIE_CFG2 0x04 */ +#define PCIE_CFG_CLASS_CODE(x) (x << 8) +#define PCIE_CFG_REV_ID(x) (x) + + +/*SSID: 1E6ED028h[19:4]*/ +/*SSVID: 1E6ED028h[3:0], 1E6ED024h[31:20]*/ + +/* AST_PCIE_SSID_A 0x24 */ +/* 31:20 */ +#define PCIE_SSVID_H(x) (x) + +/* AST_PCIE_SSID_B 0x28 */ +/* 19:14 */ +#define PCIE_SSID(x) (x << 4) +/* 3:0 */ +#define PCIE_SSVID_L(x) (x) + + +/* AST_PCIE_GLOBAL 0x30 */ +#define ROOT_COMPLEX_ID(x) (x << 4) + + +/* AST_PCIE_LOCK 0x7C */ +#define PCIE_UNLOCK 0xa8 + +/* AST_PCIE_LINK 0xC0 */ +#define PCIE_LINK_STS (1 << 5) + +/* AST_PCIE_INT 0xC4 */ +#define PCIE_INTD (1 << 16) +#define PCIE_INTC (1 << 15) +#define PCIE_INTB (1 << 14) +#define PCIE_INTA (1 << 13) + +#define AST_PCIE_NONP_MEM_BASE AST_PCIE0_WIN_BASE0 +#define AST_PCIE_NONP_MEM_SIZE AST_PCIE0_WIN_SIZE0 +#define AST_PCIE_PREF_MEM_BASE 0x0 +#define AST_PCIE_PREF_MEM_SIZE 0x0 + +#endif + diff --git a/arch/arm/plat-aspeed/include/plat/regs-peci.h b/arch/arm/plat-aspeed/include/plat/regs-peci.h new file mode 100644 index 000000000000..266dacab5a2f --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-peci.h @@ -0,0 +1,106 @@ +/* arch/arm/plat-aspeed/include/mach/regs-peci.h + * + * Copyright (c) 2012 ASPEED Technology Inc. <ryan_chen@aspeedtech.com> + * http://www.aspeedtech.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ASPEED PECI Controller +*/ + +#ifndef __ASM_ARCH_REGS_PECI_H +#define __ASM_ARCH_REGS_PECI_H __FILE__ + +/*AST PECI Register Definition */ +#define AST_PECI_CTRL 0x00 +#define AST_PECI_TIMING 0x04 +#define AST_PECI_CMD 0x08 +#define AST_PECI_CMD_CTRL 0x0C +#define AST_PECI_EXP_FCS 0x10 +#define AST_PECI_CAP_FCS 0x14 +#define AST_PECI_INT_CTRL 0x18 +#define AST_PECI_INT_STS 0x1C +#define AST_PECI_W_DATA0 0x20 +#define AST_PECI_W_DATA1 0x24 +#define AST_PECI_W_DATA2 0x28 +#define AST_PECI_W_DATA3 0x2c +#define AST_PECI_R_DATA0 0x30 +#define AST_PECI_R_DATA1 0x34 +#define AST_PECI_R_DATA2 0x38 +#define AST_PECI_R_DATA3 0x3c +#define AST_PECI_W_DATA4 0x40 +#define AST_PECI_W_DATA5 0x44 +#define AST_PECI_W_DATA6 0x48 +#define AST_PECI_W_DATA7 0x4c +#define AST_PECI_R_DATA4 0x50 +#define AST_PECI_R_DATA5 0x54 +#define AST_PECI_R_DATA6 0x58 +#define AST_PECI_R_DATA7 0x5c + + +/* AST_PECI_CTRL - 0x00 : Control Register */ +#define PECI_CTRL_SAMPLING_MASK (0xf << 16) +#define PECI_CTRL_SAMPLING(x) (x << 16) +#define PECI_CTRL_READ_MODE_MASK (0xf << 12) +#define PECI_CTRL_CONT_MODE (1 << 16) +#define PECI_CTRL_DBG_MODE (2 << 16) +#define PECI_CTRL_CLK_SOURCE (0x1 << 11) //0: 24Mhz, 1: MCLK +#define PECI_CTRL_CLK_DIV_MASK (0x3 << 8) +#define PECI_CTRL_CLK_DIV(x) (x << 8) +#define PECI_CTRL_INVERT_OUT (0x1 << 7) +#define PECI_CTRL_INVERT_IN (0x1 << 6) +#define PECI_CTRL_BUS_CONTENT_EN (0x1 << 5) +#define PECI_CTRL_PECI_EN (0x1 << 4) +#define PECI_CTRL_PECI_CLK_EN (0x1) + +/* AST_PECI_TIMING - 0x04 : Timing Negotiation */ +#define PECI_TIMING_MESSAGE_GET(x) ((x & 0xff00) >> 8) +#define PECI_TIMING_MESSAGE(x) (x << 8) +#define PECI_TIMING_ADDRESS_GET(x) (x & 0xff) +#define PECI_TIMING_ADDRESS(x) (x) + +/* AST_PECI_CMD - 0x08 : Command Register */ +#define PECI_CMD_PIN_MON (0x1 << 31) +#define PECI_CMD_STS (0xf << 24) +#define PECI_CMD_FIRE (0x1) + +/* AST_PECI_LEN - 0x0C : Read/Write Length Register */ +#define PECI_AW_FCS_EN (0x1 << 31) +#define PECI_READ_LEN_MASK (0xff << 16) +#define PECI_READ_LEN(x) (x << 16) +#define PECI_WRITE_LEN_MASK (0xff << 8) +#define PECI_WRITE_LEN(x) (x << 8) +#define PECI_TAGET_ADDR_MASK (0xff) +#define PECI_TAGET_ADDR(x) (x) + + +/* AST_PECI_EXP_FCS - 0x10 : Expected FCS Data Register */ +#define PECI_PROGRAM_AW_FCS (0xf << 24) +#define PECI_EXPECT_READ_FCS (0xf << 16) +#define PECI_EXPECT_AW_FCS_AUTO (0xf << 8) +#define PECI_EXPECT_WRITE_FCS (0xf) + +/* AST_PECI_CAP_FCS - 0x14 : Captured FCS Data Register */ +#define PECI_CAPTURE_READ_FCS(x) ((x & 0xff) >> 16) +#define PECI_CAPTURE_WRITE_FCS (0xff) + +/* AST_PECI_INT_CTRL/ STS - 0x18/0x1c : Interrupt Register */ +#define PECI_INT_TIMING_RESULT_MASK (0x3 << 30) +#define PECI_INT_TIMEOUT (0x1 << 4) +#define PECI_INT_CONNECT (0x1 << 3) +#define PECI_INT_W_FCS_BAD (0x1 << 2) +#define PECI_INT_W_FCS_ABORT (0x1 << 1) +#define PECI_INT_CMD_DONE (0x1) + +#define AUTO_GEN_AWFCS 1 +//#define ENABLE_BUS_CONTENTION 0x20 + +#define DISABLE_ENGINE 0 +#define ENABLE_RX_ENGINE (1 << 0) +#define ENABLE_TX_ENGINE (1 << 1) +#define LEFT_CHANNEL_HIGH (1 << 16) +#define DELAY_CLOCK_CYCLE (1 << 17) + +#endif /* __ASM_ARCH_REGS_PECI_H */ diff --git a/arch/arm/plat-aspeed/include/plat/regs-pwm_fan.h b/arch/arm/plat-aspeed/include/plat/regs-pwm_fan.h new file mode 100644 index 000000000000..23d5b77ed524 --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-pwm_fan.h @@ -0,0 +1,250 @@ +/* arch/arm/plat-aspeed/include/mach/regs-pwm-fan.h + * + * Copyright (c) 2012 ASPEED Technology Inc. <ryan_chen@aspeedtech.com> + * http://www.aspeedtech.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ASPEED PWM & Fan Tacho Controller +*/ + +#ifndef __ASM_ARCH_REGS_PWM_FAN_H +#define __ASM_ARCH_REGS_PWM_FAN_H __FILE__ + +/*AST PWM & FAN Register Definition */ +#define AST_PTCR_CTRL 0x00 +#define AST_PTCR_CLK_CTRL 0x04 +#define AST_PTCR_DUTY0_CTRL 0x08 +#define AST_PTCR_DUTY1_CTRL 0x0c +#define AST_PTCR_TYPEM_CTRL0 0x10 +#define AST_PTCR_TYPEM_CTRL1 0x14 +#define AST_PTCR_TYPEN_CTRL0 0x18 +#define AST_PTCR_TYPEN_CTRL1 0x1c +#define AST_PTCR_TACH_SOURCE 0x20 +// no 0x24 +#define AST_PTCR_TRIGGER 0x28 +#define AST_PTCR_RESULT 0x2c +#define AST_PTCR_INTR_CTRL 0x30 +#define AST_PTCR_INTR_STS 0x34 +#define AST_PTCR_TYPEM_LIMIT 0x38 +#define AST_PTCR_TYPEN_LIMIT 0x3C +#define AST_PTCR_CTRL_EXT 0x40 +#define AST_PTCR_CLK_EXT_CTRL 0x44 +#define AST_PTCR_DUTY2_CTRL 0x48 +#define AST_PTCR_DUTY3_CTRL 0x4c +#define AST_PTCR_TYPEO_CTRL0 0x50 +#define AST_PTCR_TYPEO_CTRL1 0x54 +#define AST_PTCR_TACH_SOURCE_EXT 0x60 +#define AST_PTCR_TYPEO_LIMIT 0x78 + +//COMMON Definition +#define FALL_EDGE (0) +#define RISE_EDGE (0x1) +#define BOTH_EDGE (0x2) + +#ifdef CONFIG_ARCH_AST1010 +#define PWM_TYPE_NUM 2 +#define PWM_TYPE_M 0x0 +#define PWM_TYPE_N 0x1 +#define PWM_TYPE_MASK 0x1 +#else +#define PWM_TYPE_NUM 3 +#define PWM_TYPE_M 0x0 +#define PWM_TYPE_N 0x1 +#define PWM_TYPE_O 0x2 +#define PWM_TYPE_MASK 0x3 + +#endif + +#define TACHO_NUM 16 +#define PWM_CH_NUM 8 +#define PWMA 0x0 +#define PWMB 0x1 +#define PWMC 0x2 +#define PWMD 0x3 +#define PWME 0x4 +#define PWMF 0x5 +#define PWMG 0x6 +#define PWMH 0x7 + + +// AST_PTCR_CTRL:0x00 - PWM-FAN General Control Register +#define AST_PTCR_CTRL_SET_PWMD_TYPE(x) ((x&0x1)<<15 | (x&0x2) <<6) +#define AST_PTCR_CTRL_GET_PWMD_TYPE(x) (((x&(0x1<<7))>>6) | ((x&(0x1<<15))>>15)) +#define AST_PTCR_CTRL_SET_PWMD_TYPE_MASK ((0x1<<7) | (0x1<<15)) + +#define AST_PTCR_CTRL_SET_PWMC_TYPE(x) ((x&0x1)<<14 | (x&0x2) <<5) +#define AST_PTCR_CTRL_GET_PWMC_TYPE(x) (((x&(0x1<<6))>>5) | ((x&(0x1<<14))>>14)) +#define AST_PTCR_CTRL_SET_PWMC_TYPE_MASK ((0x1<<6) | (0x1<<14)) + +#define AST_PTCR_CTRL_SET_PWMB_TYPE(x) ((x&0x1)<<13 | (x&0x2) <<4) +#define AST_PTCR_CTRL_GET_PWMB_TYPE(x) (((x&(0x1<<5))>>4) | ((x&(0x1<<13))>>13)) +#define AST_PTCR_CTRL_SET_PWMB_TYPE_MASK ((0x1<<5) | (0x1<<13)) + + +#define AST_PTCR_CTRL_SET_PWMA_TYPE(x) ((x&0x1)<<12 | (x&0x2) <<3) +#define AST_PTCR_CTRL_GET_PWMA_TYPE(x) (((x&(0x1<<4))>>3) | ((x&(0x1<<12))>>12)) +#define AST_PTCR_CTRL_SET_PWMA_TYPE_MASK ((0x1<<4) | (0x1<<12)) + +#define AST_PTCR_CTRL_FAN_NUM_EN(x) (0x1 << (16+x)) + +#define AST_PTCR_CTRL_PMWD (11) +#define AST_PTCR_CTRL_PMWD_EN (0x1 << 11) +#define AST_PTCR_CTRL_PMWC (10) +#define AST_PTCR_CTRL_PMWC_EN (0x1 << 10) +#define AST_PTCR_CTRL_PMWB (9) +#define AST_PTCR_CTRL_PMWB_EN (0x1 << 9) +#define AST_PTCR_CTRL_PMWA (8) +#define AST_PTCR_CTRL_PMWA_EN (0x1 << 8) + +#define AST_PTCR_CTRL_CLK_MCLK 0x2 //0:24Mhz, 1:MCLK +#define AST_PTCR_CTRL_CLK_EN 0x1 + +// AST_PTCR_CLK_CTRL:0x04 - PWM-FAN Clock Control Register +//TYPE N +#define AST_PTCR_CLK_CTRL_TYPEN_UNIT (24) +#define AST_PTCR_CLK_CTRL_TYPEN_UNIT_MASK (0xff<<24) +#define AST_PTCR_CLK_CTRL_TYPEN_H (20) +#define AST_PTCR_CLK_CTRL_TYPEN_H_MASK (0xf<<20) +#define AST_PTCR_CLK_CTRL_TYPEN_L (16) +#define AST_PTCR_CLK_CTRL_TYPEN_L_MASK (0xf<<16) +//TYPE M +#define AST_PTCR_CLK_CTRL_TYPEM_UNIT (8) +#define AST_PTCR_CLK_CTRL_TYPEM_UNIT_MASK (0xff<<8) +#define AST_PTCR_CLK_CTRL_TYPEM_H (4) +#define AST_PTCR_CLK_CTRL_TYPEM_H_MASK (0xf<<4) +#define AST_PTCR_CLK_CTRL_TYPEM_L (0) +#define AST_PTCR_CLK_CTRL_TYPEM_L_MASK (0xf) + + +// AST_PTCR_DUTY_CTRL0:0x08 - PWM-FAN duty control 0 register +#define DUTY_CTRL0_PWMB_FALL_POINT (24) +#define DUTY_CTRL0_PWMB_FALL_POINT_MASK (0xff<<24) +#define DUTY_CTRL0_PWMB_RISE_POINT (16) +#define DUTY_CTRL0_PWMB_RISE_POINT_MASK (0xff<<16) +#define DUTY_CTRL0_PWMA_FALL_POINT (8) +#define DUTY_CTRL0_PWMA_FALL_POINT_MASK (0xff<<8) +#define DUTY_CTRL0_PWMA_RISE_POINT (0) +#define DUTY_CTRL0_PWMA_RISE_POINT_MASK (0xff) + + +// AST_PTCR_DUTY_CTRL1 : 0x0c - PWM-FAN duty control 1 register +#define DUTY_CTRL1_PWMD_FALL_POINT (24) +#define DUTY_CTRL1_PWMD_FALL_POINT_MASK (0xff<<24) +#define DUTY_CTRL1_PWMD_RISE_POINT (16) +#define DUTY_CTRL1_PWMD_RISE_POINT_MASK (0xff<<16) +#define DUTY_CTRL1_PWMC_FALL_POINT (8) +#define DUTY_CTRL1_PWMC_FALL_POINT_MASK (0xff<<8) +#define DUTY_CTRL1_PWMC_RISE_POINT (0) +#define DUTY_CTRL1_PWMC_RISE_POINT_MASK (0xff) + + +// AST_PTCR_TYPEM_CTRL0 : 0x10/0x18/0x50 - Type M/N/O Ctrl 0 Register +#define TYPE_CTRL0_FAN_PERIOD (16) +#define TYPE_CTRL0_FAN_PERIOD_MASK (0xffff<<16) +//Type O not have this +#define TYPE_CTRL0_FLAT_EN (0x1<<7) + + +// 0 : FALL_EDGE, 0x1 : RISE_EDGE , 0x2 :BOTH_EDGE +#define TYPE_CTRL0_FAN_MODE (4) +#define TYPE_CTRL0_FAN_MODE_MASK (0x3<<4) + + + +#define TYPE_CTRL0_CLK_DIVISION (1) +#define TYPE_CTRL0_CLK_DIVISION_MASK (0x7<<1) + +#define TYPE_CTRL0_FAN_TYPE_EN (1) + + +// AST_PTCR_TYPEM_CTRL1 : 0x14/0x1c/0x54 - Type M/N/O Ctrl 1 Register +#define TYPE_CTRL1_FALL_POINT (16) +#define TYPE_CTRL1_FALL_POINT_MASK (0xff<<16) +#define TYPE_CTRL1_RISE_POINT (0) +#define TYPE_CTRL1_RISE_POINT_MASK (0xff) + + +// AST_PTCR_TACH_SOURCE : 0x20/0x60 - Tach Source Register +//bit [0,1] at 0x20, bit [2] at 0x60 +#define TACH_PWM_SOURCE_BIT01(x) (x*2) +#define TACH_PWM_SOURCE_BIT2(x) (x*2) + +#define TACH_PWM_SOURCE_MASK_BIT01(x) (0x3<<(x*2)) +#define TACH_PWM_SOURCE_MASK_BIT2(x) (0x1<<(x*2)) + +// AST_PTCR_TRIGGER : 0x28 - Trigger Register +#define TRIGGER_READ_FAN_NUM(x) (0x1<<x) + +// AST_PTCR_RESULT : 0x2c - Result Register +#define RESULT_STATUS (31) + +#define RESULT_VALUE_MASK (0xfffff) + +// AST_PTCR_INTR_CTRL : 0x30 - Interrupt Ctrl Register +#define INTR_CTRL_EN_NUM(x) (0x1<<x) + +// AST_PTCR_INTR_STS : 0x34 - Interrupt Status Register +#define INTR_CTRL_NUM(x) (0x1<<x) + +//AST_PTCR_TYPEM_LIMIT, AST_PTCR_TYPEN_LIMIT,AST_PTCR_TYPEO_LIMIT : 0x38/0x3C/0x78 - Type M / N / O Limit Register +#define FAN_LIMIT_MASK (0xfffff) + +// AST_PTCR_CTRL_EXT : 0x40 - General Ctrl Extension #1 +#define AST_PTCR_CTRL_SET_PWMH_TYPE(x) ((x&0x1)<<15 | (x&0x2) <<6) +#define AST_PTCR_CTRL_GET_PWMH_TYPE(x) (((x&(0x1<<7))>>6) | ((x&(0x1<<15))>>15)) +#define AST_PTCR_CTRL_SET_PWMH_TYPE_MASK ((0x1<<7) | (0x1<<15)) + +#define AST_PTCR_CTRL_SET_PWMG_TYPE(x) ((x&0x1)<<14 | (x&0x2) <<5) +#define AST_PTCR_CTRL_GET_PWMG_TYPE(x) (((x&(0x1<<6))>>5) | ((x&(0x1<<14))>>14)) +#define AST_PTCR_CTRL_SET_PWMG_TYPE_MASK ((0x1<<6) | (0x1<<14)) + +#define AST_PTCR_CTRL_SET_PWMF_TYPE(x) ((x&0x1)<<13 | (x&0x2) <<4) +#define AST_PTCR_CTRL_GET_PWMF_TYPE(x) (((x&(0x1<<5))>>4) | ((x&(0x1<<13))>>13)) +#define AST_PTCR_CTRL_SET_PWMF_TYPE_MASK ((0x1<<5) | (0x1<<13)) + +#define AST_PTCR_CTRL_SET_PWME_TYPE(x) ((x&0x1)<<12 | (x&0x2) <<3) +#define AST_PTCR_CTRL_GET_PWME_TYPE(x) (((x&(0x1<<4))>>3) | ((x&(0x1<<12))>>12)) +#define AST_PTCR_CTRL_SET_PWME_TYPE_MASK ((0x1<<4) | (0x1<<12)) + +#define AST_PTCR_CTRL_PMWH (11) +#define AST_PTCR_CTRL_PMWH_EN (0x1 << 11) +#define AST_PTCR_CTRL_PMWG (10) +#define AST_PTCR_CTRL_PMWG_EN (0x1 << 10) +#define AST_PTCR_CTRL_PMWF (9) +#define AST_PTCR_CTRL_PMWF_EN (0x1 << 9) +#define AST_PTCR_CTRL_PMWE (8) +#define AST_PTCR_CTRL_PMWE_EN (0x1 << 8) + +// AST_PTCR_CLK_EXT_CTRL : 0x44 - Clock Control Extension #1 +//TYPE O +#define AST_PTCR_CLK_CTRL_TYPEO_UNIT (8) +#define AST_PTCR_CLK_CTRL_TYPEO_UNIT_MASK (0xff<<8) +#define AST_PTCR_CLK_CTRL_TYPEO_H (4) +#define AST_PTCR_CLK_CTRL_TYPEO_H_MASK (0xf<<4) +#define AST_PTCR_CLK_CTRL_TYPEO_L (0) +#define AST_PTCR_CLK_CTRL_TYPEO_L_MASK (0xf) + +// AST_PTCR_DUTY2_CTRL : 0x48 - Duty Control 2 Register +#define DUTY_CTRL2_PWMF_FALL_POINT (24) +#define DUTY_CTRL2_PWMF_FALL_POINT_MASK (0xff<<24) +#define DUTY_CTRL2_PWMF_RISE_POINT (16) +#define DUTY_CTRL2_PWMF_RISE_POINT_MASK (0xff<<16) +#define DUTY_CTRL2_PWME_FALL_POINT (8) +#define DUTY_CTRL2_PWME_FALL_POINT_MASK (0xff<<8) +#define DUTY_CTRL2_PWME_RISE_POINT (0) +#define DUTY_CTRL2_PWME_RISE_POINT_MASK (0xff) + +// AST_PTCR_DUTY3_CTRL : 0x4c - Duty Control 3 Register +#define DUTY_CTRL3_PWMH_FALL_POINT (24) +#define DUTY_CTRL3_PWMH_FALL_POINT_MASK (0xff<<24) +#define DUTY_CTRL3_PWMH_RISE_POINT (16) +#define DUTY_CTRL3_PWMH_RISE_POINT_MASK (0xff<<16) +#define DUTY_CTRL3_PWMG_FALL_POINT (8) +#define DUTY_CTRL3_PWMG_FALL_POINT_MASK (0xff<<8) +#define DUTY_CTRL3_PWMG_RISE_POINT (0) +#define DUTY_CTRL3_PWMG_RISE_POINT_MASK (0xff) + +#endif /* __ASM_ARCH_REGS_PWM_FAN_H */ diff --git a/arch/arm/plat-aspeed/include/plat/regs-rtc.h b/arch/arm/plat-aspeed/include/plat/regs-rtc.h new file mode 100644 index 000000000000..8a09a4b8dfea --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-rtc.h @@ -0,0 +1,64 @@ +/* arch/arm/plat-aspeed/include/mach/regs-iic.h + * + * Copyright (c) 2012 ASPEED Technology Inc. <ryan_chen@aspeedtech.com> + * http://www.aspeedtech.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ASPEED I2C Controller +*/ + +#ifndef __ASM_ARCH_REGS_RTC_H +#define __ASM_ARCH_REGS_RTC_H __FILE__ + +#define RTC_CNTR_STS_1 0x00 +#define RTC_CNTR_STS_2 0x04 +#define RTC_ALARM 0x08 +#define RTC_CONTROL 0x10 +#define RTC_ALARM_STS 0x14 + +/* RTC_CNTR_STS_1 0x00 */ +/* RTC_ALARM 0x08 */ +#define GET_DAY_VAL(x) ((x >> 24)&0x1f) +#define GET_HOUR_VAL(x) ((x >> 16)&0x1f) +#define GET_MIN_VAL(x) ((x >> 8)&0x3f) +#define GET_SEC_VAL(x) (x & 0x3f) + +#define SET_DAY_VAL(x) ((x&0x1f) << 24) +#define SET_HOUR_VAL(x) ((x&0x1f) << 16) +#define SET_MIN_VAL(x) ((x&0x3f) << 8) +#define SET_SEC_VAL(x) (x & 0x3f) + +/* RTC_CNTR_STS_2 0x04 */ +#define GET_CENT_VAL(x) ((x >> 16)&0x1f) +#define GET_YEAR_VAL(x) ((x >> 8)&0x7f) +#define GET_MON_VAL(x) (x & 0xf) + +#define SET_CENT_VAL(x) ((x &0x1f) << 16) +#define SET_YEAR_VAL(x) ((x &0x7f) << 8) +#define SET_MON_VAL(x) (x & 0xf) + +/* RTC_CONTROL 0x10 */ +#define ENABLE_SEC_INTERRUPT (1 << 7) +#define ENABLE_DAY_ALARM (1 << 6) +#define ENABLE_HOUR_ALARM (1 << 5) +#define ENABLE_MIN_ALARM (1 << 4) +#define ENABLE_SEC_ALARM (1 << 3) +#define ALARM_MODE_SELECT (1 << 2) +#define RTC_LOCK (1 << 1) +#define RTC_ENABLE (1 << 0) +#define ENABLE_ALL_ALARM 0x0000007c + + +/* RTC_ALARM_STS 0x14 */ +#define SEC_INTERRUPT_STATUS (1 << 4) +#define DAY_ALARM_STATUS (1 << 3) +#define HOUR_ALARM_STATUS (1 << 2) +#define MIN_ALARM_STATUS (1 << 1) +#define SEC_ALARM_STATUS (1 << 0) + + + +#endif /* __ASM_ARCH_REGS_RTC_H */ diff --git a/arch/arm/plat-aspeed/include/plat/regs-scu-g5.h b/arch/arm/plat-aspeed/include/plat/regs-scu-g5.h new file mode 100644 index 000000000000..0720be5393fb --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-scu-g5.h @@ -0,0 +1,702 @@ +/* arch/arm/mach-aspeed/include/mach/regs-ast2300-scu.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * History : + * 1. 2012/12/29 Ryan Chen Create + * +********************************************************************************/ +#ifndef __AST_SCU_G5_REGS_H +#define __AST_SCU_G5_REGS_H 1 + +/* + * Register for SCU + * */ +#define AST_SCU_PROTECT 0x00 /* protection key register */ +#define AST_SCU_RESET 0x04 /* system reset control register */ +#define AST_SCU_CLK_SEL 0x08 /* clock selection register */ +#define AST_SCU_CLK_STOP 0x0C /* clock stop control register */ +#define AST_SCU_COUNT_CTRL 0x10 /* frequency counter control register */ +#define AST_SCU_INTR_CTRL 0x14 /* Interrupt control and status register */ +#define AST_SCU_D1_PLL 0x18 /* D1-PLL Parameter register */ +#define AST_SCU_D2_PLL 0x1C /* D2-PLL Parameter register */ +#define AST_SCU_M_PLL 0x20 /* M-PLL Parameter register */ +#define AST_SCU_H_PLL 0x24 /* H-PLL Parameter register */ +#define AST_SCU_FREQ_LIMIT 0x28 /* frequency counter comparsion register */ +#define AST_SCU_MISC1_CTRL 0x2C /* Misc. Control register */ +#define AST_SCU_PCI_CONF1 0x30 /* PCI configuration setting register#1 */ +#define AST_SCU_PCI_CONF2 0x34 /* PCI configuration setting register#2 */ +#define AST_SCU_PCI_CONF3 0x38 /* PCI configuration setting register#3 */ +#define AST_SCU_SYS_CTRL 0x3C /* System reset contrl/status register*/ +#define AST_SCU_SOC_SCRATCH0 0x40 /* SOC scratch 0~31 register */ +#define AST_SCU_SOC_SCRATCH1 0x44 /* SOC scratch 32~63 register */ +#define AST_SCU_VGA0 0x40 /* VGA fuction handshake register */ +#define AST_SCU_VGA1 0x44 /* VGA fuction handshake register */ +#define AST_SCU_MAC_CLK 0x48 /* MAC interface clock delay setting register */ +#define AST_SCU_MISC2_CTRL 0x4C /* Misc. 2 Control register */ +#define AST_SCU_VGA_SCRATCH0 0x50 /* VGA Scratch register */ +#define AST_SCU_VGA_SCRATCH1 0x54 /* VGA Scratch register */ +#define AST_SCU_VGA_SCRATCH2 0x58 /* VGA Scratch register */ +#define AST_SCU_VGA_SCRATCH3 0x5c /* VGA Scratch register */ +#define AST_SCU_VGA_SCRATCH4 0x60 /* VGA Scratch register */ +#define AST_SCU_VGA_SCRATCH5 0x64 /* VGA Scratch register */ +#define AST_SCU_VGA_SCRATCH6 0x68 /* VGA Scratch register */ +#define AST_SCU_VGA_SCRATCH7 0x6c /* VGA Scratch register */ +#define AST_SCU_HW_STRAP1 0x70 /* hardware strapping register */ +#define AST_SCU_RAMDOM_GEN 0x74 /* random number generator register */ +#if defined(CONFIG_ARCH_1100) || defined(CONFIG_ARCH_2050) || defined(CONFIG_ARCH_2100) || defined(CONFIG_ARCH_2200) +#define AST_SCU_MULTI_FUNC_2 0x78 +#else +#define AST_SCU_RAMDOM_DATA 0x78 /* random number generator data output*/ +#endif +#define AST_SCU_REVISION_ID 0x7C /* Silicon revision ID register */ +#define AST_SCU_FUN_PIN_CTRL1 0x80 /* Multi-function Pin Control#1*/ +#define AST_SCU_FUN_PIN_CTRL2 0x84 /* Multi-function Pin Control#2*/ +#define AST_SCU_FUN_PIN_CTRL3 0x88 /* Multi-function Pin Control#3*/ +#define AST_SCU_FUN_PIN_CTRL4 0x8C /* Multi-function Pin Control#4*/ +#define AST_SCU_FUN_PIN_CTRL5 0x90 /* Multi-function Pin Control#5*/ +#define AST_SCU_FUN_PIN_CTRL6 0x94 /* Multi-function Pin Control#6*/ +#define AST_SCU_WDT_RESET 0x9C /* Watchdog Reset Selection */ +#define AST_SCU_FUN_PIN_CTRL7 0xA0 /* Multi-function Pin Control#7*/ +#define AST_SCU_FUN_PIN_CTRL8 0xA4 /* Multi-function Pin Control#8*/ +#define AST_SCU_FUN_PIN_CTRL9 0xA8 /* Multi-function Pin Control#9*/ +#define AST_SCU_PWR_SAVING_EN 0xC0 /* Power Saving Wakeup Enable*/ +#define AST_SCU_PWR_SAVING_CTRL 0xC4 /* Power Saving Wakeup Control*/ +#define AST_SCU_HW_STRAP2 0xD0 /* Haardware strapping register set 2*/ +#define AST_SCU_COUNTER4 0xE0 /* SCU Free Run Counter Read Back #4*/ +#define AST_SCU_COUNTER4_EXT 0xE4 /* SCU Free Run Counter Extended Read Back #4*/ + +//CPU 2 +#define AST_SCU_CPU2_CTRL 0x100 /* CPU2 Control Register*/ +#define AST_SCU_CPU2_BASE0_ADDR 0x104 /* CPU2 Base Address for Segment 0x00:0000~0x1F:FFFF*/ +#define AST_SCU_CPU2_BASE1_ADDR 0x108 /* CPU2 Base Address for Segment 0x20:0000~0x3F:FFFF*/ +#define AST_SCU_CPU2_BASE2_ADDR 0x10C /* CPU2 Base Address for Segment 0x40:0000~0x5F:FFFF*/ +#define AST_SCU_CPU2_BASE3_ADDR 0x110 /* CPU2 Base Address for Segment 0x60:0000~0x7F:FFFF*/ +#define AST_SCU_CPU2_BASE4_ADDR 0x114 /* CPU2 Base Address for Segment 0x80:0000~0xFF:FFFF*/ +#define AST_SCU_CPU2_CACHE_CTRL 0x118 /* CPU2 Cache Function Control */ + +// +#define AST_SCU_UART24_REF 0x160 /* Generate UART 24Mhz Ref from H-PLL when CLKIN is 25Mhz */ +#define AST_SCU_PCIE_CONFIG_SET 0x180 /* PCI-E Configuration Setting Control Register */ +#define AST_SCU_BMC_MMIO_DEC 0x184 /* BMC MMIO Decode Setting Register */ +#define AST_SCU_DEC_AREA1 0x188 /* 1st relocated controller decode area location */ +#define AST_SCU_DEC_AREA2 0x18C /* 2nd relocated controller decode area location */ +#define AST_SCU_MBOX_DEC_AREA 0x190 /* Mailbox decode area location*/ +#define AST_SCU_SRAM_DEC_AREA0 0x194 /* Shared SRAM area decode location*/ +#define AST_SCU_SRAM_DEC_AREA1 0x198 /* Shared SRAM area decode location*/ +#define AST_SCU_BMC_CLASS 0x19C /* BMC device class code and revision ID */ +#define AST_SCU_BMC_DEV_ID 0x1A4 /* BMC device ID */ + + +/* AST_SCU_PROTECT: 0x00 - protection key register */ +#define SCU_PROTECT_UNLOCK 0x1688A8A8 + +/* AST_SCU_RESET :0x04 - system reset control register */ +#define SCU_RESET_I2S (0x1 << 31) +#define SCU_RESET_IR (0x1 << 30) +#define SCU_RESET_PS21 (0x1 << 29) +#define SCU_RESET_PS20 (0x1 << 28) +#define SCU_PWAKE_PIN_EN (0x1 << 27) +#define SCU_PWAKE_PIN_OUT (0x1 << 26 +#define SCU_RESET_X_DMA (0x1 << 25) +#define SCU_RESET_MCTP (0x1 << 24) +//#define SCU_RESET_ADC (0x1 << 23) reserved +#define SCU_RESET_JTAG (0x1 << 22) +#define SCU_RESET_PCIE_EN (0x1 << 21) +#define SCU_RESET_PCIE_OUT (0x1 << 20) +#define SCU_RESET_PCIE (0x1 << 19) +#define SCU_RESET_H264 (0x1 << 18) +#define SCU_RESET_RFX (0x1 << 17) +#define SCU_RESET_SD (0x1 << 16) +#define SCU_RESET_USB11 (0x1 << 15) +#define SCU_RESET_USB20 (0x1 << 14) +#define SCU_RESET_CRT (0x1 << 13) +//#define SCU_RESET_MAC1 (0x1 << 12) reserved +#define SCU_RESET_MAC0 (0x1 << 11) +//#define SCU_RESET_PECI (0x1 << 10) +//#define SCU_RESET_PWM (0x1 << 9) +#define SCU_PCI_VGA_DIS (0x1 << 8) +#define SCU_RESET_2D (0x1 << 7) +#define SCU_RESET_VIDEO (0x1 << 6) +//#define SCU_RESET_LPC (0x1 << 5) +#define SCU_RESET_HAC (0x1 << 4) +//#define SCU_RESET_USB11_HID (0x1 << 3) +#define SCU_RESET_I2C (0x1 << 2) +#define SCU_RESET_AHB (0x1 << 1) +#define SCU_RESET_SRAM_CTRL (0x1 << 0) + +/* AST_SCU_CLK_SEL : 0x08 - clock selection register */ +#define SCU_CLK_VIDEO_SLOW_EN (0x1 << 31) +#define SCU_CLK_VIDEO_SLOW_SET(x) ((x & 0x7) << 28) +#define SCU_CLK_VIDEO_SLOW_MASK (0x7 << 28) +#define SCU_CLK_2D_ENG_GCLK_INVERT (0x1 << 27) //valid only at CRT mode SCU2C[7] +#define SCU_CLK_2D_ENG_THROT_EN (0x1 << 26) //valid only at CRT mode SCU2C[7] +#define SCU_PCLK_APB_DIV(x) ((x & 0x7) << 23) +#define SCU_GET_PCLK_DIV(x) ((x >> 23) & 0x7) +#define SCU_PCLK_APB_DIV_MASK (0x7 << 23) //limitation on PCLK .. PCLK > 0.5*LCLK (33Mhz) +//#define SCU_GET_LHCLK_DIV(x) ((x >> 20) & 0x7) +//#define SCU_SET_LHCLK_DIV(x) (x << 20) +//#define SCU_LHCLK_DIV_MASK (0x7 << 20) +//#define SCU_LHCLK_SOURCE_EN (0x1 << 19) //0: ext , 1:internel +#define SCU_SET_MAC_DIV(x) ((x & 0x7) << 16) +#define SCU_GET_MAC_DIV(x) ((x >> 16) & 0x7) +#define SCU_CLK_MAC_MASK (0x7 << 16) +#define SCU_CLK_SD_EN (0x1 << 15) +#define SCU_SET_SD_DIV(x) ((x & 0x7) << 12) +#define SCU_GET_SD_DIV(x) ((x >> 12) & 0x7) +#define SCU_CLK_SD_MASK (0x7 << 12) +// +#define SCU_CLK_VIDEO_DELAY(x) ((x & 0xf) << 8) +#define SCU_CLK_VIDEO_DELAY_MASK (0xf << 8) +#define SCU_CLK_CPU_AHB_SLOW_EN (0x1 << 7) +#define SCU_CLK_CPU_AHB_SLOW(x) ((x & 0x7) << 4) +#define SCU_CLK_CPU_AHB_SLOW_MASK (0x7 << 4) +#define SCU_GET_CPU_AHB_DIV(x) ((x >> 4) & 0x7) +#define SCU_ECLK_SOURCE(x) (x << 2) +#define SCU_ECLK_SOURCE_MASK (0x3 << 2) +#define SCU_CLK_CPU_AHB_SLOW_IDLE (0x1 << 1) +#define SCU_CLK_CPU_AHB_DYN_SLOW_EN (0x1 << 0) + +/* AST_SCU_CLK_STOP : 0x0C - clock stop control register */ +//#define SCU_LHCLK_STOP_EN (0x1 << 28) +#define SCU_SDCLK_STOP_EN (0x1 << 27) +#define SCU_IRCLK_STOP_EN (0x1 << 26) +#define SCU_I2SCLK_STOP_EN (0x1 << 25) +#define SCU_RSACLK_STOP_EN (0x1 << 24) +#define SCU_H264CLK_STOP_EN (0x1 << 23) +//bit 22 must keep 1 +//#define SCU_MAC1CLK_STOP_EN (0x1 << 21) +#define SCU_MAC0CLK_STOP_EN (0x1 << 20) +#define SCU_BBCLK_STOP_EN (0x1 << 19) +#define SCU_RFXCLK_STOP_EN (0x1 << 18) +#define SCU_UART0_CLK_STOP_EN (0x1 << 17) +#define SCU_UART2_CLK_STOP_EN (0x1 << 16) +#define SCU_UART1_CLK_STOP_EN (0x1 << 15) +#define SCU_USB20_CLK_EN (0x1 << 14) +#define SCU_YCLK_STOP_EN (0x1 << 13) +#define SCU_PS2CLK_STOP_EN (0x1 << 12) +// +#define SCU_D1CLK_STOP_EN (0x1 << 10) +#define SCU_USB11CLK_STOP_EN (0x1 << 9) +#define SCU_D4CLK_STOP_EN (0x1 << 8) +#define SCU_D3CLK_STOP_EN (0x1 << 7) +#define SCU_REFCLK_STOP_EN (0x1 << 6) +#define SCU_D2CLK_STOP_EN (0x1 << 5) +#define SCU_SACLK_STOP_EN (0x1 << 4) +#define SCU_VCLK_STOP_EN (0x1 << 3) +#define SCU_MCLK_STOP_EN (0x1 << 2) +#define SCU_GCLK_STOP_EN (0x1 << 1) +#define SCU_ECLK_STOP_EN (0x1 << 0) + +/* AST_SCU_COUNT_CTRL : 0x10 - frequency counter control register */ +#define SCU_FREQ_COMP_RESULT (0x1 << 7) +#define SCU_FREQ_MEASU_FINISH (0x1 << 6) +#define SCU_FREQ_SOURCE_FOR_MEASU(x) ((x & 0xf) << 2) +#define SCU_FREQ_SOURCE_FOR_MEASU_MASK (0xf << 2) + +#define SCU_SOURCE_6M 0xf +#define SCU_SOURCE_12M 0xe +#define SCU_SOURCE_I2SM_CLK 0xd +#define SCU_SOURCE_H_CLK 0xc +#define SCU_SOURCE_B_CLK 0xb +#define SCU_SOURCE_D2_PLL 0xa + +#define SCU_SOURCE_VIDEO_CLK 0x7 +#define SCU_SOURCE_LPC_CLK 0x6 +#define SCU_SOURCE_JITTER_CLK 0x5 +#define SCU_SOURCE_M_CLK 0x4 +#define SCU_SOURCE_XP_CLK 0x3 +#define SCU_SOURCE_D_PLL 0x2 +#define SCU_SOURCE_NAND 0x1 +#define SCU_SOURCE_DEL_CELL 0x0 + +#define SCU_OSC_COUNT_EN (0x1 << 1) +#define SCU_RING_OSC_EN (0x1 << 0) + +/* AST_SCU_INTR_CTRL : 0x14 - Interrupt control and status register */ +//#define INTR_LPC_H_L_RESET (0x1 << 21) +//#define INTR_LPC_L_H_RESET (0x1 << 20) +#define INTR_PCIE_H_L_RESET (0x1 << 17) +#define INTR_PCIE_L_H_RESET (0x1 << 16) +//#define INTR_VGA_SCRATCH_CHANGE (0x1 << 17) +//#define INTR_VGA_CURSOR_CHANGE (0x1 << 16) +#define INTR_MSI_EN (0x1 << 2) +//#define INTR_LPC_H_L_RESET_EN (0x1 << 1) +//#define INTR_LPC_L_H_RESET_EN (0x1 << 0) +#define INTR_PCIE_H_L_RESET_EN (0x1 << 1) +#define INTR_PCIE_L_H_RESET_EN (0x1 << 0) +//#define INTR_VGA_SCRATCH_CHANGE_EN (0x1 << 1) +//#define INTR_VGA_CURSOR_CHANGE_EN (0x1 << 0) + + +/* AST_SCU_D1_PLL: 0x18 - D1-PLL Parameter register */ +#define SCU_D1_PLL_SET_PD2(x) ((x & 0x7) << 19) +#define SCU_D1_PLL_GET_PD2(x) ((x >> 19) & 0x7) +#define SCU_D1_PLL_PD2_MASK (0x7 << 19) +#define SCU_D1_PLL_BYPASS_EN (0x1 << 18) +#define SCU_D1_PLL_OFF (0x1 << 17) +#define SCU_D1_PLL_SET_PD(x) ((x & 0x3) << 15) +#define SCU_D1_PLL_GET_PD(x) ((x >> 15) & 0x3) +#define SCU_D1_PLL_PD_MASK (0x3 << 15) +#define SCU_D1_PLL_SET_OD(x) ((x & 0x3) << 13) +#define SCU_D1_PLL_GET_OD(x) ((x >> 13) & 0x3) +#define SCU_D1_PLL_OD_MASK (0x3 << 13) +#define SCU_D1_PLL_SET_DENUM(x) ((x & 0x1f) << 8) +#define SCU_D1_PLL_GET_DENUM(x) ((x >> 8) & 0x1f) +#define SCU_D1_PLL_DENUM_MASK (0x1f << 8) +#define SCU_D1_PLL_SET_NUM(x) (x & 0xff) +#define SCU_D1_PLL_GET_NUM(x) (x & 0xff) +#define SCU_D1_PLL_NUM_MASK (0xff) + +/* AST_SCU_D2_PLL: 0x1C - D2-PLL Parameter register */ +#define SCU_D2_PLL_SET_PD2(x) ((x & 0x7) << 19) +#define SCU_D2_PLL_GET_PD2(x) ((x >> 19) & 0x7) +#define SCU_D2_PLL_PD2_MASK (0x7 << 19) +#define SCU_D2_PLL_BYPASS_EN (0x1 << 18) +#define SCU_D2_PLL_OFF (0x1 << 17) +#define SCU_D2_PLL_SET_PD(x) ((x & 0x3) << 15) +#define SCU_D2_PLL_GET_PD(x) ((x >> 15) & 0x3) +#define SCU_D2_PLL_PD_MASK (0x3 << 15) +#define SCU_D2_PLL_SET_OD(x) ((x & 0x3) << 13) +#define SCU_D2_PLL_GET_OD(x) ((x >> 13) & 0x3) +#define SCU_D2_PLL_OD_MASK (0x3 << 13) +#define SCU_D2_PLL_SET_DENUM(x) ((x & 0x1f) << 8) +#define SCU_D2_PLL_GET_DENUM(x) ((x >> 8) & 0x1f) +#define SCU_D2_PLL_DENUM_MASK (0x1f << 8) +#define SCU_D2_PLL_SET_NUM(x) (x & 0xff) +#define SCU_D2_PLL_GET_NUM(x) (x & 0xff) +#define SCU_D2_PLL_NUM_MASK (0xff) + +/* AST_SCU_M_PLL : 0x20 - M-PLL Parameter register */ +#define SCU_M_PLL_BYPASS_EN (0x1 << 17) +#define SCU_M_PLL_OFF (0x1 << 16) +#define SCU_M_PLL_NUM(x) ((x & 0x3f) << 5) +#define SCU_M_PLL_GET_NUM(x) ((x >> 5) & 0x3f) +#define SCU_M_PLL_NUM_MASK (0x3f << 5) +#define SCU_M_PLL_OUT_DIV (0x1 << 4) +#define SCU_M_PLL_GET_DIV(x) ((x >> 4) & 0x1) +#define SCU_M_PLL_SET_DENUM(x) (x & 0xf) +#define SCU_M_PLL_GET_DENUM(x) (x & 0xf) + +/* AST_SCU_H_PLL: 0x24- H-PLL Parameter register */ +#define SCU_H_PLL_BYPASS_EN (0x1 << 17) +#define SCU_H_PLL_OFF (0x1 << 16) +#define SCU_H_PLL_SET_NUM(x) ((x & 0x3f) << 5) +#define SCU_H_PLL_GET_NUM(x) ((x >> 5) & 0x3f) +#define SCU_H_PLL_NUM_MASK (0x3f << 5) +#define SCU_H_PLL_OUT_DIV (0x1 << 4) +#define SCU_H_PLL_GET_DIV(x) ((x >> 4) & 0x1) +#define SCU_H_PLL_SET_DENUM(x) (x & 0xf) +#define SCU_H_PLL_GET_DENUM(x) (x & 0xf) +#define SCU_H_PLL_DENUM_MASK (0xf) + +/* AST_SCU_FREQ_LIMIT : 0x28 - frequency counter comparsion register */ +#define SCU_FREQ_U_LIMIT(x) ((x & 0x3fff) << 16) +#define SCU_FREQ_U_LIMIT_MASK (0x3fff << 16) +#define SCU_FREQ_L_LIMIT(x) (x & 0x3fff) +#define SCU_FREQ_L_LIMIT_MASK (0x3fff) + +/* AST_SCU_MISC_CTRL : 0x2C - Misc. Control register */ +#define HPLL_MPLL 0 +#define HPLL_DIV2 1 +#define SCU_MISC_24MHZ_BCLK (0x1 << 28) +#define SCU_MISC_RFX_CLK_SEL(x) ((x & 0x1) << 27) +#define SCU_MISC_RFX_CLK_HPLL_DIV2 (0x1 << 27) +#define SCU_MISC_JTAG_MASTER_DIS (0x1 << 26) +#define SCU_MISC_ST_CLK_HPLL_DIV2 (0x1 << 25) +#define SCU_MISC_H264_CLK_HPLL_DIV2 (0x1 << 24) +#define SCU_MISC_AX_CLK_HPLL_DIV2 (0x1 << 23) +#define SCU_MISC_BB_CLK_HPLL_DIV2 (0x1 << 22) +#define SCU_MISC_D4_CLK_D2_PLL (0x1 << 21) +#define SCU_MISC_D3_CLK_D2_PLL (0x1 << 20) +#define SCU_MISC_D2_CLK_D2_PLL (0x1 << 19) +#define SCU_MISC_D1_CLK_D2_PLL (0x1 << 18) +#define SCU_MISC_DAC_MASK (0x3 << 16) +#define SCU_MISC_DAC_SOURCE_CRT (0x1 << 16) //00 VGA, 01: CRT, 1x: PASS-Through DVO +#define SCU_MISC_DAC_SOURCE_MASK (0x3 << 16) +#define SCU_MISC_RST_CRT1_EN (0x1 << 15) +#define SCU_MISC_RST_CRT2_EN (0x1 << 14) +#define SCU_MISC_RST_CRT3_EN (0x1 << 13) +#define SCU_MISC_RST_CRT4_EN (0x1 << 12) +#define SCU_MISC_Y_CLK_INVERT (0x1 << 11) + +#define SCU_MISC_OUT_DELAY (0x1 << 9) +#define SCU_MISC_PCI_TO_AHB_DIS (0x1 << 8) +//#define SCU_MISC_2D_CRT_EN (0x1 << 7) +//#define SCU_MISC_VGA_CRT_DIS (0x1 << 6) +//#define SCU_MISC_VGA_REG_ACCESS_EN (0x1 << 5) +#define SCU_MISC_D2_PLL_DIS (0x1 << 4) +#define SCU_MISC_DAC_DIS (0x1 << 3) +#define SCU_MISC_D1_PLL_DIS (0x1 << 2) +#define SCU_MISC_OSC_CLK_OUT_PIN (0x1 << 1) +//#define SCU_MISC_LPC_TO_SPI_DIS (0x1 << 0) + +/* AST_SCU_PCI_CONF1 : 0x30 - PCI configuration setting register#1 */ +#define SCU_PCI_DEVICE_ID(x) (x << 16) +#define SCU_PCI_VENDOR_ID(x) (x) + +/* AST_SCU_PCI_CONF2 0x34 PCI configuration setting register#2 */ +#define SCU_PCI_SUB_SYS_ID(x) (x << 16) +#define SCU_PCI_SUB_VENDOR_ID(x) (x) + +/* AST_SCU_PCI_CONF3 0x38 PCI configuration setting register#3 */ +#define SCU_PCI_CLASS_CODE(x) (x << 8) +#define SCU_PCI_REVISION_ID(x) (x) + +/* AST_SCU_SYS_CTRL 0x3C System reset contrl/status register*/ +#define SCU_SYS_EXT_SOC_RESET_EN (0x1 << 3) +#define SCU_SYS_EXT_RESET_FLAG (0x1 << 2) +#define SCU_SYS_WDT_RESET_FLAG (0x1 << 1) +#define SCU_SYS_PWR_RESET_FLAG (0x1 << 0) + +/* AST_SCU_SOC_SCRATCH0 0x40 SOC scratch 0~31 register */ + + + + +/* AST_SCU_SOC_SCRATCH1 0x44 SOC scratch 32~63 register */ + + +/* AST_SCU_VGA0 0x40 VGA fuction handshake register */ +#define SCU_VGA_SLT_HANDSHAKE(x) (x << 24) +#define SCU_VGA_SLT_HANDSHAKE_MASK (0xff << 24) +#define SCU_VGA_CTM_DEF(x) (x << 16) +#define SCU_VGA_CTM_DEF_MASK (0xff << 16) +#define SCU_MAC0_PHY_MODE(x) (x << 14) +#define SCU_MAC0_GET_PHY_MODE(x) ((x >> 14) & 0x3) +#define SCU_MAC0_PHY_MODE_MASK(x) (0x3 << 14) +#define SCU_MAC1_PHY_MODE(x) (x << 12) +#define SCU_MAC1_PHY_MODE_MASK (0x3 << 12) +#define SCU_MAC1_GET_PHY_MODE(x) ((x >> 12) & 0x3) + +#define SCU_VGA_ASPEED_DEF(x) (x << 8) +#define SCU_VGA_ASPEED_DEF_MASK (0xf << 8) + +#define SCU_VGA_DRAM_INIT_MASK(x) ((x >> 7) & 0x1) + +/* AST_SCU_VGA1 0x44 VGA fuction handshake register */ + + +/* AST_SCU_MAC_CLK 0x48 MAC interface clock delay setting register */ + + + +/* AST_SCU_MISC_CTRL 0x4C Misc. 2 Control register */ +/* AST_SCU_VGA_SCRATCH0 0x50 VGA Scratch register */ +/* AST_SCU_VGA_SCRATCH1 0x54 VGA Scratch register */ +/* AST_SCU_VGA_SCRATCH2 0x58 VGA Scratch register */ +/* AST_SCU_VGA_SCRATCH3 0x5c VGA Scratch register */ +/* AST_SCU_VGA_SCRATCH4 0x60 VGA Scratch register */ +/* AST_SCU_VGA_SCRATCH5 0x64 VGA Scratch register */ +/* AST_SCU_VGA_SCRATCH6 0x68 VGA Scratch register */ +/* AST_SCU_VGA_SCRATCH7 0x6c VGA Scratch register */ + +/* AST_SCU_HW_STRAP1 0x70 hardware strapping register */ +#define SCU_HW_STRAP_SW_DEFINE(x) (x << 29) +#define SCU_HW_STRAP_SW_DEFINE_MASK (0x3 << 29) +#define SCU_HW_STRAP_DRAM_SIZE(x) (x << 27) +#define SCU_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27) + +#define VGA_64M_DRAM 0 +#define VGA_128M_DRAM 1 +#define VGA_256M_DRAM 2 +#define VGA_512M_DRAM 3 + +#define SCU_HW_STRAP_DRAM_CONFIG(x) ((x & 0x7) << 24) +#define SCU_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24) + +#define SCU_HW_STRAP_SPI_MODE(x) ((x & 0x3) << 12) +#define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12) +#define SPI_MODE_DIS (0) +#define SPI_MODE_MASTER_EN (1) +#define SPI_MODE_M_S_EN (2) +#define SPI_MODE_PS (3) + +#define SCU_HW_STRAP_SET_CPU_AHB_RATIO(x) (x << 10) +#define SCU_HW_STRAP_GET_CPU_AHB_RATIO(x) ((x >> 10) & 3) +#define SCU_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10) + + +#define CPU_AHB_RATIO_1_1 0 +#define CPU_AHB_RATIO_2_1 1 +#define CPU_AHB_RATIO_4_1 2 +#define CPU_AHB_RATIO_3_1 3 + +#define SCU_HW_STRAP_GET_H_PLL_CLK(x) ((x >> 8 )& 0x3) +#define SCU_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8) +#define CPU_384MHZ 0 +#define CPU_360MHZ 1 +#define CPU_336MHZ 2 +#define CPU_408MHZ 3 + +//#define SCU_HW_STRAP_MAC1_INF (0x1 << 7) +#define SCU_HW_STRAP_MAC0_INF (0x1 << 6) +//#define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5) +#define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4) +//#define SCU_HW_STRAP_VGA_SIZE_GET(x) ((x >> 2)& 0x3) + +#define SCU_HW_STRAP_BOOT_MODE(x) (x) +#define NOR_BOOT 0 +#define NAND_BOOT 1 +#define SPI_BOOT 2 +#define DIS_BOOT 3 + +/* AST_SCU_RAMDOM_GEN 0x74 random number generator register */ +/* AST_SCU_RAMDOM_DATA 0x78 random number generator data output*/ + +/* AST_SCU_MULTI_FUNC_2 0x78 */ + +/* AST_SCU_REVISION_ID 0x7C Silicon revision ID register */ +#define AST1100_A0 0x00000200 +#define AST1100_A1 0x00000201 +#define AST1100_A2 0x00000202 +#define AST1100_A3 0x00000202 + +#define AST2050_A0 0x00000200 +#define AST2050_A1 0x00000201 +#define AST2050_A2 0x00000202 +#define AST2050_A3 0x00000202 + +#define AST2100_A0 0x00000300 +#define AST2100_A1 0x00000301 +#define AST2100_A2 0x00000302 +#define AST2100_A3 0x00000302 + +#define AST2200_A0 0x00000102 +#define AST2200_A1 0x00000102 + +#define AST2300_A0 0x01000003 +#define AST2300_A1 0x01010303 +#define AST1300_A1 0x01010003 +#define AST1050_A1 0x01010203 + +#define AST2400_A0 0x02000303 + + +/* AST_SCU_FUN_PIN_CTRL1 0x80 Multi-function Pin Control#1*/ +#define SCU_FUN_PIN_UART4_RXD (0x1 << 31) +#define SCU_FUN_PIN_UART4_TXD (0x1 << 30) +#define SCU_FUN_PIN_UART4_NRTS (0x1 << 29) +#define SCU_FUN_PIN_UART4_NDTR (0x1 << 28) +#define SCU_FUN_PIN_UART4_NRI (0x1 << 27) +#define SCU_FUN_PIN_UART4_NDSR (0x1 << 26) +#define SCU_FUN_PIN_UART4_NDCD (0x1 << 25) +#define SCU_FUN_PIN_UART4_NCTS (0x1 << 24) +#define SCU_FUN_PIN_UART3_RXD (0x1 << 23) +#define SCU_FUN_PIN_UART3_TXD (0x1 << 22) +#define SCU_FUN_PIN_UART3_NRTS (0x1 << 21) +#define SCU_FUN_PIN_UART3_NDTR (0x1 << 20) +#define SCU_FUN_PIN_UART3_NRI (0x1 << 19) +#define SCU_FUN_PIN_UART3_NDSR (0x1 << 18) +#define SCU_FUN_PIN_UART3_NDCD (0x1 << 17) +#define SCU_FUN_PIN_UART3_NCTS (0x1 << 16) +#define SCU_FUN_PIN_SPICS1 (0x1 << 15) +#define SCU_FUN_PIN_LPCPME (0x1 << 14) +#define SCU_FUN_PIN_LPCPD (0x1 << 13) +#define SCU_FUN_PIN_LPCRST (0x1 << 12) +#define SCU_FUN_PIN_I2C_SALT4 (0x1 << 11) +#define SCU_FUN_PIN_I2C_SALT3 (0x1 << 10) +#define SCU_FUN_PIN_I2C_SALT2 (0x1 << 9) +#define SCU_FUN_PIN_I2C_SALT1 (0x1 << 8) +#define SCU_FUN_PIN_TIMER8 (0x1 << 7) +#define SCU_FUN_PIN_TIMER7 (0x1 << 6) +#define SCU_FUN_PIN_TIMER6 (0x1 << 5) +#define SCU_FUN_PIN_TIMER5 (0x1 << 4) +#define SCU_FUN_PIN_TIMER4 (0x1 << 3) +#define SCU_FUN_PIN_TIMER3 (0x1 << 2) +#define SCU_FUN_PIN_MAC1_PHY_LINK (0x1 << 1) +#define SCU_FUN_PIN_MAC0_PHY_LINK (0x1) + +/* AST_SCU_FUN_PIN_CTRL2 0x84 Multi-function Pin Control#2*/ +#define SCU_FUN_PIN_VPIB9 (0x1 << 31) +#define SCU_FUN_PIN_VPIB8 (0x1 << 30) +#define SCU_FUN_PIN_VPIB7 (0x1 << 29) +#define SCU_FUN_PIN_VPIB6 (0x1 << 28) +#define SCU_FUN_PIN_VPIB5 (0x1 << 27) +#define SCU_FUN_PIN_VPIB4 (0x1 << 26) +#define SCU_FUN_PIN_VPIB3 (0x1 << 25) +#define SCU_FUN_PIN_VPIB2 (0x1 << 24) +#define SCU_FUN_PIN_VPIB1 (0x1 << 23) +#define SCU_FUN_PIN_VPIB0 (0x1 << 22) +#define SCU_FUN_PIN_VPICLK (0x1 << 21) +#define SCU_FUN_PIN_VPIVS (0x1 << 20) +#define SCU_FUN_PIN_VPIHS (0x1 << 19) +#define SCU_FUN_PIN_VPIODD (0x1 << 18) +#define SCU_FUN_PIN_VPIDE (0x1 << 17) + +#define SCU_FUN_PIN_UART2_RXD (0x1 << 31) +#define SCU_FUN_PIN_UART2_TXD (0x1 << 30) +#define SCU_FUN_PIN_UART2_NRTS (0x1 << 29) +#define SCU_FUN_PIN_UART2_NDTR (0x1 << 28) +#define SCU_FUN_PIN_UART2_NRI (0x1 << 27) +#define SCU_FUN_PIN_UART2_NDSR (0x1 << 26) +#define SCU_FUN_PIN_UART2_NDCD (0x1 << 25) +#define SCU_FUN_PIN_UART2_NCTS (0x1 << 24) +#define SCU_FUN_PIN_UART1_RXD (0x1 << 23) +#define SCU_FUN_PIN_UART1_TXD (0x1 << 22) +#define SCU_FUN_PIN_UART1_NRTS (0x1 << 21) +#define SCU_FUN_PIN_UART1_NDTR (0x1 << 20) +#define SCU_FUN_PIN_UART1_NRI (0x1 << 19) +#define SCU_FUN_PIN_UART1_NDSR (0x1 << 18) +#define SCU_FUN_PIN_UART1_NDCD (0x1 << 17) +#define SCU_FUN_PIN_UART1_NCTS (0x1 << 16) + + +#define SCU_FUN_PIN_NAND_FLWP (0x1 << 7) +#define SCU_FUN_PIN_NAND_FLBUSY (0x1 << 6) + +/* AST_SCU_FUN_PIN_CTRL3 0x88 Multi-function Pin Control#3*/ +#define SCU_FUN_PIN_MAC0_MDIO (0x1 << 31) +#define SCU_FUN_PIN_MAC0_MDC (0x1 << 30) +#define SCU_FUN_PIN_ROMA25 (0x1 << 29) +#define SCU_FUN_PIN_ROMA24 (0x1 << 28) +#define SCU_FUN_PIN_ROMCS4 (0x1 << 27) +#define SCU_FUN_PIN_ROMCS3 (0x1 << 26) +#define SCU_FUN_PIN_ROMCS2 (0x1 << 25) +#define SCU_FUN_PIN_ROMCS1 (0x1 << 24) +#define SCU_FUN_PIN_ROMCS(x) (0x1 << (23+x)) + +//Video pin +#define SCU_FUN_PIN_VPIR9 (0x1 << 19) +#define SCU_FUN_PIN_VPIR8 (0x1 << 18) +#define SCU_FUN_PIN_VPIR7 (0x1 << 17) +#define SCU_FUN_PIN_VPIR6 (0x1 << 16) +#define SCU_FUN_PIN_VPIR5 (0x1 << 15) +#define SCU_FUN_PIN_VPIR4 (0x1 << 14) +#define SCU_FUN_PIN_VPIR3 (0x1 << 13) +#define SCU_FUN_PIN_VPIR2 (0x1 << 12) +#define SCU_FUN_PIN_VPIR1 (0x1 << 11) +#define SCU_FUN_PIN_VPIR0 (0x1 << 10) +#define SCU_FUN_PIN_VPIG9 (0x1 << 9) +#define SCU_FUN_PIN_VPIG8 (0x1 << 8) +#define SCU_FUN_PIN_VPIG7 (0x1 << 7) +#define SCU_FUN_PIN_VPIG6 (0x1 << 6) +#define SCU_FUN_PIN_VPIG5 (0x1 << 5) +#define SCU_FUN_PIN_VPIG4 (0x1 << 4) +#define SCU_FUN_PIN_VPIG3 (0x1 << 3) +#define SCU_FUN_PIN_VPIG2 (0x1 << 2) +#define SCU_FUN_PIN_VPIG1 (0x1 << 1) +#define SCU_FUN_PIN_VPIG0 (0x1 << 0) + +//pwm pin +#define SCU_FUN_PIN_PWM_TACHO (0) + +/* AST_SCU_FUN_PIN_CTRL4 0x8C Multi-function Pin Control#4*/ +#define SCU_FUN_PIN_ROMA23 (0x1 << 7) +#define SCU_FUN_PIN_ROMA22 (0x1 << 6) + +#define SCU_FUN_PIN_ROMWE (0x1 << 5) +#define SCU_FUN_PIN_ROMOE (0x1 << 4) +#define SCU_FUN_PIN_ROMD7 (0x1 << 3) +#define SCU_FUN_PIN_ROMD6 (0x1 << 2) +#define SCU_FUN_PIN_ROMD5 (0x1 << 1) +#define SCU_FUN_PIN_ROMD4 (0x1) + +/* AST_SCU_FUN_PIN_CTRL5 0x90 Multi-function Pin Control#5*/ +#define SCU_FUN_PIN_SPICS1 (0x1 << 31) +#define SCU_FUN_PIN_LPC_PLUS (0x1 << 30) +#define SCU_FUC_PIN_USB20_HOST (0x1 << 29) +#define SCU_FUC_PIN_USB11_PORT4 (0x1 << 28) +#define SCU_FUC_PIN_I2C14 (0x1 << 27) +#define SCU_FUC_PIN_I2C13 (0x1 << 26) +#define SCU_FUC_PIN_I2C12 (0x1 << 25) +#define SCU_FUC_PIN_I2C11 (0x1 << 24) +#define SCU_FUC_PIN_I2C10 (0x1 << 23) +#define SCU_FUC_PIN_I2C9 (0x1 << 22) +#define SCU_FUC_PIN_I2C8 (0x1 << 21) +#define SCU_FUC_PIN_I2C7 (0x1 << 20) +#define SCU_FUC_PIN_I2C6 (0x1 << 19) +#define SCU_FUC_PIN_I2C5 (0x1 << 18) +#define SCU_FUC_PIN_I2C4 (0x1 << 17) +#define SCU_FUC_PIN_I2C3 (0x1 << 16) +#define SCU_FUC_PIN_MII2_RX_DWN_DIS (0x1 << 15) +#define SCU_FUC_PIN_MII2_TX_DWN_DIS (0x1 << 14) +#define SCU_FUC_PIN_MII1_RX_DWN_DIS (0x1 << 13) +#define SCU_FUC_PIN_MII1_TX_DWN_DIS (0x1 << 12) + +#define SCU_FUC_PIN_MII2_TX_DRIV(x) (x << 10) +#define SCU_FUC_PIN_MII2_TX_DRIV_MASK (0x3 << 10) +#define SCU_FUC_PIN_MII1_TX_DRIV(x) (x << 8) +#define SCU_FUC_PIN_MII1_TX_DRIV_MASK (0x3 << 8) + +#define MII_NORMAL_DRIV 0x0 +#define MII_HIGH_DRIV 0x2 + +#define SCU_FUC_PIN_UART6 (0x1 << 7) +#define SCU_FUC_PIN_ROM_16BIT (0x1 << 6) +#define SCU_FUC_PIN_DIGI_V_OUT(x) (x << 4) +#define SCU_FUC_PIN_DIGI_V_OUT_MASK (0x3 << 4) + +#define VIDEO_DISABLE 0x0 +#define VIDEO_12BITS 0x1 +#define VIDEO_24BITS 0x2 +//#define VIDEO_DISABLE 0x3 + +#define SCU_FUC_PIN_USB11_PORT2 (0x1 << 3) +#define SCU_FUC_PIN_MAC1_MDIO (0x1 << 2) +#define SCU_FUC_PIN_SD2 (0x1 << 1) +#define SCU_FUC_PIN_SD1 (0x1 << 0) + + +/* AST_SCU_FUN_PIN_CTRL6 0x94 Multi-function Pin Control#6*/ +#define SCU_VIDEO_OUT_MASK (~0x3) + +/* AST_SCU_WDT_RESET 0x9C Watchdog Reset Selection */ +/* AST_SCU_FUN_PIN_CTRL7 0xA0 Multi-function Pin Control#7*/ +/* AST_SCU_FUN_PIN_CTRL8 0xA4 Multi-function Pin Control#8*/ +#define SCU_FUN_PIN_ROMA17 (0x1 << 31) +#define SCU_FUN_PIN_ROMA16 (0x1 << 30) +#define SCU_FUN_PIN_ROMA15 (0x1 << 29) +#define SCU_FUN_PIN_ROMA14 (0x1 << 28) +#define SCU_FUN_PIN_ROMA13 (0x1 << 27) +#define SCU_FUN_PIN_ROMA12 (0x1 << 26) +#define SCU_FUN_PIN_ROMA11 (0x1 << 25) +#define SCU_FUN_PIN_ROMA10 (0x1 << 24) +#define SCU_FUN_PIN_ROMA9 (0x1 << 23) +#define SCU_FUN_PIN_ROMA8 (0x1 << 22) +#define SCU_FUN_PIN_ROMA7 (0x1 << 21) +#define SCU_FUN_PIN_ROMA6 (0x1 << 20) +#define SCU_FUN_PIN_ROMA5 (0x1 << 19) +#define SCU_FUN_PIN_ROMA4 (0x1 << 18) +#define SCU_FUN_PIN_ROMA3 (0x1 << 17) +#define SCU_FUN_PIN_ROMA2 (0x1 << 16) + +/* AST_SCU_FUN_PIN_CTRL9 0xA8 Multi-function Pin Control#9*/ +#define SCU_FUN_PIN_ROMA21 (0x1 << 3) +#define SCU_FUN_PIN_ROMA20 (0x1 << 2) +#define SCU_FUN_PIN_ROMA19 (0x1 << 1) +#define SCU_FUN_PIN_ROMA18 (0x1) + +/* AST_SCU_PWR_SAVING_EN 0xC0 Power Saving Wakeup Enable*/ +/* AST_SCU_PWR_SAVING_CTRL 0xC4 Power Saving Wakeup Control*/ +/* AST_SCU_HW_STRAP2 0xD0 Haardware strapping register set 2*/ +/* AST_SCU_COUNTER4 0xE0 SCU Free Run Counter Read Back #4*/ +/* AST_SCU_COUNTER4_EXT 0xE4 SCU Free Run Counter Extended Read Back #4*/ + +//CPU 2 +/* AST_SCU_CPU2_CTRL 0x100 CPU2 Control Register*/ +/* AST_SCU_CPU2_BASE0_ADDR 0x104 CPU2 Base Address for Segment 0x00:0000~0x1F:FFFF*/ +/* AST_SCU_CPU2_BASE1_ADDR 0x108 CPU2 Base Address for Segment 0x20:0000~0x3F:FFFF*/ +/* AST_SCU_CPU2_BASE2_ADDR 0x10C CPU2 Base Address for Segment 0x40:0000~0x5F:FFFF*/ +/* AST_SCU_CPU2_BASE3_ADDR 0x110 CPU2 Base Address for Segment 0x60:0000~0x7F:FFFF*/ +/* AST_SCU_CPU2_BASE4_ADDR 0x114 CPU2 Base Address for Segment 0x80:0000~0xFF:FFFF*/ +/* AST_SCU_CPU2_CACHE_CTRL 0x118 CPU2 Cache Function Control */ + +// +/* AST_SCU_UART24_REF 0x160 Generate UART 24Mhz Ref from H-PLL when CLKIN is 25Mhz */ +/* AST_SCU_PCIE_CONFIG_SET 0x180 PCI-E Configuration Setting Control Register */ +/* AST_SCU_BMC_MMIO_DEC 0x184 BMC MMIO Decode Setting Register */ +/* AST_SCU_DEC_AREA1 0x188 1st relocated controller decode area location */ +/* AST_SCU_DEC_AREA2 0x18C 2nd relocated controller decode area location */ +/* AST_SCU_MBOX_DEC_AREA 0x190 Mailbox decode area location*/ +/* AST_SCU_SRAM_DEC_AREA0 0x194 Shared SRAM area decode location*/ +/* AST_SCU_SRAM_DEC_AREA1 0x198 Shared SRAM area decode location*/ +/* AST_SCU_BMC_CLASS 0x19C BMC device class code and revision ID */ +/* AST_SCU_BMC_DEV_ID 0x1A4 BMC device ID */ + +#endif /* __AST_SCU_G5_REGS_H */ + diff --git a/arch/arm/plat-aspeed/include/plat/regs-scu.h b/arch/arm/plat-aspeed/include/plat/regs-scu.h new file mode 100644 index 000000000000..0abdcbdd47ee --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-scu.h @@ -0,0 +1,740 @@ +/* arch/arm/mach-aspeed/include/mach/regs-ast2300-scu.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * History : + * 1. 2012/12/29 Ryan Chen Create + * +********************************************************************************/ +#ifndef __AST_SCU_H +#define __AST_SCU_H 1 + +/* + * Register for SCU + * */ +#define AST_SCU_PROTECT 0x00 /* protection key register */ +#define AST_SCU_RESET 0x04 /* system reset control register */ +#define AST_SCU_CLK_SEL 0x08 /* clock selection register */ +#define AST_SCU_CLK_STOP 0x0C /* clock stop control register */ +#define AST_SCU_COUNT_CTRL 0x10 /* frequency counter control register */ +#define AST_SCU_COUNT_VAL 0x14 /* frequency counter measure register */ +#define AST_SCU_INTR_CTRL 0x18 /* Interrupt control and status register */ +#define AST_SCU_D2_PLL 0x1C /* D2-PLL Parameter register */ +#define AST_SCU_M_PLL 0x20 /* M-PLL Parameter register */ +#define AST_SCU_H_PLL 0x24 /* H-PLL Parameter register */ +#define AST_SCU_FREQ_LIMIT 0x28 /* frequency counter comparsion register */ +#define AST_SCU_MISC1_CTRL 0x2C /* Misc. Control register */ +#define AST_SCU_PCI_CONF1 0x30 /* PCI configuration setting register#1 */ +#define AST_SCU_PCI_CONF2 0x34 /* PCI configuration setting register#2 */ +#define AST_SCU_PCI_CONF3 0x38 /* PCI configuration setting register#3 */ +#define AST_SCU_SYS_CTRL 0x3C /* System reset contrl/status register*/ +#define AST_SCU_SOC_SCRATCH0 0x40 /* SOC scratch 0~31 register */ +#define AST_SCU_SOC_SCRATCH1 0x44 /* SOC scratch 32~63 register */ +#define AST_SCU_VGA0 0x40 /* VGA fuction handshake register */ +#define AST_SCU_VGA1 0x44 /* VGA fuction handshake register */ +#define AST_SCU_MAC_CLK 0x48 /* MAC interface clock delay setting register */ +#define AST_SCU_MISC2_CTRL 0x4C /* Misc. 2 Control register */ +#define AST_SCU_VGA_SCRATCH0 0x50 /* VGA Scratch register */ +#define AST_SCU_VGA_SCRATCH1 0x54 /* VGA Scratch register */ +#define AST_SCU_VGA_SCRATCH2 0x58 /* VGA Scratch register */ +#define AST_SCU_VGA_SCRATCH3 0x5c /* VGA Scratch register */ +#define AST_SCU_VGA_SCRATCH4 0x60 /* VGA Scratch register */ +#define AST_SCU_VGA_SCRATCH5 0x64 /* VGA Scratch register */ +#define AST_SCU_VGA_SCRATCH6 0x68 /* VGA Scratch register */ +#define AST_SCU_VGA_SCRATCH7 0x6c /* VGA Scratch register */ +#define AST_SCU_HW_STRAP1 0x70 /* hardware strapping register */ +#define AST_SCU_RAMDOM_GEN 0x74 /* random number generator register */ +#if defined(CONFIG_ARCH_1100) || defined(CONFIG_ARCH_2050) || defined(CONFIG_ARCH_2100) || defined(CONFIG_ARCH_2200) +#define AST_SCU_MULTI_FUNC_2 0x78 +#else +#define AST_SCU_RAMDOM_DATA 0x78 /* random number generator data output*/ +#endif +#define AST_SCU_REVISION_ID 0x7C /* Silicon revision ID register */ +#define AST_SCU_FUN_PIN_CTRL1 0x80 /* Multi-function Pin Control#1*/ +#define AST_SCU_FUN_PIN_CTRL2 0x84 /* Multi-function Pin Control#2*/ +#define AST_SCU_FUN_PIN_CTRL3 0x88 /* Multi-function Pin Control#3*/ +#define AST_SCU_FUN_PIN_CTRL4 0x8C /* Multi-function Pin Control#4*/ +#define AST_SCU_FUN_PIN_CTRL5 0x90 /* Multi-function Pin Control#5*/ +#define AST_SCU_FUN_PIN_CTRL6 0x94 /* Multi-function Pin Control#6*/ +#define AST_SCU_WDT_RESET 0x9C /* Watchdog Reset Selection */ +#define AST_SCU_FUN_PIN_CTRL7 0xA0 /* Multi-function Pin Control#7*/ +#define AST_SCU_FUN_PIN_CTRL8 0xA4 /* Multi-function Pin Control#8*/ +#define AST_SCU_FUN_PIN_CTRL9 0xA8 /* Multi-function Pin Control#9*/ +#define AST_SCU_PWR_SAVING_EN 0xC0 /* Power Saving Wakeup Enable*/ +#define AST_SCU_PWR_SAVING_CTRL 0xC4 /* Power Saving Wakeup Control*/ +#define AST_SCU_HW_STRAP2 0xD0 /* Haardware strapping register set 2*/ +#define AST_SCU_COUNTER4 0xE0 /* SCU Free Run Counter Read Back #4*/ +#define AST_SCU_COUNTER4_EXT 0xE4 /* SCU Free Run Counter Extended Read Back #4*/ + +//CPU 2 +#define AST_SCU_CPU2_CTRL 0x100 /* CPU2 Control Register*/ +#define AST_SCU_CPU2_BASE0_ADDR 0x104 /* CPU2 Base Address for Segment 0x00:0000~0x1F:FFFF*/ +#define AST_SCU_CPU2_BASE1_ADDR 0x108 /* CPU2 Base Address for Segment 0x20:0000~0x3F:FFFF*/ +#define AST_SCU_CPU2_BASE2_ADDR 0x10C /* CPU2 Base Address for Segment 0x40:0000~0x5F:FFFF*/ +#define AST_SCU_CPU2_BASE3_ADDR 0x110 /* CPU2 Base Address for Segment 0x60:0000~0x7F:FFFF*/ +#define AST_SCU_CPU2_BASE4_ADDR 0x114 /* CPU2 Base Address for Segment 0x80:0000~0xFF:FFFF*/ +#define AST_SCU_CPU2_CACHE_CTRL 0x118 /* CPU2 Cache Function Control */ + +// +#define AST_SCU_UART24_REF 0x160 /* Generate UART 24Mhz Ref from H-PLL when CLKIN is 25Mhz */ +#define AST_SCU_PCIE_CONFIG_SET 0x180 /* PCI-E Configuration Setting Control Register */ +#define AST_SCU_BMC_MMIO_DEC 0x184 /* BMC MMIO Decode Setting Register */ +#define AST_SCU_DEC_AREA1 0x188 /* 1st relocated controller decode area location */ +#define AST_SCU_DEC_AREA2 0x18C /* 2nd relocated controller decode area location */ +#define AST_SCU_MBOX_DEC_AREA 0x190 /* Mailbox decode area location*/ +#define AST_SCU_SRAM_DEC_AREA0 0x194 /* Shared SRAM area decode location*/ +#define AST_SCU_SRAM_DEC_AREA1 0x198 /* Shared SRAM area decode location*/ +#define AST_SCU_BMC_CLASS 0x19C /* BMC device class code and revision ID */ +#define AST_SCU_BMC_DEV_ID 0x1A4 /* BMC device ID */ + + +/* AST_SCU_PROTECT: 0x00 - protection key register */ +#define SCU_PROTECT_UNLOCK 0x1688A8A8 + +/* AST_SCU_RESET :0x04 - system reset control register */ +#if defined (CONFIG_ARCH_AST1010) +#define SCU_RESET_ADC (0x1 << 6) +#define SCU_RESET_JTAG (0x1 << 5) +#define SCU_RESET_MAC0 (0x1 << 4) +#define SCU_RESET_PECI (0x1 << 3) +#define SCU_RESET_PWM (0x1 << 2) +#define SCU_RESET_LPC (0x1 << 1) +#define SCU_RESET_I2C (0x1) +#else +#define SCU_RESET_X_DMA (0x1 << 25) +#define SCU_RESET_MCTP (0x1 << 24) +#define SCU_RESET_ADC (0x1 << 23) +#define SCU_RESET_JTAG (0x1 << 22) +#define SCU_PWAKE_PIN_EN (0x1 << 20) +#define SCU_PWAKE_PIN_OUT (0x1 << 19) +#define SCU_RESET_MIC (0x1 << 18) +#define SCU_RESET_RESV (0x1 << 17) //must keep 1 +#define SCU_RESET_SD (0x1 << 16) +#define SCU_RESET_USB11 (0x1 << 15) +#define SCU_RESET_USB20 (0x1 << 14) +#define SCU_RESET_CRT (0x1 << 13) +#define SCU_RESET_MAC1 (0x1 << 12) +#define SCU_RESET_MAC0 (0x1 << 11) +#define SCU_RESET_PECI (0x1 << 10) +#define SCU_RESET_PWM (0x1 << 9) +#define SCU_PCI_VGA_DIS (0x1 << 8) +#define SCU_RESET_2D (0x1 << 7) +#define SCU_RESET_VIDEO (0x1 << 6) +#define SCU_RESET_LPC (0x1 << 5) +#define SCU_RESET_HAC (0x1 << 4) +#define SCU_RESET_USB11_HID (0x1 << 3) +#define SCU_RESET_I2C (0x1 << 2) +#define SCU_RESET_AHB (0x1 << 1) +#define SCU_RESET_SRAM_CTRL (0x1 << 0) +#endif + +/* AST_SCU_CLK_SEL : 0x08 - clock selection register */ +#if defined(CONFIG_ARCH_AST1010) +#define SCU_CLK_MAC_DIV(x) (x << 12) +#define SCU_CLK_MAC_MASK (0x3 << 12) +#define SCU_LHCLK_SOURCE_EN (0x1 << 11) //0: ext , 1:internel +#define SCU_LHCLK_LPC_DIV(x) (x << 8) +#define SCU_LHCLK_LPC_MASK (0x7 << 8) +#define SCU_PCLK_APB_DIV(x) (x << 5) +#define SCU_GET_PCLK_DIV(x) ((x >> 5) & 0x7) +#define SCU_PCLK_APB_DIV_MASK (0x7 << 5) //limitation on PCLK .. PCLK > 0.5*LCLK (33Mhz) +#define SCU_CLK_CPU_AHB_SLOW_EN (0x1 << 4) +#define SCU_CLK_CPU_AHB_SLOW(x) (x << 3) +#define SCU_CLK_CPU_AHB_SLOW_MASK (0x3 << 3) +#define SCU_GET_AHB_DIV(x) ((x >> 3) & 0x3) +#define SCU_CLK_CPU_AHB_SLOW_IDLE (0x1 << 1) +#define SCU_CLK_CPU_AHB_DYN_SLOW_EN (0x1) +#else +#define SCU_CLK_VIDEO_SLOW_EN (0x1 << 31) +#define SCU_CLK_VIDEO_SLOW_SET(x) (x << 28) +#define SCU_CLK_VIDEO_SLOW_MASK (0x7 << 28) +#define SCU_CLK_2D_ENG_GCLK_INVERT (0x1 << 27) //valid only at CRT mode SCU2C[7] +#define SCU_CLK_2D_ENG_THROT_EN (0x1 << 26) //valid only at CRT mode SCU2C[7] +#define SCU_PCLK_APB_DIV(x) (x << 23) +#define SCU_GET_PCLK_DIV(x) ((x >> 23) & 0x7) +#define SCU_PCLK_APB_DIV_MASK (0x7 << 23) //limitation on PCLK .. PCLK > 0.5*LCLK (33Mhz) +#define SCU_GET_LHCLK_DIV(x) ((x >> 20) & 0x7) +#define SCU_SET_LHCLK_DIV(x) (x << 20) +#define SCU_LHCLK_DIV_MASK (0x7 << 20) +#define SCU_LHCLK_SOURCE_EN (0x1 << 19) //0: ext , 1:internel +#define SCU_CLK_MAC_DIV(x) (x << 16) +#define SCU_CLK_MAC_MASK (0x7 << 16) +#define SCU_CLK_SD_EN (0x1 << 15) +#define SCU_CLK_SD_DIV(x) (x << 12) +#define SCU_CLK_SD_GET_DIV(x) ((x >> 12) & 0x7) +#define SCU_CLK_SD_MASK (0x7 << 12) +#define SCU_CLK_VIDEO_DELAY(x) (x << 8) +#define SCU_CLK_VIDEO_DELAY_MASK (0xf << 8) +#define SCU_CLK_CPU_AHB_SLOW_EN (0x1 << 7) +#define SCU_CLK_CPU_AHB_SLOW(x) (x << 4) +#define SCU_CLK_CPU_AHB_SLOW_MASK (0x7 << 4) +#define SCU_GET_AHB_DIV(x) ((x >> 4) & 0x7) +#define SCU_ECLK_SOURCE(x) (x << 2) +#define SCU_ECLK_SOURCE_MASK (0x3 << 2) +#define SCU_CLK_CPU_AHB_SLOW_IDLE (0x1 << 1) +#define SCU_CLK_CPU_AHB_DYN_SLOW_EN (0x1 << 0) + +#endif + +/* AST_SCU_CLK_STOP : 0x0C - clock stop control register */ +#if defined(CONFIG_ARCH_AST1010) +#define SCU_LHCLK_STOP_EN (0x1 << 7) +#define SCU_MAC0CLK_STOP_EN (0x1 << 6) +#define SCU_UART3_CLK_STOP_EN (0x1 << 5) +#define SCU_UART2_CLK_STOP_EN (0x1 << 4) +#define SCU_UART1_CLK_STOP_EN (0x1 << 3) +#define SCU_LCLK_STOP_EN (0x1 << 2) +#define SCU_REFCLK_STOP_EN (0x1 << 1) +#define SCU_MCLK_STOP_EN (0x1) +#else +#define SCU_LHCLK_STOP_EN (0x1 << 28) +#define SCU_SDCLK_STOP_EN (0x1 << 27) +#define SCU_UART4CLK_STOP_EN (0x1 << 26) +#define SCU_UART3CLK_STOP_EN (0x1 << 25) +#define SCU_RSACLK_STOP_EN (0x1 << 24) +//bit 22~23 must keep 1 +#define SCU_MAC1CLK_STOP_EN (0x1 << 21) +#define SCU_MAC0CLK_STOP_EN (0x1 << 20) +//bit 18~19 must keep 1 +#define SCU_UART5_CLK_STOP_EN (0x1 << 17) +#define SCU_UART2_CLK_STOP_EN (0x1 << 16) +#define SCU_UART1_CLK_STOP_EN (0x1 << 15) +#define SCU_USB20_CLK_EN (0x1 << 14) +#define SCU_YCLK_STOP_EN (0x1 << 13) +#define SCU_D2CLK_STOP_EN (0x1 << 10) +#define SCU_USB11CLK_STOP_EN (0x1 << 9) +#define SCU_LCLK_STOP_EN (0x1 << 8) +#define SCU_UCLK_STOP_EN (0x1 << 7) +#define SCU_REFCLK_STOP_EN (0x1 << 6) +#define SCU_DCLK_STOP_EN (0x1 << 5) +#define SCU_SACLK_STOP_EN (0x1 << 4) +#define SCU_VCLK_STOP_EN (0x1 << 3) +#define SCU_MCLK_STOP_EN (0x1 << 2) +#define SCU_GCLK_STOP_EN (0x1 << 1) +#define SCU_ECLK_STOP_EN (0x1 << 0) +#endif + +/* AST_SCU_COUNT_CTRL : 0x10 - frequency counter control register */ +#define SCU_FREQ_COMP_RESULT (0x1 << 7) +#define SCU_FREQ_MEASU_FINISH (0x1 << 6) +#define SCU_FREQ_SOURCE_FOR_MEASU(x) (x << 2) +#define SCU_FREQ_SOURCE_FOR_MEASU_MASK (0xf << 2) + +#define SCU_SOURCE_6M 0xf +#define SCU_SOURCE_12M 0xe +#define SCU_SOURCE_I2SM_CLK 0xd +#define SCU_SOURCE_H_CLK 0xc +#define SCU_SOURCE_B_CLK 0xb +#define SCU_SOURCE_D2_PLL 0xa + +#define SCU_SOURCE_VIDEO_CLK 0x7 +#define SCU_SOURCE_LPC_CLK 0x6 +#define SCU_SOURCE_I2S_CLK 0x5 +#define SCU_SOURCE_M_CLK 0x4 +#define SCU_SOURCE_SALI_CLK 0x3 +#define SCU_SOURCE_D_PLL 0x2 +#define SCU_SOURCE_NAND 0x1 +#define SCU_SOURCE_DEL_CELL 0x0 + +#define SCU_OSC_COUNT_EN (0x1 << 1) +#define SCU_RING_OSC_EN (0x1 << 0) + + +/* AST_SCU_INTR_CTRL : 0x18 - Interrupt control and status register */ +#define INTR_LPC_H_L_RESET (0x1 << 21) +#define INTR_LPC_L_H_RESET (0x1 << 20) +#define INTR_PCIE_H_L_RESET (0x1 << 19) +#define INTR_PCIE_L_H_RESET (0x1 << 18) +#define INTR_VGA_SCRATCH_CHANGE (0x1 << 17) +#define INTR_VGA_CURSOR_CHANGE (0x1 << 16) +#define INTR_MSI_EN (0x1 << 6) +#define INTR_LPC_H_L_RESET_EN (0x1 << 5) +#define INTR_LPC_L_H_RESET_EN (0x1 << 4) +#define INTR_PCIE_H_L_RESET_EN (0x1 << 3) +#define INTR_PCIE_L_H_RESET_EN (0x1 << 2) +#define INTR_VGA_SCRATCH_CHANGE_EN (0x1 << 1) +#define INTR_VGA_CURSOR_CHANGE_EN (0x1 << 0) + +/* AST_SCU_D2_PLL: 0x1C - D2-PLL Parameter register */ +#define SCU_D2_PLL_SET_PD2(x) (x << 19) +#define SCU_D2_PLL_GET_PD2(x) ((x >> 19)&0x7) +#define SCU_D2_PLL_PD2_MASK (0x7 << 19) +#define SCU_D2_PLL_BYPASS_EN (0x1 << 18) +#define SCU_D2_PLL_OFF (0x1 << 17) +#define SCU_D2_PLL_SET_PD(x) (x << 15) +#define SCU_D2_PLL_GET_PD(x) ((x >> 15) &0x3) +#define SCU_D2_PLL_PD_MASK (0x3 << 15) +#define SCU_D2_PLL_SET_OD(x) (x << 13) +#define SCU_D2_PLL_GET_OD(x) ((x >> 13) & 0x3) +#define SCU_D2_PLL_OD_MASK (0x3 << 13) +#define SCU_D2_PLL_SET_DENUM(x) (x << 8) +#define SCU_D2_PLL_GET_DENUM(x) ((x >>8)&0x1f) +#define SCU_D2_PLL_DENUM_MASK (0x1f << 8) +#define SCU_D2_PLL_SET_NUM(x) (x) +#define SCU_D2_PLL_GET_NUM(x) (x & 0xff) +#define SCU_D2_PLL_NUM_MASK (0xff) + + +/* AST_SCU_M_PLL : 0x20 - M-PLL Parameter register */ +#define SCU_M_PLL_BYPASS_EN (0x1 << 17) +#define SCU_M_PLL_OFF (0x1 << 16) +#define SCU_M_PLL_NUM(x) (x << 5) +#define SCU_M_PLL_GET_NUM(x) ((x >> 5) & 0x3f) +#define SCU_M_PLL_NUM_MASK (0x3f << 5) +#define SCU_M_PLL_OUT_DIV (0x1 << 4) +#define SCU_M_PLL_GET_DIV(x) ((x >> 4) & 0x1) +#define SCU_M_PLL_DENUM(x) (x) +#define SCU_M_PLL_GET_DENUM(x) (x & 0xf) + + +/* AST_SCU_H_PLL: 0x24- H-PLL Parameter register */ +#if defined(CONFIG_ARCH_AST1010) +#define SCU_H_PLL_MASK_EN (0x1 << 10) +#define SCU_H_PLL_REST_EN (0x1 << 9) +#define SCU_H_PLL_OUT_DIV(x) (x << 7) +#define SCU_H_PLL_GET_DIV(x) ((x >> 7) & 0x3) +#define SCU_H_PLL_GET_DENUM(x) ((x >> 6) & 0x1) +#define SCU_H_PLL_NUM(x) (x) +#define SCU_H_PLL_GET_NUM(x) (x & 0x3f) +#define SCU_H_PLL_NUM_MASK (0x3f) + +#else +#define SCU_H_PLL_PARAMETER (0x1 << 18) +#define SCU_H_PLL_BYPASS_EN (0x1 << 17) +#define SCU_H_PLL_OFF (0x1 << 16) +#define SCU_H_PLL_NUM(x) (x << 5) +#define SCU_H_PLL_GET_NUM(x) ((x >> 5) & 0x3f) +#define SCU_H_PLL_NUM_MASK (0x3f << 5) +#define SCU_H_PLL_OUT_DIV (0x1 << 4) +#define SCU_H_PLL_GET_DIV(x) ((x >> 4) & 0x1) +#define SCU_H_PLL_DENUM(x) (x) +#define SCU_H_PLL_GET_DENUM(x) (x & 0xf) +#define SCU_H_PLL_DENUM_MASK (0xf) +#endif + +/* AST_SCU_FREQ_LIMIT : 0x28 - frequency counter comparsion register */ +#define SCU_FREQ_U_LIMIT(x) (x << 16) +#define SCU_FREQ_U_LIMIT_MASK (0x3fff << 16) +#define SCU_FREQ_L_LIMIT(x) (x) +#define SCU_FREQ_L_LIMIT_MASK (0x3fff) + + +/* AST_SCU_MISC_CTRL : 0x2C - Misc. Control register */ +#define SCU_MISC_JTAG_MASTER_DIS (0x1 << 26) +#define SCU_MISC_DRAM_W_P2A_DIS (0x1 << 25) +#define SCU_MISC_SPI_W_P2A_DIS (0x1 << 24) +#define SCU_MISC_SOC_W_P2A_DIS (0x1 << 23) +#define SCU_MISC_FLASH_W_P2A_DIS (0x1 << 22) +#define SCU_MISC_D_PLL_ASSIGN(x) (x << 20) +#define SCU_MISC_D_PLL_ASSIGN_MASK (0x3 << 20) +#define SCU_MISC_VGA_CONFIG_PREFETCH (0x1 << 19) +#define SCU_MISC_DVO_SOURCE_CRT (0x1 << 18) //0:VGA , 1:CRT +#define SCU_MISC_DAC_MASK (0x3 << 16) +#define SCU_MISC_DAC_SOURCE_CRT (0x1 << 16) //00 VGA, 01: CRT, 1x: PASS-Through DVO +#define SCU_MISC_DAC_SOURCE_MASK (0x3 << 16) +#define SCU_MISC_JTAG_TO_PCIE_EN (0x1 << 15) +#define SCU_MISC_JTAG__M_TO_PCIE_EN (0x1 << 14) +#define SCU_MISC_VUART_TO_CTRL (0x1 << 13) +#define SCU_MISC_DIV13_EN (0x1 << 12) +#define SCU_MISC_Y_CLK_INVERT (0x1 << 11) +#define SCU_MISC_OUT_DELAY (0x1 << 9) +#define SCU_MISC_PCI_TO_AHB_DIS (0x1 << 8) +#define SCU_MISC_2D_CRT_EN (0x1 << 7) +#define SCU_MISC_VGA_CRT_DIS (0x1 << 6) +#define SCU_MISC_VGA_REG_ACCESS_EN (0x1 << 5) +#define SCU_MISC_D2_PLL_DIS (0x1 << 4) +#define SCU_MISC_DAC_DIS (0x1 << 3) +#define SCU_MISC_D_PLL_DIS (0x1 << 2) +#define SCU_MISC_OSC_CLK_OUT_PIN (0x1 << 1) +#define SCU_MISC_LPC_TO_SPI_DIS (0x1 << 0) + +/* AST_SCU_PCI_CONF1 : 0x30 - PCI configuration setting register#1 */ +#define SCU_PCI_DEVICE_ID(x) (x << 16) +#define SCU_PCI_VENDOR_ID(x) (x) + +/* AST_SCU_PCI_CONF2 0x34 PCI configuration setting register#2 */ +#define SCU_PCI_SUB_SYS_ID(x) (x << 16) +#define SCU_PCI_SUB_VENDOR_ID(x) (x) + +/* AST_SCU_PCI_CONF3 0x38 PCI configuration setting register#3 */ +#define SCU_PCI_CLASS_CODE(x) (x << 8) +#define SCU_PCI_REVISION_ID(x) (x) + +/* AST_SCU_SYS_CTRL 0x3C System reset contrl/status register*/ +#define SCU_SYS_EXT_SOC_RESET_EN (0x1 << 3) +#define SCU_SYS_EXT_RESET_FLAG (0x1 << 2) +#define SCU_SYS_WDT_RESET_FLAG (0x1 << 1) +#define SCU_SYS_PWR_RESET_FLAG (0x1 << 0) + +/* AST_SCU_SOC_SCRATCH0 0x40 SOC scratch 0~31 register */ + + + + +/* AST_SCU_SOC_SCRATCH1 0x44 SOC scratch 32~63 register */ + + +/* AST_SCU_VGA0 0x40 VGA fuction handshake register */ +#define SCU_VGA_SLT_HANDSHAKE(x) (x << 24) +#define SCU_VGA_SLT_HANDSHAKE_MASK (0xff << 24) +#define SCU_VGA_CTM_DEF(x) (x << 16) +#define SCU_VGA_CTM_DEF_MASK (0xff << 16) +#define SCU_MAC0_PHY_MODE(x) (x << 14) +#define SCU_MAC0_GET_PHY_MODE(x) ((x >> 14) & 0x3) +#define SCU_MAC0_PHY_MODE_MASK(x) (0x3 << 14) +#define SCU_MAC1_PHY_MODE(x) (x << 12) +#define SCU_MAC1_PHY_MODE_MASK (0x3 << 12) +#define SCU_MAC1_GET_PHY_MODE(x) ((x >> 12) & 0x3) + +#define SCU_VGA_ASPEED_DEF(x) (x << 8) +#define SCU_VGA_ASPEED_DEF_MASK (0xf << 8) + +#define SCU_VGA_DRAM_INIT_MASK(x) ((x >> 7) & 0x1) + +/* AST_SCU_VGA1 0x44 VGA fuction handshake register */ + + +/* AST_SCU_MAC_CLK 0x48 MAC interface clock delay setting register */ + + + +/* AST_SCU_MISC_CTRL 0x4C Misc. 2 Control register */ +/* AST_SCU_VGA_SCRATCH0 0x50 VGA Scratch register */ +/* AST_SCU_VGA_SCRATCH1 0x54 VGA Scratch register */ +/* AST_SCU_VGA_SCRATCH2 0x58 VGA Scratch register */ +/* AST_SCU_VGA_SCRATCH3 0x5c VGA Scratch register */ +/* AST_SCU_VGA_SCRATCH4 0x60 VGA Scratch register */ +/* AST_SCU_VGA_SCRATCH5 0x64 VGA Scratch register */ +/* AST_SCU_VGA_SCRATCH6 0x68 VGA Scratch register */ +/* AST_SCU_VGA_SCRATCH7 0x6c VGA Scratch register */ + +/* AST_SCU_HW_STRAP1 0x70 hardware strapping register */ +#define SCU_HW_STRAP_SW_DEFINE(x) (x << 29) +#define SCU_HW_STRAP_SW_DEFINE_MASK (0x3 << 29) +#define SCU_HW_STRAP_DRAM_SIZE (x << 29) +#define SCU_HW_STRAP_DRAM_SIZE_MASK (0x3 << 29) + +#define VGA_64M_DRAM 0 +#define VGA_128M_DRAM 1 +#define VGA_256M_DRAM 2 +#define VGA_512M_DRAM 3 + +#define SCU_HW_STRAP_DRAM_CONFIG (x << 24) +#define SCU_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24) + +#define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22) +#define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21) +#define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20) +#define SCU_HW_STRAP_ACPI_DIS (0x1 << 19) + +//bit 23, 18 [1,0] +#define SCU_HW_STRAP_SET_CLK_SOURCE(x) ((((x&0x3) >> 1)<<23)||((x&0x1) << 18)) +#define SCU_HW_STRAP_GET_CLK_SOURCE(x) (((x>>23)&0x1<<1) | ((x>>18)&0x1)) +#define SCU_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18)) + +#define CLK_25M_IN (0x1 << 23) +#define CLK_24M_IN 0 +#define CLK_48M_IN 1 +#define CLK_25M_IN_24M_USB_CKI 3 +#define CLK_25M_IN_48M_USB_CKI 3 + +#define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17) +#define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16) +#define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15) +#define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14) +#define SCU_HW_STRAP_SPI_MODE(x) (x << 12) +#define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12) +#define SPI_MODE_DIS (0) +#define SPI_MODE_MASTER_EN (1) +#define SPI_MODE_M_S_EN (2) +#define SPI_MODE_PS (3) + +#define SCU_HW_STRAP_SET_CPU_AHB_RATIO(x) (x << 10) +#define SCU_HW_STRAP_GET_CPU_AHB_RATIO(x) ((x >> 10) & 3) +#define SCU_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10) + + +#define CPU_AHB_RATIO_1_1 0 +#define CPU_AHB_RATIO_2_1 1 +#define CPU_AHB_RATIO_4_1 2 +#define CPU_AHB_RATIO_3_1 3 + +#define SCU_HW_STRAP_GET_H_PLL_CLK(x) ((x >> 8 )& 0x3) +#define SCU_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8) +#define CPU_384MHZ 0 +#define CPU_360MHZ 1 +#define CPU_336MHZ 2 +#define CPU_408MHZ 3 + +#define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7) +#define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6) +#define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5) +#define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4) +#define SCU_HW_STRAP_VGA_SIZE_GET(x) ((x >> 2)& 0x3) + +#define SCU_HW_STRAP_BOOT_MODE(x) (x) +#define NOR_BOOT 0 +#define NAND_BOOT 1 +#define SPI_BOOT 2 +#define DIS_BOOT 3 + +/* AST_SCU_RAMDOM_GEN 0x74 random number generator register */ +/* AST_SCU_RAMDOM_DATA 0x78 random number generator data output*/ + +/* AST_SCU_MULTI_FUNC_2 0x78 */ + +#define MULTI_FUNC_VIDEO_RGB18 (0x1 << 2) +#define MULTI_FUNC_VIDEO_SINGLE_EDGE (0x1 << 0) + + + +/* AST_SCU_REVISION_ID 0x7C Silicon revision ID register */ +#define AST1100_A0 0x00000200 +#define AST1100_A1 0x00000201 +#define AST1100_A2 0x00000202 +#define AST1100_A3 0x00000202 + +#define AST2050_A0 0x00000200 +#define AST2050_A1 0x00000201 +#define AST2050_A2 0x00000202 +#define AST2050_A3 0x00000202 + +#define AST2100_A0 0x00000300 +#define AST2100_A1 0x00000301 +#define AST2100_A2 0x00000302 +#define AST2100_A3 0x00000302 + +#define AST2200_A0 0x00000102 +#define AST2200_A1 0x00000102 + +#define AST2300_A0 0x01000003 +#define AST2300_A1 0x01010303 +#define AST1300_A1 0x01010003 +#define AST1050_A1 0x01010203 + +#define AST2400_A0 0x02000303 + + +/* AST_SCU_FUN_PIN_CTRL1 0x80 Multi-function Pin Control#1*/ +#define SCU_FUN_PIN_UART4_RXD (0x1 << 31) +#define SCU_FUN_PIN_UART4_TXD (0x1 << 30) +#define SCU_FUN_PIN_UART4_NRTS (0x1 << 29) +#define SCU_FUN_PIN_UART4_NDTR (0x1 << 28) +#define SCU_FUN_PIN_UART4_NRI (0x1 << 27) +#define SCU_FUN_PIN_UART4_NDSR (0x1 << 26) +#define SCU_FUN_PIN_UART4_NDCD (0x1 << 25) +#define SCU_FUN_PIN_UART4_NCTS (0x1 << 24) +#define SCU_FUN_PIN_UART3_RXD (0x1 << 23) +#define SCU_FUN_PIN_UART3_TXD (0x1 << 22) +#define SCU_FUN_PIN_UART3_NRTS (0x1 << 21) +#define SCU_FUN_PIN_UART3_NDTR (0x1 << 20) +#define SCU_FUN_PIN_UART3_NRI (0x1 << 19) +#define SCU_FUN_PIN_UART3_NDSR (0x1 << 18) +#define SCU_FUN_PIN_UART3_NDCD (0x1 << 17) +#define SCU_FUN_PIN_UART3_NCTS (0x1 << 16) + + + + +#define SCU_FUN_PIN_MAC1_PHY_LINK (0x1 << 1) +#define SCU_FUN_PIN_MAC0_PHY_LINK (0x1) + + +/* AST_SCU_FUN_PIN_CTRL2 0x84 Multi-function Pin Control#2*/ +#define SCU_FUN_PIN_VPIB9 (0x1 << 31) +#define SCU_FUN_PIN_VPIB8 (0x1 << 30) +#define SCU_FUN_PIN_VPIB7 (0x1 << 29) +#define SCU_FUN_PIN_VPIB6 (0x1 << 28) +#define SCU_FUN_PIN_VPIB5 (0x1 << 27) +#define SCU_FUN_PIN_VPIB4 (0x1 << 26) +#define SCU_FUN_PIN_VPIB3 (0x1 << 25) +#define SCU_FUN_PIN_VPIB2 (0x1 << 24) +#define SCU_FUN_PIN_VPIB1 (0x1 << 23) +#define SCU_FUN_PIN_VPIB0 (0x1 << 22) +#define SCU_FUN_PIN_VPICLK (0x1 << 21) +#define SCU_FUN_PIN_VPIVS (0x1 << 20) +#define SCU_FUN_PIN_VPIHS (0x1 << 19) +#define SCU_FUN_PIN_VPIODD (0x1 << 18) +#define SCU_FUN_PIN_VPIDE (0x1 << 17) + +#define SCU_FUN_PIN_UART2_RXD (0x1 << 31) +#define SCU_FUN_PIN_UART2_TXD (0x1 << 30) +#define SCU_FUN_PIN_UART2_NRTS (0x1 << 29) +#define SCU_FUN_PIN_UART2_NDTR (0x1 << 28) +#define SCU_FUN_PIN_UART2_NRI (0x1 << 27) +#define SCU_FUN_PIN_UART2_NDSR (0x1 << 26) +#define SCU_FUN_PIN_UART2_NDCD (0x1 << 25) +#define SCU_FUN_PIN_UART2_NCTS (0x1 << 24) +#define SCU_FUN_PIN_UART1_RXD (0x1 << 23) +#define SCU_FUN_PIN_UART1_TXD (0x1 << 22) +#define SCU_FUN_PIN_UART1_NRTS (0x1 << 21) +#define SCU_FUN_PIN_UART1_NDTR (0x1 << 20) +#define SCU_FUN_PIN_UART1_NRI (0x1 << 19) +#define SCU_FUN_PIN_UART1_NDSR (0x1 << 18) +#define SCU_FUN_PIN_UART1_NDCD (0x1 << 17) +#define SCU_FUN_PIN_UART1_NCTS (0x1 << 16) + + +#define SCU_FUN_PIN_NAND_FLWP (0x1 << 7) +#define SCU_FUN_PIN_NAND_FLBUSY (0x1 << 6) + +/* AST_SCU_FUN_PIN_CTRL3 0x88 Multi-function Pin Control#3*/ +#if defined(CONFIG_ARCH_AST1010) +#define SCU_FUN_PIN_MAC0_MDIO (0x1 << 23) +#define SCU_FUN_PIN_MAC0_MDC (0x1 << 22) +#else +#define SCU_FUN_PIN_MAC0_MDIO (0x1 << 31) +#define SCU_FUN_PIN_MAC0_MDC (0x1 << 30) +#define SCU_FUN_PIN_ROMA25 (0x1 << 29) +#define SCU_FUN_PIN_ROMA24 (0x1 << 28) +#define SCU_FUN_PIN_ROMCS4 (0x1 << 27) +#define SCU_FUN_PIN_ROMCS3 (0x1 << 26) +#define SCU_FUN_PIN_ROMCS2 (0x1 << 25) +#define SCU_FUN_PIN_ROMCS1 (0x1 << 24) +#define SCU_FUN_PIN_ROMCS(x) (0x1 << (23+x)) + +//Video pin +#define SCU_FUN_PIN_VPIR9 (0x1 << 19) +#define SCU_FUN_PIN_VPIR8 (0x1 << 18) +#define SCU_FUN_PIN_VPIR7 (0x1 << 17) +#define SCU_FUN_PIN_VPIR6 (0x1 << 16) +#define SCU_FUN_PIN_VPIR5 (0x1 << 15) +#define SCU_FUN_PIN_VPIR4 (0x1 << 14) +#define SCU_FUN_PIN_VPIR3 (0x1 << 13) +#define SCU_FUN_PIN_VPIR2 (0x1 << 12) +#define SCU_FUN_PIN_VPIR1 (0x1 << 11) +#define SCU_FUN_PIN_VPIR0 (0x1 << 10) +#define SCU_FUN_PIN_VPIG9 (0x1 << 9) +#define SCU_FUN_PIN_VPIG8 (0x1 << 8) +#define SCU_FUN_PIN_VPIG7 (0x1 << 7) +#define SCU_FUN_PIN_VPIG6 (0x1 << 6) +#define SCU_FUN_PIN_VPIG5 (0x1 << 5) +#define SCU_FUN_PIN_VPIG4 (0x1 << 4) +#define SCU_FUN_PIN_VPIG3 (0x1 << 3) +#define SCU_FUN_PIN_VPIG2 (0x1 << 2) +#define SCU_FUN_PIN_VPIG1 (0x1 << 1) +#define SCU_FUN_PIN_VPIG0 (0x1 << 0) +#endif + + +//pwm pin +#define SCU_FUN_PIN_PWM_TACHO (0) +/* AST_SCU_FUN_PIN_CTRL4 0x8C Multi-function Pin Control#4*/ +#define SCU_FUN_PIN_ROMA23 (0x1 << 7) +#define SCU_FUN_PIN_ROMA22 (0x1 << 6) + +#define SCU_FUN_PIN_ROMWE (0x1 << 5) +#define SCU_FUN_PIN_ROMOE (0x1 << 4) +#define SCU_FUN_PIN_ROMD7 (0x1 << 3) +#define SCU_FUN_PIN_ROMD6 (0x1 << 2) +#define SCU_FUN_PIN_ROMD5 (0x1 << 1) +#define SCU_FUN_PIN_ROMD4 (0x1) + +/* AST_SCU_FUN_PIN_CTRL5 0x90 Multi-function Pin Control#5*/ +#define SCU_FUN_PIN_SPICS1 (0x1 << 31) +#define SCU_FUN_PIN_LPC_PLUS (0x1 << 30) +#define SCU_FUC_PIN_USB20_HOST (0x1 << 29) +#define SCU_FUC_PIN_USB11_PORT4 (0x1 << 28) +#define SCU_FUC_PIN_I2C14 (0x1 << 27) +#define SCU_FUC_PIN_I2C13 (0x1 << 26) +#define SCU_FUC_PIN_I2C12 (0x1 << 25) +#define SCU_FUC_PIN_I2C11 (0x1 << 24) +#define SCU_FUC_PIN_I2C10 (0x1 << 23) +#define SCU_FUC_PIN_I2C9 (0x1 << 22) +#define SCU_FUC_PIN_I2C8 (0x1 << 21) +#define SCU_FUC_PIN_I2C7 (0x1 << 20) +#define SCU_FUC_PIN_I2C6 (0x1 << 19) +#define SCU_FUC_PIN_I2C5 (0x1 << 18) +#define SCU_FUC_PIN_I2C4 (0x1 << 17) +#define SCU_FUC_PIN_I2C3 (0x1 << 16) +#define SCU_FUC_PIN_MII2_RX_DWN_DIS (0x1 << 15) +#define SCU_FUC_PIN_MII2_TX_DWN_DIS (0x1 << 14) +#define SCU_FUC_PIN_MII1_RX_DWN_DIS (0x1 << 13) +#define SCU_FUC_PIN_MII1_TX_DWN_DIS (0x1 << 12) + +#define SCU_FUC_PIN_MII2_TX_DRIV(x) (x << 10) +#define SCU_FUC_PIN_MII2_TX_DRIV_MASK (0x3 << 10) +#define SCU_FUC_PIN_MII1_TX_DRIV(x) (x << 8) +#define SCU_FUC_PIN_MII1_TX_DRIV_MASK (0x3 << 8) + +#define MII_NORMAL_DRIV 0x0 +#define MII_HIGH_DRIV 0x2 + +#define SCU_FUC_PIN_UART6 (0x1 << 7) +#define SCU_FUC_PIN_ROM_16BIT (0x1 << 6) +#define SCU_FUC_PIN_DIGI_V_OUT(x) (x << 4) +#define SCU_FUC_PIN_DIGI_V_OUT_MASK (0x3 << 4) + +#define VIDEO_DISABLE 0x0 +#define VIDEO_12BITS 0x1 +#define VIDEO_24BITS 0x2 +//#define VIDEO_DISABLE 0x3 + +#define SCU_FUC_PIN_USB11_PORT2 (0x1 << 3) +#define SCU_FUC_PIN_MAC1_MDIO (0x1 << 2) +#define SCU_FUC_PIN_SD2 (0x1 << 1) +#define SCU_FUC_PIN_SD1 (0x1 << 0) + + +/* AST_SCU_FUN_PIN_CTRL6 0x94 Multi-function Pin Control#6*/ +#define SCU_VIDEO_OUT_MASK (~0x3) + +/* AST_SCU_WDT_RESET 0x9C Watchdog Reset Selection */ +/* AST_SCU_FUN_PIN_CTRL7 0xA0 Multi-function Pin Control#7*/ +/* AST_SCU_FUN_PIN_CTRL8 0xA4 Multi-function Pin Control#8*/ +#define SCU_FUN_PIN_ROMA17 (0x1 << 31) +#define SCU_FUN_PIN_ROMA16 (0x1 << 30) +#define SCU_FUN_PIN_ROMA15 (0x1 << 29) +#define SCU_FUN_PIN_ROMA14 (0x1 << 28) +#define SCU_FUN_PIN_ROMA13 (0x1 << 27) +#define SCU_FUN_PIN_ROMA12 (0x1 << 26) +#define SCU_FUN_PIN_ROMA11 (0x1 << 25) +#define SCU_FUN_PIN_ROMA10 (0x1 << 24) +#define SCU_FUN_PIN_ROMA9 (0x1 << 23) +#define SCU_FUN_PIN_ROMA8 (0x1 << 22) +#define SCU_FUN_PIN_ROMA7 (0x1 << 21) +#define SCU_FUN_PIN_ROMA6 (0x1 << 20) +#define SCU_FUN_PIN_ROMA5 (0x1 << 19) +#define SCU_FUN_PIN_ROMA4 (0x1 << 18) +#define SCU_FUN_PIN_ROMA3 (0x1 << 17) +#define SCU_FUN_PIN_ROMA2 (0x1 << 16) + +/* AST_SCU_FUN_PIN_CTRL9 0xA8 Multi-function Pin Control#9*/ +#define SCU_FUN_PIN_ROMA21 (0x1 << 3) +#define SCU_FUN_PIN_ROMA20 (0x1 << 2) +#define SCU_FUN_PIN_ROMA19 (0x1 << 1) +#define SCU_FUN_PIN_ROMA18 (0x1) + +/* AST_SCU_PWR_SAVING_EN 0xC0 Power Saving Wakeup Enable*/ +/* AST_SCU_PWR_SAVING_CTRL 0xC4 Power Saving Wakeup Control*/ +/* AST_SCU_HW_STRAP2 0xD0 Haardware strapping register set 2*/ +/* AST_SCU_COUNTER4 0xE0 SCU Free Run Counter Read Back #4*/ +/* AST_SCU_COUNTER4_EXT 0xE4 SCU Free Run Counter Extended Read Back #4*/ + +//CPU 2 +/* AST_SCU_CPU2_CTRL 0x100 CPU2 Control Register*/ +/* AST_SCU_CPU2_BASE0_ADDR 0x104 CPU2 Base Address for Segment 0x00:0000~0x1F:FFFF*/ +/* AST_SCU_CPU2_BASE1_ADDR 0x108 CPU2 Base Address for Segment 0x20:0000~0x3F:FFFF*/ +/* AST_SCU_CPU2_BASE2_ADDR 0x10C CPU2 Base Address for Segment 0x40:0000~0x5F:FFFF*/ +/* AST_SCU_CPU2_BASE3_ADDR 0x110 CPU2 Base Address for Segment 0x60:0000~0x7F:FFFF*/ +/* AST_SCU_CPU2_BASE4_ADDR 0x114 CPU2 Base Address for Segment 0x80:0000~0xFF:FFFF*/ +/* AST_SCU_CPU2_CACHE_CTRL 0x118 CPU2 Cache Function Control */ + +// +/* AST_SCU_UART24_REF 0x160 Generate UART 24Mhz Ref from H-PLL when CLKIN is 25Mhz */ +/* AST_SCU_PCIE_CONFIG_SET 0x180 PCI-E Configuration Setting Control Register */ +/* AST_SCU_BMC_MMIO_DEC 0x184 BMC MMIO Decode Setting Register */ +/* AST_SCU_DEC_AREA1 0x188 1st relocated controller decode area location */ +/* AST_SCU_DEC_AREA2 0x18C 2nd relocated controller decode area location */ +/* AST_SCU_MBOX_DEC_AREA 0x190 Mailbox decode area location*/ +/* AST_SCU_SRAM_DEC_AREA0 0x194 Shared SRAM area decode location*/ +/* AST_SCU_SRAM_DEC_AREA1 0x198 Shared SRAM area decode location*/ +/* AST_SCU_BMC_CLASS 0x19C BMC device class code and revision ID */ +/* AST_SCU_BMC_DEV_ID 0x1A4 BMC device ID */ + +#endif + diff --git a/arch/arm/plat-aspeed/include/plat/regs-sdmc.h b/arch/arm/plat-aspeed/include/plat/regs-sdmc.h new file mode 100644 index 000000000000..2bcc9488ca72 --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-sdmc.h @@ -0,0 +1,31 @@ +/* arch/arm/mach-aspeed/include/mach/regs-ast1010-scu.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * History : + * 1. 2012/12/29 Ryan Chen Create + * +********************************************************************************/ +#ifndef __AST_SDMC_H +#define __AST_SDMC_H 1 + +/* + * Register for SDMC + * */ +#define AST_SDMC_PROTECT 0x00 /* protection key register */ +#define AST_SDMC_CONFIG 0x04 /* Configuration register */ + + +/* AST_SDMC_PROTECT: 0x00 - protection key register */ +#define SDMC_PROTECT_UNLOCK 0xFC600309 + +/* AST_SDMC_CONFIG :0x04 - Configuration register */ +#define SDMC_CONFIG_MEM_GET(x) (x & 0x3) + + +#endif + diff --git a/arch/arm/plat-aspeed/include/plat/regs-smc.h b/arch/arm/plat-aspeed/include/plat/regs-smc.h new file mode 100644 index 000000000000..d4e02524c9d9 --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-smc.h @@ -0,0 +1,54 @@ +/* arch/arm/plat-aspeed/include/mach/regs-smc.h + * + * Copyright (c) 2012 ASPEED Technology Inc. <ryan_chen@aspeedtech.com> + * http://www.aspeedtech.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ASPEED Static memory ctrol +*/ + +#ifndef __ASM_ARCH_REGS_FMC_H +#define __ASM_ARCH_REGS_FMC_H __FILE__ + +#define FMC_CE_TYPE 0x00 +#define FMC_CE_CTRL 0x04 +#define FMC_INTR_CTRL 0x08 +#define FMC_CE0_CTRL 0x10 +#define FMC_CE1_CTRL 0x14 +#define FMC_CE2_CTRL 0x18 +#define FMC_CE3_CTRL 0x1c +#define FMC_CE4_CTRL 0x20 + +#define FMC_CE0_ADDR 0x30 +#define FMC_CE1_ADDR 0x34 +#define FMC_CE2_ADDR 0x38 +#define FMC_CE3_ADDR 0x3c +#define FMC_CE4_ADDR 0x40 + +#define FMC_MISC_CTRL1 0x50 +#define FMC_MISC_CTRL2 0x54 +#define FMC_NAND_CTRL 0x58 +#define FMC_NAND_ECC 0x5c +#define FMC_NAND_ECC_CK1 0x60 +#define FMC_NAND_ECC_CK2 0x64 +#define FMC_NAND_ECC_CK3 0x68 +#define FMC_NAND_ECC_GEN1 0x6c +#define FMC_NAND_ECC_GEN2 0x70 +#define FMC_NAND_ECC_GEN3 0x74 +#define FMC_NAND_ECC_CK_R1 0x78 +#define FMC_NAND_ECC_CK_R2 0x7c +#define FMC_DMA_CTRL 0x80 +#define FMC_DMA_FLASH_ADDR 0x84 +#define FMC_DMA_DRAM_ADDR 0x88 +#define FMC_DMA_LEN 0x8C +#define FMC_CHECK_SUM 0x90 +#define FMC_SPI_TIMING 0x94 + + + + + +#endif /* __ASM_ARCH_REGS_FMC_H */ diff --git a/arch/arm/plat-aspeed/include/plat/regs-spi.h b/arch/arm/plat-aspeed/include/plat/regs-spi.h new file mode 100644 index 000000000000..9b20cf80e71e --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-spi.h @@ -0,0 +1,51 @@ +/******************************************************************************** +* File Name : regs-spi.h +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +********************************************************************************/ + +/* Register offsets */ +#define AST_SPI_CONFIG 0x00 +#define AST_SPI_CTRL 0x04 +#define AST_SPI_MISC 0x10 +#define AST_SPI_TIMING 0x14 + +/* AST_SPI_CONFIG 0x00 : SPI Flash Configuration Register */ +#define SPI_CONF_CLKX2 (0x1 << 1) +#define SPI_CONF_WRITE_EN (0x1) + +/* FMC_CE0_CTRL for SPI 0x10, 0x14, 0x18, 0x1c, 0x20 */ +#define SPI_IO_MODE(x) (x << 28) +#define SPI_SINGLE_BIT 0 +#define SPI_DUAL_BIT_D 2 +#define SPI_DUAL_BIT_DA 3 +#define SPI_CE_WIDTH(x) (x << 24) +#define SPI_CMD_DATA(x) (x << 16) +#define SPI_DUMMY_CMD (1 << 15) +#define SPI_DUMMY_HIGH (1 << 14) +//#define SPI_CLK_DIV (1 << 13) ?? TODO ask.... +//#define SPI_ADDR_CYCLE (1 << 13) ?? TODO ask.... +#define SPI_CMD_MERGE_DIS (1 << 12) +#define SPI_CLK_DIV(x) (x << 8) +#define SPI_CLK_DIV_MASK (0xf << 8) + +#define SPI_DUMMY_LOW (x << 6) +#define SPI_LSB_FIRST_CTRL (1 << 5) +#define SPI_CPOL_1 (1 << 4) +#define SPI_DUAL_DATA (1 << 3) +#define SPI_CE_INACTIVE (1 << 2) +#define SPI_CMD_MODE (x) +#define SPI_CMD_NOR_R_MODE 0 +#define SPI_CMD_FAST_R_MODE 1 +#define SPI_CMD_NOR_W_MODE 2 +#define SPI_CMD_USER_MODE 3 + diff --git a/arch/arm/plat-aspeed/include/plat/regs-uart-dma.h b/arch/arm/plat-aspeed/include/plat/regs-uart-dma.h new file mode 100644 index 000000000000..2282bb184166 --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-uart-dma.h @@ -0,0 +1,79 @@ +/* arch/arm/mach-aspeed/include/mach/regs-uart-dma.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * History : + * 1. 2013/05/15 Ryan Chen Create + * +********************************************************************************/ +#ifndef __AST1070_UART_DMA_H +#define __AST1070_UART_DMA_H 1 + +#define UART_DMA0_TX_CTRL 0x00 +#define UART_DMA0_TX_DESCPT 0x04 +#define UART_DMA1_TX_CTRL 0x08 +#define UART_DMA1_TX_DESCPT 0x0C +#define UART_DMA2_TX_CTRL 0x10 +#define UART_DMA2_TX_DESCPT 0x14 +#define UART_DMA3_TX_CTRL 0x18 +#define UART_DMA3_TX_DESCPT 0x1C +#define UART_DMA0_RX_CTRL 0x20 +#define UART_DMA0_RX_DESCPT 0x24 +#define UART_DMA1_RX_CTRL 0x28 +#define UART_DMA1_RX_DESCPT 0x2C +#define UART_DMA2_RX_CTRL 0x30 +#define UART_DMA2_RX_DESCPT 0x34 +#define UART_DMA3_RX_CTRL 0x38 +#define UART_DMA3_RX_DESCPT 0x3C +#define UART_DMA_CTRL 0x40 +#define UART_DMA_IER 0x44 +#define UART_DMA_ISR 0x48 + +/* */ +#define DMA_TRIGGER (1 << 2) +#define DMA_ENABLE (1 << 0) + +/* UART_DMA_CTRL 0x40 */ +#define SPI_CLK_MASK (0x1f << 16) +#define SPI_CLK_SET(x) ((x) << 16) +#define DMA_RX_TIMEOUT(x) ((x) << 4) +#define DMA_BURST_LEN(x) ((x) << 2) +#define DMA_BURST_MASK (0x3 << 2) +#define BURST_1 0 +#define BURST_2 1 +#define BURST_4 2 +#define BURST_8 3 +#define RXDESC_AUTO_POLLING (1 << 1) +#define TXDESC_AUTO_POLLING (1 << 0) + +/* UART_DMA_IER / UART_DMA_ISR 0x44 0x48 */ + +#define UART_DMA3_RX_INT (1 << 7) +#define UART_DMA2_RX_INT (1 << 6) +#define UART_DMA1_RX_INT (1 << 5) +#define UART_DMA0_RX_INT (1 << 4) +#define UART_DMA3_TX_INT (1 << 3) +#define UART_DMA2_TX_INT (1 << 2) +#define UART_DMA1_TX_INT (1 << 1) +#define UART_DMA0_TX_INT (1 << 0) + + +/* UART DESC #0 Command Register */ +#define DESC0_INT_EN (1 << 9) +#define DESC0_END (1 << 8) +#define DESC0_HW_OWN (1 << 0) + +/* UART DESC #1 Base Address of Data */ +#define DESC1_LEN(x) ((x) << 16) +#define DESC1_NEXT(x) (x) + +/* UART DESC #2 Base Address of Data */ + +/* UART DESC #3 Descriptor Status Register */ +#define DESC3_TIMEOUT_STS (1 << 16) +#define DESC3_GET_LEN(x) ((x) & 0xffff) +#endif diff --git a/arch/arm/plat-aspeed/include/plat/regs-udc11.h b/arch/arm/plat-aspeed/include/plat/regs-udc11.h new file mode 100644 index 000000000000..3b74d63cab8e --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-udc11.h @@ -0,0 +1,98 @@ +/* arch/arm/plat-aspeed/include/mach/regs-udc11.h + * + * Copyright (c) 2012 ASPEED Technology Inc. <ryan_chen@aspeedtech.com> + * http://www.aspeedtech.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ASPEED UDC11 Controller +*/ + +#ifndef __ASM_ARCH_REGS_UDC11_H +#define __ASM_ARCH_REGS_UDC11_H __FILE__ + +#define AST_UDC11_CTRL 0x00 /* Function Control and Status Register */ +#define AST_UDC11_CONF 0x04 /* Function Configuration Setting Register */ +#define AST_UDC11_REST 0x08 /* Endpoint Toggle Bit Reset Register */ +#define AST_UDC11_STS 0x0C /* USB Status Register */ +#define AST_UDC11_IER 0x10 /* Interrupt Control Register */ +#define AST_UDC11_ISR 0x14 /* Interrupt Status Register */ +#define AST_UDC11_EP0_CTRL 0x18 /* Endpoint 0 Control and Status Register */ +#define AST_UDC11_EP1_CTRL 0x1C /* Endpoint 1 Control and Status Register */ +#define AST_UDC11_EP2_CTRL 0x20 /* Endpoint 2 Control and Status Register */ +#define AST_UDC11_EP0_SETUP0 0x24 /* Endpoint 0 Setup/OUT Data Buffer LOW Register */ +#define AST_UDC11_EP0_SETUP1 0x28 /* Endpoint 0 Setup/OUT Data Buffer HIGH Register */ +#define AST_UDC11_EP0_DATA0 0x2C /* Endpoint 0 IN DATA Buffer LOW Register */ +#define AST_UDC11_EP0_DATA1 0x30 /* Endpoint 0 IN DATA Buffer HIGH Register */ +#define AST_UDC11_EP1_DATA0 0x34 /* Endpoint 1 IN DATA Buffer LOW Register */ +#define AST_UDC11_EP1_DATA1 0x38 /* Endpoint 1 IN DATA Buffer HIGH Register */ +#define AST_UDC11_EP2_DATA0 0x3C /* Endpoint 2 IN DATA Buffer LOW Register */ +#define AST_UDC11_EP2_DATA1 0x40 /* Endpoint 2 IN DATA Buffer HIGH Register */ + +/* AST_UDC11_CTRL 0x00 Function Control and Status Register */ +#define UDC11_CTRL_TEST_RESULT (1 << 10) +#define UDC11_CTRL_TEST_STS (1 << 9) +#define UDC11_CTRL_TEST_MODE(x) ((x) << 6) +#define UDC11_CTRL_WKP(x) ((x) << 4) +#define UDC11_CTRL_WKP_EN (1 << 3) +#define UDC11_CTRL_CLK_STOP (1 << 2) +#define UDC11_CTRL_LS_EN (1 << 1) +#define UDC11_CTRL_CONNECT_EN (1) + +/* AST_UDC11_CONF 0x04 Function Configuration Setting Register */ +#define UDC11_CONF_ADDR_MASK (0x3f << 1) +#define UDC11_CONF_SET_ADDR(x) (x << 1) +#define UDC11_CONF_SET_CONF (1) + +/* AST_UDC11_REST 0x08 Endpoint Toggle Bit Reset Register */ +#define UDC11_REST_EP2 (1 << 1) +#define UDC11_REST_EP1 (1) + + +/* AST_UDC11_STS 0x0C USB Status Register */ +#define UDC11_STS_SUSPEND (1 << 31) +#define UDC11_STS_BUS_RST (1 << 30) +#define UDC11_STS_LINE_DP (1 << 29) +#define UDC11_STS_LINE_DN (1 << 28) +#define UDC11_STS_FRAM_NUM_MASK (0x7ff << 16) +#define UDC11_STS_GET_FRAM_NUM(x) ((x >> 16) & 0x7ff) +#define UDC11_STS_LAST_ADDR (0x7f << 4) +#define UDC11_STS_LAST_EP (0xf) + +/* AST_UDC11_IER 0x10 Interrupt Control Register */ +/* AST_UDC11_ISR 0x14 Interrupt Status Register */ +#define UDC11_EP0_OUT (1 << 9) +#define UDC11_EP0_NAK (1 << 8) +#define UDC11_EP2_IN_ACK (1 << 7) +#define UDC11_EP1_IN_ACK (1 << 6) +#define UDC11_EP0_IN_ACK (1 << 5) +#define UDC11_EP0_OUT_ACK (1 << 4) +#define UDC11_EP0_SETUP (1 << 3) +#define UDC11_SUSPEND_RESUME (1 << 2) +#define UDC11_SUSPEND_ENTRY (1 << 1) +#define UDC11_BUS_REST (1) + +/* AST_UDC11_EP0_CTRL 0x18 Endpoint 0 Control and Status Register */ +/* AST_UDC11_EP1_CTRL 0x1C Endpoint 1 Control and Status Register */ +/* AST_UDC11_EP2_CTRL 0x20 Endpoint 2 Control and Status Register */ +#define GET_EP_OUT_RX_LEN(x) ((x & 0xf) >> 8) //only for EP0 +#define GET_EP_IN_TX_LEN(x) ((x & 0xf) >> 4) +#define SET_EP_IN_TX_LEN(x) ((x & 0xf) << 4) +#define EP_OUT_BUFF_RX_RDY (1 << 2) //only for EP0 +#define EP_IN_BUFF_TX_RDY (1 << 1) +#define EP_CTRL_STALL + + + + + + + + + + + + +#endif /* __ASM_ARCH_REGS_UDC11_H */ diff --git a/arch/arm/plat-aspeed/include/plat/regs-video.h b/arch/arm/plat-aspeed/include/plat/regs-video.h new file mode 100644 index 000000000000..ee990750f64f --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-video.h @@ -0,0 +1,348 @@ +/* arch/arm/mach-aspeed/include/mach/regs-video.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * History : + * 1. 2012/08/15 Ryan Chen Create + * +********************************************************************************/ +#ifndef __AST_VIDEO_H +#define __AST_VIDEO_H 1 + +/* + * Register for VIDEO + * */ +#define AST_VIDEO_PROTECT 0x000 /* protection key register */ +#define AST_VIDEO_SEQ_CTRL 0x004 /* Video Sequence Control register */ +#define AST_VIDEO_PASS_CTRL 0x008 /* Video Pass 1 Control register */ + +#define AST_VIDEO_DIRECT_BASE 0x00C /* Video Direct Frame buffer mode control Register VR008[5]=1 */ +#define AST_VIDEO_DIRECT_CTRL 0x010 /* Video Direct Frame buffer mode control Register VR008[5]=1 */ + +#define AST_VIDEO_TIMING_H 0x00C /* Video Timing Generation Setting Register */ +#define AST_VIDEO_TIMING_V 0x010 /* Video Timing Generation Setting Register */ +#define AST_VIDEO_SCAL_FACTOR 0x014 /* Video Scaling Factor Register */ + +#define AST_VIDEO_SCALING0 0x018 /* Video Scaling Filter Parameter Register #0 */ +#define AST_VIDEO_SCALING1 0x01C /* Video Scaling Filter Parameter Register #1 */ +#define AST_VIDEO_SCALING2 0x020 /* Video Scaling Filter Parameter Register #2 */ +#define AST_VIDEO_SCALING3 0x024 /* Video Scaling Filter Parameter Register #3 */ + +#define AST_VIDEO_BCD_CTRL 0x02C /* Video BCD Control Register */ +#define AST_VIDEO_CAPTURE_WIN 0x030 /* Video Capturing Window Setting Register */ +#define AST_VIDEO_COMPRESS_WIN 0x034 /* Video Compression Window Setting Register */ + + +#define AST_VIDEO_COMPRESS_PRO 0x038 /* Video Compression Stream Buffer Processing Offset Register */ +#define AST_VIDEO_COMPRESS_READ 0x03C /* Video Compression Stream Buffer Read Offset Register */ + +#define AST_VIDEO_SOURCE_BUFF0 0x044 /* Video Based Address of Video Source Buffer #1 Register */ +#define AST_VIDEO_SOURCE_SCAN_LINE 0x048 /* Video Scan Line Offset of Video Source Buffer Register */ +#define AST_VIDEO_SOURCE_BUFF1 0x04C /* Video Based Address of Video Source Buffer #2 Register */ +#define AST_VIDEO_BCD_BUFF 0x050 /* Video Base Address of BCD Flag Buffer Register */ +#define AST_VIDEO_STREAM_BUFF 0x054 /* Video Base Address of Compressed Video Stream Buffer Register */ +#define AST_VIDEO_STREAM_SIZE 0x058 /* Video Stream Buffer Size Register */ + + +#define AST_VIDEO_COMPRESS_CTRL 0x060 /* Video Compression Control Register */ + + +#define AST_VIDEO_DEF_HEADER 0x080 /* Video User Defined Header Parameter Setting with Compression */ + +#define AST_VIDEO_H_DETECT_STS 0x090 /* Video Source Left/Right Edge Detection Read Back Register */ +#define AST_VIDEO_V_DETECT_STS 0x094 /* Video Source Top/Bottom Edge Detection Read Back Register */ + + +#define AST_VIDEO_MODE_DET_STS 0x098 /* Video Mode Detection Status Read Back Register */ + +#define AST_VIDEO_MODE_DET1 0x0A4 /* Video Mode Detection Control Register 1*/ + + +#define AST_VIDEO_CTRL 0x300 /* Video Control Register */ +#define AST_VIDEO_INT_EN 0x304 /* Video interrupt Enable */ +#define AST_VIDEO_INT_STS 0x308 /* Video interrupt status */ +#define AST_VIDEO_MODE_DETECT 0x30C /* Video Mode Detection Parameter Register */ + +#define AST_VIDEO_CRC1 0x320 /* Primary CRC Parameter Register */ +#define AST_VIDEO_CRC2 0x324 /* Second CRC Parameter Register */ +#define AST_VIDEO_DATA_TRUNCA 0x328 /* Video Data Truncation Register */ + + +#define AST_VIDEO_SCRATCH_340 0x340 /* Video Scratch Remap Read Back */ +#define AST_VIDEO_SCRATCH_344 0x344 /* Video Scratch Remap Read Back */ +#define AST_VIDEO_SCRATCH_348 0x348 /* Video Scratch Remap Read Back */ +#define AST_VIDEO_SCRATCH_34C 0x34C /* Video Scratch Remap Read Back */ +#define AST_VIDEO_SCRATCH_350 0x350 /* Video Scratch Remap Read Back */ +#define AST_VIDEO_SCRATCH_354 0x354 /* Video Scratch Remap Read Back */ +#define AST_VIDEO_SCRATCH_358 0x358 /* Video Scratch Remap Read Back */ +#define AST_VIDEO_SCRATCH_35C 0x35C /* Video Scratch Remap Read Back */ +#define AST_VIDEO_SCRATCH_360 0x360 /* Video Scratch Remap Read Back */ +#define AST_VIDEO_SCRATCH_364 0x364 /* Video Scratch Remap Read Back */ + + +#define AST_VIDEO_ENCRYPT_SRAM 0x400 /* Video RC4/AES128 Encryption Key Register #0 ~ #63 */ + +///////////////////////////////////////////////////////////////////////////// + +/* AST_VIDEO_PROTECT: 0x000 - protection key register */ +#define VIDEO_PROTECT_UNLOCK 0x1A038AA8 + +/* AST_VIDEO_SEQ_CTRL 0x004 Video Sequence Control register */ +#define VIDEO_HALT_ENG_STS (1 << 21) +#define VIDEO_COMPRESS_BUSY (1 << 18) +#define VIDEO_CAPTURE_BUSY (1 << 16) +#define VIDEO_HALT_ENG_TRIGGER (1 << 12) +#define VIDEO_COMPRESS_FORMAT_MASK (3 << 10) +#define VIDEO_COMPRESS_FORMAT(x) (x << 10) // 0 YUV444 +#define YUV420 1 +#define VIDEO_COMPRESS_JPEG_CPB (1 << 8) +//if bit 0 : 1 +#define VIDEO_INPUT_MODE_CHG_WDT (1 << 7) +#define VIDEO_INSERT_FULL_COMPRESS (1 << 6) +#define VIDEO_AUTO_COMPRESS (1 << 5) +#define VIDEO_COMPRESS_TRIGGER (1 << 4) +#define VIDEO_CAPTURE_MULTI_FRAME (1 << 3) +#define VIDEO_COMPRESS_FORCE_IDLE (1 << 2) +#define VIDEO_CAPTURE_TIRGGER (1 << 1) +#define VIDEO_DETECT_TRIGGER (1 << 0) + + +#define VIDEO_HALT_ENG_RB (1 << 21) +#define VIDEO_HALT_ENG_RB (1 << 21) +#define VIDEO_HALT_ENG_RB (1 << 21) +#define VIDEO_HALT_ENG_RB (1 << 21) +#define VIDEO_HALT_ENG_RB (1 << 21) +#define VIDEO_HALT_ENG_RB (1 << 21) + + +/* AST_VIDEO_PASS_CTRL 0x008 Video Pass1 Control register */ +//x * source frame rate / 60 +#define VIDEO_FRAME_RATE_CTRL(x) (x << 16) +#define VIDEO_HSYNC_POLARITY_CTRL (1 << 15) +#define VIDEO_INTERLANCE_MODE (1 << 14) +#define VIDEO_DUAL_EDGE_MODE (1 << 13) //0 : Single edage +#define VIDEO_18BIT_SINGLE_EDGE (1 << 12) //0: 24bits +#define VIDEO_DVO_INPUT_DELAY_MASK (7 << 9) +#define VIDEO_DVO_INPUT_DELAY(x) (x << 9) //0 : no delay , 1: 1ns, 2: 2ns, 3:3ns +// if biit 5 : 0 +#define VIDEO_HW_CURSOR_DIS (1 << 8) +// if biit 5 : 1 +#define VIDEO_AUTO_FATCH (1 << 8) +#define VIDEO_CAPTURE_MODE(x) (x << 6) +#define YUV_MODE 1 +#define RGB_MODE 2 +#define GRAY_MODE 3 +#define VIDEO_DIRT_FATCH (1 << 5) +// if biit 5 : 0 +#define VIDEO_INTERNAL_DE (1 << 4) +#define VIDEO_EXT_ADC_ATTRIBUTE (1 << 3) + +// if biit 5 : 1 +#define VIDEO_16BPP_MODE (1 << 4) +#define VIDEO_16BPP_MODE_555 (1 << 3) //0:565 + +#define VIDEO_FROM_EXT_SOURCE (1 << 2) +#define VIDEO_SO_VSYNC_POLARITY (1 << 1) +#define VIDEO_SO_HSYNC_POLARITY (1 << 0) + +/* AST_VIDEO_TIMING_H 0x00C Video Timing Generation Setting Register */ +#define VIDEO_HSYNC_PIXEL_FIRST_SET(x) ((x) << 16) +#define VIDEO_HSYNC_PIXEL_LAST_SET(x) (x) + + +/* AST_VIDEO_DIRECT_CTRL 0x010 Video Direct Frame buffer mode control Register VR008[5]=1 */ +#define VIDEO_FETCH_TIMING(x) ((x) << 16) +#define VIDEO_FETCH_LINE_OFFSET(x) (x) + +/* AST_VIDEO_TIMING_V 0x010 Video Timing Generation Setting Register */ +#define VIDEO_VSYNC_PIXEL_FIRST_SET(x) ((x) << 16) +#define VIDEO_VSYNC_PIXEL_LAST_SET(x) (x) + + +/* AST_VIDEO_SCAL_FACTOR 0x014 Video Scaling Factor Register */ +#define VIDEO_V_SCAL_FACTOR(x) (((x) & 0xffff) << 16) +#define VIDEO_H_SCAL_FACTOR(x) (x & 0xffff) + + +/* AST_VIDEO_SCALING0 0x018 Video Scaling Filter Parameter Register #0 */ +/* AST_VIDEO_SCALING1 0x01C Video Scaling Filter Parameter Register #1 */ +/* AST_VIDEO_SCALING2 0x020 Video Scaling Filter Parameter Register #2 */ +/* AST_VIDEO_SCALING3 0x024 Video Scaling Filter Parameter Register #3 */ + + +/* AST_VIDEO_BCD_CTRL 0x02C Video BCD Control Register */ +#define VIDEO_ABCD_TOL(x) (x << 24) +#define VIDEO_BCD_TOL(x) (x << 16) +#define VIDEO_ABCD_CHG_EN (1 << 1) +#define VIDEO_BCD_CHG_EN (1 << 0) + + + +/* AST_VIDEO_CAPTURE_WIN 0x030 Video Capturing Window Setting Register */ +#define VIDEO_CAPTURE_V(x) (x & 0x7ff) +#define VIDEO_CAPTURE_H(x) ((x & 0x7ff) << 16) + +/* AST_VIDEO_COMPRESS_WIN 0x034 Video Compression Window Setting Register */ +#define VIDEO_COMPRESS_V(x) (x & 0x7ff) +#define VIDEO_COMPRESS_H(x) ((x & 0x7ff) << 16) + + + +/* AST_VIDEO_RESET :0x03c - system reset control register */ + +/* AST_VIDEO_STREAM_SIZE 0x058 Video Stream Buffer Size Register */ +#define VIDEO_STREAM_PKT_N(x) (x << 3) +#define STREAM_4_PKTS 0 +#define STREAM_8_PKTS 1 +#define STREAM_16_PKTS 2 +#define STREAM_32_PKTS 3 +#define STREAM_64_PKTS 4 +#define STREAM_128_PKTS 5 + +#define VIDEO_STREAM_PKT_SIZE(x) (x) +#define STREAM_1KB 0 +#define STREAM_2KB 1 +#define STREAM_4KB 2 +#define STREAM_8KB 3 +#define STREAM_16KB 4 +#define STREAM_32KB 5 +#define STREAM_64KB 6 +#define STREAM_128KB 7 + + + + + + + + +/* AST_VIDEO_COMPRESS_CTRL 0x060 Video Compression Control Register */ +#define VIDEO_HQ_DCT_LUM(x) ((x) << 27) +#define VIDEO_HQ_DCT_CHROM(x) ((x) << 22) +#define VIDEO_DCT_HUFFMAN_ENCODE(x) ((x) << 20) +#define VIDEO_DCT_RESET (1 << 17) +#define VIDEO_HQ_ENABLE (1 << 16) +#define VIDEO_DCT_LUM(x) ((x) << 11) +#define VIDEO_DCT_CHROM(x) ((x) << 6) +#define VIDEO_RC4_ENABLE (1 << 5) +#define VIDEO_COMPRESS_QUANTIZ_MODE (1 << 2) +#define VIDEO_4COLOR_VQ_ENCODE (1 << 1) +#define VIDEO_DCT_ONLY_ENCODE (1 << 0) + + +/* AST_VIDEO_H_DETECT_STS 0x090 Video Source Left/Right Edge Detection Read Back Register */ +#define VIDEO_DET_INTERLANCE_MODE (1 << 31) +#define VIDEO_GET_HSYNC_RIGHT(x) ((x & 0x0FFF0000) >> 16) +#define VIDEO_GET_HSYNC_LEFT(x) (x & 0xFFF) +#define VIDEO_NO_DISPLAY_CLOCK_DET (1 << 15) +#define VIDEO_NO_ACT_DISPLAY_DET (1 << 14) +#define VIDEO_NO_HSYNC_DET (1 << 13) +#define VIDEO_NO_VSYNC_DET (1 << 12) + +/* AST_VIDEO_V_DETECT_STS 0x094 Video Source Top/Bottom Edge Detection Read Back Register */ +#define VIDEO_GET_VSYNC_BOTTOM(x) ((x & 0x0FFF0000) >> 16) +#define VIDEO_GET_VSYNC_TOP(x) (x & 0xFFF) + + +/* AST_VIDEO_MODE_DET_STS 0x098 Video Mode Detection Status Read Back Register */ +#define VIDEO_DET_HSYNC_RDY (1 << 31) +#define VIDEO_DET_VSYNC_RDY (1 << 30) +#define VIDEO_DET_HSYNC_POLAR (1 << 29) +#define VIDEO_DET_VSYNC_POLAR (1 << 28) +#define VIDEO_GET_VER_SCAN_LINE(x) ((x >> 16) & 0xfff) +#define VIDEO_OUT_SYNC (1 << 15) +#define VIDEO_DET_VER_STABLE (1 << 14) +#define VIDEO_DET_HOR_STABLE (1 << 13) +#define VIDEO_DET_FROM_ADC (1 << 12) +#define VIDEO_DET_HOR_PERIOD(x) (x & 0xfff) + + +/* AST_VIDEO_MODE_DET1 0x0A4 Video Mode Detection Control Register 1*/ +#define VIDEO_DET_HSYNC_DELAY_MASK (0xff << 16) +#define VIDEO_DET_LONG_H_STABLE_EN (1 << 29) + + +/* AST_VIDEO_CTRL 0x300 Video Control Register */ +#define VIDEO_CTRL_CRYPTO(x) (x << 17) +#define VIDEO_CTRL_CRYPTO_MASK (1 << 17) +#define CRYPTO_RC4_MODE 0 +#define CRYPTO_AES_MODE 1 +#define VIDEO_CTRL_CRYPTO_FAST (1 << 16) +//15 reserved +#define VIDEO_CTRL_RC4_VC (1 << 14) +#define VIDEO_CTRL_CAPTURE_MASK (3 << 12) +#define VIDEO_CTRL_CAPTURE_MODE(x) (x << 12) +#define VIDEO_CTRL_COMPRESS_MASK (3 << 10) +#define VIDEO_CTRL_COMPRESS_MODE(x) (x << 10) +#define MODE_32BPP_YUV444 0 +#define MODE_24BPP_YUV444 1 +#define MODE_16BPP_YUV422 3 + +#define VIDEO_CTRL_RC4_TEST_MODE (1 << 9) +#define VIDEO_CTRL_RC4_RST (1 << 8) +#define VIDEO_CTRL_RC4_VIDEO_M_SEL (1 << 7) //video management +#define VIDEO_CTRL_RC4_VIDEO_2_SEL (1 << 6) // Video 2 + +#define VIDEO_CTRL_DWN_SCALING_MASK (0x3 << 4) +#define VIDEO_CTRL_DWN_SCALING(x) (x << 4) +#define DWN_V1 0x1 +#define DWN_V2 0x2 +#define DWN_VM 0x3 + + + +#define VIDEO_CTRL_VSYNC_DELAY_MASK (3 << 2) +#define VIDEO_CTRL_VSYNC_DELAY(x) (x << 2) +#define NO_DELAY 0 +#define DELAY_DIV12_HSYNC 1 +#define AUTO_DELAY 2 + + +/* AST_VIDEO_INT_EN 0x304 Video interrupt Enable */ +/* AST_VIDEO_INT_STS 0x308 Video interrupt status */ +#define VIDEO_FRAME_COMPLETE (1 << 5) +#define VIDEO_MODE_DETECT_RDY (1 << 4) +#define VIDEO_COMPRESS_COMPLETE (1 << 3) +#define VIDEO_COMPRESS_PKT_COMPLETE (1 << 2) +#define VIDEO_CAPTURE_COMPLETE (1 << 1) +#define VIDEO_MODE_DETECT_WDT (1 << 0) + +/* AST_VIDEO_MODE_DETECT 0x30C Video Mode Detection Parameter Register */ +#define VIDEO_MODE_HOR_TOLER(x) (x << 28) +#define VIDEO_MODE_VER_TOLER(x) (x << 24) +#define VIDEO_MODE_HOR_STABLE(x) (x << 20) +#define VIDEO_MODE_VER_STABLE(x) (x << 16) +#define VIDEO_MODE_EDG_THROD(x) (x << 8) + +#define MODEDETECTION_VERTICAL_STABLE_MAXIMUM 0x6 +#define MODEDETECTION_HORIZONTAL_STABLE_MAXIMUM 0x6 +#define MODEDETECTION_VERTICAL_STABLE_THRESHOLD 0x2 +#define MODEDETECTION_HORIZONTAL_STABLE_THRESHOLD 0x2 + +/* AST_VIDEO_SCRATCH_34C 0x34C Video Scratch Remap Read Back */ +#define SCRATCH_VGA_GET_REFLASH_RATE(x) ((x >> 8) & 0xf) +#define SCRATCH_VGA_GET_COLOR_MODE(x) ((x >> 4) & 0xf) + +/* AST_VIDEO_SCRATCH_350 0x350 Video Scratch Remap Read Back */ +#define SCRATCH_VGA_GET_MODE_HEADER(x) ((x >> 8) & 0xff) +#define SCRATCH_VGA_GET_NEW_COLOR_MODE(x) ((x >> 16) & 0xff) +#define SCRATCH_VGA_GET_NEW_PIXEL_CLK(x) ((x >> 24) & 0xff) + + +/* AST_VIDEO_SCRATCH_35C 0x35C Video Scratch Remap Read Back */ +#define SCRATCH_VGA_PWR_STS_HSYNC (1 << 31) +#define SCRATCH_VGA_PWR_STS_VSYNC (1 << 30) +#define SCRATCH_VGA_ATTRIBTE_INDEX_BIT5 (1 << 29) +#define SCRATCH_VGA_MASK_REG (1 << 28) +#define SCRATCH_VGA_CRT_RST (1 << 27) +#define SCRATCH_VGA_SCREEN_OFF (1 << 26) +#define SCRATCH_VGA_RESET (1 << 25) +#define SCRATCH_VGA_ENABLE (1 << 24) + + +#endif + diff --git a/arch/arm/plat-aspeed/include/plat/regs-vuart.h b/arch/arm/plat-aspeed/include/plat/regs-vuart.h new file mode 100644 index 000000000000..b4bb88a0912c --- /dev/null +++ b/arch/arm/plat-aspeed/include/plat/regs-vuart.h @@ -0,0 +1,39 @@ +/* arch/arm/plat-aspeed/include/mach/regs-iic.h + * + * Copyright (c) 2012 ASPEED Technology Inc. <ryan_chen@aspeedtech.com> + * http://www.aspeedtech.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ASPEED VUART Controller +*/ + +#ifndef __AST_VUART_H_ +#define __AST_VUART_H_ + +#define AST_VUART_CTRLA 0x20 +#define AST_VUART_CTRLB 0x24 +#define AST_VUART_ADDRL 0x28 +#define AST_VUART_ADDRH 0x2C +#define AST_VUART_CTRLE 0x30 +#define AST_VUART_CTRLF 0x34 +#define AST_VUART_CTRLG 0x38 +#define AST_VUART_CTRLH 0x3C + + + +/* AST_VUART_CTRLA 0x20 */ +#define VUART_ENABLE (1 << 0) +#define VUART_SIRQ_POLARITY (1 << 1) +#define VUART_DISABLE_H_TX_DISCARD (1 << 5) + + +/* AST_VUART_CTRLB 0x24 */ +#define SET_SIRQ_NUM(x) (x << 4) + + + + +#endif diff --git a/arch/arm/plat-aspeed/irq.c b/arch/arm/plat-aspeed/irq.c new file mode 100644 index 000000000000..b1183591ae67 --- /dev/null +++ b/arch/arm/plat-aspeed/irq.c @@ -0,0 +1,136 @@ +/* + * linux/arch/arm/plat-aspeed/irq.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/init.h> +#include <linux/stddef.h> +#include <linux/list.h> +#include <linux/timer.h> + +#include <linux/device.h> +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> +#include <linux/sysdev.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <asm/system.h> +#include <asm/irq.h> +#include <asm/io.h> +#include <asm/mach/irq.h> +#include <mach/hardware.h> + +#include <plat/regs-intr.h> + +static void ast_mask_irq(unsigned int irq) +{ + int i=0; + u32 regVal; + u8 timer; + +#ifdef IRQ_TIMER7 + if(((irq >= IRQ_TIMER0) && (irq <= IRQ_TIMER2)) || ((i >= IRQ_TIMER3) && (i <= IRQ_TIMER7))) + timer = 1; + +#else + if((irq >= IRQ_TIMER0) && (irq <= IRQ_TIMER2)) + timer = 1; +#endif + + if (irq > 32) { + i=1; + irq = irq - 32; + } else + i=0; + + regVal = readl(AST_INTR_DIS(i)); + regVal |= (1 << irq); + writel(regVal, AST_INTR_DIS(i)); + + /* + * clear the interrupt + */ + if(timer) + IRQ_EDGE_CLEAR(i,irq); + +} + +static void ast_unmask_irq(unsigned int irq) +{ + int i; + u32 regVal; + + if (irq > 32) { + i=1; + irq = irq - 32; + } else + i=0; + + regVal = readl(AST_INTR_EN(i)); + regVal |= (1 << irq); + writel(regVal, AST_INTR_EN(i)); +} + +static struct irq_chip ast_irq_chip = { + .name = "ast_irq", + .ack = ast_mask_irq, + .mask = ast_mask_irq, + .unmask = ast_unmask_irq, +}; + +void __init ast_init_irq(void) +{ + unsigned int i; + + /* VIC1 */ + writel(0, AST_INTR_SEL(0)); + writel(0, AST_INTR_EN(0)); + writel(0xFFFFFFFF, AST_INTR_DIS(0)); + writel(0xFFFFFFFF, AST_INTR_EDGE_CLR(0)); + +#if defined(NEW_VIC) + writel(0, AST_INTR_SEL(1)); + writel(0, AST_INTR_EN(1)); + writel(0xFFFFFFFF, AST_INTR_DIS(1)); + writel(0xFFFFFFFF, AST_INTR_EDGE_CLR(1)); +#endif + + //TOTAL IRQ NUM = + for (i = 0; i < AST_VIC_NUM; i++) + { + if(i<32) { + if((i >= IRQ_TIMER0) && (i <= IRQ_TIMER2)) //Timer0/1/2 + IRQ_SET_RISING_EDGE(0,i); + else { + IRQ_SET_HIGH_LEVEL(0,i); + IRQ_SET_LEVEL_TRIGGER(0,i); + } +#ifdef IRQ_TIMER7 + } else { + if((i >= IRQ_TIMER3) && (i <= IRQ_TIMER7)) //Timer3/4/5/6/7 + IRQ_SET_RISING_EDGE(0,i-32); + else { + IRQ_SET_HIGH_LEVEL(1,i-32); + IRQ_SET_LEVEL_TRIGGER(1,i-32); + } +#endif + } + + set_irq_chip(i, &ast_irq_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + +} diff --git a/arch/arm/plat-aspeed/timer.c b/arch/arm/plat-aspeed/timer.c new file mode 100644 index 000000000000..079d958c6e3f --- /dev/null +++ b/arch/arm/plat-aspeed/timer.c @@ -0,0 +1,137 @@ +/* + * timer.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/device.h> +#include <linux/spinlock.h> +#include <linux/interrupt.h> +#include <linux/sched.h> + +#include <linux/irq.h> +#include <asm/system.h> +#include <asm/io.h> +#include <mach/hardware.h> +#include <mach/irqs.h> +#include <mach/time.h> +#include <plat/ast-scu.h> + +#define ASPEED_TIMER0_VA_BASE (IO_ADDRESS(AST_TIMER_BASE)+ASPEED_TIMER0_OFFSET) +#define ASPEED_TIMER1_VA_BASE (IO_ADDRESS(AST_TIMER_BASE)+ASPEED_TIMER1_OFFSET) +#define ASPEED_TIMER2_VA_BASE (IO_ADDRESS(AST_TIMER_BASE)+ASPEED_TIMER2_OFFSET) +#define ASPEED_TIMERC_VA_BASE (IO_ADDRESS(AST_TIMER_BASE)+ASPEED_TIMERRC_OFFSET) + +/* + * Returns number of ms since last clock interrupt. Note that interrupts + * will have been disabled by do_gettimeoffset() + */ +static unsigned long ast_gettimeoffset(void) +{ + volatile TimerStruct_t *timer0 = (TimerStruct_t *) ASPEED_TIMER0_VA_BASE; + unsigned long ticks1, ticks2;//, status; + + /* + * Get the current number of ticks. Note that there is a race + * condition between us reading the timer and checking for + * an interrupt. We get around this by ensuring that the + * counter has not reloaded between our two reads. + */ + ticks2 = timer0->TimerValue; + do { + ticks1 = ticks2; +// status = readl(AST_RAW_STS(0));// __raw_readl(IO_ADDRESS(ASPEED_VIC_BASE) + ASPEED_VIC_RAW_STATUS_OFFSET); + ticks2 = timer0->TimerValue; + } while (ticks2 > ticks1); + + /* + * Number of ticks since last interrupt. + */ + ticks1 = TIMER_RELOAD - ticks2; + + /* + * Interrupt pending? If so, we've reloaded once already. + */ +// if (status & (1 << IRQ_TIMER0)) +// ticks1 += TIMER_RELOAD; + + /* + * Convert the ticks to usecs + */ + return TICKS2USECS(ticks1); +} + + +/* + * IRQ handler for the timer + */ +static irqreturn_t +ast_timer_interrupt(int irq, void *dev_id) +{ + +// write_seqlock(&xtime_lock); + + /* + * clear the interrupt in Irq.c + */ +// IRQ_EDGE_CLEAR(0,IRQ_TIMER0); + + timer_tick(); + + +// write_sequnlock(&xtime_lock); + + return IRQ_HANDLED; +} + +static struct irqaction ast_timer_irq = { + .name = "ast timer", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = ast_timer_interrupt, +}; + +/* + * Set up timer interrupt, and return the current time in seconds. + */ +static void __init ast_setup_timer(void) +{ + volatile TimerStruct_t *timer0 = (volatile TimerStruct_t *) ASPEED_TIMER0_VA_BASE; + volatile __u32 *timerc = (volatile __u32*) ASPEED_TIMERC_VA_BASE; + + /* + * Initialise to a known state (all timers off) + */ + *timerc = 0; + + timer0->TimerLoad = TIMER_RELOAD - 1; + timer0->TimerValue = TIMER_RELOAD - 1; + *timerc = TIMER0_ENABLE | TIMER0_RefExt; + + /* + * Make irqs happen for the system timer + */ + ast_scu_show_system_info(); + + setup_irq(IRQ_TIMER0, &ast_timer_irq); + +} + +struct sys_timer ast_timer = { + .init = ast_setup_timer, +// .offset = ast_gettimeoffset, +}; diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 43aa2020f85c..d2bf53959921 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -1899,3 +1899,4 @@ rut100 MACH_RUT100 RUT100 1908 asusp535 MACH_ASUSP535 ASUSP535 1909 htcraphael MACH_HTCRAPHAEL HTCRAPHAEL 1910 sygdg1 MACH_SYGDG1 SYGDG1 1911 +aspeed MACH_ASPEED ASPEED 8888 |