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| author | Todd Poynor <tpoynor@mvista.com> | 2005-07-12 03:34:39 +0100 |
|---|---|---|
| committer | Thomas Gleixner <tglx@mtd.linutronix.de> | 2005-07-13 00:58:44 +0200 |
| commit | a98a5d04f400ad112e59cadd739dbabf89417e60 (patch) | |
| tree | 5eeb7f45c0090de40c7523e2b9dfd5e86b22169e /include/asm-ppc64/processor.h | |
| parent | 751382dd5cb2702368d281a50b55c2d6c4e8fbfc (diff) | |
| parent | 7ac3db59fd4410405ce55e2a25c397aec440d8da (diff) | |
| download | linux-stable-a98a5d04f400ad112e59cadd739dbabf89417e60.tar.gz | |
Merge with rsync://fileserver/linux
Diffstat (limited to 'include/asm-ppc64/processor.h')
| -rw-r--r-- | include/asm-ppc64/processor.h | 26 |
1 files changed, 20 insertions, 6 deletions
diff --git a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h index af28aa55d8c1..352306cfb579 100644 --- a/include/asm-ppc64/processor.h +++ b/include/asm-ppc64/processor.h @@ -20,6 +20,7 @@ #include <asm/ptrace.h> #include <asm/types.h> #include <asm/systemcfg.h> +#include <asm/cputable.h> /* Machine State Register (MSR) Fields */ #define MSR_SF_LG 63 /* Enable 64 bit mode */ @@ -501,24 +502,37 @@ static inline void ppc64_runlatch_on(void) { unsigned long ctrl; - ctrl = mfspr(SPRN_CTRLF); - ctrl |= CTRL_RUNLATCH; - mtspr(SPRN_CTRLT, ctrl); + if (cpu_has_feature(CPU_FTR_CTRL)) { + ctrl = mfspr(SPRN_CTRLF); + ctrl |= CTRL_RUNLATCH; + mtspr(SPRN_CTRLT, ctrl); + } } static inline void ppc64_runlatch_off(void) { unsigned long ctrl; - ctrl = mfspr(SPRN_CTRLF); - ctrl &= ~CTRL_RUNLATCH; - mtspr(SPRN_CTRLT, ctrl); + if (cpu_has_feature(CPU_FTR_CTRL)) { + ctrl = mfspr(SPRN_CTRLF); + ctrl &= ~CTRL_RUNLATCH; + mtspr(SPRN_CTRLT, ctrl); + } } #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ +#ifdef __KERNEL__ +#define RUNLATCH_ON(REG) \ +BEGIN_FTR_SECTION \ + mfspr (REG),SPRN_CTRLF; \ + ori (REG),(REG),CTRL_RUNLATCH; \ + mtspr SPRN_CTRLT,(REG); \ +END_FTR_SECTION_IFSET(CPU_FTR_CTRL) +#endif + /* * Number of entries in the SLB. If this ever changes we should handle * it with a use a cpu feature fixup. |