diff options
Diffstat (limited to 'src/gen9_vme.c')
| -rw-r--r-- | src/gen9_vme.c | 183 |
1 files changed, 179 insertions, 4 deletions
diff --git a/src/gen9_vme.c b/src/gen9_vme.c index 8dde7e71..d7262cd1 100644 --- a/src/gen9_vme.c +++ b/src/gen9_vme.c @@ -40,6 +40,9 @@ #include "i965_encoder.h" #include "gen6_vme.h" #include "gen6_mfc.h" +#include "gen9_mfc.h" +#include "intel_media.h" +#include "gen9_vp9_encapi.h" #ifdef SURFACE_STATE_PADDED_SIZE #undef SURFACE_STATE_PADDED_SIZE @@ -210,7 +213,8 @@ gen9_vme_media_source_surface_state(VADriverContextP ctx, &vme_context->gpe_context, obj_surface, BINDING_TABLE_OFFSET(index), - SURFACE_STATE_OFFSET(index)); + SURFACE_STATE_OFFSET(index), + 0); } static void @@ -225,7 +229,8 @@ gen9_vme_media_chroma_source_surface_state(VADriverContextP ctx, &vme_context->gpe_context, obj_surface, BINDING_TABLE_OFFSET(index), - SURFACE_STATE_OFFSET(index)); + SURFACE_STATE_OFFSET(index), + 0); } static void @@ -332,6 +337,7 @@ gen9_vme_surface_setup(VADriverContextP ctx, /*Setup surfaces state*/ /* current picture for encoding */ obj_surface = encode_state->input_yuv_object; + assert(obj_surface); gen9_vme_source_surface_state(ctx, 0, obj_surface, encoder_context); gen9_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context); gen9_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context); @@ -617,7 +623,7 @@ gen9_vme_fill_vme_batchbuffer(VADriverContextP ctx, if (encoder_context->rate_control_mode == VA_RC_CQP) qp = pic_param->pic_init_qp + slice_param->slice_qp_delta; else - qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY; + qp = mfc_context->brc.qp_prime_y[encoder_context->layer.curr_frame_layer_id][slice_type]; dri_bo_map(vme_context->vme_batchbuffer.bo, 1); command_ptr = vme_context->vme_batchbuffer.bo->virtual; @@ -1416,10 +1422,19 @@ gen9_vme_hevc_surface_setup(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct object_surface *obj_surface; + VAEncSequenceParameterBufferHEVC *pSequenceParameter = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer; + GenHevcSurface *hevc_encoder_surface = NULL; /*Setup surfaces state*/ /* current picture for encoding */ obj_surface = encode_state->input_yuv_object; + + if((pSequenceParameter->seq_fields.bits.bit_depth_luma_minus8 > 0) + || (pSequenceParameter->seq_fields.bits.bit_depth_chroma_minus8 > 0)) { + hevc_encoder_surface = (GenHevcSurface *) obj_surface->private_data; + assert(hevc_encoder_surface); + obj_surface = hevc_encoder_surface->nv12_surface_obj; + } gen9_vme_source_surface_state(ctx, 0, obj_surface, encoder_context); gen9_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context); gen9_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context); @@ -1733,6 +1748,151 @@ static void gen9_vme_hevc_pipeline_programing(VADriverContextP ctx, intel_batchbuffer_end_atomic(batch); } +static VAStatus gen9_intel_init_hevc_surface(VADriverContextP ctx, + struct intel_encoder_context *encoder_context, + struct encode_state *encode_state, + struct object_surface *input_obj_surface) +{ + struct i965_driver_data *i965 = i965_driver_data(ctx); + struct gen9_hcpe_context *mfc_context = encoder_context->mfc_context; + VAEncSequenceParameterBufferHEVC *pSequenceParameter = (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer; + GenHevcSurface *hevc_encoder_surface; + struct i965_surface src_surface, dst_surface; + struct object_surface *obj_surface; + VARectangle rect; + VAStatus status; + + uint32_t size; + + obj_surface = input_obj_surface; + assert(obj_surface && obj_surface->bo); + + if (obj_surface->private_data == NULL) { + + if (mfc_context->pic_size.ctb_size == 16) + size = ((pSequenceParameter->pic_width_in_luma_samples + 63) >> 6) * + ((pSequenceParameter->pic_height_in_luma_samples + 15) >> 4); + else + size = ((pSequenceParameter->pic_width_in_luma_samples + 31) >> 5) * + ((pSequenceParameter->pic_height_in_luma_samples + 31) >> 5); + size <<= 6; /* in unit of 64bytes */ + + hevc_encoder_surface = calloc(sizeof(GenHevcSurface), 1); + + assert(hevc_encoder_surface); + hevc_encoder_surface->motion_vector_temporal_bo = + dri_bo_alloc(i965->intel.bufmgr, + "motion vector temporal buffer", + size, + 0x1000); + assert(hevc_encoder_surface->motion_vector_temporal_bo); + + hevc_encoder_surface->ctx = ctx; + hevc_encoder_surface->nv12_surface_obj = NULL; + hevc_encoder_surface->nv12_surface_id = VA_INVALID_SURFACE; + hevc_encoder_surface->has_p010_to_nv12_done = 0; + + obj_surface->private_data = (void *)hevc_encoder_surface; + obj_surface->free_private_data = (void *)gen_free_hevc_surface; + } + + hevc_encoder_surface = (GenHevcSurface *) obj_surface->private_data; + + if(!hevc_encoder_surface->has_p010_to_nv12_done && obj_surface->fourcc == VA_FOURCC_P010) + { + // convert input + rect.x = 0; + rect.y = 0; + rect.width = obj_surface->orig_width; + rect.height = obj_surface->orig_height; + + src_surface.base = (struct object_base *)obj_surface; + src_surface.type = I965_SURFACE_TYPE_SURFACE; + src_surface.flags = I965_SURFACE_FLAG_FRAME; + + if(SURFACE(hevc_encoder_surface->nv12_surface_id) == NULL) + { + status = i965_CreateSurfaces(ctx, + obj_surface->orig_width, + obj_surface->orig_height, + VA_RT_FORMAT_YUV420, + 1, + &hevc_encoder_surface->nv12_surface_id); + assert(status == VA_STATUS_SUCCESS); + + if (status != VA_STATUS_SUCCESS) + return status; + } + + obj_surface = SURFACE(hevc_encoder_surface->nv12_surface_id); + hevc_encoder_surface->nv12_surface_obj = obj_surface; + assert(obj_surface); + i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420); + + dst_surface.base = (struct object_base *)obj_surface; + dst_surface.type = I965_SURFACE_TYPE_SURFACE; + dst_surface.flags = I965_SURFACE_FLAG_FRAME; + + status = i965_image_processing(ctx, + &src_surface, + &rect, + &dst_surface, + &rect); + assert(status == VA_STATUS_SUCCESS); + hevc_encoder_surface->has_p010_to_nv12_done = 1; + i965_SyncSurface(ctx,hevc_encoder_surface->nv12_surface_id); + } + return VA_STATUS_SUCCESS; +} + +static VAStatus gen9_intel_hevc_input_check(VADriverContextP ctx, + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) +{ + struct i965_driver_data *i965 = i965_driver_data(ctx); + struct gen9_hcpe_context *mfc_context = encoder_context->mfc_context; + struct object_surface *obj_surface; + GenHevcSurface *hevc_encoder_surface = NULL; + int i; + int fourcc; + + obj_surface = SURFACE(encode_state->current_render_target); + assert(obj_surface && obj_surface->bo); + hevc_encoder_surface = (GenHevcSurface *) obj_surface->private_data; + if(hevc_encoder_surface) + hevc_encoder_surface->has_p010_to_nv12_done = 0; + gen9_intel_init_hevc_surface(ctx,encoder_context,encode_state,obj_surface); + + fourcc = obj_surface->fourcc; + /* Setup current frame and current direct mv buffer*/ + obj_surface = encode_state->reconstructed_object; + if(fourcc == VA_FOURCC_P010) + i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_P010, SUBSAMPLE_YUV420); + else + i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420); + hevc_encoder_surface = NULL; + hevc_encoder_surface = (GenHevcSurface *) obj_surface->private_data; + if(hevc_encoder_surface) + hevc_encoder_surface->has_p010_to_nv12_done = 1; + gen9_intel_init_hevc_surface(ctx,encoder_context,encode_state,obj_surface); + + /* Setup reference frames and direct mv buffers*/ + for (i = 0; i < MAX_HCP_REFERENCE_SURFACES; i++) { + obj_surface = encode_state->reference_objects[i]; + + if (obj_surface && obj_surface->bo) { + mfc_context->reference_surfaces[i].bo = obj_surface->bo; + dri_bo_reference(obj_surface->bo); + + gen9_intel_init_hevc_surface(ctx,encoder_context,encode_state,obj_surface); + } else { + break; + } + } + + return VA_STATUS_SUCCESS; +} + static VAStatus gen9_vme_hevc_prepare(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) @@ -1749,6 +1909,9 @@ static VAStatus gen9_vme_hevc_prepare(VADriverContextP ctx, vme_context->hevc_level = pSequenceParameter->general_level_idc; } + //internal input check for main10 + gen9_intel_hevc_input_check(ctx,encode_state,encoder_context); + intel_vme_hevc_update_mbmv_cost(ctx, encode_state, encoder_context); /*Setup all the memory object*/ @@ -1815,10 +1978,22 @@ gen9_vme_context_destroy(void *context) Bool gen9_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { - struct gen6_vme_context *vme_context = calloc(1, sizeof(struct gen6_vme_context)); + struct gen6_vme_context *vme_context; struct i965_kernel *vme_kernel_list = NULL; int i965_kernel_num; + if (encoder_context->low_power_mode || encoder_context->codec == CODEC_JPEG) { + encoder_context->vme_context = NULL; + encoder_context->vme_pipeline = NULL; + encoder_context->vme_context_destroy = NULL; + + return True; + } else if (encoder_context->codec == CODEC_VP9) { + return gen9_vp9_vme_context_init(ctx, encoder_context); + } + + vme_context = calloc(1, sizeof(struct gen6_vme_context)); + switch (encoder_context->codec) { case CODEC_H264: case CODEC_H264_MVC: |