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* arm64: 64bit iOS and SMP support (#7942)Luke Iannini2014-11-191-2/+77
| | | | Signed-off-by: Austin Seipp <austin@well-typed.com>
* Fix globalRegMaybe for unregisterised build.Peter Trommler2014-05-131-0/+2
| | | | | | | | | | In commit 83a003f globalRegMaybe will be called but panics for unregisterised compilers. In an unregisterised compiler there are no global registers so always return `Nothing`. Fixes #9055.
* Revert "Per-thread allocation counters and limits"Simon Marlow2014-05-041-1/+3
| | | | | | | | Problems were found on 32-bit platforms, I'll commit again when I have a fix. This reverts the following commits: 54b31f744848da872c7c6366dea840748e01b5cf b0534f78a73f972e279eed4447a5687bd6a8308e
* Per-thread allocation counters and limitsSimon Marlow2014-05-021-3/+1
| | | | | | | | | | | | | | | | | | | | | | | This tracks the amount of memory allocation by each thread in a counter stored in the TSO. Optionally, when the counter drops below zero (it counts down), the thread can be sent an asynchronous exception: AllocationLimitExceeded. When this happens, given a small additional limit so that it can handle the exception. See documentation in GHC.Conc for more details. Allocation limits are similar to timeouts, but - timeouts use real time, not CPU time. Allocation limits do not count anything while the thread is blocked or in foreign code. - timeouts don't re-trigger if the thread catches the exception, allocation limits do. - timeouts can catch non-allocating loops, if you use -fno-omit-yields. This doesn't work for allocation limits. I couldn't measure any impact on benchmarks with these changes, even for nofib/smp.
* Pass 512-bit-wide vectors in registers.Geoffrey Mainland2013-09-221-0/+55
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* Pass 256-bit-wide vectors in registers.Geoffrey Mainland2013-09-221-0/+55
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* Ensure that globalRegMaybe returns accurate information for XMM registers.Geoffrey Mainland2013-09-221-1/+13
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* Rename SSE -> XMM for consistency.Geoffrey Mainland2013-08-061-4/+4
| | | | | We were using SSE is some places and XMM in others. Better to keep a consistent naming scheme.
* Add support for passing SSE vectors in registers.Geoffrey Mainland2013-02-011-0/+26
| | | | | | | This patch adds support for 6 XMM registers on x86-64 which overlap with the F and D registers and may hold 128-bit wide SIMD vectors. Because there is not a good way to attach type information to STG registers, we aggressively bitcast in the LLVM back-end.
* MachRegs.h requires ghcautoconf.h to be included before it (#7591)Stephen Blackheath2013-02-011-0/+1
| | | | | | | Because, in the case of ARM processors, it needs to know what ARM variant is being used. This patch fixes that in includes/CodeGen.Platform.hs, otherwise there is a mismatch between the compiler and llvm.
* Draw STG F and D registers from the same pool of available SSE registers on ↵Geoffrey Mainland2012-10-301-0/+161
| | | | | | | | | | | | x86-64. On x86-64 F and D registers are both drawn from SSE registers, so there is no reason not to draw them from the same pool of available SSE registers. This means that whereas previously a function could only receive two Double arguments in registers even if it did not have any Float arguments, now it can receive up to 6 arguments that are any mix of Float and Double in registers. This patch breaks the LLVM back end. The next patch will fix this breakage.
* Move more code into codeGen/CodeGen/Platform.hsIan Lynagh2012-08-281-1/+584
| | | | | | | | HaskellMachRegs.h is no longer included in anything under compiler/ Also, includes/CodeGen.Platform.hs now includes "stg/MachRegs.h" rather than <stg/MachRegs.h> which means that we always get the file from the tree, rather than from the bootstrapping compiler.
* Add haveRegBase to CodeGen.PlatformIan Lynagh2012-08-211-0/+7
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* Move activeStgRegs into CodeGen.PlatformIan Lynagh2012-08-211-0/+145