| Commit message (Collapse) | Author | Age | Files | Lines |
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Merge backend-hacking-branch onto HEAD. Yay!
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Import wibbles
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Add just enough infrastructure to the NCG that it can deal with simple 64-bit
code on 32-bit platforms. Main changes are:
* Addition of a simple 64-bit instruction selection fn iselExpr64 to MachCode.
This generates code for a 64-bit value and places the results into two
virtual registers, related thusly:
* Add a new type VRegUnique, which is used to label Stix virtual registers.
This type used to be a plain Unique, but that forces the assumption that
each Abstract-C level C temporary corresponds to exactly one Stix virtual
register, which is untrue when the C temporary is 64-bit sized on a
32-bit machine. In the new scheme, the Unique for the C temporary can
turn into two related VRegUniques, related by having the same embedded
unique.
* Made a start on 'target metrics' by adding ncg_target_is_32bits to the
end of Stix.lhs.
* Cleaned up numerous other gruesomenesses in the NCG which never came
to light before now. Got rid of MachMisc.sizeOf, which doesn't make
sense in a 64-bit setting, and replaced it by calls to
PrimRep.getPrimRepArrayElemSize, which, as far as I'm concerned, is the
definitive answer to the questio `How Big Is This PrimRep Really?'
Result: on x86-linux, at least, you can now compile the Entire Prelude
with -fasm! At this stage I cannot claim that the resulting code is
correct, but it's a start.
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Updates to the native code generator following the changes to fix the
large block allocation bug, and changes to use the new
function-address cache in the register table to reduce code size.
Also: I changed the pretty-printing machinery for assembly code to use
Pretty rather than Outputable, since we don't make use of the styles
and it should improve performance. Perhaps the same should be done
for abstract C.
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Dealing with instance-decl imports; and removing unnecessary imports
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Make the back-end world compile.
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Partially back out changes mistakenly included in last commit :-(
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Implement initial-state (emptyTy :: Ty) functions.
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Make the register allocator deal properly with switch tables.
Previously, it didn't calculate the correct flow edges away from the
indirect jump (in fact it didn't reckon there were any flow edges
leaving it :) which makes a nonsense of the live variable analysis in
the branches.
A jump insn can now optionally be annotated with a list of destination
labels, and if so, the register allocator creates flow edges to all of
them.
Jump tables are now re-enabled. They remain disabled for 4.08.1,
since we aren't fixing the problem properly on that branch.
I assume this problem wasn't exposed by the old register allocator
because of the live-range-approximation hacks used in it. Since it
was undocumented, we'll never know.
Sparc builds will now break until I fix them.
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Make the x86 NCG work again following recent sparc hackage.
Also, fix the x86 bits pertaining to the floats-promoted-to-doubles-
in-ccalls problem. So this problem should no longer exist on x86
or sparc via NCG.
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remove unused imports
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Fix up the sparc native code generator. Mostly dull stuff. Notable
changes:
* Cleaned up ccall mechanism for sparc somewhat.
* Rearranged assignment of sparc floating point registers (includes/MachRegs.h)
so the NCG's register allocator can handle the double-single pairing
issue without modification. Split VirtualRegF into VirtualRegF and
VirtualRegD, and split RcFloating into RcFloat and RcDouble. Net effect
is that there are now three register classes -- int, float and double,
and we pretend that sparc has some float and some double real regs.
* (A fix for all platforms): propagate MachFloats through as StFloats,
not StDoubles. Amazingly, until now literal floats had been converted
to and treated as doubles, including in ccalls.
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DEBUG ==> NCG_DEBUG
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Major thing: new register allocator. Brief description follows.
Should correctly handle code with loops in, even though we don't
generate any such at the moment. A lot of comments. The previous
machinery for spilling is retained, as is the idea of a fast-and-easy
initial allocation attempt intended to deal with the majority of code
blocks (about 60% on x86) very cheaply. Many comments explaining
in detail how it works :-)
The Stix inliner is now on by default. Integer code seems to run
within about 1% of that -fvia-C. x86 fp code is significantly worse,
up to about 30% slower, depending on the amount of fp activity.
Minor thing: lazyfication of the top-level NCG plumbing, so that the
NCG doesn't require any greater residency than compiling to C, just a
bit more time. Created lazyThenUs and lazyMapUs for this purpose.
The new allocator is somewhat, although not catastophically, slower
than the old one. Fixing of the long-standing NCG space leak more
than makes up for it; overall hsc run-time is down about 5%, due to
significantly reduced GC time.
--------------------------------------------------------------------
Instructions are numbered sequentially, starting at zero.
A flow edge (FE) is a pair of insn numbers (MkFE Int Int) denoting
a possible flow of control from the first insn to the second.
The input to the register allocator is a list of instructions, which
mention Regs. A Reg can be a RealReg -- a real machine reg -- or a
VirtualReg, which carries a unique. After allocation, all the
VirtualReg references will have been converted into RealRegs, and
possibly some spill code will have been inserted.
The heart of the register allocator works in four phases.
1. (find_flow_edges) Calculate all the FEs for the code list.
Return them not as a [FE], but implicitly, as a pair of
Array Int [Int], being the successor and predecessor maps
for instructions.
2. (calc_liveness) Returns a FiniteMap FE RegSet. For each
FE, indicates the set of registers live on that FE. Note
that the set includes both RealRegs and VirtualRegs. The
former appear because the code could mention fixed register
usages, and we need to take them into account from the start.
3. (calc_live_range_sets) Invert the above mapping, giving a
FiniteMap Reg FeSet, indicating, for each virtual and real
reg mentioned in the code, which FEs it is live on.
4. (calc_vreg_to_rreg_mapping) For virtual reg, try and find
an allocatable real register for it. Each real register has
a "current commitment", indicating the set of FEs it is
currently live on. A virtual reg v can be assigned to
real reg r iff v's live-fe-set does not intersect with r's
current commitment fe-set. If the assignment is made,
v's live-fe-set is union'd into r's current commitment fe-set.
There is also the minor restriction that v and r must be of
the same register class (integer or floating).
Once this mapping is established, we simply apply it to the
input insns, and that's it.
If no suitable real register can be found, the vreg is mapped
to itself, and we deem allocation to have failed. The partially
allocated code is returned. The higher echelons of the allocator
(doGeneralAlloc and runRegAlloc) then cooperate to insert spill
code and re-run allocation, until a successful allocation is found.
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Teach the NCG about the dereferencing and naming conventions to be
used when compiling for a DLLised world. Some cleanups on the way
too. The scheme is that
* All CLabels which are in different DLLs from the current module
will, via the renamer, already be such that labelDynamic returns
True for them.
* Redo the StixPrim/StixMacro stuff so that all references to symbols
in the RTS are via CLabels. That means that the usual labelDynamic
story can be used.
* When a label is printed in PprMach, labelDynamic is consulted, to
generate the __imp_ prefix if necessary.
* In MachCode.stmt2Instrs, selectively ask derefDLL to walk trees
before code generation and insert deferencing code around other-DLL
symbols.
* When generating Stix for SRTs, add 1 to other-DLL refs.
* When generating static closures, insert a zero word before
the _closure label.
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Many changes to improve the quality and correctness of generated code,
both for x86 and all-platforms. The intent is that the x86 NCG will
now be good enough for general use.
-- Add an almost-trivial Stix (generic) peephole optimiser, whose sole
purpose is elide assignments to temporaries used only once, in the
very next tree. This generates substantially better code for
conditionals on all platforms. Enhance Stix constant folding to
take advantage of the inlining.
The inlining presents subsequent insn selection phases with more
complex trees than would have previously been used to. This has
shown up several bugs in the x86 insn selectors, now fixed.
(assumptions that data size is Word, when could be Byte,
assumptions that an operand will always be in a temp reg, etc)
-- x86: Use the FLDZ and FLD1 insns.
-- x86: spill FP registers with 80-bit loads/stores so that
Intel's extra 16 bits of accuracy are not lost. If this isn't
done, FP spills are not suitably transparent. Increase the
number of spill words available to 2048.
-- x86: give the register allocator more flexibility in choosing
spill temporaries.
-- x86, RegAllocInfo.regUsage: fix error for GST, and rewrite to
make it clearer.
-- Correctly track movements in the C stack pointer, and generate
correct spill code for archs which spill against the stack pointer
even when the stack pointer moves. Redo the x86 ccall mechanism
to push args on the C stack in the normal way. Rather than have
the spiller have to analyse code sequences to determine the current
stack offset, the insn selectors communicate the current offset
whenever it changes by inserting a DELTA pseudo-insn. Then the
spiller only has to spot DELTAs.
This means having a new native-code-generator monad (Stix.NatM)
which carries both a UniqSupply and the current stack offset.
-- Remove the asmPar/asmSeq ways of grouping insns together.
In the presence of fixed registers, it is hard to demonstrate
that insn selectors using asmPar always give correct code, and
the extra complication doesn't help any.
Also, directly construct code sequences using tree-based ordered
lists (utils/OrdList.lhs) for linear-time appends, rather than
the bizarrely complex method using fns and fn composition.
-- Inline some hcats in printing of x86 address modes.
-- Document more of the hidden assumptions which insn selection relies
on, particular wrt addressing modes.
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-- Cosmetic changes in register allocator.
-- Implement macro HP_GEN_SEQ_NP.
-- MachCode(trivialCode, x86): because one of the operands is also
the destination (on this 2-address arch), it's invalid to sequence
the code to compute the operands using asmParThen [code1, code2].
since the order of assignments matters. Fixed.
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Modifications to make x86 register spilling to work reasonably. It
should work ok most of the time, although there is still a remote
possibility that the allocator simply will be unable to complete
spilling, and will just give up.
-- Incrementally try with 0, 1, 2 and 3 spill regs, so as not to
unduly restrict the supply of regs in code which doesn't need spilling.
-- Remove the use of %ecx for shift values, so it is always available
as the first-choice spill temporary. For code which doesn't do
int division, make %edx and %eax available for spilling too.
Shifts by a non-constant amount (very rare) are now done by
a short test-and-jump sequence, so that %ecx is not tied up.
-- x86 FP: do sin, cos, tan in-line so we get the same answers as gcc.
-- Moved a little code around to remove recursive dependencies.
-- Fix a subtle bug in x86 regUsage, which could cause underestimation
of live ranges.
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Another big commit from Simon. Actually, the last one
didn't all go into the main trunk; because of a CVS glitch it
ended up in the wrong branch.
So this commit includes:
* Scoped type variables
* Warnings for unused variables should work now (they didn't before)
* Simplifier improvements:
- Much better treatment of strict arguments
- Better treatment of bottoming Ids
- No need for w/w split for fns that are merely strict
- Fewer iterations needed, I hope
* Less gratuitous renaming in interface files and abs C
* OccName is a separate module, and is an abstract data type
I think the whole Prelude and Exts libraries compile correctly.
Something isn't quite right about typechecking existentials though.
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Move 4.01 onto the main trunk.
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StCall now takes extra callconv arg; StixPrim.primCode doesn't flush stdout and stderr anymore (it's done in the .hc code)
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Simons changes while away at Tic/WG2.8
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The Great Multi-Parameter Type Classes Merge.
Notes from Simon (abridged):
* Multi-parameter type classes are fully implemented.
* Error messages from the type checker should be noticeably improved
* Warnings for unused bindings (-fwarn-unused-names)
* many other minor bug fixes.
Internally there are the following changes
* Removal of Haskell 1.2 compatibility.
* Dramatic clean-up of the PprStyle stuff.
* The type Type has been substantially changed.
* The dictionary for each class is represented by a new
data type for that purpose, rather than by a tuple.
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changes for MachRegs.Addr -> MachRegs.Address
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2.04 changes
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partain 1.3 changes through 960629
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SLPJ changes through 960604
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SLPJ 1.3 changes to 960430
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Add SLPJ/WDP 1.3 changes through 960404
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simonpj/sansom/partain/dnt 1.3 compiler stuff through 96/03/18
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Initial revision
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