7 files changed, 11 insertions, 12 deletions
diff --git a/compiler/nativeGen/AsmCodeGen.lhs b/compiler/nativeGen/AsmCodeGen.lhs
index e0608cb80c..6d3bf7ca75 100644
--- a/compiler/nativeGen/AsmCodeGen.lhs
+++ b/compiler/nativeGen/AsmCodeGen.lhs
@@ -40,7 +40,7 @@ import MachOp
 import CLabel
 import State
 
-import LazyUniqFM
+import UniqFM
 import Unique		( Unique, getUnique )
 import UniqSupply
 import List		( groupBy, sortBy )
diff --git a/compiler/nativeGen/MachRegs.lhs b/compiler/nativeGen/MachRegs.lhs
index 2c6238d834..5832abe786 100644
--- a/compiler/nativeGen/MachRegs.lhs
+++ b/compiler/nativeGen/MachRegs.lhs
@@ -105,8 +105,7 @@ import UniqSet
 import Constants
 import FastTypes
 import FastBool
-import qualified UniqFM as S
-import LazyUniqFM
+import UniqFM
 
 #if powerpc_TARGET_ARCH
 import Data.Word	( Word8, Word16, Word32 )
@@ -520,20 +519,20 @@ worst n classN classC
 
 {-# INLINE regClass      #-}
 trivColorable :: RegClass -> UniqSet Reg -> UniqSet Reg -> Bool
-trivColorable classN (MkUniqFM conflicts) (MkUniqFM exclusions)
+trivColorable classN conflicts exclusions
  = {-# SCC "trivColorable" #-}
    let
 	{-# INLINE   isSqueesed    #-}
 	isSqueesed cI cF ufm
 	  = case ufm of
-		S.NodeUFM _ _ left right
+		NodeUFM _ _ left right
 		 -> case isSqueesed cI cF right of
 		 	(# s, cI', cF' #)
 			 -> case s of
 			 	False	-> isSqueesed cI' cF' left
 				True	-> (# True, cI', cF' #)
 
-		S.LeafUFM _ (Lazy reg)
+		LeafUFM _ reg
 		 -> case regClass reg of
 		 	RcInteger
 			 -> case cI +# _ILIT(1) of
@@ -543,7 +542,7 @@ trivColorable classN (MkUniqFM conflicts) (MkUniqFM exclusions)
 			 -> case cF +# _ILIT(1) of
 			 	cF' -> (# cF' >=# ALLOCATABLE_REGS_DOUBLE,  cI, cF' #)
 
-		S.EmptyUFM
+		EmptyUFM
 		 ->	(# False, cI, cF #)
 
    in case isSqueesed (_ILIT(0)) (_ILIT(0)) conflicts of
diff --git a/compiler/nativeGen/RegAllocColor.hs b/compiler/nativeGen/RegAllocColor.hs
index e2e002af35..51a0bffbc6 100644
--- a/compiler/nativeGen/RegAllocColor.hs
+++ b/compiler/nativeGen/RegAllocColor.hs
@@ -24,7 +24,7 @@ import PprMach
 
 import UniqSupply
 import UniqSet
-import LazyUniqFM
+import UniqFM
 import Bag
 import Outputable
 import DynFlags
diff --git a/compiler/nativeGen/RegAllocLinear.hs b/compiler/nativeGen/RegAllocLinear.hs
index b333c68d5d..e6491b77ee 100644
--- a/compiler/nativeGen/RegAllocLinear.hs
+++ b/compiler/nativeGen/RegAllocLinear.hs
@@ -97,7 +97,7 @@ import Cmm hiding (RegSet)
 import Digraph
 import Unique		( Uniquable(getUnique), Unique )
 import UniqSet
-import LazyUniqFM
+import UniqFM
 import UniqSupply
 import Outputable
 import State
diff --git a/compiler/nativeGen/RegAllocStats.hs b/compiler/nativeGen/RegAllocStats.hs
index 32c0942488..58a69fa76e 100644
--- a/compiler/nativeGen/RegAllocStats.hs
+++ b/compiler/nativeGen/RegAllocStats.hs
@@ -30,7 +30,7 @@ import MachInstrs
 import Cmm
 
 import Outputable
-import LazyUniqFM
+import UniqFM
 import UniqSet
 import State
 
diff --git a/compiler/nativeGen/RegLiveness.hs b/compiler/nativeGen/RegLiveness.hs
index 6f21db8b77..9ee98971ba 100644
--- a/compiler/nativeGen/RegLiveness.hs
+++ b/compiler/nativeGen/RegLiveness.hs
@@ -42,7 +42,7 @@ import Digraph
 import Outputable
 import Unique
 import UniqSet
-import LazyUniqFM
+import UniqFM
 import UniqSupply
 import Bag
 import State
diff --git a/compiler/nativeGen/RegSpillCost.hs b/compiler/nativeGen/RegSpillCost.hs
index b492738238..d987937102 100644
--- a/compiler/nativeGen/RegSpillCost.hs
+++ b/compiler/nativeGen/RegSpillCost.hs
@@ -23,7 +23,7 @@ import MachInstrs
 import MachRegs
 import Cmm
 
-import LazyUniqFM
+import UniqFM
 import UniqSet
 import Outputable
 import State