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-rw-r--r--compiler/nativeGen/PPC/Regs.hs33
-rw-r--r--compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs52
-rw-r--r--compiler/nativeGen/SPARC/Regs.hs45
-rw-r--r--compiler/nativeGen/TargetReg.hs5
-rw-r--r--compiler/nativeGen/X86/Regs.hs42
5 files changed, 85 insertions, 92 deletions
diff --git a/compiler/nativeGen/PPC/Regs.hs b/compiler/nativeGen/PPC/Regs.hs
index d0eb183ea7..05efaeb1f4 100644
--- a/compiler/nativeGen/PPC/Regs.hs
+++ b/compiler/nativeGen/PPC/Regs.hs
@@ -60,7 +60,6 @@ import Unique
import CodeGen.Platform
import DynFlags
import Outputable
-import FastTypes
import Platform
import Data.Word ( Word8, Word16, Word32, Word64 )
@@ -75,44 +74,44 @@ import Data.Int ( Int8, Int16, Int32, Int64 )
-- as a neighbour.
--
{-# INLINE virtualRegSqueeze #-}
-virtualRegSqueeze :: RegClass -> VirtualReg -> FastInt
+virtualRegSqueeze :: RegClass -> VirtualReg -> Int
virtualRegSqueeze cls vr
= case cls of
RcInteger
-> case vr of
- VirtualRegI{} -> _ILIT(1)
- VirtualRegHi{} -> _ILIT(1)
- _other -> _ILIT(0)
+ VirtualRegI{} -> 1
+ VirtualRegHi{} -> 1
+ _other -> 0
RcDouble
-> case vr of
- VirtualRegD{} -> _ILIT(1)
- VirtualRegF{} -> _ILIT(0)
- _other -> _ILIT(0)
+ VirtualRegD{} -> 1
+ VirtualRegF{} -> 0
+ _other -> 0
- _other -> _ILIT(0)
+ _other -> 0
{-# INLINE realRegSqueeze #-}
-realRegSqueeze :: RegClass -> RealReg -> FastInt
+realRegSqueeze :: RegClass -> RealReg -> Int
realRegSqueeze cls rr
= case cls of
RcInteger
-> case rr of
RealRegSingle regNo
- | regNo < 32 -> _ILIT(1) -- first fp reg is 32
- | otherwise -> _ILIT(0)
+ | regNo < 32 -> 1 -- first fp reg is 32
+ | otherwise -> 0
- RealRegPair{} -> _ILIT(0)
+ RealRegPair{} -> 0
RcDouble
-> case rr of
RealRegSingle regNo
- | regNo < 32 -> _ILIT(0)
- | otherwise -> _ILIT(1)
+ | regNo < 32 -> 0
+ | otherwise -> 1
- RealRegPair{} -> _ILIT(0)
+ RealRegPair{} -> 0
- _other -> _ILIT(0)
+ _other -> 0
mkVirtualReg :: Unique -> Format -> VirtualReg
mkVirtualReg u format
diff --git a/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs b/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs
index b42fb4c39e..be9248f9b6 100644
--- a/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs
+++ b/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs
@@ -1,4 +1,4 @@
-{-# LANGUAGE BangPatterns, CPP #-}
+{-# LANGUAGE CPP #-}
module RegAlloc.Graph.TrivColorable (
trivColorable,
@@ -14,11 +14,9 @@ import Reg
import GraphBase
import UniqFM
-import FastTypes
import Platform
import Panic
-
-- trivColorable ---------------------------------------------------------------
-- trivColorable function for the graph coloring allocator
@@ -55,16 +53,16 @@ import Panic
-- different regSqueeze function for each.
--
accSqueeze
- :: FastInt
- -> FastInt
- -> (reg -> FastInt)
+ :: Int
+ -> Int
+ -> (reg -> Int)
-> UniqFM reg
- -> FastInt
+ -> Int
accSqueeze count maxCount squeeze ufm = acc count (eltsUFM ufm)
where acc count [] = count
- acc count _ | count >=# maxCount = count
- acc count (r:rs) = acc (count +# squeeze r) rs
+ acc count _ | count >= maxCount = count
+ acc count (r:rs) = acc (count + squeeze r) rs
{- Note [accSqueeze]
~~~~~~~~~~~~~~~~~~~~
@@ -100,13 +98,13 @@ the most efficient variant tried. Benchmark compiling 10-times SHA1.hs follows.
trivColorable
:: Platform
- -> (RegClass -> VirtualReg -> FastInt)
- -> (RegClass -> RealReg -> FastInt)
+ -> (RegClass -> VirtualReg -> Int)
+ -> (RegClass -> RealReg -> Int)
-> Triv VirtualReg RegClass RealReg
trivColorable platform virtualRegSqueeze realRegSqueeze RcInteger conflicts exclusions
- | let !cALLOCATABLE_REGS_INTEGER
- = iUnbox (case platformArch platform of
+ | let cALLOCATABLE_REGS_INTEGER
+ = (case platformArch platform of
ArchX86 -> 3
ArchX86_64 -> 5
ArchPPC -> 16
@@ -119,7 +117,7 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcInteger conflicts excl
ArchMipsel -> panic "trivColorable ArchMipsel"
ArchJavaScript-> panic "trivColorable ArchJavaScript"
ArchUnknown -> panic "trivColorable ArchUnknown")
- , count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_INTEGER
+ , count2 <- accSqueeze 0 cALLOCATABLE_REGS_INTEGER
(virtualRegSqueeze RcInteger)
conflicts
@@ -127,11 +125,11 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcInteger conflicts excl
(realRegSqueeze RcInteger)
exclusions
- = count3 <# cALLOCATABLE_REGS_INTEGER
+ = count3 < cALLOCATABLE_REGS_INTEGER
trivColorable platform virtualRegSqueeze realRegSqueeze RcFloat conflicts exclusions
- | let !cALLOCATABLE_REGS_FLOAT
- = iUnbox (case platformArch platform of
+ | let cALLOCATABLE_REGS_FLOAT
+ = (case platformArch platform of
ArchX86 -> 0
ArchX86_64 -> 0
ArchPPC -> 0
@@ -144,7 +142,7 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcFloat conflicts exclus
ArchMipsel -> panic "trivColorable ArchMipsel"
ArchJavaScript-> panic "trivColorable ArchJavaScript"
ArchUnknown -> panic "trivColorable ArchUnknown")
- , count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_FLOAT
+ , count2 <- accSqueeze 0 cALLOCATABLE_REGS_FLOAT
(virtualRegSqueeze RcFloat)
conflicts
@@ -152,11 +150,11 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcFloat conflicts exclus
(realRegSqueeze RcFloat)
exclusions
- = count3 <# cALLOCATABLE_REGS_FLOAT
+ = count3 < cALLOCATABLE_REGS_FLOAT
trivColorable platform virtualRegSqueeze realRegSqueeze RcDouble conflicts exclusions
- | let !cALLOCATABLE_REGS_DOUBLE
- = iUnbox (case platformArch platform of
+ | let cALLOCATABLE_REGS_DOUBLE
+ = (case platformArch platform of
ArchX86 -> 6
ArchX86_64 -> 0
ArchPPC -> 26
@@ -169,7 +167,7 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcDouble conflicts exclu
ArchMipsel -> panic "trivColorable ArchMipsel"
ArchJavaScript-> panic "trivColorable ArchJavaScript"
ArchUnknown -> panic "trivColorable ArchUnknown")
- , count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_DOUBLE
+ , count2 <- accSqueeze 0 cALLOCATABLE_REGS_DOUBLE
(virtualRegSqueeze RcDouble)
conflicts
@@ -177,11 +175,11 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcDouble conflicts exclu
(realRegSqueeze RcDouble)
exclusions
- = count3 <# cALLOCATABLE_REGS_DOUBLE
+ = count3 < cALLOCATABLE_REGS_DOUBLE
trivColorable platform virtualRegSqueeze realRegSqueeze RcDoubleSSE conflicts exclusions
- | let !cALLOCATABLE_REGS_SSE
- = iUnbox (case platformArch platform of
+ | let cALLOCATABLE_REGS_SSE
+ = (case platformArch platform of
ArchX86 -> 8
ArchX86_64 -> 10
ArchPPC -> 0
@@ -194,7 +192,7 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcDoubleSSE conflicts ex
ArchMipsel -> panic "trivColorable ArchMipsel"
ArchJavaScript-> panic "trivColorable ArchJavaScript"
ArchUnknown -> panic "trivColorable ArchUnknown")
- , count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_SSE
+ , count2 <- accSqueeze 0 cALLOCATABLE_REGS_SSE
(virtualRegSqueeze RcDoubleSSE)
conflicts
@@ -202,7 +200,7 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcDoubleSSE conflicts ex
(realRegSqueeze RcDoubleSSE)
exclusions
- = count3 <# cALLOCATABLE_REGS_SSE
+ = count3 < cALLOCATABLE_REGS_SSE
-- Specification Code ----------------------------------------------------------
diff --git a/compiler/nativeGen/SPARC/Regs.hs b/compiler/nativeGen/SPARC/Regs.hs
index 4ae114b0ef..14a5192c2d 100644
--- a/compiler/nativeGen/SPARC/Regs.hs
+++ b/compiler/nativeGen/SPARC/Regs.hs
@@ -39,7 +39,6 @@ import Format
import Unique
import Outputable
-import FastTypes
{-
The SPARC has 64 registers of interest; 32 integer registers and 32
@@ -81,60 +80,60 @@ classOfRealReg reg
-- as a neighbour.
--
{-# INLINE virtualRegSqueeze #-}
-virtualRegSqueeze :: RegClass -> VirtualReg -> FastInt
+virtualRegSqueeze :: RegClass -> VirtualReg -> Int
virtualRegSqueeze cls vr
= case cls of
RcInteger
-> case vr of
- VirtualRegI{} -> _ILIT(1)
- VirtualRegHi{} -> _ILIT(1)
- _other -> _ILIT(0)
+ VirtualRegI{} -> 1
+ VirtualRegHi{} -> 1
+ _other -> 0
RcFloat
-> case vr of
- VirtualRegF{} -> _ILIT(1)
- VirtualRegD{} -> _ILIT(2)
- _other -> _ILIT(0)
+ VirtualRegF{} -> 1
+ VirtualRegD{} -> 2
+ _other -> 0
RcDouble
-> case vr of
- VirtualRegF{} -> _ILIT(1)
- VirtualRegD{} -> _ILIT(1)
- _other -> _ILIT(0)
+ VirtualRegF{} -> 1
+ VirtualRegD{} -> 1
+ _other -> 0
- _other -> _ILIT(0)
+ _other -> 0
{-# INLINE realRegSqueeze #-}
-realRegSqueeze :: RegClass -> RealReg -> FastInt
+realRegSqueeze :: RegClass -> RealReg -> Int
realRegSqueeze cls rr
= case cls of
RcInteger
-> case rr of
RealRegSingle regNo
- | regNo < 32 -> _ILIT(1)
- | otherwise -> _ILIT(0)
+ | regNo < 32 -> 1
+ | otherwise -> 0
- RealRegPair{} -> _ILIT(0)
+ RealRegPair{} -> 0
RcFloat
-> case rr of
RealRegSingle regNo
- | regNo < 32 -> _ILIT(0)
- | otherwise -> _ILIT(1)
+ | regNo < 32 -> 0
+ | otherwise -> 1
- RealRegPair{} -> _ILIT(2)
+ RealRegPair{} -> 2
RcDouble
-> case rr of
RealRegSingle regNo
- | regNo < 32 -> _ILIT(0)
- | otherwise -> _ILIT(1)
+ | regNo < 32 -> 0
+ | otherwise -> 1
- RealRegPair{} -> _ILIT(1)
+ RealRegPair{} -> 1
- _other -> _ILIT(0)
+ _other -> 0
-- | All the allocatable registers in the machine,
-- including register pairs.
diff --git a/compiler/nativeGen/TargetReg.hs b/compiler/nativeGen/TargetReg.hs
index 606e6f5d9e..9bd470b0d6 100644
--- a/compiler/nativeGen/TargetReg.hs
+++ b/compiler/nativeGen/TargetReg.hs
@@ -27,7 +27,6 @@ import Format
import Outputable
import Unique
-import FastTypes
import Platform
import qualified X86.Regs as X86
@@ -37,7 +36,7 @@ import qualified PPC.Regs as PPC
import qualified SPARC.Regs as SPARC
-targetVirtualRegSqueeze :: Platform -> RegClass -> VirtualReg -> FastInt
+targetVirtualRegSqueeze :: Platform -> RegClass -> VirtualReg -> Int
targetVirtualRegSqueeze platform
= case platformArch platform of
ArchX86 -> X86.virtualRegSqueeze
@@ -54,7 +53,7 @@ targetVirtualRegSqueeze platform
ArchUnknown -> panic "targetVirtualRegSqueeze ArchUnknown"
-targetRealRegSqueeze :: Platform -> RegClass -> RealReg -> FastInt
+targetRealRegSqueeze :: Platform -> RegClass -> RealReg -> Int
targetRealRegSqueeze platform
= case platformArch platform of
ArchX86 -> X86.realRegSqueeze
diff --git a/compiler/nativeGen/X86/Regs.hs b/compiler/nativeGen/X86/Regs.hs
index 5c484743ca..4cb82ea224 100644
--- a/compiler/nativeGen/X86/Regs.hs
+++ b/compiler/nativeGen/X86/Regs.hs
@@ -57,8 +57,6 @@ import CLabel ( CLabel )
import DynFlags
import Outputable
import Platform
-import FastTypes
-
-- | regSqueeze_class reg
-- Calculuate the maximum number of register colors that could be
@@ -66,55 +64,55 @@ import FastTypes
-- as a neighbour.
--
{-# INLINE virtualRegSqueeze #-}
-virtualRegSqueeze :: RegClass -> VirtualReg -> FastInt
+virtualRegSqueeze :: RegClass -> VirtualReg -> Int
virtualRegSqueeze cls vr
= case cls of
RcInteger
-> case vr of
- VirtualRegI{} -> _ILIT(1)
- VirtualRegHi{} -> _ILIT(1)
- _other -> _ILIT(0)
+ VirtualRegI{} -> 1
+ VirtualRegHi{} -> 1
+ _other -> 0
RcDouble
-> case vr of
- VirtualRegD{} -> _ILIT(1)
- VirtualRegF{} -> _ILIT(0)
- _other -> _ILIT(0)
+ VirtualRegD{} -> 1
+ VirtualRegF{} -> 0
+ _other -> 0
RcDoubleSSE
-> case vr of
- VirtualRegSSE{} -> _ILIT(1)
- _other -> _ILIT(0)
+ VirtualRegSSE{} -> 1
+ _other -> 0
- _other -> _ILIT(0)
+ _other -> 0
{-# INLINE realRegSqueeze #-}
-realRegSqueeze :: RegClass -> RealReg -> FastInt
+realRegSqueeze :: RegClass -> RealReg -> Int
realRegSqueeze cls rr
= case cls of
RcInteger
-> case rr of
RealRegSingle regNo
- | regNo < firstfake -> _ILIT(1)
- | otherwise -> _ILIT(0)
+ | regNo < firstfake -> 1
+ | otherwise -> 0
- RealRegPair{} -> _ILIT(0)
+ RealRegPair{} -> 0
RcDouble
-> case rr of
RealRegSingle regNo
- | regNo >= firstfake && regNo <= lastfake -> _ILIT(1)
- | otherwise -> _ILIT(0)
+ | regNo >= firstfake && regNo <= lastfake -> 1
+ | otherwise -> 0
- RealRegPair{} -> _ILIT(0)
+ RealRegPair{} -> 0
RcDoubleSSE
-> case rr of
- RealRegSingle regNo | regNo >= firstxmm -> _ILIT(1)
- _otherwise -> _ILIT(0)
+ RealRegSingle regNo | regNo >= firstxmm -> 1
+ _otherwise -> 0
- _other -> _ILIT(0)
+ _other -> 0
-- -----------------------------------------------------------------------------
-- Immediates
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