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-rw-r--r--compiler/nativeGen/SPARC/Ppr.hs14
-rw-r--r--compiler/nativeGen/SPARC/Regs.hs2
2 files changed, 5 insertions, 11 deletions
diff --git a/compiler/nativeGen/SPARC/Ppr.hs b/compiler/nativeGen/SPARC/Ppr.hs
index fc67f77541..aa355f97cb 100644
--- a/compiler/nativeGen/SPARC/Ppr.hs
+++ b/compiler/nativeGen/SPARC/Ppr.hs
@@ -45,7 +45,6 @@ import CLabel
import Hoopl.Label
import Hoopl.Collections
-import Unique ( pprUniqueAlways )
import Outputable
import GHC.Platform
import FastString
@@ -148,12 +147,7 @@ pprReg :: Reg -> SDoc
pprReg reg
= case reg of
RegVirtual vr
- -> case vr of
- VirtualRegI u -> text "%vI_" <> pprUniqueAlways u
- VirtualRegHi u -> text "%vHi_" <> pprUniqueAlways u
- VirtualRegF u -> text "%vF_" <> pprUniqueAlways u
- VirtualRegD u -> text "%vD_" <> pprUniqueAlways u
-
+ -> ppr vr
RegReal rr
-> case rr of
@@ -221,7 +215,8 @@ pprFormat x
II32 -> sLit ""
II64 -> sLit "d"
FF32 -> sLit ""
- FF64 -> sLit "d")
+ FF64 -> sLit "d"
+ VecFormat _ _ _ -> panic "SPARC.Ppr.pprFormat: VecFormat")
-- | Pretty print a format for an instruction suffix.
@@ -235,7 +230,8 @@ pprStFormat x
II32 -> sLit ""
II64 -> sLit "x"
FF32 -> sLit ""
- FF64 -> sLit "d")
+ FF64 -> sLit "d"
+ VecFormat _ _ _ -> panic "SPARC.Ppr.pprFormat: VecFormat")
diff --git a/compiler/nativeGen/SPARC/Regs.hs b/compiler/nativeGen/SPARC/Regs.hs
index 0d7edc346a..e46dbd0d38 100644
--- a/compiler/nativeGen/SPARC/Regs.hs
+++ b/compiler/nativeGen/SPARC/Regs.hs
@@ -104,7 +104,6 @@ virtualRegSqueeze cls vr
VirtualRegD{} -> 1
_other -> 0
-
{-# INLINE realRegSqueeze #-}
realRegSqueeze :: RegClass -> RealReg -> Int
@@ -134,7 +133,6 @@ realRegSqueeze cls rr
RealRegPair{} -> 1
-
-- | All the allocatable registers in the machine,
-- including register pairs.
allRealRegs :: [RealReg]