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-rw-r--r--compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs4
1 files changed, 2 insertions, 2 deletions
diff --git a/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs b/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs
index 07ff1ca887..ac38e2b450 100644
--- a/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs
@@ -169,7 +169,7 @@ joinToTargets_again
--
-- We need to do the R2 -> R3 move before R1 -> R2.
--
- let sccs = stronglyConnCompFromEdgedVerticesR graph
+ let sccs = stronglyConnCompFromEdgedVerticesOrdR graph
{- -- debugging
pprTrace
@@ -313,7 +313,7 @@ handleComponent delta instr
instrLoad <- loadR (RegReal dreg) slot
remainingFixUps <- mapM (handleComponent delta instr)
- (stronglyConnCompFromEdgedVerticesR rest)
+ (stronglyConnCompFromEdgedVerticesOrdR rest)
-- make sure to do all the reloads after all the spills,
-- so we don't end up clobbering the source values.