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-rw-r--r--compiler/nativeGen/RegAlloc/Linear/Base.hs2
-rw-r--r--compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs2
-rw-r--r--compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs2
-rw-r--r--compiler/nativeGen/RegAlloc/Linear/Main.hs28
-rw-r--r--compiler/nativeGen/RegAlloc/Linear/PPC/FreeRegs.hs2
-rw-r--r--compiler/nativeGen/RegAlloc/Linear/SPARC/FreeRegs.hs2
-rw-r--r--compiler/nativeGen/RegAlloc/Linear/StackMap.hs2
-rw-r--r--compiler/nativeGen/RegAlloc/Linear/State.hs2
-rw-r--r--compiler/nativeGen/RegAlloc/Linear/Stats.hs3
-rw-r--r--compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs2
-rw-r--r--compiler/nativeGen/RegAlloc/Linear/X86_64/FreeRegs.hs2
11 files changed, 36 insertions, 13 deletions
diff --git a/compiler/nativeGen/RegAlloc/Linear/Base.hs b/compiler/nativeGen/RegAlloc/Linear/Base.hs
index d4f124e297..1172870729 100644
--- a/compiler/nativeGen/RegAlloc/Linear/Base.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/Base.hs
@@ -17,6 +17,8 @@ module RegAlloc.Linear.Base (
where
+import GhcPrelude
+
import RegAlloc.Linear.StackMap
import RegAlloc.Liveness
import Reg
diff --git a/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs b/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs
index 9933f5bb49..b4e79432d8 100644
--- a/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs
@@ -9,6 +9,8 @@ module RegAlloc.Linear.FreeRegs (
where
+import GhcPrelude
+
import Reg
import RegClass
diff --git a/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs b/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs
index c262b2b059..89f496c409 100644
--- a/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs
@@ -9,6 +9,8 @@
--
module RegAlloc.Linear.JoinToTargets (joinToTargets) where
+import GhcPrelude
+
import RegAlloc.Linear.State
import RegAlloc.Linear.Base
import RegAlloc.Linear.FreeRegs
diff --git a/compiler/nativeGen/RegAlloc/Linear/Main.hs b/compiler/nativeGen/RegAlloc/Linear/Main.hs
index 2ba682ad17..6171d8d20d 100644
--- a/compiler/nativeGen/RegAlloc/Linear/Main.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/Main.hs
@@ -102,6 +102,8 @@ module RegAlloc.Linear.Main (
#include "HsVersions.h"
+import GhcPrelude
+
import RegAlloc.Linear.State
import RegAlloc.Linear.Base
import RegAlloc.Linear.StackMap
@@ -496,7 +498,7 @@ genRaInsn block_live new_instrs block_id instr r_dying w_dying = do
-- debugging
{- freeregs <- getFreeRegsR
assig <- getAssigR
- pprDebugAndThen (defaultDynFlags Settings{ sTargetPlatform=platform }) trace "genRaInsn"
+ pprDebugAndThen (defaultDynFlags Settings{ sTargetPlatform=platform } undefined) trace "genRaInsn"
(ppr instr
$$ text "r_dying = " <+> ppr r_dying
$$ text "w_dying = " <+> ppr w_dying
@@ -807,27 +809,29 @@ allocRegsAndSpill_spill reading keep spills alloc r rs assig spill_loc
-- case (3): we need to push something out to free up a register
[] ->
- do let keep' = map getUnique keep
+ do let inRegOrBoth (InReg _) = True
+ inRegOrBoth (InBoth _ _) = True
+ inRegOrBoth _ = False
+ let candidates' =
+ flip delListFromUFM keep $
+ filterUFM inRegOrBoth $
+ assig
+ -- This is non-deterministic but we do not
+ -- currently support deterministic code-generation.
+ -- See Note [Unique Determinism and code generation]
+ let candidates = nonDetUFMToList candidates'
-- the vregs we could kick out that are already in a slot
let candidates_inBoth
= [ (temp, reg, mem)
- | (temp, InBoth reg mem) <- nonDetUFMToList assig
- -- This is non-deterministic but we do not
- -- currently support deterministic code-generation.
- -- See Note [Unique Determinism and code generation]
- , temp `notElem` keep'
+ | (temp, InBoth reg mem) <- candidates
, targetClassOfRealReg platform reg == classOfVirtualReg r ]
-- the vregs we could kick out that are only in a reg
-- this would require writing the reg to a new slot before using it.
let candidates_inReg
= [ (temp, reg)
- | (temp, InReg reg) <- nonDetUFMToList assig
- -- This is non-deterministic but we do not
- -- currently support deterministic code-generation.
- -- See Note [Unique Determinism and code generation]
- , temp `notElem` keep'
+ | (temp, InReg reg) <- candidates
, targetClassOfRealReg platform reg == classOfVirtualReg r ]
let result
diff --git a/compiler/nativeGen/RegAlloc/Linear/PPC/FreeRegs.hs b/compiler/nativeGen/RegAlloc/Linear/PPC/FreeRegs.hs
index 5d369249c7..581548212a 100644
--- a/compiler/nativeGen/RegAlloc/Linear/PPC/FreeRegs.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/PPC/FreeRegs.hs
@@ -2,6 +2,8 @@
module RegAlloc.Linear.PPC.FreeRegs
where
+import GhcPrelude
+
import PPC.Regs
import RegClass
import Reg
diff --git a/compiler/nativeGen/RegAlloc/Linear/SPARC/FreeRegs.hs b/compiler/nativeGen/RegAlloc/Linear/SPARC/FreeRegs.hs
index db4d6ba376..653b2707c9 100644
--- a/compiler/nativeGen/RegAlloc/Linear/SPARC/FreeRegs.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/SPARC/FreeRegs.hs
@@ -3,6 +3,8 @@
module RegAlloc.Linear.SPARC.FreeRegs
where
+import GhcPrelude
+
import SPARC.Regs
import RegClass
import Reg
diff --git a/compiler/nativeGen/RegAlloc/Linear/StackMap.hs b/compiler/nativeGen/RegAlloc/Linear/StackMap.hs
index 748fb98c30..95819c6fb3 100644
--- a/compiler/nativeGen/RegAlloc/Linear/StackMap.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/StackMap.hs
@@ -20,6 +20,8 @@ module RegAlloc.Linear.StackMap (
where
+import GhcPrelude
+
import DynFlags
import UniqFM
import Unique
diff --git a/compiler/nativeGen/RegAlloc/Linear/State.hs b/compiler/nativeGen/RegAlloc/Linear/State.hs
index 8b17d3ab88..6554188f41 100644
--- a/compiler/nativeGen/RegAlloc/Linear/State.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/State.hs
@@ -31,6 +31,8 @@ module RegAlloc.Linear.State (
)
where
+import GhcPrelude
+
import RegAlloc.Linear.Stats
import RegAlloc.Linear.StackMap
import RegAlloc.Linear.Base
diff --git a/compiler/nativeGen/RegAlloc/Linear/Stats.hs b/compiler/nativeGen/RegAlloc/Linear/Stats.hs
index 71dedaeb55..74f3c834d0 100644
--- a/compiler/nativeGen/RegAlloc/Linear/Stats.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/Stats.hs
@@ -6,6 +6,8 @@ module RegAlloc.Linear.Stats (
where
+import GhcPrelude
+
import RegAlloc.Linear.Base
import RegAlloc.Liveness
import Instruction
@@ -13,7 +15,6 @@ import Instruction
import UniqFM
import Outputable
-import Data.List
import State
-- | Build a map of how many times each reg was alloced, clobbered, loaded etc.
diff --git a/compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs b/compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs
index ae4aa53254..65a566d1c3 100644
--- a/compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs
@@ -3,6 +3,8 @@
module RegAlloc.Linear.X86.FreeRegs
where
+import GhcPrelude
+
import X86.Regs
import RegClass
import Reg
diff --git a/compiler/nativeGen/RegAlloc/Linear/X86_64/FreeRegs.hs b/compiler/nativeGen/RegAlloc/Linear/X86_64/FreeRegs.hs
index 5a7f71e3f0..713b053356 100644
--- a/compiler/nativeGen/RegAlloc/Linear/X86_64/FreeRegs.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/X86_64/FreeRegs.hs
@@ -3,6 +3,8 @@
module RegAlloc.Linear.X86_64.FreeRegs
where
+import GhcPrelude
+
import X86.Regs
import RegClass
import Reg
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