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-rw-r--r--compiler/nativeGen/RegAlloc/Graph/Main.hs20
1 files changed, 11 insertions, 9 deletions
diff --git a/compiler/nativeGen/RegAlloc/Graph/Main.hs b/compiler/nativeGen/RegAlloc/Graph/Main.hs
index 298b5673d4..9e8c25e68d 100644
--- a/compiler/nativeGen/RegAlloc/Graph/Main.hs
+++ b/compiler/nativeGen/RegAlloc/Graph/Main.hs
@@ -28,6 +28,7 @@ import UniqSet
import UniqFM
import Bag
import Outputable
+import Platform
import DynFlags
import Data.List
@@ -44,7 +45,7 @@ maxSpinCount = 10
-- | The top level of the graph coloring register allocator.
regAlloc
- :: (Outputable statics, Outputable instr, Instruction instr)
+ :: (Outputable statics, PlatformOutputable instr, Instruction instr)
=> DynFlags
-> UniqFM (UniqSet RealReg) -- ^ the registers we can use for allocation
-> UniqSet Int -- ^ the set of available spill slots.
@@ -79,6 +80,7 @@ regAlloc_spin
debug_codeGraphs
code
= do
+ let platform = targetPlatform dflags
-- if any of these dump flags are turned on we want to hang on to
-- intermediate structures in the allocator - otherwise tell the
-- allocator to ditch them early so we don't end up creating space leaks.
@@ -111,7 +113,7 @@ regAlloc_spin
-- build a map of the cost of spilling each instruction
-- this will only actually be computed if we have to spill something.
let spillCosts = foldl' plusSpillCostInfo zeroSpillCostInfo
- $ map slurpSpillCostInfo code
+ $ map (slurpSpillCostInfo platform) code
-- the function to choose regs to leave uncolored
let spill = chooseSpill spillCosts
@@ -159,14 +161,14 @@ regAlloc_spin
else graph_colored
-- patch the registers using the info in the graph
- let code_patched = map (patchRegsFromGraph graph_colored_lint) code_coalesced
+ let code_patched = map (patchRegsFromGraph platform graph_colored_lint) code_coalesced
-- clean out unneeded SPILL/RELOADs
let code_spillclean = map cleanSpills code_patched
-- strip off liveness information,
-- and rewrite SPILL/RELOAD pseudos into real instructions along the way
- let code_final = map stripLive code_spillclean
+ let code_final = map (stripLive platform) code_spillclean
-- record what happened in this stage for debugging
let stat =
@@ -211,7 +213,7 @@ regAlloc_spin
-- NOTE: we have to reverse the SCCs here to get them back into the reverse-dependency
-- order required by computeLiveness. If they're not in the correct order
-- that function will panic.
- code_relive <- mapM (regLiveness . reverseBlocksInTops) code_spilled
+ code_relive <- mapM (regLiveness platform . reverseBlocksInTops) code_spilled
-- record what happened in this stage for debugging
let stat =
@@ -320,11 +322,11 @@ graphAddCoalesce _ _
-- | Patch registers in code using the reg -> reg mapping in this graph.
patchRegsFromGraph
- :: (Outputable statics, Outputable instr, Instruction instr)
- => Color.Graph VirtualReg RegClass RealReg
+ :: (Outputable statics, PlatformOutputable instr, Instruction instr)
+ => Platform -> Color.Graph VirtualReg RegClass RealReg
-> LiveCmmTop statics instr -> LiveCmmTop statics instr
-patchRegsFromGraph graph code
+patchRegsFromGraph platform graph code
= let
-- a function to lookup the hardreg for a virtual reg from the graph.
patchF reg
@@ -343,7 +345,7 @@ patchRegsFromGraph graph code
| otherwise
= pprPanic "patchRegsFromGraph: register mapping failed."
( text "There is no node in the graph for register " <> ppr reg
- $$ ppr code
+ $$ pprPlatform platform code
$$ Color.dotGraph
(\_ -> text "white")
(trivColorable