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-rw-r--r--compiler/nativeGen/PPC/Regs.hs33
1 files changed, 16 insertions, 17 deletions
diff --git a/compiler/nativeGen/PPC/Regs.hs b/compiler/nativeGen/PPC/Regs.hs
index d0eb183ea7..05efaeb1f4 100644
--- a/compiler/nativeGen/PPC/Regs.hs
+++ b/compiler/nativeGen/PPC/Regs.hs
@@ -60,7 +60,6 @@ import Unique
import CodeGen.Platform
import DynFlags
import Outputable
-import FastTypes
import Platform
import Data.Word ( Word8, Word16, Word32, Word64 )
@@ -75,44 +74,44 @@ import Data.Int ( Int8, Int16, Int32, Int64 )
-- as a neighbour.
--
{-# INLINE virtualRegSqueeze #-}
-virtualRegSqueeze :: RegClass -> VirtualReg -> FastInt
+virtualRegSqueeze :: RegClass -> VirtualReg -> Int
virtualRegSqueeze cls vr
= case cls of
RcInteger
-> case vr of
- VirtualRegI{} -> _ILIT(1)
- VirtualRegHi{} -> _ILIT(1)
- _other -> _ILIT(0)
+ VirtualRegI{} -> 1
+ VirtualRegHi{} -> 1
+ _other -> 0
RcDouble
-> case vr of
- VirtualRegD{} -> _ILIT(1)
- VirtualRegF{} -> _ILIT(0)
- _other -> _ILIT(0)
+ VirtualRegD{} -> 1
+ VirtualRegF{} -> 0
+ _other -> 0
- _other -> _ILIT(0)
+ _other -> 0
{-# INLINE realRegSqueeze #-}
-realRegSqueeze :: RegClass -> RealReg -> FastInt
+realRegSqueeze :: RegClass -> RealReg -> Int
realRegSqueeze cls rr
= case cls of
RcInteger
-> case rr of
RealRegSingle regNo
- | regNo < 32 -> _ILIT(1) -- first fp reg is 32
- | otherwise -> _ILIT(0)
+ | regNo < 32 -> 1 -- first fp reg is 32
+ | otherwise -> 0
- RealRegPair{} -> _ILIT(0)
+ RealRegPair{} -> 0
RcDouble
-> case rr of
RealRegSingle regNo
- | regNo < 32 -> _ILIT(0)
- | otherwise -> _ILIT(1)
+ | regNo < 32 -> 0
+ | otherwise -> 1
- RealRegPair{} -> _ILIT(0)
+ RealRegPair{} -> 0
- _other -> _ILIT(0)
+ _other -> 0
mkVirtualReg :: Unique -> Format -> VirtualReg
mkVirtualReg u format