[project @ 2000-02-28 12:02:31 by sewardj]

Many changes to improve the quality and correctness of generated code,
both for x86 and all-platforms.  The intent is that the x86 NCG will
now be good enough for general use.

-- Add an almost-trivial Stix (generic) peephole optimiser, whose sole
   purpose is elide assignments to temporaries used only once, in the
   very next tree.  This generates substantially better code for
   conditionals on all platforms.  Enhance Stix constant folding to
   take advantage of the inlining.

   The inlining presents subsequent insn selection phases with more
   complex trees than would have previously been used to.  This has
   shown up several bugs in the x86 insn selectors, now fixed.
   (assumptions that data size is Word, when could be Byte,
    assumptions that an operand will always be in a temp reg, etc)

-- x86: Use the FLDZ and FLD1 insns.

-- x86: spill FP registers with 80-bit loads/stores so that
   Intel's extra 16 bits of accuracy are not lost.  If this isn't
   done, FP spills are not suitably transparent.  Increase the
   number of spill words available to 2048.

-- x86: give the register allocator more flexibility in choosing
   spill temporaries.

-- x86, RegAllocInfo.regUsage: fix error for GST, and rewrite to
   make it clearer.

-- Correctly track movements in the C stack pointer, and generate
   correct spill code for archs which spill against the stack pointer
   even when the stack pointer moves.  Redo the x86 ccall mechanism
   to push args on the C stack in the normal way.  Rather than have
   the spiller have to analyse code sequences to determine the current
   stack offset, the insn selectors communicate the current offset
   whenever it changes by inserting a DELTA pseudo-insn.  Then the
   spiller only has to spot DELTAs.

   This means having a new native-code-generator monad (Stix.NatM)
   which carries both a UniqSupply and the current stack offset.

-- Remove the asmPar/asmSeq ways of grouping insns together.
   In the presence of fixed registers, it is hard to demonstrate
   that insn selectors using asmPar always give correct code, and
   the extra complication doesn't help any.

   Also, directly construct code sequences using tree-based ordered
   lists (utils/OrdList.lhs) for linear-time appends, rather than
   the bizarrely complex method using fns and fn composition.

-- Inline some hcats in printing of x86 address modes.

-- Document more of the hidden assumptions which insn selection relies
   on, particular wrt addressing modes.

1 files changed, 14 insertions, 3 deletions

diff --git a/ghc/compiler/nativeGen/MachMisc.lhs b/ghc/compiler/nativeGen/MachMisc.lhs
index 6f5337339d..ddbc1fdd3e 100644
--- a/ghc/compiler/nativeGen/MachMisc.lhs
+++ b/ghc/compiler/nativeGen/MachMisc.lhs
@@ -301,6 +301,7 @@ data Size
     | L
     | F	    -- IEEE single-precision floating pt
     | DF    -- IEEE single-precision floating pt
+    | F80   -- Intel 80-bit internal FP format; only used for spilling
 #endif
 #if sparc_TARGET_ARCH
     = B     -- byte (signed)
@@ -351,6 +352,8 @@ data Instr
 	    String		-- the literal string
   | DATA    Size
 	    [Imm]
+  | DELTA   Int                 -- specify current stack offset for
+                                -- benefit of subsequent passes
 \end{code}
 
 \begin{code}
@@ -470,6 +473,10 @@ contents, would not impose a fixed mapping from %fake to %st regs, and
 hopefully could avoid most of the redundant reg-reg moves of the
 current translation.
 
+We might as well make use of whatever unique FP facilities Intel have
+chosen to bless us with (let's not be churlish, after all).
+Hence GLDZ and GLD1.  Bwahahahahahahaha!
+
 \begin{code}
 #if i386_TARGET_ARCH
 
@@ -509,10 +516,10 @@ current translation.
               | BT            Size Imm Operand
 	      | NOP
 
--- Float Arithmetic. -- ToDo for 386
+-- Float Arithmetic.
 
--- Note that we cheat by treating G{ABS,MOV,NEG} of doubles as single instructions
--- right up until we spit them out.
+-- Note that we cheat by treating G{ABS,MOV,NEG} of doubles 
+-- as single instructions right up until we spit them out.
 
               -- all the 3-operand fake fp insns are src1 src2 dst
               -- and furthermore are constrained to be fp regs only.
@@ -521,6 +528,9 @@ current translation.
               | GLD           Size MachRegsAddr Reg -- src, dst(fpreg)
               | GST           Size Reg MachRegsAddr -- src(fpreg), dst
 
+              | GLDZ          Reg -- dst(fpreg)
+              | GLD1          Reg -- dst(fpreg)
+
     	      | GFTOD	      Reg Reg -- src(fpreg), dst(fpreg)
               | GFTOI         Reg Reg -- src(fpreg), dst(intreg)
 
@@ -595,6 +605,7 @@ is_G_instr :: Instr -> Bool
 is_G_instr instr
    = case instr of
         GMOV _ _ -> True; GLD _ _ _ -> True; GST _ _ _ -> True;
+        GLDZ _ -> True; GLD1 _ -> True;
         GFTOD _ _ -> True; GFTOI _ _ -> True;
         GDTOF _ _ -> True; GDTOI _ _ -> True;
         GITOF _ _ -> True; GITOD _ _ -> True;