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authorsewardj <unknown>2002-01-08 10:59:42 +0000
committersewardj <unknown>2002-01-08 10:59:42 +0000
commit20d7560469e59d78c17992ce4be75360c91587bb (patch)
treee01fcb601571b3d61343858cdcd26702b6681a5c /ghc/compiler/nativeGen/MachMisc.lhs
parentd1a3ff224190eed70da56f68cb06e92d691fe131 (diff)
downloadhaskell-20d7560469e59d78c17992ce4be75360c91587bb.tar.gz
[project @ 2002-01-08 10:59:42 by sewardj]
merge from stable branch: 1.46.4.3 +14 -7 fptools/ghc/compiler/nativeGen/AsmCodeGen.lhs 1.47.4.3 +2 -0 fptools/ghc/compiler/nativeGen/MachMisc.lhs Treat literal appearances of BaseReg in Stix trees uniformly. This is now taken to mean the &MainCapability.r, regardless of whether BaseReg is in a register (x86) or synthesised (sparc).
Diffstat (limited to 'ghc/compiler/nativeGen/MachMisc.lhs')
-rw-r--r--ghc/compiler/nativeGen/MachMisc.lhs2
1 files changed, 2 insertions, 0 deletions
diff --git a/ghc/compiler/nativeGen/MachMisc.lhs b/ghc/compiler/nativeGen/MachMisc.lhs
index de69ab6516..ad711882d5 100644
--- a/ghc/compiler/nativeGen/MachMisc.lhs
+++ b/ghc/compiler/nativeGen/MachMisc.lhs
@@ -113,6 +113,8 @@ volatileSavesOrRestores do_saves vols
= catMaybes (map mkCode vols)
where
mkCode mid
+ | case mid of { BaseReg -> True; _ -> False }
+ = panic "volatileSavesOrRestores:BaseReg"
| not (callerSaves mid)
= Nothing
| otherwise -- must be callee-saves ...