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| author | Bartosz Nitka <niteria@gmail.com> | 2016-06-14 03:28:30 -0700 |
|---|---|---|
| committer | Bartosz Nitka <niteria@gmail.com> | 2016-06-23 07:53:12 -0700 |
| commit | 35d1564cea2e611a4fecf24f09eff83f8a55af1c (patch) | |
| tree | 5d46f89500052d356bf68e2befd6bf854550193a /compiler/nativeGen | |
| parent | 7fc20b02b20c97209b97f0e36d34a4ef40f537a4 (diff) | |
| download | haskell-35d1564cea2e611a4fecf24f09eff83f8a55af1c.tar.gz | |
Provide Uniquable version of SCC
We want to remove the `Ord Unique` instance because there's
no way to implement it in deterministic way and it's too
easy to use by accident.
We sometimes compute SCC for datatypes whose Ord instance
is implemented in terms of Unique. The Ord constraint on
SCC is just an artifact of some internal data structures.
We can have an alternative implementation with a data
structure that uses Uniquable instead.
This does exactly that and I'm pleased that I didn't have
to introduce any duplication to do that.
Test Plan:
./validate
I looked at performance tests and it's a tiny bit better.
Reviewers: bgamari, simonmar, ezyang, austin, goldfire
Subscribers: thomie
Differential Revision: https://phabricator.haskell.org/D2359
GHC Trac Issues: #4012
Diffstat (limited to 'compiler/nativeGen')
| -rw-r--r-- | compiler/nativeGen/AsmCodeGen.hs | 2 | ||||
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs | 4 | ||||
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Liveness.hs | 6 |
3 files changed, 6 insertions, 6 deletions
diff --git a/compiler/nativeGen/AsmCodeGen.hs b/compiler/nativeGen/AsmCodeGen.hs index 6bb7f8a875..2bf9e1cc2e 100644 --- a/compiler/nativeGen/AsmCodeGen.hs +++ b/compiler/nativeGen/AsmCodeGen.hs @@ -764,7 +764,7 @@ sccBlocks , BlockId , [BlockId])] -sccBlocks blocks = stronglyConnCompFromEdgedVerticesR (map mkNode blocks) +sccBlocks blocks = stronglyConnCompFromEdgedVerticesUniqR (map mkNode blocks) -- we're only interested in the last instruction of -- the block, and only if it has a single destination. diff --git a/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs b/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs index 07ff1ca887..ac38e2b450 100644 --- a/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs +++ b/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs @@ -169,7 +169,7 @@ joinToTargets_again -- -- We need to do the R2 -> R3 move before R1 -> R2. -- - let sccs = stronglyConnCompFromEdgedVerticesR graph + let sccs = stronglyConnCompFromEdgedVerticesOrdR graph {- -- debugging pprTrace @@ -313,7 +313,7 @@ handleComponent delta instr instrLoad <- loadR (RegReal dreg) slot remainingFixUps <- mapM (handleComponent delta instr) - (stronglyConnCompFromEdgedVerticesR rest) + (stronglyConnCompFromEdgedVerticesOrdR rest) -- make sure to do all the reloads after all the spills, -- so we don't end up clobbering the source values. diff --git a/compiler/nativeGen/RegAlloc/Liveness.hs b/compiler/nativeGen/RegAlloc/Liveness.hs index ed2ff7bf93..b97246012a 100644 --- a/compiler/nativeGen/RegAlloc/Liveness.hs +++ b/compiler/nativeGen/RegAlloc/Liveness.hs @@ -679,13 +679,13 @@ sccBlocks blocks entries = map (fmap get_node) sccs nodes = [ (block, id, getOutEdges instrs) | block@(BasicBlock id instrs) <- blocks ] - g1 = graphFromEdgedVertices nodes + g1 = graphFromEdgedVerticesUniq nodes reachable :: BlockSet reachable = setFromList [ id | (_,id,_) <- reachablesG g1 roots ] - g2 = graphFromEdgedVertices [ node | node@(_,id,_) <- nodes - , id `setMember` reachable ] + g2 = graphFromEdgedVerticesUniq [ node | node@(_,id,_) <- nodes + , id `setMember` reachable ] sccs = stronglyConnCompG g2 |