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| author | Erik de Castro Lopo <erikd@mega-nerd.com> | 2015-09-13 18:57:40 +1000 |
|---|---|---|
| committer | Erik de Castro Lopo <erikd@mega-nerd.com> | 2015-10-12 13:09:40 +1100 |
| commit | 4bd58c179b8d0f8cf2850acb920cef8605826a2a (patch) | |
| tree | 4510817f8d70aadd80c81b58f7386e36a279397f /compiler/nativeGen | |
| parent | f0023409211f619e7676fa5cdac139e14aeaedd4 (diff) | |
| download | haskell-4bd58c179b8d0f8cf2850acb920cef8605826a2a.tar.gz | |
PPC: Fix right shift by 32 bits #10870
Summary: Test included.
Test Plan: Run test T10870.hs on X86/X86_64/Arm/Arm64 etc
Reviewers: bgamari, nomeata, austin
Subscribers: thomie
Differential Revision: https://phabricator.haskell.org/D1322
GHC Trac Issues: #10870
Diffstat (limited to 'compiler/nativeGen')
| -rw-r--r-- | compiler/nativeGen/PPC/Ppr.hs | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/compiler/nativeGen/PPC/Ppr.hs b/compiler/nativeGen/PPC/Ppr.hs index b2bfb4efbe..e5147794ce 100644 --- a/compiler/nativeGen/PPC/Ppr.hs +++ b/compiler/nativeGen/PPC/Ppr.hs @@ -710,6 +710,21 @@ pprInstr (EXTS fmt reg1 reg2) = hcat [ pprInstr (NEG reg1 reg2) = pprUnary (sLit "neg") reg1 reg2 pprInstr (NOT reg1 reg2) = pprUnary (sLit "not") reg1 reg2 +pprInstr (SR II32 reg1 reg2 (RIImm (ImmInt i))) | i < 0 || i > 31 = + -- Handle the case where we are asked to shift a 32 bit register by + -- less than zero or more than 31 bits. We convert this into a clear + -- of the destination register. + -- Fixes ticket http://ghc.haskell.org/trac/ghc/ticket/5900 + pprInstr (XOR reg1 reg2 (RIReg reg2)) + +pprInstr (SL II32 reg1 reg2 (RIImm (ImmInt i))) | i < 0 || i > 31 = + -- As aboce for SR, but for left shifts. + -- Fixes ticket http://ghc.haskell.org/trac/ghc/ticket/10870 + pprInstr (XOR reg1 reg2 (RIReg reg2)) + +pprInstr (SRA II32 reg1 reg2 (RIImm (ImmInt i))) | i < 0 || i > 31 = + pprInstr (XOR reg1 reg2 (RIReg reg2)) + pprInstr (SL fmt reg1 reg2 ri) = let op = case fmt of II32 -> "slw" @@ -717,12 +732,6 @@ pprInstr (SL fmt reg1 reg2 ri) = _ -> panic "PPC.Ppr.pprInstr: shift illegal size" in pprLogic (sLit op) reg1 reg2 (limitShiftRI fmt ri) -pprInstr (SR II32 reg1 reg2 (RIImm (ImmInt i))) | i > 31 || i < 0 = - -- Handle the case where we are asked to shift a 32 bit register by - -- less than zero or more than 31 bits. We convert this into a clear - -- of the destination register. - -- Fixes ticket http://ghc.haskell.org/trac/ghc/ticket/5900 - pprInstr (XOR reg1 reg2 (RIReg reg2)) pprInstr (SR fmt reg1 reg2 ri) = let op = case fmt of II32 -> "srw" |