update to current master againwip/T13904

7 files changed, 33 insertions, 1 deletions

diff --git a/compiler/nativeGen/SPARC/CodeGen/Amode.hs b/compiler/nativeGen/SPARC/CodeGen/Amode.hs
index a59287f171..33e3f535da 100644
--- a/compiler/nativeGen/SPARC/CodeGen/Amode.hs
+++ b/compiler/nativeGen/SPARC/CodeGen/Amode.hs
@@ -4,6 +4,8 @@ module SPARC.CodeGen.Amode (
 
 where
 
+import GhcPrelude
+
 import {-# SOURCE #-} SPARC.CodeGen.Gen32
 import SPARC.CodeGen.Base
 import SPARC.AddrMode
diff --git a/compiler/nativeGen/SPARC/CodeGen/Base.hs b/compiler/nativeGen/SPARC/CodeGen/Base.hs
index 27b533f46b..039bb6496c 100644
--- a/compiler/nativeGen/SPARC/CodeGen/Base.hs
+++ b/compiler/nativeGen/SPARC/CodeGen/Base.hs
@@ -13,6 +13,8 @@ module SPARC.CodeGen.Base (
 
 where
 
+import GhcPrelude
+
 import SPARC.Instr
 import SPARC.Cond
 import SPARC.AddrMode
diff --git a/compiler/nativeGen/SPARC/CodeGen/CondCode.hs b/compiler/nativeGen/SPARC/CodeGen/CondCode.hs
index e5fb82df4d..e6b2e174b6 100644
--- a/compiler/nativeGen/SPARC/CodeGen/CondCode.hs
+++ b/compiler/nativeGen/SPARC/CodeGen/CondCode.hs
@@ -6,6 +6,8 @@ module SPARC.CodeGen.CondCode (
 
 where
 
+import GhcPrelude
+
 import {-# SOURCE #-} SPARC.CodeGen.Gen32
 import SPARC.CodeGen.Base
 import SPARC.Instr
diff --git a/compiler/nativeGen/SPARC/CodeGen/Expand.hs b/compiler/nativeGen/SPARC/CodeGen/Expand.hs
index 70cb0111c0..0b318740db 100644
--- a/compiler/nativeGen/SPARC/CodeGen/Expand.hs
+++ b/compiler/nativeGen/SPARC/CodeGen/Expand.hs
@@ -5,6 +5,8 @@ module SPARC.CodeGen.Expand (
 
 where
 
+import GhcPrelude
+
 import SPARC.Instr
 import SPARC.Imm
 import SPARC.AddrMode
@@ -140,7 +142,7 @@ expandMisalignedDoubles instr
 
 
 
--- | The the high partner for this float reg.
+-- | The high partner for this float reg.
 fRegHi :: Reg -> Reg
 fRegHi (RegReal (RealRegSingle r1))
         | r1            >= 32
diff --git a/compiler/nativeGen/SPARC/CodeGen/Gen32.hs b/compiler/nativeGen/SPARC/CodeGen/Gen32.hs
index a0e86f14c4..a7a1f60416 100644
--- a/compiler/nativeGen/SPARC/CodeGen/Gen32.hs
+++ b/compiler/nativeGen/SPARC/CodeGen/Gen32.hs
@@ -6,6 +6,8 @@ module SPARC.CodeGen.Gen32 (
 
 where
 
+import GhcPrelude
+
 import SPARC.CodeGen.CondCode
 import SPARC.CodeGen.Amode
 import SPARC.CodeGen.Gen64
diff --git a/compiler/nativeGen/SPARC/CodeGen/Gen64.hs b/compiler/nativeGen/SPARC/CodeGen/Gen64.hs
index f186d437d0..6fa7482f9b 100644
--- a/compiler/nativeGen/SPARC/CodeGen/Gen64.hs
+++ b/compiler/nativeGen/SPARC/CodeGen/Gen64.hs
@@ -7,6 +7,8 @@ module SPARC.CodeGen.Gen64 (
 
 where
 
+import GhcPrelude
+
 import {-# SOURCE #-} SPARC.CodeGen.Gen32
 import SPARC.CodeGen.Base
 import SPARC.CodeGen.Amode
@@ -191,6 +193,24 @@ iselExpr64 (CmmMachOp (MO_UU_Conv _ W64) [expr])
 
         return  $ ChildCode64 code r_dst_lo
 
+-- only W32 supported for now
+iselExpr64 (CmmMachOp (MO_SS_Conv W32 W64) [expr])
+ = do
+        r_dst_lo        <- getNewRegNat II32
+        let r_dst_hi    = getHiVRegFromLo r_dst_lo
+
+        -- compute expr and load it into r_dst_lo
+        (a_reg, a_code) <- getSomeReg expr
+
+        dflags          <- getDynFlags
+        let platform    = targetPlatform dflags
+            code        = a_code
+                `appOL` toOL
+                        [ SRA a_reg (RIImm (ImmInt 31)) r_dst_hi
+                        , mkRegRegMoveInstr platform a_reg r_dst_lo ]
+
+        return  $ ChildCode64 code r_dst_lo
+
 
 iselExpr64 expr
    = pprPanic "iselExpr64(sparc)" (ppr expr)
diff --git a/compiler/nativeGen/SPARC/CodeGen/Sanity.hs b/compiler/nativeGen/SPARC/CodeGen/Sanity.hs
index 81641326f2..fcf5b65bde 100644
--- a/compiler/nativeGen/SPARC/CodeGen/Sanity.hs
+++ b/compiler/nativeGen/SPARC/CodeGen/Sanity.hs
@@ -6,6 +6,8 @@ module SPARC.CodeGen.Sanity (
 
 where
 
+import GhcPrelude
+
 import SPARC.Instr
 import SPARC.Ppr        ()
 import Instruction