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author | Ian Lynagh <ian@well-typed.com> | 2012-08-21 19:39:20 +0100 |
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committer | Ian Lynagh <ian@well-typed.com> | 2012-08-21 19:39:20 +0100 |
commit | ac21fdb440d4cf44134f609d2aec73e1fcacf424 (patch) | |
tree | 885ea98506fb81261f3291f7be7f7d47b354d18d /compiler/nativeGen/RegAlloc/Linear | |
parent | d182285fa4ee18f76060a526927396f4cfb11043 (diff) | |
download | haskell-ac21fdb440d4cf44134f609d2aec73e1fcacf424.tar.gz |
Pass platform down to lastxmm
Diffstat (limited to 'compiler/nativeGen/RegAlloc/Linear')
-rw-r--r-- | compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs | 6 | ||||
-rw-r--r-- | compiler/nativeGen/RegAlloc/Linear/Main.hs | 23 | ||||
-rw-r--r-- | compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs | 7 |
3 files changed, 19 insertions, 17 deletions
diff --git a/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs b/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs index fd1fd272bd..5fc389b89e 100644 --- a/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs +++ b/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs @@ -44,7 +44,7 @@ import qualified X86.Instr class Show freeRegs => FR freeRegs where frAllocateReg :: RealReg -> freeRegs -> freeRegs frGetFreeRegs :: RegClass -> freeRegs -> [RealReg] - frInitFreeRegs :: freeRegs + frInitFreeRegs :: Platform -> freeRegs frReleaseReg :: RealReg -> freeRegs -> freeRegs instance FR X86.FreeRegs where @@ -56,13 +56,13 @@ instance FR X86.FreeRegs where instance FR PPC.FreeRegs where frAllocateReg = PPC.allocateReg frGetFreeRegs = PPC.getFreeRegs - frInitFreeRegs = PPC.initFreeRegs + frInitFreeRegs = \_ -> PPC.initFreeRegs frReleaseReg = PPC.releaseReg instance FR SPARC.FreeRegs where frAllocateReg = SPARC.allocateReg frGetFreeRegs = SPARC.getFreeRegs - frInitFreeRegs = SPARC.initFreeRegs + frInitFreeRegs = \_ -> SPARC.initFreeRegs frReleaseReg = SPARC.releaseReg maxSpillSlots :: Platform -> Int diff --git a/compiler/nativeGen/RegAlloc/Linear/Main.hs b/compiler/nativeGen/RegAlloc/Linear/Main.hs index 07b6e33d25..7d6e85e664 100644 --- a/compiler/nativeGen/RegAlloc/Linear/Main.hs +++ b/compiler/nativeGen/RegAlloc/Linear/Main.hs @@ -191,10 +191,10 @@ linearRegAlloc linearRegAlloc dflags first_id block_live sccs = let platform = targetPlatform dflags in case platformArch platform of - ArchX86 -> linearRegAlloc' platform (frInitFreeRegs :: X86.FreeRegs) first_id block_live sccs - ArchX86_64 -> linearRegAlloc' platform (frInitFreeRegs :: X86.FreeRegs) first_id block_live sccs - ArchSPARC -> linearRegAlloc' platform (frInitFreeRegs :: SPARC.FreeRegs) first_id block_live sccs - ArchPPC -> linearRegAlloc' platform (frInitFreeRegs :: PPC.FreeRegs) first_id block_live sccs + ArchX86 -> linearRegAlloc' platform (frInitFreeRegs platform :: X86.FreeRegs) first_id block_live sccs + ArchX86_64 -> linearRegAlloc' platform (frInitFreeRegs platform :: X86.FreeRegs) first_id block_live sccs + ArchSPARC -> linearRegAlloc' platform (frInitFreeRegs platform :: SPARC.FreeRegs) first_id block_live sccs + ArchPPC -> linearRegAlloc' platform (frInitFreeRegs platform :: PPC.FreeRegs) first_id block_live sccs ArchARM _ _ _ -> panic "linearRegAlloc ArchARM" ArchPPC_64 -> panic "linearRegAlloc ArchPPC_64" ArchUnknown -> panic "linearRegAlloc ArchUnknown" @@ -304,7 +304,7 @@ processBlock -> RegM freeRegs [NatBasicBlock instr] -- ^ block with registers allocated processBlock platform block_live (BasicBlock id instrs) - = do initBlock id block_live + = do initBlock platform id block_live (instrs', fixups) <- linearRA platform block_live [] [] id instrs return $ BasicBlock id instrs' : fixups @@ -312,8 +312,9 @@ processBlock platform block_live (BasicBlock id instrs) -- | Load the freeregs and current reg assignment into the RegM state -- for the basic block with this BlockId. -initBlock :: FR freeRegs => BlockId -> BlockMap RegSet -> RegM freeRegs () -initBlock id block_live +initBlock :: FR freeRegs + => Platform -> BlockId -> BlockMap RegSet -> RegM freeRegs () +initBlock platform id block_live = do block_assig <- getBlockAssigR case mapLookup id block_assig of -- no prior info about this block: we must consider @@ -325,9 +326,9 @@ initBlock id block_live -> do -- pprTrace "initFreeRegs" (text $ show initFreeRegs) (return ()) case mapLookup id block_live of Nothing -> - setFreeRegsR frInitFreeRegs + setFreeRegsR (frInitFreeRegs platform) Just live -> - setFreeRegsR $ foldr frAllocateReg frInitFreeRegs [ r | RegReal r <- uniqSetToList live ] + setFreeRegsR $ foldr frAllocateReg (frInitFreeRegs platform) [ r | RegReal r <- uniqSetToList live ] setAssigR emptyRegMap -- load info about register assignments leading into this block. @@ -447,7 +448,7 @@ genRaInsn :: (FR freeRegs, Instruction instr, Outputable instr) -> RegM freeRegs ([instr], [NatBasicBlock instr]) genRaInsn platform block_live new_instrs block_id instr r_dying w_dying = - case regUsageOfInstr instr of { RU read written -> + case regUsageOfInstr platform instr of { RU read written -> do let real_written = [ rr | (RegReal rr) <- written ] let virt_written = [ vr | (RegVirtual vr) <- written ] @@ -822,7 +823,7 @@ allocRegsAndSpill_spill platform reading keep spills alloc r rs assig spill_loc [ text "allocating vreg: " <> text (show r) , text "assignment: " <> text (show $ ufmToList assig) , text "freeRegs: " <> text (show freeRegs) - , text "initFreeRegs: " <> text (show (frInitFreeRegs `asTypeOf` freeRegs)) ] + , text "initFreeRegs: " <> text (show (frInitFreeRegs platform `asTypeOf` freeRegs)) ] result diff --git a/compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs b/compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs index 7e7d99b008..debdf3cd03 100644 --- a/compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs +++ b/compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs @@ -14,6 +14,7 @@ import X86.Regs import RegClass import Reg import Panic +import Platform import Data.Word import Data.Bits @@ -35,9 +36,9 @@ releaseReg (RealRegSingle n) f releaseReg _ _ = panic "RegAlloc.Linear.X86.FreeRegs.realeaseReg: no reg" -initFreeRegs :: FreeRegs -initFreeRegs - = foldr releaseReg noFreeRegs allocatableRegs +initFreeRegs :: Platform -> FreeRegs +initFreeRegs platform + = foldr releaseReg noFreeRegs (allocatableRegs platform) getFreeRegs :: RegClass -> FreeRegs -> [RealReg] -- lazilly getFreeRegs cls f = go f 0 |