Move some more constants into platformConstants

5 files changed, 19 insertions, 19 deletions

diff --git a/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs b/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs
index 4a5af75ce8..fffdef761b 100644
--- a/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs
@@ -18,6 +18,7 @@ where
 import Reg
 import RegClass
 
+import DynFlags
 import Panic
 import Platform
 
@@ -72,13 +73,13 @@ instance FR SPARC.FreeRegs where
     frInitFreeRegs = SPARC.initFreeRegs
     frReleaseReg   = SPARC.releaseReg
 
-maxSpillSlots :: Platform -> Int
-maxSpillSlots platform
-              = case platformArch platform of
-                ArchX86       -> X86.Instr.maxSpillSlots True  -- 32bit
-                ArchX86_64    -> X86.Instr.maxSpillSlots False -- not 32bit
-                ArchPPC       -> PPC.Instr.maxSpillSlots
-                ArchSPARC     -> SPARC.Instr.maxSpillSlots
+maxSpillSlots :: DynFlags -> Int
+maxSpillSlots dflags
+              = case platformArch (targetPlatform dflags) of
+                ArchX86       -> X86.Instr.maxSpillSlots dflags
+                ArchX86_64    -> X86.Instr.maxSpillSlots dflags
+                ArchPPC       -> PPC.Instr.maxSpillSlots dflags
+                ArchSPARC     -> SPARC.Instr.maxSpillSlots dflags
                 ArchARM _ _ _ -> panic "maxSpillSlots ArchARM"
                 ArchPPC_64    -> panic "maxSpillSlots ArchPPC_64"
                 ArchUnknown   -> panic "maxSpillSlots ArchUnknown"
diff --git a/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs b/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs
index 69bd8a7a0e..6294743c48 100644
--- a/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/JoinToTargets.hs
@@ -344,10 +344,10 @@ makeMove delta vreg src dst
                  return $ mkRegRegMoveInstr platform (RegReal s) (RegReal d)
           (InMem s, InReg d) ->
               do recordSpill (SpillJoinRM vreg)
-                 return $ mkLoadInstr platform (RegReal d) delta s
+                 return $ mkLoadInstr dflags (RegReal d) delta s
           (InReg s, InMem d) ->
               do recordSpill (SpillJoinRM vreg)
-                 return $ mkSpillInstr platform (RegReal s) delta d
+                 return $ mkSpillInstr dflags (RegReal s) delta d
           _ ->
               -- we don't handle memory to memory moves.
               -- they shouldn't happen because we don't share
diff --git a/compiler/nativeGen/RegAlloc/Linear/Main.hs b/compiler/nativeGen/RegAlloc/Linear/Main.hs
index 8b8afd05af..3f92ed975b 100644
--- a/compiler/nativeGen/RegAlloc/Linear/Main.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/Main.hs
@@ -208,9 +208,8 @@ linearRegAlloc'
 
 linearRegAlloc' dflags initFreeRegs first_id block_live sccs
  = do   us      <- getUs
-        let platform = targetPlatform dflags
-            (_, _, stats, blocks) =
-                runR dflags emptyBlockMap initFreeRegs emptyRegMap (emptyStackMap platform) us
+        let (_, _, stats, blocks) =
+                runR dflags emptyBlockMap initFreeRegs emptyRegMap (emptyStackMap dflags) us
                     $ linearRA_SCCs first_id block_live [] sccs
         return  (blocks, stats)
 
diff --git a/compiler/nativeGen/RegAlloc/Linear/StackMap.hs b/compiler/nativeGen/RegAlloc/Linear/StackMap.hs
index ea05cf0d0f..b1fc3c169e 100644
--- a/compiler/nativeGen/RegAlloc/Linear/StackMap.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/StackMap.hs
@@ -28,8 +28,8 @@ where
 
 import RegAlloc.Linear.FreeRegs
 
+import DynFlags
 import Outputable
-import Platform
 import UniqFM
 import Unique
 
@@ -47,8 +47,8 @@ data StackMap
 
 
 -- | An empty stack map, with all slots available.
-emptyStackMap :: Platform -> StackMap
-emptyStackMap platform = StackMap [0 .. maxSpillSlots platform] emptyUFM
+emptyStackMap :: DynFlags -> StackMap
+emptyStackMap dflags = StackMap [0 .. maxSpillSlots dflags] emptyUFM
 
 
 -- | If this vreg unique already has a stack assignment then return the slot number,
diff --git a/compiler/nativeGen/RegAlloc/Linear/State.hs b/compiler/nativeGen/RegAlloc/Linear/State.hs
index 81b97ead9c..a608a947e7 100644
--- a/compiler/nativeGen/RegAlloc/Linear/State.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/State.hs
@@ -96,9 +96,9 @@ spillR :: Instruction instr
        => Reg -> Unique -> RegM freeRegs (instr, Int)
 
 spillR reg temp = RegM $ \ s@RA_State{ra_delta=delta, ra_stack=stack} ->
-  let platform = targetPlatform (ra_DynFlags s)
+  let dflags = ra_DynFlags s
       (stack',slot) = getStackSlotFor stack temp
-      instr  = mkSpillInstr platform reg delta slot
+      instr  = mkSpillInstr dflags reg delta slot
   in
   (# s{ra_stack=stack'}, (instr,slot) #)
 
@@ -107,8 +107,8 @@ loadR :: Instruction instr
       => Reg -> Int -> RegM freeRegs instr
 
 loadR reg slot = RegM $ \ s@RA_State{ra_delta=delta} ->
-  let platform = targetPlatform (ra_DynFlags s)
-  in (# s, mkLoadInstr platform reg delta slot #)
+  let dflags = ra_DynFlags s
+  in (# s, mkLoadInstr dflags reg delta slot #)
 
 getFreeRegsR :: RegM freeRegs freeRegs
 getFreeRegsR = RegM $ \ s@RA_State{ra_freeregs = freeregs} ->