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authorKavon Farvardin <kavon@farvard.in>2018-09-23 15:29:37 -0500
committerKavon Farvardin <kavon@farvard.in>2018-09-23 15:29:37 -0500
commit84c2ad99582391005b5e873198b15e9e9eb4f78d (patch)
treecaa8c2f2ec7e97fbb4977263c6817c9af5025cf4 /compiler/nativeGen/RegAlloc/Linear/Stats.hs
parent8ddb47cfcf5776e9a3c55fd37947c8a95e00fa12 (diff)
parente68b439fe5de61b9a2ca51af472185c62ccb8b46 (diff)
downloadhaskell-wip/T13904.tar.gz
update to current master againwip/T13904
Diffstat (limited to 'compiler/nativeGen/RegAlloc/Linear/Stats.hs')
-rw-r--r--compiler/nativeGen/RegAlloc/Linear/Stats.hs3
1 files changed, 2 insertions, 1 deletions
diff --git a/compiler/nativeGen/RegAlloc/Linear/Stats.hs b/compiler/nativeGen/RegAlloc/Linear/Stats.hs
index 71dedaeb55..74f3c834d0 100644
--- a/compiler/nativeGen/RegAlloc/Linear/Stats.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/Stats.hs
@@ -6,6 +6,8 @@ module RegAlloc.Linear.Stats (
where
+import GhcPrelude
+
import RegAlloc.Linear.Base
import RegAlloc.Liveness
import Instruction
@@ -13,7 +15,6 @@ import Instruction
import UniqFM
import Outputable
-import Data.List
import State
-- | Build a map of how many times each reg was alloced, clobbered, loaded etc.