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| author | Simon Peyton Jones <simonpj@microsoft.com> | 2015-01-05 16:57:01 +0000 |
|---|---|---|
| committer | Simon Peyton Jones <simonpj@microsoft.com> | 2015-01-05 17:00:05 +0000 |
| commit | 0b3f53fb8d86278ead96ea08bedd8990d3256dc4 (patch) | |
| tree | d3ae62380f95ab44b711a4d4a7b8eb9630746069 /compiler/nativeGen/RegAlloc/Linear/Main.hs | |
| parent | d6c8da69ed75f0a046bfcf779e71a4ecd2dab106 (diff) | |
| download | haskell-wip/redundant-constraints.tar.gz | |
Remove redundant constraints in the compiler itself, found by -fwarn-redundant-constraintswip/redundant-constraints
Diffstat (limited to 'compiler/nativeGen/RegAlloc/Linear/Main.hs')
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Linear/Main.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/compiler/nativeGen/RegAlloc/Linear/Main.hs b/compiler/nativeGen/RegAlloc/Linear/Main.hs index d602d60d10..434c00f9b8 100644 --- a/compiler/nativeGen/RegAlloc/Linear/Main.hs +++ b/compiler/nativeGen/RegAlloc/Linear/Main.hs @@ -606,7 +606,7 @@ releaseRegs regs = do -- saveClobberedTemps - :: (Outputable instr, Instruction instr, FR freeRegs) + :: (Instruction instr, FR freeRegs) => [RealReg] -- real registers clobbered by this instruction -> [Reg] -- registers which are no longer live after this insn -> RegM freeRegs [instr] -- return: instructions to spill any temps that will @@ -873,7 +873,7 @@ newLocation _ my_reg = InReg my_reg -- | Load up a spilled temporary if we need to (read from memory). loadTemp - :: (Outputable instr, Instruction instr) + :: (Instruction instr) => VirtualReg -- the temp being loaded -> SpillLoc -- the current location of this temp -> RealReg -- the hreg to load the temp into |