diff options
| author | Brian Wignall <brianwignall@gmail.com> | 2019-12-19 09:11:42 -0500 |
|---|---|---|
| committer | Marge Bot <ben+marge-bot@smart-cactus.org> | 2020-01-04 15:55:06 -0500 |
| commit | 3c9dc06ba2034e867c9169e60e854539875654fd (patch) | |
| tree | f06e599ca380ee9ad599918b2ae4c78cd4afce2b /compiler/nativeGen/RegAlloc/Graph | |
| parent | b2e0323f318959c879629ef277f6433b44473c4b (diff) | |
| download | haskell-3c9dc06ba2034e867c9169e60e854539875654fd.tar.gz | |
Fix typos, via a Levenshtein-style corrector
Diffstat (limited to 'compiler/nativeGen/RegAlloc/Graph')
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Graph/Main.hs | 2 | ||||
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Graph/SpillCost.hs | 2 | ||||
| -rw-r--r-- | compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/compiler/nativeGen/RegAlloc/Graph/Main.hs b/compiler/nativeGen/RegAlloc/Graph/Main.hs index e756068ca1..1171689e66 100644 --- a/compiler/nativeGen/RegAlloc/Graph/Main.hs +++ b/compiler/nativeGen/RegAlloc/Graph/Main.hs @@ -83,7 +83,7 @@ regAlloc dflags regsFree slotsFree slotsCount code cfg -- | Perform solver iterations for the graph coloring allocator. -- --- We extract a register confict graph from the provided cmm code, +-- We extract a register conflict graph from the provided cmm code, -- and try to colour it. If that works then we use the solution rewrite -- the code with real hregs. If coloring doesn't work we add spill code -- and try to colour it again. After `maxSpinCount` iterations we give up. diff --git a/compiler/nativeGen/RegAlloc/Graph/SpillCost.hs b/compiler/nativeGen/RegAlloc/Graph/SpillCost.hs index 4be25a71ba..42de5503ba 100644 --- a/compiler/nativeGen/RegAlloc/Graph/SpillCost.hs +++ b/compiler/nativeGen/RegAlloc/Graph/SpillCost.hs @@ -38,7 +38,7 @@ import Data.Maybe import Control.Monad (join) --- | Records the expected cost to spill some regster. +-- | Records the expected cost to spill some register. type SpillCostRecord = ( VirtualReg -- register name , Int -- number of writes to this reg diff --git a/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs b/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs index 773db33293..cc2ad7d594 100644 --- a/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs +++ b/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs @@ -26,7 +26,7 @@ import Panic -- This gets hammered by scanGraph during register allocation, -- so needs to be fairly efficient. -- --- NOTE: This only works for arcitectures with just RcInteger and RcDouble +-- NOTE: This only works for architectures with just RcInteger and RcDouble -- (which are disjoint) ie. x86, x86_64 and ppc -- -- The number of allocatable regs is hard coded in here so we can do |